CA2040659A1 - Digital signal processing device - Google Patents

Digital signal processing device

Info

Publication number
CA2040659A1
CA2040659A1 CA2040659A CA2040659A CA2040659A1 CA 2040659 A1 CA2040659 A1 CA 2040659A1 CA 2040659 A CA2040659 A CA 2040659A CA 2040659 A CA2040659 A CA 2040659A CA 2040659 A1 CA2040659 A1 CA 2040659A1
Authority
CA
Canada
Prior art keywords
communication
linear array
interface
video
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2040659A
Other languages
French (fr)
Other versions
CA2040659C (en
Inventor
Keping Chen
Christer Martinus Svensson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to EP19910303836 priority Critical patent/EP0463721A3/en
Priority to JP3099138A priority patent/JPH0689271A/en
Publication of CA2040659A1 publication Critical patent/CA2040659A1/en
Application granted granted Critical
Publication of CA2040659C publication Critical patent/CA2040659C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)

Abstract

A device for digital signal processing and particularly suited for video and image processing applications. The device includes a linear array of 1024 processing elements (PE's), an external controller interface, input/output ports, and an external memory interface. The input/output ports allow the device to interface to equipment such as digitizing cameras and video display monitors. The device uses a single instruction multiple data topology (SIMD) and incorporates two modes of communication: horizontal and vertical. Shift registers provide horizontal, i.e. parallel, communication between the PE's in the linear array. The linear array of processing elements provides one PE for each digital sample, e.g. a pixel, thereby allowing a sequence of data samples, e.g. a video line, to be processed in real-time.
Each PE includes a bit-serial arithmetic logic unit, a cache memory and an external memory interface. All communication within a PE is along a one-bit wide bus, i.e. vertical mode, using a single move instruction with variable source and destination addresses. The processing capability of the device is further enhanced by having a serial-parallel multiplier in each PE. For applications requiring more than 1024 PE's, two or more devices can be cascaded together. In another embodiment of the present invention, dual-port memories provide horizontal communication between the PE's in the linear array.
CA002040659A 1990-04-30 1991-04-17 Digital signal processing device Expired - Fee Related CA2040659C (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP19910303836 EP0463721A3 (en) 1990-04-30 1991-04-26 Digital signal processing device
JP3099138A JPH0689271A (en) 1990-04-30 1991-04-30 Digital signal processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9001556A SE466074B (en) 1990-04-30 1990-04-30 Digital signal-processing arrangement with processor elements comprising a single-bit bus
CH9001556-1 1990-04-30

Publications (2)

Publication Number Publication Date
CA2040659A1 true CA2040659A1 (en) 1991-10-31
CA2040659C CA2040659C (en) 1996-05-07

Family

ID=20379345

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002040659A Expired - Fee Related CA2040659C (en) 1990-04-30 1991-04-17 Digital signal processing device

Country Status (2)

Country Link
CA (1) CA2040659C (en)
SE (1) SE466074B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109298886A (en) * 2017-07-25 2019-02-01 合肥君正科技有限公司 SIMD instruction executes method, apparatus and processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE9402551L (en) * 1994-07-22 1995-10-30 Integrated Vision Prod Device for an image processing processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109298886A (en) * 2017-07-25 2019-02-01 合肥君正科技有限公司 SIMD instruction executes method, apparatus and processor

Also Published As

Publication number Publication date
SE9001556D0 (en) 1990-04-30
CA2040659C (en) 1996-05-07
SE9001556L (en) 1991-10-31
SE466074B (en) 1991-12-09

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