CA2011807A1 - Systeme de traitement de bases de donnees a multiprocesseur - Google Patents

Systeme de traitement de bases de donnees a multiprocesseur

Info

Publication number
CA2011807A1
CA2011807A1 CA2011807A CA2011807A CA2011807A1 CA 2011807 A1 CA2011807 A1 CA 2011807A1 CA 2011807 A CA2011807 A CA 2011807A CA 2011807 A CA2011807 A CA 2011807A CA 2011807 A1 CA2011807 A1 CA 2011807A1
Authority
CA
Canada
Prior art keywords
data base
processing operation
processor module
resource
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2011807A
Other languages
English (en)
Other versions
CA2011807C (fr
Inventor
Katsumi Hayashi
Masaaki Mitani
Yutaka Sekine
Tomohiro Hayashi
Kazuhiko Saito
Yoshinori Shimogai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1068814A external-priority patent/JP2825839B2/ja
Priority claimed from JP1068815A external-priority patent/JPH07120305B2/ja
Application filed by Individual filed Critical Individual
Publication of CA2011807A1 publication Critical patent/CA2011807A1/fr
Application granted granted Critical
Publication of CA2011807C publication Critical patent/CA2011807C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/524—Deadlock detection or avoidance
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/912—Applications of a database
    • Y10S707/922—Communications
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99938—Concurrency, e.g. lock management in shared database

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

L'invention est un système de traitement de bases de données utilisant un multiprocesseur. Le système de l'invention comprend : une unité de stockage incorporée à la mémoire mise en commun et utilisé pour stocker les informations de gestion de la base de données qui représentent pour chaque ressource soit un objet d'une opération de traitement commune, soit un objet d'une opération de traitement locale; une unité de gestion d'accès incorporée à chacun des modules de traitement qui sert à contrôler les accès à la base de données demandés dans le cadre de l'opération de traitement commune ou de l'opération de traitement locale selon les informations de gestion de la base de données, l'opération de traitement commune étant effectuée de façon symétrique et l'opération de traitement locale étant effectuée de façon asymétrique dans chaque module de traitement; et une unité de commande incorporée à chaque module de traitement pour contrôler la conversion entre une opération commune et une opération locale de la façon suivante : un état d'accès à la ressource est géré pour chaque ressource; quand une fréquence d'accès est attribuée de façon non uniforme à un module de traitement particulier, la ressource de ce module de traitement est choisie comme objet de l'opération de traitement locale à ce module de traitement particulier; et quand la fréquence d'accès n'est pas attribuée de façon non uniforme à un module de traitement particulier, la ressource de ce module de traitement particulier est choisie comme objet de l'opération de traitement commune. Le système de traitement de base de données de l'invention est également doté d'un système de détection d'interblocages.
CA002011807A 1989-03-20 1990-03-15 Systeme de traitement de bases de donnees a multiprocesseur Expired - Fee Related CA2011807C (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP1-068814 1989-03-20
JP1068814A JP2825839B2 (ja) 1989-03-20 1989-03-20 デッドロック検出処理方式
JP1068815A JPH07120305B2 (ja) 1989-03-20 1989-03-20 マルチプロセッサによるデータベース処理方式
JP1-068815 1989-03-20

Publications (2)

Publication Number Publication Date
CA2011807A1 true CA2011807A1 (fr) 1990-09-20
CA2011807C CA2011807C (fr) 1999-02-23

Family

ID=26410003

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002011807A Expired - Fee Related CA2011807C (fr) 1989-03-20 1990-03-15 Systeme de traitement de bases de donnees a multiprocesseur

Country Status (7)

Country Link
US (1) US5649184A (fr)
EP (1) EP0389242B1 (fr)
KR (1) KR930000853B1 (fr)
AU (1) AU614225B2 (fr)
CA (1) CA2011807C (fr)
DE (1) DE69032337T2 (fr)
ES (1) ES2116267T3 (fr)

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JP3857409B2 (ja) * 1998-03-17 2006-12-13 富士通株式会社 分散処理システム、分散処理方法及び分散処理プログラムを記録したコンピュータ読み取り可能な記録媒体
JP2000047994A (ja) * 1998-07-27 2000-02-18 Fujitsu Ltd 情報処理装置
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US7523157B2 (en) * 2003-09-25 2009-04-21 International Business Machines Corporation Managing a plurality of processors as devices
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US20050071828A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation System and method for compiling source code for multi-processor environments
US7549145B2 (en) * 2003-09-25 2009-06-16 International Business Machines Corporation Processor dedicated code handling in a multi-processor environment
US7496917B2 (en) * 2003-09-25 2009-02-24 International Business Machines Corporation Virtual devices using a pluarlity of processors
US7444632B2 (en) * 2003-09-25 2008-10-28 International Business Machines Corporation Balancing computational load across a plurality of processors
US7389508B2 (en) * 2003-09-25 2008-06-17 International Business Machines Corporation System and method for grouping processors and assigning shared memory space to a group in heterogeneous computer environment
US7516456B2 (en) * 2003-09-25 2009-04-07 International Business Machines Corporation Asymmetric heterogeneous multi-threaded operating system
US7478390B2 (en) * 2003-09-25 2009-01-13 International Business Machines Corporation Task queue management of virtual devices using a plurality of processors
US20050289143A1 (en) * 2004-06-23 2005-12-29 Exanet Ltd. Method for managing lock resources in a distributed storage system
US7735089B2 (en) * 2005-03-08 2010-06-08 Oracle International Corporation Method and system for deadlock detection in a distributed environment
US7616218B1 (en) * 2005-12-05 2009-11-10 Nvidia Corporation Apparatus, system, and method for clipping graphics primitives
JP2007328461A (ja) * 2006-06-06 2007-12-20 Matsushita Electric Ind Co Ltd 非対称マルチプロセッサ
US8543792B1 (en) 2006-09-19 2013-09-24 Nvidia Corporation Memory access techniques including coalesing page table entries
US8352709B1 (en) 2006-09-19 2013-01-08 Nvidia Corporation Direct memory access techniques that include caching segmentation data
US8347064B1 (en) 2006-09-19 2013-01-01 Nvidia Corporation Memory access techniques in an aperture mapped memory space
US8601223B1 (en) 2006-09-19 2013-12-03 Nvidia Corporation Techniques for servicing fetch requests utilizing coalesing page table entries
US8700883B1 (en) 2006-10-24 2014-04-15 Nvidia Corporation Memory access techniques providing for override of a page table
US8707011B1 (en) 2006-10-24 2014-04-22 Nvidia Corporation Memory access techniques utilizing a set-associative translation lookaside buffer
US8607008B1 (en) 2006-11-01 2013-12-10 Nvidia Corporation System and method for independent invalidation on a per engine basis
US8347065B1 (en) 2006-11-01 2013-01-01 Glasco David B System and method for concurrently managing memory access requests
US8706975B1 (en) 2006-11-01 2014-04-22 Nvidia Corporation Memory access management block bind system and method
US8533425B1 (en) 2006-11-01 2013-09-10 Nvidia Corporation Age based miss replay system and method
US8504794B1 (en) 2006-11-01 2013-08-06 Nvidia Corporation Override system and method for memory access management
US8700865B1 (en) 2006-11-02 2014-04-15 Nvidia Corporation Compressed data access system and method
US8543773B2 (en) 2008-08-25 2013-09-24 International Business Machines Corporation Distributed shared memory
US9411661B2 (en) * 2009-04-08 2016-08-09 International Business Machines Corporation Deadlock avoidance
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US9104502B2 (en) 2012-12-15 2015-08-11 International Business Machines Corporation Managing resource pools for deadlock avoidance
US20140189310A1 (en) 2012-12-27 2014-07-03 Nvidia Corporation Fault detection in instruction translations
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
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Also Published As

Publication number Publication date
US5649184A (en) 1997-07-15
EP0389242A2 (fr) 1990-09-26
KR930000853B1 (ko) 1993-02-06
KR900015010A (ko) 1990-10-25
DE69032337T2 (de) 1998-09-24
EP0389242A3 (fr) 1993-06-30
EP0389242B1 (fr) 1998-05-27
AU614225B2 (en) 1991-08-22
ES2116267T3 (es) 1998-07-16
DE69032337D1 (de) 1998-07-02
AU5200190A (en) 1990-09-27
CA2011807C (fr) 1999-02-23

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Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed
MKLA Lapsed

Effective date: 20070315