CA2008553A1 - Arrangement of a semiconductor component suitable for surface mounting and a method for the surface mounting thereof on carrier plates - Google Patents
Arrangement of a semiconductor component suitable for surface mounting and a method for the surface mounting thereof on carrier platesInfo
- Publication number
- CA2008553A1 CA2008553A1 CA002008553A CA2008553A CA2008553A1 CA 2008553 A1 CA2008553 A1 CA 2008553A1 CA 002008553 A CA002008553 A CA 002008553A CA 2008553 A CA2008553 A CA 2008553A CA 2008553 A1 CA2008553 A1 CA 2008553A1
- Authority
- CA
- Canada
- Prior art keywords
- terminal
- tapes
- semiconductor chip
- arrangement
- carrier plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10439—Position of a single component
- H05K2201/10477—Inverted
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10742—Details of leads
- H05K2201/10886—Other details
- H05K2201/10946—Leads attached onto leadless component after manufacturing the component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
- Packaging Frangible Articles (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A semiconductor component is provided in an arrangement suitable for surface mounting on a carrier plate. With the semiconductor arrangement, there is an exclusive holding of the terminal tapes by a semiconductor chip itself so that the previously-standard frame can be eliminated. In addition, the ductile terminal tapes are angled off by 90° relative to a principal face of the semiconductor chip so that a significantly smaller structure and a higher packing density are possible in comparison to previously known and standard TAB versions. For surface mounting of the semiconductor arrangement, the semiconductor chip is put in place on the carrier plate, as a result whereof the ductile terminal tapes deform and a reliable contacting to terminal areas on the carrier plate is guaranteed.
The surface mounting is possible with additional SMD
installations.
A semiconductor component is provided in an arrangement suitable for surface mounting on a carrier plate. With the semiconductor arrangement, there is an exclusive holding of the terminal tapes by a semiconductor chip itself so that the previously-standard frame can be eliminated. In addition, the ductile terminal tapes are angled off by 90° relative to a principal face of the semiconductor chip so that a significantly smaller structure and a higher packing density are possible in comparison to previously known and standard TAB versions. For surface mounting of the semiconductor arrangement, the semiconductor chip is put in place on the carrier plate, as a result whereof the ductile terminal tapes deform and a reliable contacting to terminal areas on the carrier plate is guaranteed.
The surface mounting is possible with additional SMD
installations.
Description
2(~08~iS~
BACKGROUND OF THE INVENTION
Field of the Invention:
The present invention relates to an arrangement of a semiconductor component suitable for surface mounting which is composed of at least one semiconductor chip and a plurality of ductile terminal leads in the form of tapes in communication therewith and initially leading away from a principal face of the semiconductor chip in a planar parallel fashion in a first section, and is also directed to a method for surface mounting of such a semiconductor component on a carrier plate.
Description of the Prior Art Components constructed in what is referred to as a tape automated bonding (TAB) version are well known as (surface mounted device) SMD components and are described, for example, in Siemens Components Vol. 26, No. 3, 1988, pp. 105-109.
FIGS. 1 and 2 herein illustrate such a TAB arrangement.
It is essentially composed of a semiconductor chip 2 and a plurality of ductile terminal tapes 3 in communication therewith and initially having a first section A thereof leading away from a principal face 4 of the semiconductor chip 2 in a planar parallel fashion. The terminal tapes 3 are essentially held by a Kapton frame 5 that contributes to the mechanical stability of the thin terminal tapes 3 that are generally composed of high-purity copper. For equipping carrier plates with this arrangement, an automatically-fetchable adapter sucks the arrangement against the Kapton fxame, whereby it is simultaneously punched from a supply reel and, moreover, the -' .-: '~ . ' . ,: ~ .
2~(~855~
terminal tapes are bent off by about 45 relative to the principal face of the semiconductor chip, as may be clearly seen at the second sections B of the terminal tapes 3 in the sectional view of FIG. 2. When placing the arrangement 1, the Kapton frame is lowered about 0.lmm above the carrier plate. The terminal tapes 3 are thereby constrained to dip into the solder paste previously applied to the terminal areas of the carrier plate and are pressed onto the terminal area of the carrier plate. Irregularities of the terminal areas of the printed circuitboard are compensated by bending the extremely ductile terminal tapes 3. What is therefore achieved is that every terminal tape 3 is, in fact, surrounded by solder paste.
The Kapton frame 5 for holding the terminal tapes 3, generally extend away from the semiconductor chip 2 in a fanned-out manner in order to guarantee a greater contact spacing of the terminal tapes 3 on the terminal areas of the carrier plate, is problematical insofar as it is processed on rollers and a type of undesired bimetal effect arises due to the different materials of copper and Kapton. The Kapton foil can be arched, this leading to the fact that the terminal tapes 3 do not lie in one plane and therefore lead to errors in the contacting of the arrangement. The great space requirement of the arrangement which is unavoidable due to the Kapton frame 5 also opposes a high packing density of this component.
SUMMARY OF THE INVENTION
.
It is therefore the object of the invention to modify the above-discussPd known arrangement such that the Kapton frame ; :0~355;~
is dispensable, a high packing density is guaranteed and a reliable contacting on the carrier plate is possible.
It is a further object of the invention to provide a method for surface mounting of this new arrangement.
The above object is achieved for the arrangement by an apparatus which is characterized in that the terminal tapes are held by the semiconductor chip, that the terminal tapes are bent off by at least approximately an angle of gO~ relative to the principal face of the semiconductor chip so that a second section B of the terminal tapes that is perpendicular to the semiconductor chip comprises a length that is greater than the thickness of the semiconductor chip present perpendicularly relative to the principal face of the semiconductor chip.
The further object of the invention relates to a method for surface mounting of the new arrangement and is particularly characterized by mechanically seizing the arrangements, aligning the terminal tapes relative to the terminal areas of the carrier plate, placing and fixing the arrangement on the carrier plate with at least partial deformation of the ductile terninal tapes and contacting of the terminal tapes to the terminal areas arising as a result thereof, and soldering the terminal tapes to the terminal areas.
According to a feature of an arrangement constructed in accordance with the invention, the ends of the terminal tapes are fashioned pointed in the perpendicular, second section B.
-: . . - - . .
,, -: , . ~: .
; :OG85S~
According to another feature of the invention, the arrangement is characterized in that the terminal tapes are provided with a solderable surface coat at least at their ends in the perpendicular, second B.
According to another feature of the invention, the arrangement is particularly characterized in that the terminal tapes are formed of copper.
According to another feature of the invention, the arrangement is particularly characterized in that the terminal tapes are formed of copper having an iron portion of 1% through 2%.
According to another feature of the invention, the arrangement is particularly characterized in that two immediately adjacent terminal tapes comprise different lengths in their first section leading away from the principal face of the semiconductor chip in a planar parallel fashion.
According to another feature of the invention, the arrangement is particularly characterized in that the terminal tapes comprise rated bend points that are suitable of bending in a privileged fashion when pressure is exerted onto the free ends of the terminal tapes perpendicularly to the principal face of the semiconductor chip.
According to another feature of the invention, the arrangement is particularly characterized in that the first sections of the terminal tapes comprise a small cross section than in the second sections of the terminal tapes.
2~3 [38~;S~
According to another feature of the invention, the arrangement is particularly characterized in that a cover plate that overlaps the principal face and serves for at least partial support of the first sections of the terminal tapes is applied onto the principal face of the semiconductor chip.
According to another feature of the invention, the method is particularly characterized in that the terminal faces are already provided with solder paste before emplacement of the arrangement.
According to another feature of the invention, the method is particularly characterized in that the carrier plate is covered with a foil comprising an opening at the terminal areas and the emplacement and fixing of the arrangement occurs upon utilization of the guide function of these openings for the terminal tapes which is obtainable as a result thereof.
According to another feature of the invention, the method is particularly characterized in that the semiconductor chip is glued onto the carrier plate by employing an electrically-conductive or non-conductive adhesive.
According to another feature of the invention, the method is particularly characterized in that the semiconductor chip is soldered onto the carrier plate.
According to another feature of the invention, the method is particularly characterized in that a spacer mount is applied at least in the center of the terminal areas of the 2~SS3 carrier plate and the emplacement of the arrangement occurs onto the spacer mount.
The significant advantage of the arrangement of the present invention is in the overall dimension of the new arrangement. The critical demand of SMD technology that is made of the SMD components that they should be optimally small, flat, light and processible on standard SMD fabrication systems is taken into account better with this new arrangement. An area reduction of more than 50% compared to previously-known TAB
versions having Kapton frames is possible with this new arrangement. Since TAB arrangements are preferably employed in apparatus wherein a smallest space requirement, lowest weight and lowest overall height are a matter of concern, the previous state of the art is significantly improved with the arrangement of the present invention.
BRIEF DESCRIPTION OF_THE DRAWINGS
Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the following detailed description taken in conjunction with the accompanying drawings, on which:
FIG. 1 is a plan view of a previously-known TAB
arrangement;
FIG. 2 is a sectional view taken substantially along the parting line II--II of FIG. l;
2~35S3 FIG. 3 is a plan view of an arrangement constructed in accordance with the present invention;
FIG. 4 is a sectional view taken substantially along the line IV--IV of FIG. 3;
FIG. 5 is a fragmentary perspective view of a portion of a new arrangement constructed in accordance with the present invention and comprising terminal tapes of different lengths; and FIG. 6 is a fragmentary view of a portion of a new arrangement constructed in accordance with the present invention on a carrier plate which has terminal areas.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 3, a plan view of an arrangement constructed in accordance with the present invention is illustrated which is composed of at least one semiconductor chip 2 and of a multitude of ductile terminal tapes 3 in communication therewith and initially extending away from a principal face 4 of the semiconductor chip 2 in a p].anar parallel fashion in a first section A as is known in the art. In contrast to the known art (see FIGS. 1 and 2), the terminal tapes 3 are held exclusively by the semiconductor chip 2 itself. To that end, the semiconductor chip 2 advantageously contains solid metal humps on its terminal contacts preferably fashioned of aluminum that are normally provided for wire mounting, the terminal tapes 3, what are referred to as the copper spider, being solderable to these solid metal humps. The copper spider is generally photochemically manufactured of copper foils that are about 35 um thick and i 8 ..} .: .
Z~G~SS3 laminated over the entire surface and is simultaneously soldered to the metal humps with a soldering die. The semiconductor chip 2 is completely covered with, for example, a plasma nitrite layer, namely overlapping to a point under the metal humps, so that the aluminum is completely protected against corrosion. As a protection against mechanical damage and as a gripping surface for automatic equipping units, the chip has its upper side covered with, for example, a plate of epoxy. A further mount for the terminal tapes 3 is not provided.
As may be seen from the sectional view of the arrangement of the invention shown in FIG. 4, the terminal tapes 3 are bent off by at least approximately an angle of 90 relative to the principal face 4 of the semiconductor chip 2, so that a second section B of the terminal tapes 3 perpendicular to the semiconductor chip 2 comprise a length that is greater than the thickness d of the semiconductor chip 2. What is achieved by the arrangement of the present invention is that the dimensions of the arrangement are significantly reduced. A greater packing density is the consequence. In comparison to the prior art, the terminal tapes 3 can also be executed shorter overall, as in FIG.
2 and FIG. 4 clearly show. The terminal tapes 3 are formed of high-purity copper in an especially advantageous manner in order to therefore keep the terminal tapes 3 easily deformable. A
reinforcement of the stiffness of the terminal tapes 3 is achieved by adding 1% through 2% iron.
FIG. 5 illustrates a portion, in a perspective view, of a preferred embodiment of the arrangement of the present invention of a semiconductor component 1 constructed in a manner suitable for surface mounting. Two terminal tapes 3 immediately 9 .~,, .
. . ::
21~3S53 adjacent to one another now have different lengths of their first sections Al, A2 extending away from the principal face 4 of the semiconductor chip 2 in a planar parallel fashion. What these different lengths of the terminal tapes 3 achieve in a simple manner is that the terminal areas on the carrier plate onto which the arrangement 1 is to be surface mounted can have a greater spacing from one another and, therefore, a halving of the connection grid of the arrangement 1 i5 possible given the same printed circuitboard technique. It is also possible to fashion the free ends of the terminal tapes pointed, in order to more easily introduce the terminal tapes 3 into the solder paste that is applied on the terminal areas of the carrier plate. In order to achieve a better solderability, the free ends of the terminal tapes 3 are provided with a solderable surface layer 9.
It is proven particularly advantageous to provide rated bend points at the terminal tapes 3 that are suitable for deforming a privileged fashion when pressure is exerted perpendicular to the principal face 4 of the semiconductor chip 2 onto the free ends of the bent sections B of the terminal tapes 3. The reliable contact of the terminal tapes 3 with the terminal areas of the carrier plate can therefore be achieved during placement onto a carrier plate. It has therefore been proven beneficial to select the cross section of the terminal tapes 3 at least partially smaller in the first section, i.e.
sections Al and A2 of FIG. 5, the perpendicular section B
remaining essentially undeformed when pressure is exerted onto the free ends of the terminal tapes 3, whereas the deformation commences at the transition from the larger to the smaller cross section of the terminal tapes 3. This tendency can be promoted in that a cover plate 6 of, preferably, plastic such as, for 2~ 55.3 example, epoxy is placed on the semiconductor chip 2, this overlapping the semiconductor chip 2, namely to such an extent that is just the section B of the shorter terminal tapes 3 that is no longer covered. The cover plate 6 therefore serves at least partially for support and, potentially, for holding the first sections Al, A2 of the terminal tapes 3.
The method of the invention for surface mounting an arrangement constructed in accordance with the invention on a carrier plate which is provided with a plurality of terminal areas is characterized by the following steps:
mechanical seizing of the arrangement, alignment of the terminal tapes relative to the terminal areas of the carrier plate, emplacement and fixing of the arrangement on the carrier plate with at least partial deformation of the ductile terminal tapes and contacting of the terminal tapes to the terminal areas of the carrier plate arising as a result thereof, and soldering of the terminal tapes to the terminal areas.
FIG. 6 illustrates an arrangement 1 which is surface mounted on a carrier plate 7 in accordance with the above method.
The terminal areas of the carrier plate are referenced 8. For the sake of greater clarity, the solder paste that may be potentially applied onto the terminal areas 8 before the 2~3553 emplacement of the arrangement 1 onto the carrier plate 7 is not shown.
The arrangement 1 constructed in accordance with the present invention can be fixed on the carrier plate 7 with the above-mentioned method of the invention either with the solder paste on the terminal areas 8 of the carrier plate 7 or by gluing or soldering the semiconductor chip 2. The gluing can occur with an electrically-conductive adhesive when, for example, a contacting of the semiconductor chip itself is necessary.
The method of the invention has been presented up to now with reference to the fact that the semiconductor chip 2 is placed onto the carrier plate 7 with direct detent, whereby the terminal tapes 3 bend so that a mechanical contact to the terminal area 8 is present in all cases. Given an appropriately long execution of the terminal tapes 3 and particularly of the perpendicular, second sections B thereof, it is also possible to arrange a spacer between the carrier plate 7 and the semiconductor chip 2. When this is the case, the semiconductor chip 2 is put in place with detent against the spacer. The prerequisite is that the terminal tapes 3 can deform at the aforementioned rated bend point.
As presented with reference to FIG. 6, it is also possible to arrange foil 10, for example, a lOO~m thick dry film solder stop mask between the carrier plate 7 and the semiconductor chip 2, the foil 10 comprising openings at the terminal areas 8 of the carrier plate 7 that serve the purpose of guiding the terminal tapes 3 to the terminal areas 8 of the carrier plate 7. To that end, the foil 10 comprises openings 11 .
. . ~
2~ 55~ :
on the terminal areas. The guide function of these openings 11 that can be achieved in this manner can be utilized to fix the terminal tapes 3 on the carrier plate 7 in a simple manner.
Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the invention may become apparent to those skilled in the art without departing from the spirit and scope of the invention. I therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.
BACKGROUND OF THE INVENTION
Field of the Invention:
The present invention relates to an arrangement of a semiconductor component suitable for surface mounting which is composed of at least one semiconductor chip and a plurality of ductile terminal leads in the form of tapes in communication therewith and initially leading away from a principal face of the semiconductor chip in a planar parallel fashion in a first section, and is also directed to a method for surface mounting of such a semiconductor component on a carrier plate.
Description of the Prior Art Components constructed in what is referred to as a tape automated bonding (TAB) version are well known as (surface mounted device) SMD components and are described, for example, in Siemens Components Vol. 26, No. 3, 1988, pp. 105-109.
FIGS. 1 and 2 herein illustrate such a TAB arrangement.
It is essentially composed of a semiconductor chip 2 and a plurality of ductile terminal tapes 3 in communication therewith and initially having a first section A thereof leading away from a principal face 4 of the semiconductor chip 2 in a planar parallel fashion. The terminal tapes 3 are essentially held by a Kapton frame 5 that contributes to the mechanical stability of the thin terminal tapes 3 that are generally composed of high-purity copper. For equipping carrier plates with this arrangement, an automatically-fetchable adapter sucks the arrangement against the Kapton fxame, whereby it is simultaneously punched from a supply reel and, moreover, the -' .-: '~ . ' . ,: ~ .
2~(~855~
terminal tapes are bent off by about 45 relative to the principal face of the semiconductor chip, as may be clearly seen at the second sections B of the terminal tapes 3 in the sectional view of FIG. 2. When placing the arrangement 1, the Kapton frame is lowered about 0.lmm above the carrier plate. The terminal tapes 3 are thereby constrained to dip into the solder paste previously applied to the terminal areas of the carrier plate and are pressed onto the terminal area of the carrier plate. Irregularities of the terminal areas of the printed circuitboard are compensated by bending the extremely ductile terminal tapes 3. What is therefore achieved is that every terminal tape 3 is, in fact, surrounded by solder paste.
The Kapton frame 5 for holding the terminal tapes 3, generally extend away from the semiconductor chip 2 in a fanned-out manner in order to guarantee a greater contact spacing of the terminal tapes 3 on the terminal areas of the carrier plate, is problematical insofar as it is processed on rollers and a type of undesired bimetal effect arises due to the different materials of copper and Kapton. The Kapton foil can be arched, this leading to the fact that the terminal tapes 3 do not lie in one plane and therefore lead to errors in the contacting of the arrangement. The great space requirement of the arrangement which is unavoidable due to the Kapton frame 5 also opposes a high packing density of this component.
SUMMARY OF THE INVENTION
.
It is therefore the object of the invention to modify the above-discussPd known arrangement such that the Kapton frame ; :0~355;~
is dispensable, a high packing density is guaranteed and a reliable contacting on the carrier plate is possible.
It is a further object of the invention to provide a method for surface mounting of this new arrangement.
The above object is achieved for the arrangement by an apparatus which is characterized in that the terminal tapes are held by the semiconductor chip, that the terminal tapes are bent off by at least approximately an angle of gO~ relative to the principal face of the semiconductor chip so that a second section B of the terminal tapes that is perpendicular to the semiconductor chip comprises a length that is greater than the thickness of the semiconductor chip present perpendicularly relative to the principal face of the semiconductor chip.
The further object of the invention relates to a method for surface mounting of the new arrangement and is particularly characterized by mechanically seizing the arrangements, aligning the terminal tapes relative to the terminal areas of the carrier plate, placing and fixing the arrangement on the carrier plate with at least partial deformation of the ductile terninal tapes and contacting of the terminal tapes to the terminal areas arising as a result thereof, and soldering the terminal tapes to the terminal areas.
According to a feature of an arrangement constructed in accordance with the invention, the ends of the terminal tapes are fashioned pointed in the perpendicular, second section B.
-: . . - - . .
,, -: , . ~: .
; :OG85S~
According to another feature of the invention, the arrangement is characterized in that the terminal tapes are provided with a solderable surface coat at least at their ends in the perpendicular, second B.
According to another feature of the invention, the arrangement is particularly characterized in that the terminal tapes are formed of copper.
According to another feature of the invention, the arrangement is particularly characterized in that the terminal tapes are formed of copper having an iron portion of 1% through 2%.
According to another feature of the invention, the arrangement is particularly characterized in that two immediately adjacent terminal tapes comprise different lengths in their first section leading away from the principal face of the semiconductor chip in a planar parallel fashion.
According to another feature of the invention, the arrangement is particularly characterized in that the terminal tapes comprise rated bend points that are suitable of bending in a privileged fashion when pressure is exerted onto the free ends of the terminal tapes perpendicularly to the principal face of the semiconductor chip.
According to another feature of the invention, the arrangement is particularly characterized in that the first sections of the terminal tapes comprise a small cross section than in the second sections of the terminal tapes.
2~3 [38~;S~
According to another feature of the invention, the arrangement is particularly characterized in that a cover plate that overlaps the principal face and serves for at least partial support of the first sections of the terminal tapes is applied onto the principal face of the semiconductor chip.
According to another feature of the invention, the method is particularly characterized in that the terminal faces are already provided with solder paste before emplacement of the arrangement.
According to another feature of the invention, the method is particularly characterized in that the carrier plate is covered with a foil comprising an opening at the terminal areas and the emplacement and fixing of the arrangement occurs upon utilization of the guide function of these openings for the terminal tapes which is obtainable as a result thereof.
According to another feature of the invention, the method is particularly characterized in that the semiconductor chip is glued onto the carrier plate by employing an electrically-conductive or non-conductive adhesive.
According to another feature of the invention, the method is particularly characterized in that the semiconductor chip is soldered onto the carrier plate.
According to another feature of the invention, the method is particularly characterized in that a spacer mount is applied at least in the center of the terminal areas of the 2~SS3 carrier plate and the emplacement of the arrangement occurs onto the spacer mount.
The significant advantage of the arrangement of the present invention is in the overall dimension of the new arrangement. The critical demand of SMD technology that is made of the SMD components that they should be optimally small, flat, light and processible on standard SMD fabrication systems is taken into account better with this new arrangement. An area reduction of more than 50% compared to previously-known TAB
versions having Kapton frames is possible with this new arrangement. Since TAB arrangements are preferably employed in apparatus wherein a smallest space requirement, lowest weight and lowest overall height are a matter of concern, the previous state of the art is significantly improved with the arrangement of the present invention.
BRIEF DESCRIPTION OF_THE DRAWINGS
Other objects, features and advantages of the invention, its organization, construction and operation will be best understood from the following detailed description taken in conjunction with the accompanying drawings, on which:
FIG. 1 is a plan view of a previously-known TAB
arrangement;
FIG. 2 is a sectional view taken substantially along the parting line II--II of FIG. l;
2~35S3 FIG. 3 is a plan view of an arrangement constructed in accordance with the present invention;
FIG. 4 is a sectional view taken substantially along the line IV--IV of FIG. 3;
FIG. 5 is a fragmentary perspective view of a portion of a new arrangement constructed in accordance with the present invention and comprising terminal tapes of different lengths; and FIG. 6 is a fragmentary view of a portion of a new arrangement constructed in accordance with the present invention on a carrier plate which has terminal areas.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 3, a plan view of an arrangement constructed in accordance with the present invention is illustrated which is composed of at least one semiconductor chip 2 and of a multitude of ductile terminal tapes 3 in communication therewith and initially extending away from a principal face 4 of the semiconductor chip 2 in a p].anar parallel fashion in a first section A as is known in the art. In contrast to the known art (see FIGS. 1 and 2), the terminal tapes 3 are held exclusively by the semiconductor chip 2 itself. To that end, the semiconductor chip 2 advantageously contains solid metal humps on its terminal contacts preferably fashioned of aluminum that are normally provided for wire mounting, the terminal tapes 3, what are referred to as the copper spider, being solderable to these solid metal humps. The copper spider is generally photochemically manufactured of copper foils that are about 35 um thick and i 8 ..} .: .
Z~G~SS3 laminated over the entire surface and is simultaneously soldered to the metal humps with a soldering die. The semiconductor chip 2 is completely covered with, for example, a plasma nitrite layer, namely overlapping to a point under the metal humps, so that the aluminum is completely protected against corrosion. As a protection against mechanical damage and as a gripping surface for automatic equipping units, the chip has its upper side covered with, for example, a plate of epoxy. A further mount for the terminal tapes 3 is not provided.
As may be seen from the sectional view of the arrangement of the invention shown in FIG. 4, the terminal tapes 3 are bent off by at least approximately an angle of 90 relative to the principal face 4 of the semiconductor chip 2, so that a second section B of the terminal tapes 3 perpendicular to the semiconductor chip 2 comprise a length that is greater than the thickness d of the semiconductor chip 2. What is achieved by the arrangement of the present invention is that the dimensions of the arrangement are significantly reduced. A greater packing density is the consequence. In comparison to the prior art, the terminal tapes 3 can also be executed shorter overall, as in FIG.
2 and FIG. 4 clearly show. The terminal tapes 3 are formed of high-purity copper in an especially advantageous manner in order to therefore keep the terminal tapes 3 easily deformable. A
reinforcement of the stiffness of the terminal tapes 3 is achieved by adding 1% through 2% iron.
FIG. 5 illustrates a portion, in a perspective view, of a preferred embodiment of the arrangement of the present invention of a semiconductor component 1 constructed in a manner suitable for surface mounting. Two terminal tapes 3 immediately 9 .~,, .
. . ::
21~3S53 adjacent to one another now have different lengths of their first sections Al, A2 extending away from the principal face 4 of the semiconductor chip 2 in a planar parallel fashion. What these different lengths of the terminal tapes 3 achieve in a simple manner is that the terminal areas on the carrier plate onto which the arrangement 1 is to be surface mounted can have a greater spacing from one another and, therefore, a halving of the connection grid of the arrangement 1 i5 possible given the same printed circuitboard technique. It is also possible to fashion the free ends of the terminal tapes pointed, in order to more easily introduce the terminal tapes 3 into the solder paste that is applied on the terminal areas of the carrier plate. In order to achieve a better solderability, the free ends of the terminal tapes 3 are provided with a solderable surface layer 9.
It is proven particularly advantageous to provide rated bend points at the terminal tapes 3 that are suitable for deforming a privileged fashion when pressure is exerted perpendicular to the principal face 4 of the semiconductor chip 2 onto the free ends of the bent sections B of the terminal tapes 3. The reliable contact of the terminal tapes 3 with the terminal areas of the carrier plate can therefore be achieved during placement onto a carrier plate. It has therefore been proven beneficial to select the cross section of the terminal tapes 3 at least partially smaller in the first section, i.e.
sections Al and A2 of FIG. 5, the perpendicular section B
remaining essentially undeformed when pressure is exerted onto the free ends of the terminal tapes 3, whereas the deformation commences at the transition from the larger to the smaller cross section of the terminal tapes 3. This tendency can be promoted in that a cover plate 6 of, preferably, plastic such as, for 2~ 55.3 example, epoxy is placed on the semiconductor chip 2, this overlapping the semiconductor chip 2, namely to such an extent that is just the section B of the shorter terminal tapes 3 that is no longer covered. The cover plate 6 therefore serves at least partially for support and, potentially, for holding the first sections Al, A2 of the terminal tapes 3.
The method of the invention for surface mounting an arrangement constructed in accordance with the invention on a carrier plate which is provided with a plurality of terminal areas is characterized by the following steps:
mechanical seizing of the arrangement, alignment of the terminal tapes relative to the terminal areas of the carrier plate, emplacement and fixing of the arrangement on the carrier plate with at least partial deformation of the ductile terminal tapes and contacting of the terminal tapes to the terminal areas of the carrier plate arising as a result thereof, and soldering of the terminal tapes to the terminal areas.
FIG. 6 illustrates an arrangement 1 which is surface mounted on a carrier plate 7 in accordance with the above method.
The terminal areas of the carrier plate are referenced 8. For the sake of greater clarity, the solder paste that may be potentially applied onto the terminal areas 8 before the 2~3553 emplacement of the arrangement 1 onto the carrier plate 7 is not shown.
The arrangement 1 constructed in accordance with the present invention can be fixed on the carrier plate 7 with the above-mentioned method of the invention either with the solder paste on the terminal areas 8 of the carrier plate 7 or by gluing or soldering the semiconductor chip 2. The gluing can occur with an electrically-conductive adhesive when, for example, a contacting of the semiconductor chip itself is necessary.
The method of the invention has been presented up to now with reference to the fact that the semiconductor chip 2 is placed onto the carrier plate 7 with direct detent, whereby the terminal tapes 3 bend so that a mechanical contact to the terminal area 8 is present in all cases. Given an appropriately long execution of the terminal tapes 3 and particularly of the perpendicular, second sections B thereof, it is also possible to arrange a spacer between the carrier plate 7 and the semiconductor chip 2. When this is the case, the semiconductor chip 2 is put in place with detent against the spacer. The prerequisite is that the terminal tapes 3 can deform at the aforementioned rated bend point.
As presented with reference to FIG. 6, it is also possible to arrange foil 10, for example, a lOO~m thick dry film solder stop mask between the carrier plate 7 and the semiconductor chip 2, the foil 10 comprising openings at the terminal areas 8 of the carrier plate 7 that serve the purpose of guiding the terminal tapes 3 to the terminal areas 8 of the carrier plate 7. To that end, the foil 10 comprises openings 11 .
. . ~
2~ 55~ :
on the terminal areas. The guide function of these openings 11 that can be achieved in this manner can be utilized to fix the terminal tapes 3 on the carrier plate 7 in a simple manner.
Although I have described my invention by reference to particular illustrative embodiments thereof, many changes and modifications of the invention may become apparent to those skilled in the art without departing from the spirit and scope of the invention. I therefore intend to include within the patent warranted hereon all such changes and modifications as may reasonably and properly be included within the scope of my contribution to the art.
Claims (17)
1. A semiconductor arrangement comprising:
a semiconductor chip including a principal face, a thickness perpendicular to said principal face, and a peripheral edge; and a plurality of ductile terminal tapes each connected in communication with said semiconductor chip and each including a first section extending in a planar parallel fashion away from said principal face and beyond said peripheral edge, and a second section bent to extend at an angle of approximately 90° relative to said principal face, said second section comprising a length that is greater than said thickness of said semiconductor chip.
a semiconductor chip including a principal face, a thickness perpendicular to said principal face, and a peripheral edge; and a plurality of ductile terminal tapes each connected in communication with said semiconductor chip and each including a first section extending in a planar parallel fashion away from said principal face and beyond said peripheral edge, and a second section bent to extend at an angle of approximately 90° relative to said principal face, said second section comprising a length that is greater than said thickness of said semiconductor chip.
2. The semiconductor arrangement of claim 1, wherein:
each of said second sections of said terminal tapes comprises a pointed distal end.
each of said second sections of said terminal tapes comprises a pointed distal end.
3. The semiconductor arrangement of claim 1, wherein:
each of said second sections of said ductile terminal tapes comprises a distal end; and a solderable surface coat is provided on at least said distal ends.
each of said second sections of said ductile terminal tapes comprises a distal end; and a solderable surface coat is provided on at least said distal ends.
4. The semiconductor arrangement of claim 1, wherein:
each of said terminal tapes comprises copper.
each of said terminal tapes comprises copper.
5. The semiconductor arrangement of claim 1, wherein:
each of said terminal tapes comprises copper and an iron portion of 1% through 2%.
each of said terminal tapes comprises copper and an iron portion of 1% through 2%.
6. The semiconductor arrangement of claim 1, wherein:
two immediately-adjacent terminal tapes comprise first sections of different lengths.
two immediately-adjacent terminal tapes comprise first sections of different lengths.
7. The semiconductor arrangement of claim 1, wherein:
each of said terminal tapes comprises a rated bend point suitable of bending in a privileged fashion when pressure is exerted onto the free end thereof perpendicularly to said principal face of said semiconductor chip.
each of said terminal tapes comprises a rated bend point suitable of bending in a privileged fashion when pressure is exerted onto the free end thereof perpendicularly to said principal face of said semiconductor chip.
8. The semiconductor arrangement of claim 1, wherein:
said first sections of said terminal tapes each comprise a cross section which is smaller than the cross section of the respective second section.
said first sections of said terminal tapes each comprise a cross section which is smaller than the cross section of the respective second section.
9. The semiconductor arrangement of claim 1, and further comprising:
a cover plate overlapping said principal face and serving for at least partial support of said first sections of said terminal tapes.
a cover plate overlapping said principal face and serving for at least partial support of said first sections of said terminal tapes.
10. A method for surface mounting a semiconductor arrangement which comprises a semiconductor chip including a principal face, a thickness perpendicular to the principal face and a peripheral edge, and a plurality of ductile terminal tapes each connected in communication with the semiconductor chip and each including a first section extending in a planar parallel fashion away from the principal face and beyond the peripheral edge of the semiconductor chip and a second section bent to extend at an angle of approximately 90° relative to the principal face and comprising a length that is greater than the thickness of the semiconductor chip, onto a carrier plate which is provided with terminal areas, comprising the steps of:
mechanically seizing the semiconductor arrangement;
aligning the terminal tapes of the semiconductor arrangement relative to the terminal areas of the carrier plate;
emplacing and fixing the semiconductor arrangement on the carrier plate with at least partial deformation of the ductile terminal tapes and contacting of the terminal tapes to the terminal areas; and soldering the terminal tapes to the terminal areas.
mechanically seizing the semiconductor arrangement;
aligning the terminal tapes of the semiconductor arrangement relative to the terminal areas of the carrier plate;
emplacing and fixing the semiconductor arrangement on the carrier plate with at least partial deformation of the ductile terminal tapes and contacting of the terminal tapes to the terminal areas; and soldering the terminal tapes to the terminal areas.
11. The method of claim 10, and further comprising the step of:
applying solder paste to the terminal tapes before emplacement of the arrangement.
applying solder paste to the terminal tapes before emplacement of the arrangement.
12. The method of claim 10, and further comprising the step of:
covering the carrier plate with a foil which comprises an opening at each of the terminal areas and emplacing and fixing the semiconductor arrangement by utilizing the openings as guides for the terminal tapes.
covering the carrier plate with a foil which comprises an opening at each of the terminal areas and emplacing and fixing the semiconductor arrangement by utilizing the openings as guides for the terminal tapes.
13. The method of claim 10, wherein the step of fixing is further defined as:
gluing the semiconductor chip to the carrier plate with an adhesive.
gluing the semiconductor chip to the carrier plate with an adhesive.
14. The method of claim 10, wherein the step of fixing is further defined as:
gluing the semiconductor chip to the carrier plate with a non-conductive adhesive.
gluing the semiconductor chip to the carrier plate with a non-conductive adhesive.
15. The method of claim 10, wherein the step of fixing is further defined as:
gluing the semiconductor chip to the carrier plate with an electrically-conductive adhesive.
gluing the semiconductor chip to the carrier plate with an electrically-conductive adhesive.
16. The method of claim 10, wherein the step of fixing is further defined as:
soldering the semiconductor chip onto the carrier plate.
soldering the semiconductor chip onto the carrier plate.
17. The method of claim 10, and further comprising the step of:
applying a spacer mount at least in the center of the terminal areas of the carrier plate, and wherein the step of emplacement is further defined as emplacing the semiconductor arrangement onto the spacer.
applying a spacer mount at least in the center of the terminal areas of the carrier plate, and wherein the step of emplacement is further defined as emplacing the semiconductor arrangement onto the spacer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP89101433A EP0379624A1 (en) | 1989-01-27 | 1989-01-27 | Arrangement of a semiconductor component suited for surface mounting and process for mounting it on a circuit board |
| EP89101433.4 | 1989-01-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2008553A1 true CA2008553A1 (en) | 1990-07-27 |
Family
ID=8200911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002008553A Abandoned CA2008553A1 (en) | 1989-01-27 | 1990-01-25 | Arrangement of a semiconductor component suitable for surface mounting and a method for the surface mounting thereof on carrier plates |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0379624A1 (en) |
| JP (1) | JPH02238654A (en) |
| CA (1) | CA2008553A1 (en) |
| FI (1) | FI900434A0 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987167B2 (en) | 2009-09-30 | 2015-03-24 | Basf Se | Low volatile amine salts of anionic pesticides |
| US10980237B2 (en) | 2010-11-05 | 2021-04-20 | Basf Se | Compositions containing identical polyamine salts of mixed anionic pesticides |
| US11109591B2 (en) | 2017-04-24 | 2021-09-07 | Taminco Bvba | Single phase liquids of alkanolamine salts of dicamba |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7292450B2 (en) | 2006-01-31 | 2007-11-06 | Microsoft Corporation | High density surface mount part array layout and assembly technique |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3123198C2 (en) * | 1980-12-08 | 1993-10-07 | Gao Ges Automation Org | Carrier elements for an IC chip |
| GB2103418B (en) * | 1981-06-18 | 1986-10-08 | Stanley Bracey | Packaging of electronics components |
| EP0077276A3 (en) * | 1981-10-13 | 1986-03-26 | FAIRCHILD CAMERA & INSTRUMENT CORPORATION | Method for fabricating a hybrid circuit module |
-
1989
- 1989-01-27 EP EP89101433A patent/EP0379624A1/en not_active Withdrawn
-
1990
- 1990-01-25 JP JP2017661A patent/JPH02238654A/en active Pending
- 1990-01-25 CA CA002008553A patent/CA2008553A1/en not_active Abandoned
- 1990-01-26 FI FI900434A patent/FI900434A0/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987167B2 (en) | 2009-09-30 | 2015-03-24 | Basf Se | Low volatile amine salts of anionic pesticides |
| US10980237B2 (en) | 2010-11-05 | 2021-04-20 | Basf Se | Compositions containing identical polyamine salts of mixed anionic pesticides |
| US11109591B2 (en) | 2017-04-24 | 2021-09-07 | Taminco Bvba | Single phase liquids of alkanolamine salts of dicamba |
Also Published As
| Publication number | Publication date |
|---|---|
| FI900434A0 (en) | 1990-01-26 |
| JPH02238654A (en) | 1990-09-20 |
| EP0379624A1 (en) | 1990-08-01 |
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