CA1331039C - Switch-mode power supply - Google Patents

Abstract

ABSTRACT
An input supply voltage is coupled via a primary winding of a flyback transformer to a collector of a chopper transistor switch that operates at a given frequency. During a portion of each period when the chopper transistor switch is conductive, a second switch applies a short-circuit across a secondary winding of the transformer at a controllable instant that causes the emitter current of the chopper transistor switch to increase at a significantly higher rate. When the emitter current exceeds a predetermined threshold level, a one-shot arrangement is triggered. Consequently, a pulse is produced that turns off the chopper transistor switch and that maintains it nonconductive for the duration of the pulse. A flyback pulse produced in a winding of the transformer is rectified to produce a DC output supply voltage. The length of the interval when the chopper transistor switch is conductive is controlled by the second switch in accordance with the level of the output supply voltage in a negative feedback manner for regulating the output supply voltage.

Description

~ -1- 1331039 RcA 85,014A
. ;- .
A SWITCH-MODE POWER SUPPLY

This is a division of Canadian Application Serial No. s89,938, filed February 2, 1989.
The invention relates to switched-mode power supplies.
Some television receivers have signal terminals for receivinq, for e~ample, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR
or a teletext decoder.
To simplify the coupling of signals between the external devices and the television receiver, the common ~-15 conductors of the recciver and of the external devices are `-connected together so that all are at the same potential.
The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corre~ponding AC
mains supply source that energize~ the device. When the common conductor is held floating, a u~er touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.
Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the te D inals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as "cold" ground conductor.
In a typical switched mode power supply ~SMPS) of a television receiver, for ex~ple, the AC mains supply 3s voltage is coupled directly to a bridge rectifier for producing an unregulated direct current (DC) input supply voltage that is, for example, referenced to a common conductor, referred to as "hot~ ground, and that is ..--2- 1331~39 RCA 85,014A

conductively isolated from the cold ground conductor. A
pulse width modulator eontrols the duty cycle of a chopper transistor switch that applies the unregulated supply - -voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a freguency that is determined by the modulator is developed at a seeondary winding of the transformer and is reetified to produce a DC
output supply voltage sueh as a voltage B+ that energizes a horizontal deflection cireuit of the television receiver.
The primary winding of the flybaek transformer is, for example, conductively eoupled to the hot qround conductor.
The seeondary winding of the flybaek transformer and voltage B+ may be eonduetively isolated from the hot ground conductor by the hot-eold barrier fo # d by the transformer.
In some prior art eireuits, voltage B+ is sensed by sensing a voltage developed at a separate winding of the - -flyback transformer. Disadvantageously, sueh sensed -- -voltage may not traek variation of voltage B+ sufficiently. ~ -In order to provide better regulation of voltage B+, it may be desirable to sense voltage B+ direetly at a terminal ~-where it is produeed.
In a SMPS e bodying an aspeet of the invention, a --~
feedback timing eontrol signal is produeed in aeeordanee 25 with the level of voltage B+, that are both referenced to -the eold ground eonduetor. The tiaing eontrol signal is applied to the ehopper tran~istor switeh that is - -~
eonduetively eoupled to the hot ground eonduetor to `, ; - -efeetuate pulse width modulation of the conduction duty cycle of the chopper transistor switeh.
It may be desirable to apply sueh timing control signal without ucing an additional isolation transfor~er.
A switeh ~ode power supply e bodying another ;-~;
aspeet of the invention includes a souree of an input- ;
supply voltage and a transformer having first and second windings. A eontrollable switeh ha~ a main eurrent condueting te Dinal that is eoupled to the first winding :
and to the source of the input supply voltage. The .... ....
, . ......
' " '~

~,- ",."~,., -,.,,~,.~,:,.~ss':'',~

-~ 3 13 310 3 9 .
controllable switch is switched by a periodic first control signal for generating a first switching current in the first winding that stores magnetic energy in the transformer. The first switching current is used for 5 producing an output supply voltaqe that is coupled to a ~-load. A current sampling first impedance is coupled in a current path that includes the first winding for conducting at least a portion of the first switching current in the first impedance. A current sa pling ~ignal is developed in the first impedance that is indicative of a level of the first switching current when the switching tran~istor is conductive. The first control signal switches the controllable switch into nonconduction when the first switching current e~ceeds a predeter~ined level in accordance with the current ~anpling ~ignal. A low impedance is applied to the second winding after a first conduction interval of the controllable ~witch has elap~ed, to cause the first switching current to e~ceed the predeter~ined level. The fir~t conduction interval is varied in accordance with the output supply voltage such that a duty cycle of the controllable ~witch varies in a negative feedbac~ anner for regulating the output supply voltage. -The fir~t switching current ay be coupled via a third winding of the transfon~er to produce the output supply voltage fron the current in the third winding. The first winding ay be electrically nonisolated fro~ the -~
input ~upply voltage with re~pect to electrical ~hock hazard; whereas the second and third windings ~ay be electrically isolated fro~ the input supply voltage.
, Advantageously, the transfor~er provides the afore entioned required electrical isolation for coupling the first -~
switching current via the third winding across an isolation barrier in one direction and for coupling control -infornation via the second winding across the isolation barrier in the oppo~ite direction.
In the Drawing~

1 ~3~ ~3~RCA 85,014A

FIGURES la and lb illustrate a power supply embodying an a6pect of the invention;
FIGURES 2a-2m illustrate waveforms useful for e~plaining the normal operation of the circuit of FIGURE 1;
FIGURES 3a and 3b illustrate an isolation transformer used in the circuit of FIGURE l;
FIGURES 4a-4h illustrate waveform w eful for explaining a tran6ition from normal to standby operation of the power supply of FIGURE l;
lo FIGURES Sa-Sh illustrate wa~eforms useful for explaining a transition from standby to normal operation of ~ -the power supply of FIGURE l;
FIGURE 6 illu~trates waveforms of the circuit of FIGURE 1 during an overload condition;
FIGURE 7 illustrates a transient wa~eform useful for explaining the operation of the circuit of FIGURE 1 ;
during start-up;
FIGURES 8a-8c illustrate waveforms of the circuit - ~-of FIGURE 1, that incorporates a ~odification, under an 20 overload condition; and `
FIGURE 9a-9e illu~trate wavefor~D of the circuit of FIGURE 1, that incorporates a ~odification, during start-up.
FIGURE 1 illuetrates a switched-~ode power supply 25 (SMPS), ~hodying an aspect of the invention. The SMPS
produces an output supply voltage B+ at +145 volts that is t used for energizing, for e~a ple, a deflection circuit of a televi~ion receiver, not shown, and an output supply ~ - ; --voltage V+ at +24 volt~ that are both regulated. A mains - - ~-supply voltage VAc is rectified in a bridge rectifier 100 to produce an unregulated voltage VuR. A pri~asy winding -~ -Wl of a flyback transformer T is coupled between a ter~inal lOOa, where voltage VuR is developed, and a collector electrode of a power switching transistor Ql. Tran~former T is constructed in the manner shown in FIGURES 3a and 3b.
Sinilar symbols and nu erals in FIGURES 1 and 3a and 3b indicate ~i~ilar ite~ or functions.
' ~

: . .
: ', ~-.

1331039 RCA 85,014A

The emitter of transistor Ql of FIGURE 1 is coupled to a common conductor, referred to herein as "hot"
ground, via an emitter current sampling resistor Rs for developing a voltage Vi6ense across re~istor Rs that is proportional to a collector current ic of transistor Ql.
The base of transistor Q1 iEi coupled via a coupling capacitor 102 to a terminal 104 where a switching signal Vc2 is produced. signal Vc2 produce~ a switching operation in tran~iistor Ql. Terminal 104 i8 coupled via a resistor 103 to a terminal W2a of a secondary winding W2 of transfonmer T.
FIGURES 2a-2m illu~itrate waveforms useful for e~plaining the normal steady state operation of the SMPS of FI~URE 1. Similar 6y bol~ and nu~erals in FIGURES la and lb, and 2a-2m indicate similar ite~fii or functions.
During, for e~ample, interval to-t2 of FIGURE 2a -of a corresponding cycle, a voltage Vw2 of FIGURE 2d developed in winding W2 of FIGURE 1 i6i po~iitive relative to the hot ground and produces a current iB in the direction of the arrow that flow~ in the base of tran~ tor Q1.
Current iB develop~i a voltage VCl02 in capacitor 102 in the polarity shown. Current iB f FIGURE 2c provide~i the base current that aaintain6 tran~iistor Q1 of FIGURE 1 conductive during interval to-t2 of FIGURE 2a. Conseguently, collector current ic of FIGURE 1 i~i upra~ping, a6 shown in FIGURE 2b during interval to-t2, that cause6 an inductive energy to be 6tored in tran6former T of FIGURE 1. As de w ribed later on, at time t2 of FIGURE 2a, tran~ tor Ql of FIGURE 1 becoaes nonconductive.
After transistor Ql become~ nonconductive, the -;
inductive energy stored in winding Wl i6 tran~ferred by a tran6fonaer, or flyback action to a secondary winding W4 of tran6for er T. Corre~ponding flyback pulses devcloped in corresponding terminali6 108 and 109 of winding W4 are rectified by diodei6 106 and 107, respectively, and filtered in capacitor6 121 and 122, re6pectively, for producing DC
volt~ge6 B+ and V+, re~pectively, that are referenced to a - -~econd common conductor, referred to herein as "cold" ~ -~

. ~

1~ 31~ 3 9 RCA 85, 014A ~ ;
ground. The cold ground is conductively isolated from the hot ground.
Terminal 109 is coupled through a voltage divider formed by resistors 110 and 111 to an inverting input terminal 113 of a comparator U2b. When transistor Ql of FIGURE la is conductive, the voltage at terminal 109 - -produced by the tran~former action is negative, causing a -, protection diode 112 that i~ coupled to terminal 113 to conduct and to clamp a signal VH developed at terminal 113 ;--to the forward voltage of diode 112, which is a negative value, during interval to-t2 of FIGURE 2m.
Three re~istor~, R10, Rll and R12 of FIGURE lb, that are coupled in 6erie~ between a terminal 150 where ~ -voltage B~ is developed and an output terminal 114 of 15 comparator U2b, cause a capacitor C10, coupled between ~ ; :
terminal 114 and ~he cold ground, to charge. Con~equently, ~ -when signal V~ is negative, an upraaping por~ion of a sawtooth signal Vs is produced at a terminal 115 between -~
resistors R10 and Rll and has a waveform that is shown in 20 FIGURE 21, during interval to-t2, for exa~ple. Prior to ~ -interval to-t2, capacitor C10 of FIGURE lb i8 completely -~- ;
discharged, re~ulting in a flat portion of ~ignal Vs FIGURE 21 at a level that is ~aller than +12V. The level of the flat portion i~ deten ined by the ratio between the ~ -25 sum of the values of resistors Rll and R12 and the value of -re~i~tor R10.
Sawtooth signal Vs i~ coupled to a noninverting input terainal of a co~parator U2a. A level of ~12 volts ~-is coupled to an inverting input terminal of coaparator - -U2a. An output terminal 116 of comparator U2a, where a pulse ~ignal VB3 of FIGURE 2k is developed, is coupled to a ba~e electrode of a switching tran~i~tor Q3. The collector of tran~istor Q3 i~ eoupled via a protection diode D3 and a current limiting inductor L3 to a ~econda n winding W3 of ;
tran~fonmer T. Transistor Q3 become6 conductive at an instant that oeeur~ during a portion of the eonduction int r~al oE tranJi~tor Ql art r a~teotb ignAl V~ beco eb ' ;"~.
, :'' .

larger than the ~12 volt level, such as, for example, during interval tl-t2 of FIGURE 2k. .
When conductive, transistor Q3 forms, with diode D3 and induetor L3, a series arrangement that is coupled across winding W3 and that operates substantially as a low impedance across winding W3. Inductor L3 limits the peak amplitude of a short cireuit eurrent iS of FIGURE 2j. The resulting low impedance is reflected by the transformer action as a low impedance across winding Wq of FIGURE 1.
The re~ult is that collector eurrent ic f transistor Q1 increases during interval tl-t2 of FIGURE 2b at a substantially faster rate than during interval to-tl.
Consequently, voltage Vsen8e of FIGURE la that is proportional to eurrent ic beeo es equal, shortly after time tl of FIGUR~ 2b, to a referenee voltage VRl of FIGURE
1 developed acros~ a zener diode Z2.7.
Voltage~ Vsense and VRl are eoupled to and compared in a eomparator Ula having an output transistor switeh, not shown, that is eoupled through an output terminal 105 aeross a eapaeitor C2. When, at time t2 of FIGURE 2b, voltage V~en8e beeo e~ egual to voltage VRl, -capaeitor C2 of FIGURE la is i~ ediately diseharged and a sawtooth signal Vin, developed in eapaeitor C2, beeomes zero, as ~hown in FIGURE 2f. During the re ainder of eaeh eyele, sueh as during interval t2-t6, sawtooth signal Vin is upra~ping at a rate deter~ined by a reei~tor R2 of FIGURE la and by eapaeitor C2. Signal Vin i~ eoupled to an inverting input tenainal of a eo parator Ulb. A referenee level VR2, developed aeross a zener diode Z5.1, is coupled to a noninverting input terminal of eomparator Ulb.
When, at time t2 of FIGURE 2f, signal Vin beeomes zero, an output signal VOUt of FIGURE 2g, developed at an output ter~inal of eo~parator Ulb nd eoupled to the base -~
of switehing tran~istor ~2 turn~ on traneistor Q2. When, at ti~e t2 of FIGURE 2e, transistor Q2 of FIGURE la ie turned-on, tran~istor Q2, eouples ten inal 104 of eapaeitor 102 to the hot ground. The other ter~inal of eapaeitor 102 that is eoupled to the base of transistor Ql i~ at a level RCA 85,014A
-8- 1 3 3 1 a 3 9 that is negative relative to that at terminal 104. ; ' Therefore, the base cbarge in transistor Ql that maintains transistor Ql conductive prior to time t2 of FIGURE 2a is ~
rapidly swept out, causing transistor Ql of FIGURE la to -5 become immediately nonconductive. -Signal VOUt that is controlled by sawtooth signal Vin maintains transistor Q2 conductive and transistor Ql nonconductive during interval t2-t4 of FIGURE 2g. Signal -VOUt changes state to attain a level of zero volts at time - -10 t4 when upramping signal Vin of FIGURE 2f becomes larger -than level VR2, thus a one-shot operation is obtained.
Transi~tor Q2 i~ maintained conduetive and transistor Ql is maintained nonconductive during, for e~ample, interval t2 t4 of FIGURE 2a having a length that is the same in each cycle.
During a portion of, for e~ample, interval t2-t4, the corresponding positive flybac~ pulses at terminals 108 and 109 of secondary winding W4 produce eurrent that maintain diode~ 106 and 107 eonduetive and cause filter capacitors 121 and 122, respectively, to eharge. The -charge stored in capaeitor 121, for e~ample, replenishes a charge removed by a load eurrent iL that flow6 through, for e~a~ple, terminal 150, and is proportional to the length of interval to-t2 of FIGURE 2a when tran~i~tor Ql of FIGURE la - -wa~ ~aintained eonduetive. The length of interval to-t2 of FIGURE 2a is, in turn, eontrolled by signal VB3. Thus, voltage B+, for e~a ple, is regulated by signal VB3 that eontrols the duty eyele of transistor Ql.
A po~itive voltage at terd nal 109 of FIGURE lb 30 that oecurs during the nonconduction interval of transistor - ; -Ql causes sign~l VH at terminal 113 of comparator U2b to be positive, as shown during interval 4 -t4 of FIGNRE 2m. The re~ult i~ that capacitor C10 of FIGURE lb is i~ediately discharged and sawtooth signal V~ is ~aintained at the constant level that i~ lower than ~12 volt~ during, for e~a~ple, interval t2-t4 of FIGURE 21, in preparation for the followinq interval t4-t6 of FIGURE 2a when tran~istor Ql of FIGURE la again beeo~e~ eonduetive.
., . . - .
.

13 ~10 3 9 Diode 106, for example, that is used for producing voltage B+, remains conductive until a time t23 of FIGURE 2a. During interval t2-t23, transistor Q1 collector voltage Vcl is at a constant positive level of +600V that is determined by voltage VuR, by voltage B+ of FIGURE lb and by the turns ratio of transformer T.
During interval t23-t4 of FIGURE 2a, voltage V
varies in a resonant manner due to the operation of an arrangement 120 of FIGURE 1 forming a resonant circuit with the inductance of winding Wl. Arrangement 120 includes a capacitor 119 of FIGURE la that is coupled in series with a parallel arrange ent of a damping resi~tor 117 and a diode 118 to form arrange~ent 120. Arrangement 120 is coupled between the collector of tran~istor Ql and the hot ground.
Diode 118 causes the voltage across capacitor 119 to be equal to voltage Vcl, during interval t2-t23 of FIGURE 2a.
During interval t23-t4, diodes 106 and 107 of FIGURE lb are nonconductive and collector voltage Vcl varies as a re~ult of a resonant ringing current that is produced in winding Wl, capacitor 119 and re6istor 117.
The resonant ringing current causes voltage Vw2, that is developed acros~ winding W2 of transformer T and that is ~ -negative until ti~e t3 of FIGURE 2d, to beco~e increasingly ~ -~
~ore po~itive after ti e t3 in a resonant anner.
At ti~e t4 of FIGURE 2g, signal VOUt at the base of transistor Q2 of FIGURE la becone~ zero a~ a result of the one-shot operation that wa6 described before, causing transi~tor Q2 to beco e nonconductive. After beco ing nonconductive, transistor Q2 enable~ the coupling of positive voltage Vw2 to the base of transistor Ql.
Positive voltage Vw2 that is coupled via resistor 103 and capacitor 102 to the base of transistor Ql produces current iB that causes transistor Ql of FIGURE 1 to be turned on.
The values of capacitor 119 and damping resistor 117 are selected so as to insure that voltage Vw2 is sufficiently positive to turn on transistor Ql at ti~e t4 of FIGURE 2d when signal VOUt of FIGNRE 2g beco~es zero. Transi~tor Ql of FIGNRE la re~ain conductive until ti~e t6 of FIGURE 2a ` - ;
; . :. ,:

-10- 1 3 3 1 0 3 9 ReA 85,014A

that is determined by pulse VB3 of FIGURE 2k, in the manner ~-described before with respect to interval to-t2.
After time t4 of FIGVRE 2a, that is analogous to -time to of the immediately preceding cycle, capacitor C10 S of FIGURE 1 i~ charged in a sawtooth manner, as de w ribed before with recpect to interval to-tl of FIGURE 2a. The DC
offset voltage of signal V~ i8 proportional to voltage B+
and may be adj w table by adju~ting re~i6tor Rll. Thus, pul6e ~ignal VB3 at the base of tran~istor Q3 of FIGURE lb ;~-having a leading edge that occurs at time t5, for example, of FIGURE 2k, occur~ after interval t4-tS f FIGURE 21 has elapsed. The length of interval t4-t5,representing the conduction ti e of transi~tor Q1 of FIGURE la, i~
proportional to voltage B+. ; --An inerease in voltage B+, for e~a~ple, causes the DC offset of ~ignal Vs to inereaffe, henee, transistor Q3 turns on earlier in a given eyele. AB deseribed before, when transistor Q3 i~ turned on by the pulse of ~ignal VB3~ -colleetor current ic of transistor Ql inereases rapidly, that eause~ tran~istor Q2 to turn o~, and that, in turn, eauses tran6i~tor Ql to turn off shortlr afterward. Thus, the length of interval to~ 4 or t4-t6, oecuring when tran~istor Ql is eonduetive, deerea~es when voltage B+
inerease~. The re~ult is that a s~aller a ount of agnetie -~
enerqy is available for produeinq the eurrent that eharges, for e~a~ple, filter capacitor 121 of FIGURE Ib aeros~ whieh voltage B+ is developed. On the other band, a deerea~e in voltage B+ will eause transistors Q2 and Q3 to turn on, and transitor Ql to turn off, later in a given eyele. Thw , a ehange in voltage B+ i~ eounteraeted in a negative feedback !' . loop ~anner by advancing or delaying the in6tant, in the given cycle, when transi6tor Q3 is turned on and when ;~
tran istor Ql i~ turned off, as eontrolled by voltage B+. -The gain of ~ueh negative feedbae~ loop i6 deter~ined~by ~ -the value of eapaeitor C10 and ~ay be raised or lowered by selecting the value of eapaeitor C10.
~ fir~t portion of the SMPS of FIGURE lb that inelude~, for oxa ple, winding W4, the re-peetive ter inals ,: , .

~ , .

331039 RCA 85~014A
where voltage B+ and signal VB3 are developed and winding W3, is conductively coupled to the cold ground. On the other hand, a second portion of the SMPS that includes, for example, transistor Q1 and winding Wl, is conductively s coupled to the hot ground. Transformer T provides a hot-cold barrier that conductively igolatcs the first portion of the SMPS from the second portion.
In accordance with an aspcct of the invention, timing signal VB3 that i6 referenced to the cold ground is applied via winding W3 of flyback trangformer T to the base electrode of transistor Q1, that is conductively coupled to the hot ground. Thug transformer T aintains the hot ground conductively isolated from the cold ground. Signal VB3 controls the turn-off instant of transistor Ql in accordance with the level of voltage B+, as explained before.
Energy ig trangfered in trangformer T acrosg the hot-cold barrier fro~ the gecond portion of the SMPS that is conductively coupled to the hot ground, that includes 20 for example, winding Wl, to the first portion of the SMPS - ~- ~
that i~ conductively coupled to the cold ground and that ~ ~-includes, for exa ple, winding W4. Such energy trangfer occurs in a direction, acrogs the hot-cold barrier, that is oppo~ite to the direction in which ~iqnal VB3 is coupled acrogg guch hot-cold barrier. Thu~, tran~fonmer T is used for pas~ing supply current in one direction acros~ the -~
hot-cold b rrier, that ig fro~ winding Wl to winding W4, and for applying ti ing ~ignal VB3 to control the switching ti~ing~ in tranfiigtor Ql, in the opposite direction across 30 the hot-cold barrier. Therefore, advantageously, there is - -no need for an additional igolation tran~former for coupling ti ing ~ignal VB3 acro~g the hot-cold barrier from ~ -the firgt portion of the SMPS that i~ conductively coupled to the cold ground, where control gignal VB3 is generated, to the second portion of the SMPS that is conductively coupled to the hot ground, where the control opcration is ~ ~-actually perfor~ed. Advuntageou~ly, ti ing signal VB3 is ~ -12- RCA 85,014A
1~31~39 generated by sensing the level of voltage B+ at terminal 150 where voltage B+ is actually developed.
A series pass regulator VR2 that is energized by voltage V+ produces a +12 volt regulated voltage V+12.
S Regulated voltage V+12 i8 produeed a~ a function of a voltage produced at a junction terminal 126 between resistor~ 124 and 125. Registor 124 and 125 form a series arrangement that i~ coupled between voltage V+12 and the cold ground.
A supply voltage VK i~ produced by rectifying, using a diode 132, a flyback voltage developed in a winding --wS. Voltage VK that is referenced to the hot ground, i~
used for energizing, for exa~ple, co parators Ulc and Uld of standby control circuit 127. Voltage VK, that is lS filtered in a capacitor CK, is coupled tbrough a re~i~tive voltage divider comprising re~i~tors 134 and 135, to an inverting input ten inal lSl of a co parator Ulc for developing at ter inal lSl a control voltage V~. A
re~istor 133 has a first ter inal that i~ coupled to ~- -junction teD~inal lSl, between resistors 135 and 134, and a second terminal that i~ coupled to an output terminal 152 ~ -of a comparator Uld. ; . ~-Voltage VR2 is coupled to the noninverting input ter~inal of co parator Ule. An output ten inal 153 of ~; ;
eo~parator Ulc, where a voltage V~ is developed, i~ coupled to an inverting input ter inal of eo parator Uld.
Referenee voltage VRl is coupled to a noninverting input ;~
ter inal of co parator Uld.
FIGURES 4a-4h illustrate waveforms useful for explaining a tranfiition of the SMPS of FIGURE 1 from normal to sitandby operation. FIGURES Sa-Sh illustrate the eorresponding wavefor~ useful for explaining a tran~ition bac~ to non al operation. Si ilar figures and numeral~ in FIGURES 1,2a-2mi, 4a-4h and Sa-Sh indicate ~i~ilar ite~çi or function~
During nor~al operation, eo parator~ Ulc and Uld of FIGURE la operate a~ a latch that aintain~i the voltage at ten~inal 152 at zero volts, eaui~ing voltage Vj to be ~`;- ;~

. ' ~ ` '' ~"`'`~

`:3 ." ` . - .. ~ . . . .

~ -13- 1 3 3 1 o 3 9 RcA 85,014A

smaller than voltage vR2 Therefore, comparator Ulc generates voltage Vm at a level that is higher than voltage VRl for maintaining a diode D20, coupled to the noninverting input terminal of comparator Ula, nonconductive Standby operation i~ initiated when a transistor Q4 of FIGURE lb, operating a~ a ~witch and coupled across -resi~tor 125, become~ conductive, a~ ~hown at time tlo of ~ ;
FIGURE 4a Con6equently, voltage V+12 of FIGURE 1 becomes -~zero The re~ult i~ that the horizontal o w illator, not shown, cea~es operating immediately and ~tandby operation begin~
The reduction of voltage V+12 to zero volts ;
cau~es voltage Vs~ at the noninverting input terminal of 15 co~parator U2a, to be cla ped to the forward voltage of a -~
diode D10 However, a voltage VvRi at the inverting input terminal of co parator U2a that is produced in a voltage regulator VRl i~ ~aintained egual to appro~i~ately +12V, ;~
during both nor~al and standby operations Therefore, -20 tran~i~tor Q3 re ain~ continuously in a nonconductive ; ~ -state; consequently, tran~i~tor Ql forog with tran~fon er T
a free-running bloe~ing oscillator that i~ no longer controlled in a negative feedbae~ loop ~anner Therefore, the duty Q ele of transistor Ql initially inerea6e~ after ` ~ -transistor Q4 beeo~es conduetive The load at ter inal 150 draws ~ub~tantially les~ rent during ~tandby Therefore, voltage~ VK~ B~ and Vj initially incr-ase after the ~ traD ition to the conductive state in transistor Q4, a~
; ~ho~n in FIGURE$ 4e and 4g during interval tl2-tl3 At tine tl3 of FIGURE 4g, voltage Vj beco e~
èqual to voltage VR2, cau~ing co parator unc of FIGURE 1 to produce output voltage V~ at zero volts, a~ shown in FIGURE
4h Cla ping diode D20 of FIGURE 1, that, during nor al operation, i~ bac~ biased by voltage V~, beco~es conductiv~
at tiue tl3 of FIGURE 4h After ti e tl3 of FIGURE 4h, an anode o diode D20 of FIGURE la, that i~ eoupled to the noninverting input t r inal of eo parator Ula, cla ps volt g VRl at the noninverting input ter inal of ~CA 85,014A
- -14- 1331~39 comparator Uld, to the forward voltage of diode D20. Thus voltage VR1, during standby, is substantially lower than during normal operation. Consequently, transistor Ql will - -be turned-off, during eaeh eycle, when a peak level of S collector current ic is substantially lower than during normal operation, as shown by the waveform of voltage -~
V8ensC of FIGURE 4c. ~enee, the stored energy in winding wq of FIGURE 1 is sub~tantially reduced during the conduction time of tran d stor Ql. The result i~ that, during standby, voltages Bl and VK ~ill ultimately decrease relative to their respeetive values during normal operation.
The decrease in voltage VK will cause the rate of change of upra ping ~ignal Vin of FIGURE 2f to decrease as ~;~
well. Therefore, the ratio of conduction ti e to noneonduetion ti~e, or duty cyele, of transistor Ql will further deerea~e. The result i~ that voltages B+ and VK
will even further deerease relative to tbeir values during normal operation. In a typieal loading condition, voltage B~ drops, during ~tandby, to about, for exa~ple, 2/3 of its nor~al operation level.
A low level voltage 8+ is desirable during start-up for reducing tbe stress on the borizontal deflection ~witeb, not ~hown, during a tran~ition from 25 standby to nornal operation, to avoid tbe ris~ of a ~ -secondary brea~down in tbe defleetion tran~i~tor. In contrast, in ~o e prior art SMPS that utilize, for exa ple, an integrated cireuit TDA4600, volt ge B+ ~ay increase from --a noreal operation level of +145V to a ~tandby level of +19OV.
After ti~e tl3 of FIGURE 4h, co~parator Uld of FIGURE la, having input ter inal~ that are coupled across -~
conductive diode D20, deeouple~ r ~i~tor 133 fro the re~i~tive voltage divider. Therefore, voltage Vj of~
FIGURE 4g beeo~es i ediately higher than voltage VR2. The re~ult i~ that co~parator Ulc of FIGURE l ~aintain~ voltage V~ of FIGURE 4h at zero volt~ throughout ~tandby.
Con~equently, eonparator~ Ulc and Uld of FIGURE la will 1S 1331039 RCA 85,014A

remain latched to their respective states throughout standby operation even though, as described before, voltage vK~ ultimately becomes gmaller, during standby, than during normal operation.
S Immediately after normal operation is initiated by the operation of trangistor Q4, as shown at time tl6 of FIGURE 5a, voltages B+ of FlGuaE 5e and voltage Vj of FIGURE 5g decrease in a down ramping manner. The decreace in voltage Bl and Vj occurs due to the sudden loading of, for example, voltage B+ by the horizontal deflection transistor, not shown, that begins ~witching. When, at time tl7 of FIGURE 5g, voltage Vj beco~es ~maller than voltage VR2, co~parators Ulc and Uld of gtandby control circuit 127 of FIGURE la reverse their respective states. - ~ ~ ~
15 Conseguently, diode D20 of FIGURE 1 becomes again back --- --biased and voltage V return~ to its normal level of Rl . ~ ,.:: .. :.. ~
+2.7V. Sub~eguently, transitor Q3 i8 turned on at time tl8 -~
of FIGURE 5b, causing the resu~ption of the feedback operation in the S~PS of FIGURE 1.
If a fault condition occurs in the deflection circuit, not shown, caui~ing a ~hort circuit or overloading ~ ~ -to be fon ed between, for e~a ple, ter inal 150, where voltage B+ is developed, and the cold ground, the SMoeS
begins operating in an interrittent aode. In the inter ittent ~ode, each pulse of current ic is followed by a relatively long dead ti e interv l in which no pulse of current ic occurs, a~ ~hown in FIGURE 6. At the end of ~~
each current pulse of current ic, the short circuit prevents voltage Vcl fro~ gubgtantially e~ceeding voltage 30 VuR. Therefore, no ringing current will be produced in ~ -!~ transforcer T. Congeguently, voltage Vw2 wiIl not beco~e positive, as in non~al operation. Therefore, voltage Vw2 ~ -c nnot initiate the conduction of tran$itor Ql.
In the beginning of a given dead ti e interval, ; ~
35 tran~i~tor Ql is maintained in cutoff by the negative --voltage developed in capacitor 102. During the dead ti~e int rval, capaeitor 102 is diischarged slowly via a resistor 156, a diode 155, resi~tor 103 and winding W2, and produces ~-., .~ .
.

-16- 13 3 1 0 3 9 RCA 85, 014A
. . .
current iB in a direction that is opposite to that shown by the arrow.
A resistor 101 is coupled between terminal lOOa where voltage VuR is developed, and the base of transistor Ql. When, as a result o the di w harge of capacitor 102, current iB~ now flowing in the opposite direction to that of the arrow, becomes smaller than a current ilol in resistor 101, transistor Ql i~ turned on and the regenerative feedback loop produces a pulse of current ic.
Thus, current ilol in resistor 101 causeg the dead time interval to end.
At some point during the pulse of current ic that occurs in the short circuit, overloaded operation, current iB produced by voltage Vw2 becomes, during the conduction time of transistor Q1, insufficient for maintaining transistor Ql in saturation. Therefore, the voltage at the collector transistor Ql begins increasing and voltage Vw2 becomes less positive, causing current iB to decrease in the regenerative feedback loop manner. When current iB
20 becomes zero, transigtor Ql turn~ off and the next dead -time interval begins. Such intermittent operation is desirable when overloading occurs because it reduces the stress on transigtor Ql by protecting trangistor Ql from -~
overheating.
As explained before, during start-up operation, the SMPS of FIGURE 1 is initially overloaded by the deflection circuit, not shown. Therefore, the SMPS
operate~ in the intermittent mode, that was explained before, as shown by the transient waYeform of voltage B+ in FIGURE 7 during interval ton-tstart. Advantageously, the intermittent mode provides a soft start operation. At time tstart, transigtor Ql of FIGUaE 1 receives a proper base drive through winding W2 for operating the regenerative feedback loop. The result is that the intermittent mode 35 operation ceases. At time to of FIGURE 7, the negative - - - -feedback loop i~ ~tabilized and operates in steady state and the soft ~tart turn-on operation ter~inateg.

~ -17- 1331039 RCA 85,014A
In the embodiment of the invention discussed above, resistor 101 of FIGURE la provides start-up base current for turning on transistor Ql. In a second modified embodiment of the invention, shown in FIGURE la, a resistor 101' is coupled between a terminal lOOb of bridge rectifier 100, where a half-wave rectified voltage V10Ob is produced, and between the base of transistor Ql. Resistor 101' is used instead of resistor 101 that is removed from the SMPS -of FIGURE la.
During an overloading condition or during start-up, in the case when resistor 101' is used instead of resistor 101, substantially no current flows in resistor 101' during alternate half cycle~ of voltage VAc. Each such half cycle has a length of 10 illi6econdg (when the mains frequency i~ 50 ~z) that occurg when half wave rectified volta~e V10Ob at terminal lOOb is zero.
Therefore, the dead time interval that wag mentioned before --extends throughout each alternately occuring 10 millisecond interval, as 6hown by the waveform6 of voltage V10Ob, voltage Vcl and current ic in FIGURES 8a, 8b and 8c, respectively. The 10 millisecond e~tended dead time ~ -~
intervals of , for e~ample, FIGURE 8c enable cooling down -of transistor Ql of FIGURE la that, advantageously, protects and reduce6 the streg6 on tran6igtor Ql. The 10 millisecond dead ti~e interval6 ~ay increage the length of an interval during which 60ft start operation occurg. (If 60 ~z ~ain6 are u6ed, the dead time interval would bo 8 milligecond6 . ) , :~, ~ .. ....
FIGURES 9a-9e illustrate wavefor~ useful for e~plaining the soft start operation of the SMæS of FIGURE
la when resistor 101' i6 used instead of resi~tor 101.
Similar symbols and numerals in FIGURES la, 2a-2m, 7, 8 and ;;~
9a-9e indicate gi~ilar item6 or functiong. At ti~e tgtart of FIGURE 9c, current ic is gufficiently large for cauging 35 the one-shot arrangement to trigger that cau6eg transigtor ;~
Ql of FIGURE la to turn off during a portion of each cycle. -~ .. 4 The energy stored in tran6for er T during the conduction --interval of tran~i~tor Ql produce~ rent iB that turns on : - ., .
, '~'' "" .'; " ' ::. ..
,. ;, " ~ ' ' '.

RCA 85,014A
-18- 1 3 3 1 ~ 3 9 transistor Ql at the end of each nonconduction interval of transistor Ql.

.
" ~ ~

Claims (3)

1. A switched mode power supply, comprising:
a switching transistor;
a transformer having a first winding that is coupled to a main current conducting electrode of said first switching transistor;
control means coupled to a control electrode of said switching transistor for producing a switching operation therein;
means coupled to said transformer for producing, in accordance with said switching operation an output supply voltage that is applied to a load and an output current that is coupled to said load to produce a load current therein;
means responsive to said output supply voltage for generating a first control signal that is coupled to said control means for varying a duty cycle of said switching transistor in accordance with said output supply voltage during a normal mode of operation;
a source of an on/off control signal that is coupled to said load that reduces said load current in said load during a standby mode of power supply operation relative to said load current during said normal mode, thereby causing said output supply voltage to increase after said on/off control signal changes from a power-on state to a power-off state;
means responsive to said output supply voltage for generating a second control signal when said output supply voltage becomes greater than a predetermined level that is indicative of a transition to said standby mode of operation, said second control signal being coupled to said first control signal generating means for varying said first control signal during said standby mode to maintain a peak level of a first switching current that flows in said switching transistor substantially below its level during said normal mode for decreasing said output supply voltage to a value smaller than during normal mode of operation; and means for maintaining the generation of said second control signal during said standby mode of operation when said supply voltage has decreased to said smaller value.

2. A power supply according to Claim 1 wherein said second control signal generation maintaining means comprises a latching arrangement that utilizes positive feedback.

3. A power supply according to Claim 1 wherein said transformer includes a second winding that is coupled to said control electrode of said transistor to form a regenerative feedback loop that operates as a blocking oscillator.