CA1325684C - Efficient computer terminal system utilizing a single slave processor - Google Patents
Efficient computer terminal system utilizing a single slave processorInfo
- Publication number
- CA1325684C CA1325684C CA000597144A CA597144A CA1325684C CA 1325684 C CA1325684 C CA 1325684C CA 000597144 A CA000597144 A CA 000597144A CA 597144 A CA597144 A CA 597144A CA 1325684 C CA1325684 C CA 1325684C
- Authority
- CA
- Canada
- Prior art keywords
- slave processor
- crt
- memory
- display
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/222—Control of the character-code memory
Abstract
Abstract A cost-efficient design for a CRT computer terminal is presented. The need for a master processor is eliminated by designing a CRT controller to initialize a slave processor.
The slave processor accesses a random access memory (RAM) in which is stored instructions which the processor executes.
Upon initialization of the computer terminal, the CRT
controller reads instructions to be executed by the slave processor from a non-volatile read-only memory (ROM). The instructions are transferred from the CRT controller to the slave processor. The slave processor stores the instructions in the random access memory. Each instruction, at the proper time, may then retrieved and executed by the slave processor.
The slave processor accesses a random access memory (RAM) in which is stored instructions which the processor executes.
Upon initialization of the computer terminal, the CRT
controller reads instructions to be executed by the slave processor from a non-volatile read-only memory (ROM). The instructions are transferred from the CRT controller to the slave processor. The slave processor stores the instructions in the random access memory. Each instruction, at the proper time, may then retrieved and executed by the slave processor.
Description
L32~6~
-~ EFFICIENT COMPUTER TERMINAL SYSTEM UTILIZINC A SINGLE SLAVE
;i 'PROCESSOR
, `~ Background ':' '~ "'' , 5 The present invention relate3 to a cathode ray tube (CRT) computqr terminal.
~: i '~ Once a CRT computer terminal has been designed for a ,'~' particular terminal, a later redeslgn of compatlble CRT
~` ','' computer termlnals focu~es on the reduction o~ de3ien ", .
', ~ 10 oomplexity, partioularly a~ to number o~ chips required ~or .: ;.,. :, ~',', a3sembly. The present invention allow~ the production Or a ' : logic ~ection wlthin a computer termlnal to be implemented .A,~" ",~ , ; ~ wlth the ~se of eight integrat~d oircuits a3,compared wlth ~ ', alternate designs whlch use from twelve ko one hundred ; . ~, ~.,.
,' 15 ~lrteen lntegrated circuits, ;a Summary Or the Inventlon ,,',~ In a¢oordance with the prererred embodiments Or the .`.~`^1 ,~,"",, pre~ent a cost-efricient desi~n for a CRT oomputer terminal : - .. ~ .. ..
~ ' ' 20 is pre3ented. The need for a master proc~Ysor i~ eliminated `','~ by de~iening a CRT controller to initialize ~ slaYe ' ;, proo~3~0r. The ~lave proce3sor aocesses a random acce~s -~, memory ~RAM) in which is stored instructions which the ; ~ 1 ~ prooessor executes. Upon lnitializat'ion o~ the oomputer ,,. . , ~ ,, .
terminal~ the CRT controller reads instructions to be ,'', executed by the slave proces~or rrom a non-volatile read-'l only memory (ROM~. The instructions are transrerred from ~,,,','~ the C~T controller to the ~lave proce~sor, The slave ;`''~ 'i' . ,. ~.
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processor stores the instructions in the random access memory. Each instruction, at the proper time, ~ay then be retrieved and executed by the slave processor.
Further, in the preferred embodiment, the CRT
controller includes a screen buffer and a row buffer.
The screen buffer is sufficiently large to contain a display screen of data to be displayed on a CRT display.
The row buffer contains two sections, each section ` ` containing a character row of data to be displayed on the ` 10 CRT display. The character row in a first of the two sections is modified with information from the screen buffer. The character row in a second of the two ` sections is the character row currently being drawn on the CRT display. Upon a signal the sections are switched so that the character row in the second section is ~'~ modified with information from the screan buffer and the character row in the first section is the character row ' i, currently being drawn on the CRT display.
Other aspects of this invention are as follows:
','`.3, 20 A computer terminal comprising:
~ a CRT display;
, .
.~ a slave processor;
random access memory, coupled to the processor and accessible by the slave processor;
~``3i 25 non-volatile read-only memory; and -3 CRT control means, coupled to the CRT display, to `.~ the non-volatile read-only memory and to the slave processor, for sending display information to the CRT
display and for sending control signals from said read-only memory to the slave processor.
;. In a computer terminal having a slave processor coupled to a random access memory and a display ,~, controller coupled to a read-only msmory, a method for initializing the slave processor comprising the steps o~:
~`$~ 35 (a) reading, by the display controller from the ,,"5' read~only memory, data containing instructions which th i slave processor is to execute;
:~ (b) sending, from the display controller to the ..
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` 2a slave processor, the data containing the instructions;
(c) storing, by the slave processor to the random access memory, the data containing the instructions; and, `~ (d) retrieving from the random access memory and executing by the slave processor the instructions.
; In a computer terminal having a slave processor, a ; read only memory and a CRT display, a CRT controller comprlsing:
~- a screen buffer with sufficient memory to contain ;,,, ! lO data for a full CRT screen display of data;
processor interface means, coupled to the screen , buffer, for interfacing with the slave processor and ;-;}~ placing data from the slave processor into the screen ~ - buffer;
.:, .,,j row buffer with sufficient memory to contain two character rows of CRT screen display; and, ~-~ remote controller means, coupled to the screen ;~; buffer and to the row buffer, for transferring onecharacter row of screen display from the screen buffer to ; ~ 20 the row buffer.
, . , j Brief Description of the Drawings ~ Figure 1 is a block diagram of the logic design for ; , a computer terminal in accordance with the preferred embodim~nt of the present invention.
Figure 2 is the block diagram of a CRT controller , shown in Figure 1, in accordance with the preferred ... : ! embodiment of the present invention.
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Deacription of the Preferred Embodiment .
Figure 1 3how3 the loglc deslgn for a ¢omputer terminal 100. A coax cable 101 conneot~ a computer (not shown) to a buf~er 102 wlthin comput0r termlnal 100. ~ufrer 102 burfers ... ..
data transferred between coax cable 101 and a processor 104.
DaSa transrerred between buPfer 102 and processor 104 i9 sent over lines 110. Processor 104 i~, for example, a ,. ;; ,.,.~.- ' ; ~ Biphase Communication Processor developed by National ~ Semlconductor Corporation~ having a bu~iness addres3 at 2900 .~,.....
~ 10 Semiconductor Drive~ Santa Clara, California 95051. The :~ ,.
~"~ Biphase Communication Proce3sor is a ~lave proce~sor ; requiring a maater processor to lnitiallze and control its .,::
~ 1 operation. In the present invention a CRT controller 107 ;
. . . .
; Punctions to perform the tasks typically done by a master ^~ 15 prooessor.
Processor 104 acce~se~ a random address memory (RAM~
`~ 105 through line~ 112. Proce3~0r 104 communicates wlth CRT
controller 107 through lines 111. Llne~ 118 are used by CRT
i controller 107 to control processor 104, whan necesaary, and ; 20 to down load instructions to procea30r 104. CRT controller 107 accesse~ a read-only memory (RQM) 106 through line3 1'3.
CRT controllRr 107 send~ data to a CRT 115 through lines ; ~ 116. CRT controller accesses an EEPROM and bell circuit 108 through lines 114 and a keyboard ~not shown) through line3 ~ 25 109. A reset line 103, conne¢ted to proce330r 104 and CRT
; controller 107, i~ u3ed to reset the s~stem.
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Figure 2 show3 a block diaeram of CRT oontroller 107.
~ A proce3sor interface 207 communicates with proces30r 104 ;~ throu~h line3 111. Processor interface 207 and all other ;~- blocks within CRT controller 107 are coupled to a data bus .. 5 221. Proce3~0r 104 generally exercisei~ control over data bu3 221 through processor interface 207~
Throuzh an addrea3 bu3 222~ proceai30r interface 207 ;. ..
` ."~ ¢ommunicates with a ROM Arbiter 202 and a screen bu~rer 208.
... Proceasor 104, through processor inter~ace 207, controls a : . 10 keyboard, bell and EEPROM interface 211 through lineis 229.
:~ Processor 104 also sends control signals through processor . ~ .
~ interface 107, through line3 230 to a controller core 209.
: Processor interface 107 decode3 addresses 3ent ~rom ~; . .
processor 104.
Screen bur~er 208 holds 2K byt~ of data, sufricient for one Acreen of data. The data in screen buf~er 208 is , .. . .
from proces30r 104, trani~ferred throu~h data bu3 221, to , . screen buffer 208. The data in 3creen burrer 208 is read by a remote oontroller 203 through data buii3 221.
, ~ . . ~ . .
i 20 Remote controller 203 has two ~unctions. Each ~unotion -~. . is performed by a ~tate machi~e within remote ¢ontroller 203. Upon sy~tem reset, remote controll0r 103 reeeives a ~ :, reset aignal over reset line 103. Remote controller 203 :~, .' :~` then acts as an inatruction down loader to procesisor 104.
. ~, .............................................. .
.~i 25 Through address llnea 235 remote controller 203 causes ROM
. arbiter to`retrieve data fro~ ROM 106. ROM arbiter 202 . . .:~, . .
.` returns the retrieved data to remote controller 203 through ~:3~:
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~" data bus 221. Through line~ 118, remote controller 203 drives the control lines of processor 104, and writes in3tructions through processor 104 to RAM 105. Once thi~ is "~ complete, control is handed to proces30r 104 whlch begins : ~, normal flrmware execution. The instruction3 in RAM 105 are used to control processor 104.
~ The second function of remote controller 203 i9 to .,;, . ~, ",, .
~ overaee the tranafer of one character row of data ~flfteen r~ ,',.. "' scan lines) from screen buffer 208 to a row bu~fer 204 .
~ 10 Once every 9iX mlcroseconda, remote controller ~03, through .~:' ;, - ; lines 118, instructs proceq~or 104 to relinguiah control ;, ::.':~.' ~ over data bus 221. Remote controller 203 then ~ends to row .' ,.. ' ~
buffer 204 through address lines 226 the address wlthin ~ creen buf~er 208 of the one row of data to be sent to row `~ 15 buf~er 204. Remote controller 203 then oontrols address :,, ~ ;,.,~
~ linea 222 to direat the tranafer of this character row from ." . ~ (.;
screen burfer 208 to row bu~fer 204.
~ Row buffer Z04 containa two ~eotions. Each section has ;`;~ enou~h memory to store one character row of data. In a ~irst ~ection 5 one character row i~ con~tantly being read ~ through line3 223 by hOM arbiter 202 ard an output ; enhancement blook 205 for the purpo~e of sending data to CRT
, :.
115 to be displayed. In the second section~ a character row of data is available for update by remote`pontroller ~;, 25 203. When CRT 115 has completed fifteen scan iines (1 ' "i character row~, the Swo 3ection~ are switched 90 that the - ~econd section i~ read by ROM arbiter 202 and output '.~ ,'~,' ;
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~ enhanoement block 205 and the rlrst section i9 available for :,. .. ..
:` update by remote controller 203.
. .
~` ~OM arbiter 202 interfaces with ROM 106 through lines 113. For instance, ROM arbiter 202 recelves through lines .,.~ -223 a character from row buffer 204 and receives through .,~,.. ..
- l llnes 224 a scan line number from a controller core 209.
With this information ROM arbLter 202 generates an addre3s -~ for the location in ROM 106 of the dot pattern for the scan :. .. .
llne o~ the character received. The ROM address i9 sent through lines 113 to ROM 106. ROM 106 returns throu~h lines 113 the dot pattern to ROM arbiter 202. ROM arbiter 202 send~ the dot pattern to a parallel-to-serial ~hifter 206 ; tnrough llnes 225.
`~ The character sent to ROM arbiter 202 from row buffer ~, l 15 204 is also 3ent throu~h llnes 223 to an output enh~ncement 3I block 205. Output enhancement block 205 notes any ! enhancement, e.g., underllnlng, itallcs, bold, etc., and ~, sends an enhancement control signal to shifter 206 through :~
line3 228. ParallPl-to-3erlal shlfter 206 recclves i~put ~i 20 ~rom ROM arblter 202 and enhancement ¢ontrol slgnals from output enhancement block 205 and converts thi3 information ~:~ to a serial transmission which is sent to CRT 115 through .
. .
j lines 116a. Lines 116a are a subset Or lines 116.
. ~, ~J A keyboard, bell and EEPROM interface 211 interfaces .j, '~.
~l 25 with a keyboard through lines 109. Keyboard, bell and ` ~, EEPROM interface lnterfaces with EEPROM and bell 108 through -:~ lines 114 Processor 104 19 able to acoes~ keyboard~ bell :, ~ :."
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, .. . . .
~ and EEPROM inter~ace 111 throu~h proc~3~0r interrace Z07 ,.
;~ through lines 229.
Controller core 209 provides control and timing for all i ; blocks wlthln CRT controller 107. Controller core 209 keeps track of data displa~ed on C~T 115, e.g., whioh row is being ~canned, which scan line i9 being scannsd, which charaoter : ,.
currently being reproduced Controller core 209 also - lnform3 row bu~fer 204 through lines 226, when to switch 1, 1 :
- sect~ons. Controller core 209 also generates horlzontal ~i~; 10 synchronization signals and vertical synchronization signals ~ which are sent to CRT 115 through line3 116b. Lines 116b .,.~., .
are a subset of lines 116. These ~ignals are used~ for example, to fill in blank spots in the display. Further, oontroller core 2C9 send3 timing information to output enhancement block 205 through line~ 227.
A clock 210 receives a system olock signal through a , ,.
clock line 231 and generates a clock signal placed on a clock llne 232 which is connected to and used by all blocks :~ ; ln CRT controller 107.
;:~. . .
A 3elr te~t block 201 is acca~sible to tester circuitry through lines 220. Self te~t blook 201 is used to test operation o~ CRT controller 107 for manufacturing and other .
, defects.
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-~ EFFICIENT COMPUTER TERMINAL SYSTEM UTILIZINC A SINGLE SLAVE
;i 'PROCESSOR
, `~ Background ':' '~ "'' , 5 The present invention relate3 to a cathode ray tube (CRT) computqr terminal.
~: i '~ Once a CRT computer terminal has been designed for a ,'~' particular terminal, a later redeslgn of compatlble CRT
~` ','' computer termlnals focu~es on the reduction o~ de3ien ", .
', ~ 10 oomplexity, partioularly a~ to number o~ chips required ~or .: ;.,. :, ~',', a3sembly. The present invention allow~ the production Or a ' : logic ~ection wlthin a computer termlnal to be implemented .A,~" ",~ , ; ~ wlth the ~se of eight integrat~d oircuits a3,compared wlth ~ ', alternate designs whlch use from twelve ko one hundred ; . ~, ~.,.
,' 15 ~lrteen lntegrated circuits, ;a Summary Or the Inventlon ,,',~ In a¢oordance with the prererred embodiments Or the .`.~`^1 ,~,"",, pre~ent a cost-efricient desi~n for a CRT oomputer terminal : - .. ~ .. ..
~ ' ' 20 is pre3ented. The need for a master proc~Ysor i~ eliminated `','~ by de~iening a CRT controller to initialize ~ slaYe ' ;, proo~3~0r. The ~lave proce3sor aocesses a random acce~s -~, memory ~RAM) in which is stored instructions which the ; ~ 1 ~ prooessor executes. Upon lnitializat'ion o~ the oomputer ,,. . , ~ ,, .
terminal~ the CRT controller reads instructions to be ,'', executed by the slave proces~or rrom a non-volatile read-'l only memory (ROM~. The instructions are transrerred from ~,,,','~ the C~T controller to the ~lave proce~sor, The slave ;`''~ 'i' . ,. ~.
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,, ,, ,s,,, .:
: ., , , - ~ 13~56~
` .
processor stores the instructions in the random access memory. Each instruction, at the proper time, ~ay then be retrieved and executed by the slave processor.
Further, in the preferred embodiment, the CRT
controller includes a screen buffer and a row buffer.
The screen buffer is sufficiently large to contain a display screen of data to be displayed on a CRT display.
The row buffer contains two sections, each section ` ` containing a character row of data to be displayed on the ` 10 CRT display. The character row in a first of the two sections is modified with information from the screen buffer. The character row in a second of the two ` sections is the character row currently being drawn on the CRT display. Upon a signal the sections are switched so that the character row in the second section is ~'~ modified with information from the screan buffer and the character row in the first section is the character row ' i, currently being drawn on the CRT display.
Other aspects of this invention are as follows:
','`.3, 20 A computer terminal comprising:
~ a CRT display;
, .
.~ a slave processor;
random access memory, coupled to the processor and accessible by the slave processor;
~``3i 25 non-volatile read-only memory; and -3 CRT control means, coupled to the CRT display, to `.~ the non-volatile read-only memory and to the slave processor, for sending display information to the CRT
display and for sending control signals from said read-only memory to the slave processor.
;. In a computer terminal having a slave processor coupled to a random access memory and a display ,~, controller coupled to a read-only msmory, a method for initializing the slave processor comprising the steps o~:
~`$~ 35 (a) reading, by the display controller from the ,,"5' read~only memory, data containing instructions which th i slave processor is to execute;
:~ (b) sending, from the display controller to the ..
~ .:
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: - . . , -:~ . . . . ..
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` 2a slave processor, the data containing the instructions;
(c) storing, by the slave processor to the random access memory, the data containing the instructions; and, `~ (d) retrieving from the random access memory and executing by the slave processor the instructions.
; In a computer terminal having a slave processor, a ; read only memory and a CRT display, a CRT controller comprlsing:
~- a screen buffer with sufficient memory to contain ;,,, ! lO data for a full CRT screen display of data;
processor interface means, coupled to the screen , buffer, for interfacing with the slave processor and ;-;}~ placing data from the slave processor into the screen ~ - buffer;
.:, .,,j row buffer with sufficient memory to contain two character rows of CRT screen display; and, ~-~ remote controller means, coupled to the screen ;~; buffer and to the row buffer, for transferring onecharacter row of screen display from the screen buffer to ; ~ 20 the row buffer.
, . , j Brief Description of the Drawings ~ Figure 1 is a block diagram of the logic design for ; , a computer terminal in accordance with the preferred embodim~nt of the present invention.
Figure 2 is the block diagram of a CRT controller , shown in Figure 1, in accordance with the preferred ... : ! embodiment of the present invention.
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Deacription of the Preferred Embodiment .
Figure 1 3how3 the loglc deslgn for a ¢omputer terminal 100. A coax cable 101 conneot~ a computer (not shown) to a buf~er 102 wlthin comput0r termlnal 100. ~ufrer 102 burfers ... ..
data transferred between coax cable 101 and a processor 104.
DaSa transrerred between buPfer 102 and processor 104 i9 sent over lines 110. Processor 104 i~, for example, a ,. ;; ,.,.~.- ' ; ~ Biphase Communication Processor developed by National ~ Semlconductor Corporation~ having a bu~iness addres3 at 2900 .~,.....
~ 10 Semiconductor Drive~ Santa Clara, California 95051. The :~ ,.
~"~ Biphase Communication Proce3sor is a ~lave proce~sor ; requiring a maater processor to lnitiallze and control its .,::
~ 1 operation. In the present invention a CRT controller 107 ;
. . . .
; Punctions to perform the tasks typically done by a master ^~ 15 prooessor.
Processor 104 acce~se~ a random address memory (RAM~
`~ 105 through line~ 112. Proce3~0r 104 communicates wlth CRT
controller 107 through lines 111. Llne~ 118 are used by CRT
i controller 107 to control processor 104, whan necesaary, and ; 20 to down load instructions to procea30r 104. CRT controller 107 accesse~ a read-only memory (RQM) 106 through line3 1'3.
CRT controllRr 107 send~ data to a CRT 115 through lines ; ~ 116. CRT controller accesses an EEPROM and bell circuit 108 through lines 114 and a keyboard ~not shown) through line3 ~ 25 109. A reset line 103, conne¢ted to proce330r 104 and CRT
; controller 107, i~ u3ed to reset the s~stem.
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.. . ..
~ ".
Figure 2 show3 a block diaeram of CRT oontroller 107.
~ A proce3sor interface 207 communicates with proces30r 104 ;~ throu~h line3 111. Processor interface 207 and all other ;~- blocks within CRT controller 107 are coupled to a data bus .. 5 221. Proce3~0r 104 generally exercisei~ control over data bu3 221 through processor interface 207~
Throuzh an addrea3 bu3 222~ proceai30r interface 207 ;. ..
` ."~ ¢ommunicates with a ROM Arbiter 202 and a screen bu~rer 208.
... Proceasor 104, through processor inter~ace 207, controls a : . 10 keyboard, bell and EEPROM interface 211 through lineis 229.
:~ Processor 104 also sends control signals through processor . ~ .
~ interface 107, through line3 230 to a controller core 209.
: Processor interface 107 decode3 addresses 3ent ~rom ~; . .
processor 104.
Screen bur~er 208 holds 2K byt~ of data, sufricient for one Acreen of data. The data in screen buf~er 208 is , .. . .
from proces30r 104, trani~ferred throu~h data bu3 221, to , . screen buffer 208. The data in 3creen burrer 208 is read by a remote oontroller 203 through data buii3 221.
, ~ . . ~ . .
i 20 Remote controller 203 has two ~unctions. Each ~unotion -~. . is performed by a ~tate machi~e within remote ¢ontroller 203. Upon sy~tem reset, remote controll0r 103 reeeives a ~ :, reset aignal over reset line 103. Remote controller 203 :~, .' :~` then acts as an inatruction down loader to procesisor 104.
. ~, .............................................. .
.~i 25 Through address llnea 235 remote controller 203 causes ROM
. arbiter to`retrieve data fro~ ROM 106. ROM arbiter 202 . . .:~, . .
.` returns the retrieved data to remote controller 203 through ~:3~:
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~" data bus 221. Through line~ 118, remote controller 203 drives the control lines of processor 104, and writes in3tructions through processor 104 to RAM 105. Once thi~ is "~ complete, control is handed to proces30r 104 whlch begins : ~, normal flrmware execution. The instruction3 in RAM 105 are used to control processor 104.
~ The second function of remote controller 203 i9 to .,;, . ~, ",, .
~ overaee the tranafer of one character row of data ~flfteen r~ ,',.. "' scan lines) from screen buffer 208 to a row bu~fer 204 .
~ 10 Once every 9iX mlcroseconda, remote controller ~03, through .~:' ;, - ; lines 118, instructs proceq~or 104 to relinguiah control ;, ::.':~.' ~ over data bus 221. Remote controller 203 then ~ends to row .' ,.. ' ~
buffer 204 through address lines 226 the address wlthin ~ creen buf~er 208 of the one row of data to be sent to row `~ 15 buf~er 204. Remote controller 203 then oontrols address :,, ~ ;,.,~
~ linea 222 to direat the tranafer of this character row from ." . ~ (.;
screen burfer 208 to row bu~fer 204.
~ Row buffer Z04 containa two ~eotions. Each section has ;`;~ enou~h memory to store one character row of data. In a ~irst ~ection 5 one character row i~ con~tantly being read ~ through line3 223 by hOM arbiter 202 ard an output ; enhancement blook 205 for the purpo~e of sending data to CRT
, :.
115 to be displayed. In the second section~ a character row of data is available for update by remote`pontroller ~;, 25 203. When CRT 115 has completed fifteen scan iines (1 ' "i character row~, the Swo 3ection~ are switched 90 that the - ~econd section i~ read by ROM arbiter 202 and output '.~ ,'~,' ;
~.,~ .;
'"'! ~'~'i . .. ~' . : .
. : :. . . :
.,.;, .:
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~ enhanoement block 205 and the rlrst section i9 available for :,. .. ..
:` update by remote controller 203.
. .
~` ~OM arbiter 202 interfaces with ROM 106 through lines 113. For instance, ROM arbiter 202 recelves through lines .,.~ -223 a character from row buffer 204 and receives through .,~,.. ..
- l llnes 224 a scan line number from a controller core 209.
With this information ROM arbLter 202 generates an addre3s -~ for the location in ROM 106 of the dot pattern for the scan :. .. .
llne o~ the character received. The ROM address i9 sent through lines 113 to ROM 106. ROM 106 returns throu~h lines 113 the dot pattern to ROM arbiter 202. ROM arbiter 202 send~ the dot pattern to a parallel-to-serial ~hifter 206 ; tnrough llnes 225.
`~ The character sent to ROM arbiter 202 from row buffer ~, l 15 204 is also 3ent throu~h llnes 223 to an output enh~ncement 3I block 205. Output enhancement block 205 notes any ! enhancement, e.g., underllnlng, itallcs, bold, etc., and ~, sends an enhancement control signal to shifter 206 through :~
line3 228. ParallPl-to-3erlal shlfter 206 recclves i~put ~i 20 ~rom ROM arblter 202 and enhancement ¢ontrol slgnals from output enhancement block 205 and converts thi3 information ~:~ to a serial transmission which is sent to CRT 115 through .
. .
j lines 116a. Lines 116a are a subset Or lines 116.
. ~, ~J A keyboard, bell and EEPROM interface 211 interfaces .j, '~.
~l 25 with a keyboard through lines 109. Keyboard, bell and ` ~, EEPROM interface lnterfaces with EEPROM and bell 108 through -:~ lines 114 Processor 104 19 able to acoes~ keyboard~ bell :, ~ :."
~ 1 .
. ,. .
~' .~ , -- . , i" ~ , . .
, .. . . .
~ and EEPROM inter~ace 111 throu~h proc~3~0r interrace Z07 ,.
;~ through lines 229.
Controller core 209 provides control and timing for all i ; blocks wlthln CRT controller 107. Controller core 209 keeps track of data displa~ed on C~T 115, e.g., whioh row is being ~canned, which scan line i9 being scannsd, which charaoter : ,.
currently being reproduced Controller core 209 also - lnform3 row bu~fer 204 through lines 226, when to switch 1, 1 :
- sect~ons. Controller core 209 also generates horlzontal ~i~; 10 synchronization signals and vertical synchronization signals ~ which are sent to CRT 115 through line3 116b. Lines 116b .,.~., .
are a subset of lines 116. These ~ignals are used~ for example, to fill in blank spots in the display. Further, oontroller core 2C9 send3 timing information to output enhancement block 205 through line~ 227.
A clock 210 receives a system olock signal through a , ,.
clock line 231 and generates a clock signal placed on a clock llne 232 which is connected to and used by all blocks :~ ; ln CRT controller 107.
;:~. . .
A 3elr te~t block 201 is acca~sible to tester circuitry through lines 220. Self te~t blook 201 is used to test operation o~ CRT controller 107 for manufacturing and other .
, defects.
., .~. .
. ,.,j .
; . .
.~ .... .
.. . ..
.::: . . - , ~ ~ .
. :-. , . :, .
. .
Claims (12)
1. A computer terminal comprising:
a CRT display;
a slave processor;
random access memory, coupled to the processor and accessible by the slave processor;
non-volatile read-only memory; and CRT control means, coupled to the CRT display, to the non volatile read-only memory and to the slave processor, for sending display information to the CRT display and for sending control signals from said read-only memory to the slave processor.
a CRT display;
a slave processor;
random access memory, coupled to the processor and accessible by the slave processor;
non-volatile read-only memory; and CRT control means, coupled to the CRT display, to the non volatile read-only memory and to the slave processor, for sending display information to the CRT display and for sending control signals from said read-only memory to the slave processor.
2. A computer terminal as in Claim 1 wherein CRT
control means includes means for, upon an initialization of the computer terminal, down loading data from the non-volatile read-only memory through the slave processor to the random access memory.
control means includes means for, upon an initialization of the computer terminal, down loading data from the non-volatile read-only memory through the slave processor to the random access memory.
3. A computer terminal as in Claim 1 additionally comprising a buffer coupled to the slave processor and to a coax cable.
4. A computer terminal as in Claim 1 wherein the CRT
control means comprising:
a screen buffer with sufficient memory to contain data for a full screen to be displayed on the CRT display;
processor interface means, coupled to the screen buffer, for interfacing with the slave processor and placing data from the slave processor into the screen buffer;
row buffer with sufficient memory to contain two character rows of CRT screen display; and, remote controller means, coupled to the screen buffer and to the row buffer, for transferring one character row of screen display from the screen buffer to the row buffer.
control means comprising:
a screen buffer with sufficient memory to contain data for a full screen to be displayed on the CRT display;
processor interface means, coupled to the screen buffer, for interfacing with the slave processor and placing data from the slave processor into the screen buffer;
row buffer with sufficient memory to contain two character rows of CRT screen display; and, remote controller means, coupled to the screen buffer and to the row buffer, for transferring one character row of screen display from the screen buffer to the row buffer.
5. A computer terminal as in Claim 4 wherein the remote controller means is coupled directly to the slave processor and to a reset line.
6. A computer terminal as in Claim 5 wherein the remote controller means includes a state machine which upon receipt of a signal over the reset line causes data from the read-only memory to be transferred from the read-only memory to the slave processor.
7. In a computer terminal having a slave processor coupled to a random access memory and a display controller coupled to a read-only memory, a method for initializing the slave processor comprising the steps of:
(a) reading, by the display controller from the read-only memory, data containing instructions which the slave processor is to execute;
(b) sending, from the display controller to the slave processor, the data containing the instructions;
(c) storing, by the slave processor to the random access memory, the data containing the instructions; and, (d) retrieving from the random access memory and executing by the slave processor the instructions.
(a) reading, by the display controller from the read-only memory, data containing instructions which the slave processor is to execute;
(b) sending, from the display controller to the slave processor, the data containing the instructions;
(c) storing, by the slave processor to the random access memory, the data containing the instructions; and, (d) retrieving from the random access memory and executing by the slave processor the instructions.
8. In a computer terminal having a slave processor, a read-only memory and a CRT display, a CRT controller comprising:
a screen buffer with sufficient memory to contain data for a full CRT screen display of data;
processor interface means, coupled to the screen buffer, for interfacing with the slave processor and placing data from the slave processor into the screen buffer;
row buffer with sufficient memory to contain two character rows of CRT screen display; and, remote controller means, coupled to the screen buffer and to the row buffer, for transferring one character row of screen display from the screen buffer to the row buffer.
a screen buffer with sufficient memory to contain data for a full CRT screen display of data;
processor interface means, coupled to the screen buffer, for interfacing with the slave processor and placing data from the slave processor into the screen buffer;
row buffer with sufficient memory to contain two character rows of CRT screen display; and, remote controller means, coupled to the screen buffer and to the row buffer, for transferring one character row of screen display from the screen buffer to the row buffer.
9. A CRT controller as in Claim 8 wherein the remote controller means is coupled directly to the slave processor and to a reset line.
A CRT controller as in Claim 9 wherein the remote controller means includes a state machine which upon receipt of a signal over the reset line causes data from the read-only memory to be transferred from the read-only memory to the slave processor.
11. A CRT controller as in Claim 8 wherein the row buffer includes two sections each section containing one of the two character rows, a first of the two sections receiving the one character row of screen display from the screen buffer and a second of the two sections being read from to supply display information to the CRT display.
12. A CRT controller as in Claim 11 wherein upon a signal the first section and the second section switch so that the second section receives the one character row of screen display from the screen buffer and the first section is read from to supply display information to the CRT
display.
display.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/238,235 US5148516A (en) | 1988-08-30 | 1988-08-30 | Efficient computer terminal system utilizing a single slave processor |
| US238,235 | 1988-08-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1325684C true CA1325684C (en) | 1993-12-28 |
Family
ID=22897029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000597144A Expired - Fee Related CA1325684C (en) | 1988-08-30 | 1989-04-19 | Efficient computer terminal system utilizing a single slave processor |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5148516A (en) |
| EP (1) | EP0356610B1 (en) |
| JP (1) | JP2760859B2 (en) |
| KR (1) | KR900003730A (en) |
| CA (1) | CA1325684C (en) |
| DE (1) | DE68920800T2 (en) |
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| US5499060A (en) * | 1994-01-04 | 1996-03-12 | Texas Instruments Incorporated | System and method for processing video data |
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| US20020154102A1 (en) * | 2001-02-21 | 2002-10-24 | Huston James R. | System and method for a programmable color rich display controller |
| US7594135B2 (en) * | 2003-12-31 | 2009-09-22 | Sandisk Corporation | Flash memory system startup operation |
| US7736528B2 (en) | 2005-10-12 | 2010-06-15 | Panasonic Corporation | Plasma processing apparatus and plasma processing method |
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-
1988
- 1988-08-30 US US07/238,235 patent/US5148516A/en not_active Expired - Lifetime
-
1989
- 1989-03-08 EP EP89104085A patent/EP0356610B1/en not_active Expired - Lifetime
- 1989-03-08 DE DE68920800T patent/DE68920800T2/en not_active Expired - Fee Related
- 1989-04-19 CA CA000597144A patent/CA1325684C/en not_active Expired - Fee Related
- 1989-08-29 KR KR1019890012311A patent/KR900003730A/en not_active Application Discontinuation
- 1989-08-30 JP JP1224308A patent/JP2760859B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5148516A (en) | 1992-09-15 |
| JPH02113330A (en) | 1990-04-25 |
| JP2760859B2 (en) | 1998-06-04 |
| DE68920800D1 (en) | 1995-03-09 |
| EP0356610A3 (en) | 1992-07-15 |
| EP0356610A2 (en) | 1990-03-07 |
| EP0356610B1 (en) | 1995-01-25 |
| DE68920800T2 (en) | 1995-09-07 |
| KR900003730A (en) | 1990-03-26 |
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