CA1320589C - Twinax interface circuit - Google Patents
Twinax interface circuitInfo
- Publication number
- CA1320589C CA1320589C CA000579456A CA579456A CA1320589C CA 1320589 C CA1320589 C CA 1320589C CA 000579456 A CA000579456 A CA 000579456A CA 579456 A CA579456 A CA 579456A CA 1320589 C CA1320589 C CA 1320589C
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- peripheral
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- address
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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- General Engineering & Computer Science (AREA)
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Abstract
ABSTRACT OF THE DISCLOSURE
An interface circuit is described for use with a plurality of peripherals or attachments connected in data communication with a central computer. The computer sends data messages, each o- which includes the unique addresses of that peripheral to which the particular data message is directed.
The peripheral interface contains areas for stripping and then storing addresses from the message received from the computer.
If the address matches that of the peripheral, the peripheral acts on the message and responds when necessary to the computer with a message return that includes the address.
An interface circuit is described for use with a plurality of peripherals or attachments connected in data communication with a central computer. The computer sends data messages, each o- which includes the unique addresses of that peripheral to which the particular data message is directed.
The peripheral interface contains areas for stripping and then storing addresses from the message received from the computer.
If the address matches that of the peripheral, the peripheral acts on the message and responds when necessary to the computer with a message return that includes the address.
Description
13205~
BACKGROUND OF THE INVENTION
The present invention relates generally to digital data communication, and more particularly to an interface for use in facilitating data communication between a computer and a plurality of peripherals.
To lncrease the utility of digital computers it has become a common practice to connect a central computer to a series of peripherals or attachments, which are typically located remote from the computer in a network configuration.
I'he peripherals are typically a printer, a terminal, a personal computer ~PC) and the like, and each includes its own microprocessor. In order for these peripherals to operate, each must be able to communicate with the central computer in accordance with a common data protocol or format established by the computer.
In order for the computer to be able to communicate selectively with the peripherclls, each of the peripherals is typically assigned a unique acldress. ~ach data stream or message from the computer includes, along with the data directed to the peripheral and sync and parity bits, the address for the peripheral to which the message is intended.
After the peripheral has processed or acted on the data transmitted to it in this ~ashion, the peripheral returns a message to the computer, which includes the address of the peripheral from which the message emanates along with appropriate data and synchronization bits.
To allow the computer to communicate with the peripheral an interface is typically provided for each peripheral to convert the message format received from the computer to a format that can be processed in the peripheral microprocessor. In the known computer peripheral interfaces, ~32~9 the address of the first message frame that is received from the computer is checked to determine if the message is directed to that peripheral; that is, if the address portion of the received message is that of the peripheral. In those cases in which a particular peripheral must respond to (or emulate) multiple addresses, the interface must check the received addresses to all the possible peripheral addresses (typically up to seven). This process requires a not insignificant time.
Moreover, after the conventional attachment determines that the message from the computer is intended for it, and that the peripheral must then respond to the computer, it must pr~vide two bytes of information for every outgoing frame --one byte for data and the second byte for the peripheral address. This is a disadvantage because the microprocessor associated with that peripheral has to save and reproduce the address and perform two write operations for every outgoing frame.
In addition, if the frame of the message from the addressed peripheral to the computer is the last frame in a multi-frame message, the microprocessor in the conventional interface must keep track of the data it is sending to determine that it is sending the last frame, and, instead of sending the peripheral address information it must send the end-of-message d~limiter (typically a three-bit address of binary 111 or seven).
In largs part owing to these requirements, the conventional peripheral interface circuits have been bulky and expensive, typically consisting of as many as 100 integrated circuits mounted on a board. There is thus a present need for a less expensive and less bulky interface for use in connecting a plurality of different peripherals to a central computer and which still allows the logic of the peripileral to conform to the protocol of the computer.
1 3 ~ 60538-975 It is accordingly an object oE the present invention to provide an interEace of the type described which is less costly and less complex than the presently known peripheral interface circuits.
It is another object of the invention to provide a peripheral interface of the type described which Eacilita-tes and speeds up data communication between a peripheral and a computer.
It is a further object of the invention to provide a peripharal interface of the type described which can function with a less complex and thus less expensive microprocessor.
It is yet a further object of the present invention to provide a peripheral interface of the type described which can be used to respond to a plurality of peripheral addresses.
To these ends, the peripheral interEace of the invention inc]udes means for stripping the address bit from the message received from the computer and for comparing the stripped address with its own address. The stripped message is saved and returned to the computer as part of a return message only if there has been a match detected between the received address and the address (or one of the addresses) of the peripheral.
In summary oE the broadest aspect, the present invention provides an interface arrangement for use in facilitating serial data communication between a computer and a plurality of peripherals located remote from the computer, a plurality of interfaces in respective operative association with each of said peripherals, each of said peripherals being assigned a plurality of unique peripheral addresses, wherein a data message including a plurality of data frames is transmitted from the computer to one of said peripherals, each of said data fra~mes including identiEication address data 1 3 2 ~ ~ ~ 9 60538-975 uniquely associated with the pe~ipheral to which the da-ta message is directed, at least one of said interfaces including means Eor receiving and separating the identi:Eication address data from each Erame of a received serial data message, means for storing said unique peripheral addresses, means coupled to said separating means and to said peripheral addresses storing means for storing the separated identification address data, means for comparing the separated identification address data and the stored peripheral addresses, means coupled to said separated address data storing means for combining the separated identification address data with each data frame o:E
the data message to be transmitted serially at a later time by the peripheral when said comparing means detects a predetermined relation between the separated identification address data and the stored perlpheral addresses, and means responsive to said comparison Eor instructing the peripheral associated with said at least one interEace to respond to the received data message at a la-ter time when the separated identification address data bears said predetermined relation to the stored peripheral addresses.
To the accomplishment of the above and such objects as may hereinafter appear, the present inven-tion relates to a peripheral lnterface substantially as defined in the appended claims and as described in the following specifica-tion as considered wi-th the accompanying drawings in which:
FIGURE 1 is a schematic block diagram illustrating one application of the interface of the invention;
FIGURE 2 is a schematic block diagram of the peripheral interface in accordance with an embodiment of the present invention;
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FIGURE 3 is a block diagrarn of the address recognition circuit of the interface of Fig. l;
FIGURE ~ is a schematic logic diagram of the comparator of Fig. 4;
FIGURE 5 is a flow diagram of the transmit control portion of the interface of Fig. l;
FIGURE 6 is a diagram of a typical computer message format that can be processed by the peripheral interface of the invention; and FIGURE 7 is a schematic block diagram of the receive control and zero strip logic circuit of the peripheral interface of Fig. 1.
Fig. 1 illustrates one possible application of the controller or interface circuit of the invention. As therein shown, the inter~ace of the present invention generally designated 10, i5 connected intermediate a central computer .~
(not shown), which may be an IBM computer that transmits data to the peripherals on an IBM twinaxial bus or cable in IBM 5250 protocol, and a host microprocessor 12 which is associated with a peripheral unit, such as a terminal or printer (not otherwise shown), it being understood that in a typical data communication network a plurality, typically up to seven, of different peripherals each having its own microprocessor and interface, are all connected for bilateral data communication with the computer.
As shown, interface 10 is connected to the computer by means of a cabl~ 14, which, as noted, may be an IBM twina~ial cable. A static RAM 16 is connected both to the microprocessor 12 and to interface 10 as well as to a s~stem bus 18. A per se conventional arbitration logic circuit 20 provides signals to the RAM 16 and receives and sends signals to the microprocessor 12. An also per se conventional address decode logic 22 13~0~
decodes address and control signals from the system bus and provides read and write signals to the arbitration logic. As is per se conventional, data is communicated between the computer over the cable 14 to the peripheral via its associated microprocessor 12. The data communication between the computer and the peripheral is in the protocol associated with the computer and is bidirectional but only in one direction at a given time. Tha` is, after the computer sends a message to a particular peripheral, the peripheral sends a message to the computer in response. When the computer sends a message destined to a pa~.ticular peripheral, no other peripheral may respond to that message. The peripheral which finds a match between the three-bit address of the message and its own address (or one of its addresses) when responding, must include the same three bit address in the outgoing message. This is to allow the computer to do some form of checking and address verification.
In the exemplary embodiment of the invention herein described, the computer with which the interface 10 is designed to operate transmits messages in accordance with the protocol or format illustrated in Fig. 6. As therein shown, each message includes a 5-bit synchronization portion and a 3-bit frame synchronization portion, which together constitute the transmission start sequence of the message. The frame sync position is followed by a sync bit which is, in turn, followed in time sequence by an 8-bit data/command word, a 3-bit address, a parity bit and a 3-bit zero fill.
The computer can transmit messages, such as in the format illustrated in Fig. 6, to any one of the peripherals with which it is in network communication. Each of the peripherals is characterized or identified by a unique address, i32~
and the selection of the particular peripheral for which the message is directed is achieved in accordance with -the particular 3-bit address contained in the message. It is the function of the interface 10 of the inventlon to facilitate communication between the central computer and the peripheral host microprocessor, particularly with respect to -the manner in which the address information from the message received from the computer is processed, and in which the address data is inserted into the message sent from the peripheral to the computer.
As shown in Fig. 2, the interface 10 of the invention comprises a receive block 24, a transmit block 26 and a microprocessor interface block 2B. A data signal RX is received by the receiver block 24 in a digital filter 30, which, in a per se conventional manner, removes or filters noise from the input signal.
The output of digita:l filter 30 is applied to a digital phase-locked loop and control circuit 32, which also receives a reference frequency signal, here shown as 16 MHz (Fig. 1~ from a crystal oscillator 3~. The digital phas0-locked loop 32 separates the clock and data from the incoming data stream and generates synchronized clock and data. Several digital phase-locked loops are known and may be used in the circuit of the invention. The clock and data pulses generated by digital phase-locked loop 32 are applied to the remaining portions of the receive block.
The output of digital filter 30 is applied to a frame sync and line idle detect circuit 36, which detects the frame sync bits of the incoming message while ignoring the preceding bit synchronization portion of the message, and provides a filtered input signal to the digital phase-locked loop 32. A
receive control and zero strip logic 38, described in greater ~32~g~
detail below with reference to Fig. 7, receives the output of the frame sync detector 36. Circuit 36 also detects when there is no message activity on the line and generates a line idle signal to control circuit 38. Receive control logic 38, as described below, identifies the various subsections or portions of the message to determine the frame sync, data address and parity portions of the message and produces, as described below, an address time and parity signal at the occurrence of the corresponding address and parity bits of the message.
The address time signal generated in the control logic circuit 38 is applied to an eleven-stage receive shift register 42, in which the 8 data bits and three address bits oE the message are stored. The three address bits of the received message which are stripped and initially stored in register 42, are transferred to and stored in a present address register 4~.
In accordance with the present invention, the three-bit address stripped from the incoming message received from the computer in the manner just described is returned to the computer only if the peripheral with which the interface circuit o~ the invention is associated has to respond to the received messa~e, that is, if there is a match between the three-bit received and stripped address and the address or one of the addresses of the peripheral stored in the address select register ~6 that is included in the microprocessor interface block 28 of the interface circuit, and into which, according to a preferred embodiment of the invention, the reference address or addresses of the peripheral are written from the microprocessor.
In a data communication network that includes a plurality of attachments or peripherals each having its own uni~ue address, stored in its address select register, each peripheral will receive a data message transmitted by the computer that is directed to one of these peripherals. Each of 132~
the peripherals that has an interface circuit of the invention as illustrated in Fig. 2 will receive that messaye, but only the one peripheral to which the message is directed will Lespond. All of the interface circuits will strip the three-bit address from the received message and store it in their respective present address register. However, since the stLipped three-bit address will match for only one of the peripherals, the one to which the message is intended, only that peripheral will initiate the transmission of a return message to the computer. Significantly, and in contrast to the prior art, the microprocessor associated with that peripheral will not have to supply any address inforrnation to the outgoing message, since tnat information will be provided from the address information that was stripped from the received message and stored in th~ present address register 44 of the addressed peripheral's interface circuit.
To -this end, as shown in Fig. 3, which illustrates the address recognition circuit in greater detail than in Fig. 2, the three-bit signal stored in the present address register 44 is applied to ths inputs of a 3-to-8 line encoder 48 which converts the 3-bit address to a 7-bit address signal. That signal, in turn, is applied to the seven-bits (AO-A6) of a 7-bit comparator 50, illustrated in greater detail in Fig. 4, where it is comp~red to the contents of the address select register 46. To this end comparator 50 receives at its other set of inputs BO-B6. When a match is detected between any corresponding bits A and B in the comparator 50, an address match signal is ~enerated at the output of the comparator.
In an alternate design contemplated by the present invention, the camparison of the contents may be read by the peripheral's microprocessor, which can then compare that address against the peripheral's address under the control of ~32~8~
appropriate software in which the reference address is employed in the cornputer ^outine. When a comparison between the reference address and the address stripped from the received message is positive, e.g., when an address match signal is generated in comparator 50, that information is applied to the associated microprocessor.
If the result of the comparison of the address removed from the incoming message and the stored address is positive, as described above, the associated peripheral will analyze the data portion (bi s DO-D7) of the received message frame and respond accordingly. That is, after the peripheral microprocessor raceives the incoming message it will analyze it and perform an a?propriate operation on the incoming data, e.g., send a message back to the computer.~
If, on the other hand, the comparison is negative, the peripheral miGroprocessor ignores the entire message until a new message, which may include the peripheral's address is received from the computer.
~ eturning to the case in which the address comparison is positive, the address match signal places an address match bit in the interrupt status register 52 which causes an interrupt control 54 to send interrupt signals INTl or INT2 to the microprocessor. The interrupt signals when received at the microprocessor thus cause an interruption in the procedure or routine that is then being carried out at the peripheral microprocessor and, in accordance with the microprocessor's software control, causes the microprocessor to respond to the received message from the computer, which, in accordance with the positive address comparison mode, is directed for that particular peripheral.
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~ eturning to the receive block 24 of the interface circuit of the invention, the data bits D0-D7 from the incoming message frame are removed from the incoming message frame and stored in one level of a two-level buffer register designated as the receive FLFO 58. The received data bits are applied through a bus 60 and a bus 61 and through an I/0 buffer 63 to the microprocessor. The receive control logic 38 also provides the parity bit from the received frame to a parity check frame check 62 which compares the incoming parity bit with an internally generated parity bit (from the receive shift register 42) to determine the validity of the incoming message frame. The result of the parity check carried out in parity circuit 62 is stored in a receive status register 64. The bit stored in register 6~ is sent to the microprocessor 12 via bus 61.
The function of the transmit block 26 of the interface circuit is to reconstitute a frame or message for transmission to the computer having the same protocol or standard as the received message frame illustrated in Fig. 6. To this end the microprocessor 1.~ transmits via buses 60, 61 to a zero fill register 66 the required number or count of the zero fill bits, here shown as three. That count is used to initialize a counter contained in a zero fill logic 68, which counts down and then transmits the zero fill bit to transmit shift register 70.
The shift register also receives the eight data bits to be included in the message to be transmitted from the addressed peripheral to the computer. Those data bits are received from the microprocessor 12 through buffer 63 and over buses 60, 61 to a transmit bu~er 72 from which the data bits to be included in the transmitted message frame are applied to transmit shift register 70.
1~2~
A transmit control 74 executes a procedure, as described below with reference to Fig. ~ and controls a parity and frame genera~ion circuit 76, which generates the required frame sync, sync bit and parity bits transmit control also sends a status bit to a two-bit transmit status register 78, which stores tha~ information and communicates it to the microprocessor to advise the latter of the readiness of the circuit to transmit a new message to the computer.
The outputs of the present address register 44 (three address bits of '_he peripheral), transmit shift register 70 (the zero fill and data bits), and the parity and frame generation circuit 76 (the frame sync , sync and parity bits) are combined in a multiplexer 7~, when a message in the desired format and including the zero fill data is formed and employed to the input of a Manchester encoder 80. Encoder 80 receives timing or clock signals from a bit rate generator 82, which receives a clock signal from the cr~stal oscillator 34. The output of the en~oder 80 is conveyed to a transmit-retiming and control circuit ~, which generates from the encoded signal it receives from the Manchester encoder 80, a true and a delayed inverted message signals TX and DTX, as well as the enabling signal TXE~ which enables the drivers in the cable 14 as shown in Fig. l, thereby to allow for transmission of the data message on cable 14 to the computer.
Turning now to Fig. 5, there is shown in flow ~hart or flow diagram form the control sequence performed by transmit control 74 with respect to the transmission of a data message from the peripheral to the computer. In Fig. 5, the states (or collection of few states) are labeled with an "S" and certain states have two-way branches (decision) where an input condition is checked to determine the next state.
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SO is the idle state. Since it has two arrows coming out of this state, it is a decision-making state. The input condition checked is Data Available (meaning that data is to be transmitted because the external microprocessor has supplied new data). If data is available, then the sequences go to the next state (Sl). If data is not available, go to SO (meaning the next state is the same as the present state so that the transmit control is to keep checking for data a~ailable). This state is one clock long.
Sl is the transmit five ones state. The five one's ~l's) of the transmit start or bit synchronization sequence are transmitted in this state. This state is five clocks long. S2 is the transmit :rame sync pattern state. The frame sync pattern of the transmit start sequence is transmitted in this state. This state is three clocks long. S3 is the transmit sync bit state. The s~vnc bit (a one) is transmitted in this state. This sta e is one clock long.
S4 is the transmit data state. The eight data bits (DO-D7) are transmitted in this state. At the end of the last data bit (D7) a decision is made based on data available to determine the next state. If more data is available, then the three bits of the present address register 44 are transmitted.
If no more data is available, then an end of message (111) signal is transmitted. This state is eight clocks long. If no more data is available, the sequence goes to the S5a state which is the transmit end of message (111) state during which the 111 pattern is transmitted. The S5a state is three clocks long.
The sequence then goes to the S6a state which is the transmit parity state during which the parity bit of the frame is transmitted. This state is one clock long. The next state is S7a which is the transmit three zero bits state during which ~32~8~
the three zero bits of the frame are transmitted. At the conclusion of this state, the sequence goes to state SO and the entire process is repeated. The S7a state is three clocks long.
If, on the other hand, more data is available for transmission to the computer, the sequence from state S4 goes to the S5b state~. which is the transmit present address state during which the three bits of the present address register ~4 are transmitted. This state is three clocks long.
The next state is the routine S6b which is the transmit parity state, during which the parity bit of the frame is transmitted. This state is one clock long. S7b is the transmit zero bits state during which the three zero bits of the frame along with the interframe zero fill bits are transmitted. ~t the conclusion of this state, the routine or sequence goes to state S3 and transmits the next frame. This state is three plus clocks long depending on the number of zero fill bits transmitted.
As shown in Fig. 7, the receive control circuit 38 includes an in-progress flip-flop 86 which receives a frame sync detect signal at its CLK input from the frame sync detect circuit 36. Flip-flop 86 also receives -the Line Idle signal from circuit 36 at its inverted CLR input and a logic "1" at its D input. Th~ output of flip-flop 86 at its Q terminal is the In-Progress signal.
Also included in receive control circuit 38 is a sync bit detected flip-flop 88, which receives the Receive Data and Receive Clock si3nals from the digital phase-locked loop 32.
The Receive Data signal is applied to the D input and the Receive Clock signal is applied to the CLK input of flip-flop 88. The output of flip~flop 88 at the Q terminal is the S~nc Bit Detect signal.
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The In-Progress signal from flip-flop 88 and the Sync Bit Detect signa: from fllp-flop 88 are respectively applied to the enable and clear inputs of a bit counter 90, which also receives the ReceiYe Clock signal at its CLK input. The outputs of the counter are applied to a decoder 92, which receives and decodes the outputs of the bit counter 90 and produces the Add-ess Time, Parity Time, and Zero Time Signals.
The latter is ap~lied to the inverted CLR terminal of flip-flop 8~.
Flip-flop 86 produces an In-Progress signal to enable the bit counter 90 upon the detection of a frame sync, which occurs when a message packet reception process is occurring.
When the message is terminated or when there is no message activity on the line, the Line Idle signal clears flip-flop 86 and removes the In-Progress signal. The Sync Bit Detect signal produced in flip-flop 88 clears bit counter 90 as an indication of the beginning of a new message frame so as to cause bit counter 90 to start counting from an initial count.
The counting operation of bit counter 90, which counts the number of bits within a received message frame, begins when a sync bit is de ected. Bit counter 90 continues to count u~til the count of 13 is reached at which time a Zero Time signal is produced; that signal is, as noted, applied to the inverted CLR terminal of flip-flop 88 to remove the Sync Bit Detect signal from the CLR terminal of the bit counter 90, to cause bit counter 90 to stop counting, and to remain doing so until a new frame sync bit is detected.
During the counts of 1 through 8 of bit counter 90 the interface receiver is receiving the eight data bits DU-D7 of the message frame; during the counts of 9-10-11, the receiver is receiving the address bits AO-A2; at the count of 12 it is parity time during which the receiver is receiving the parity bit P; and a count of 13 is zero time. To this end, the count 1~20~$~
in bit counter 90 is decoded in decoder 92, which generates an Address Time signal for a detected count of 9, 10 or 11, a Parity Time signal for a count of 12, and a Zero Time signal for a count of 13.
During the count of 1 through 8, no signal is produced by decoder 90 which causes the eight data bits to be transferred to the 8-bit section of receive shift register 42.
During the Address Time, which occurs the ne~t 3 counts, the three address bi s are transferred and stored in the other 3-bit section of receive shift register 42, as described above. The Parity Time signal is applied to parity check circuit 62, and, as described, the Zero Time signal is returned to the flip-flop 88 to thereby carry out the zero strip logic function in circuit 38.
It will be appreciated from the foregoing description of a preferred embodiment that the peripheral interface of the invention provides improved communication between a computer and a peripheral. It will further be appreciated that modifications to the described embodiment may be made without necessarily departing from the spirit and scope of the appended claims.
BACKGROUND OF THE INVENTION
The present invention relates generally to digital data communication, and more particularly to an interface for use in facilitating data communication between a computer and a plurality of peripherals.
To lncrease the utility of digital computers it has become a common practice to connect a central computer to a series of peripherals or attachments, which are typically located remote from the computer in a network configuration.
I'he peripherals are typically a printer, a terminal, a personal computer ~PC) and the like, and each includes its own microprocessor. In order for these peripherals to operate, each must be able to communicate with the central computer in accordance with a common data protocol or format established by the computer.
In order for the computer to be able to communicate selectively with the peripherclls, each of the peripherals is typically assigned a unique acldress. ~ach data stream or message from the computer includes, along with the data directed to the peripheral and sync and parity bits, the address for the peripheral to which the message is intended.
After the peripheral has processed or acted on the data transmitted to it in this ~ashion, the peripheral returns a message to the computer, which includes the address of the peripheral from which the message emanates along with appropriate data and synchronization bits.
To allow the computer to communicate with the peripheral an interface is typically provided for each peripheral to convert the message format received from the computer to a format that can be processed in the peripheral microprocessor. In the known computer peripheral interfaces, ~32~9 the address of the first message frame that is received from the computer is checked to determine if the message is directed to that peripheral; that is, if the address portion of the received message is that of the peripheral. In those cases in which a particular peripheral must respond to (or emulate) multiple addresses, the interface must check the received addresses to all the possible peripheral addresses (typically up to seven). This process requires a not insignificant time.
Moreover, after the conventional attachment determines that the message from the computer is intended for it, and that the peripheral must then respond to the computer, it must pr~vide two bytes of information for every outgoing frame --one byte for data and the second byte for the peripheral address. This is a disadvantage because the microprocessor associated with that peripheral has to save and reproduce the address and perform two write operations for every outgoing frame.
In addition, if the frame of the message from the addressed peripheral to the computer is the last frame in a multi-frame message, the microprocessor in the conventional interface must keep track of the data it is sending to determine that it is sending the last frame, and, instead of sending the peripheral address information it must send the end-of-message d~limiter (typically a three-bit address of binary 111 or seven).
In largs part owing to these requirements, the conventional peripheral interface circuits have been bulky and expensive, typically consisting of as many as 100 integrated circuits mounted on a board. There is thus a present need for a less expensive and less bulky interface for use in connecting a plurality of different peripherals to a central computer and which still allows the logic of the peripileral to conform to the protocol of the computer.
1 3 ~ 60538-975 It is accordingly an object oE the present invention to provide an interEace of the type described which is less costly and less complex than the presently known peripheral interface circuits.
It is another object of the invention to provide a peripheral interface of the type described which Eacilita-tes and speeds up data communication between a peripheral and a computer.
It is a further object of the invention to provide a peripharal interface of the type described which can function with a less complex and thus less expensive microprocessor.
It is yet a further object of the present invention to provide a peripheral interface of the type described which can be used to respond to a plurality of peripheral addresses.
To these ends, the peripheral interEace of the invention inc]udes means for stripping the address bit from the message received from the computer and for comparing the stripped address with its own address. The stripped message is saved and returned to the computer as part of a return message only if there has been a match detected between the received address and the address (or one of the addresses) of the peripheral.
In summary oE the broadest aspect, the present invention provides an interface arrangement for use in facilitating serial data communication between a computer and a plurality of peripherals located remote from the computer, a plurality of interfaces in respective operative association with each of said peripherals, each of said peripherals being assigned a plurality of unique peripheral addresses, wherein a data message including a plurality of data frames is transmitted from the computer to one of said peripherals, each of said data fra~mes including identiEication address data 1 3 2 ~ ~ ~ 9 60538-975 uniquely associated with the pe~ipheral to which the da-ta message is directed, at least one of said interfaces including means Eor receiving and separating the identi:Eication address data from each Erame of a received serial data message, means for storing said unique peripheral addresses, means coupled to said separating means and to said peripheral addresses storing means for storing the separated identification address data, means for comparing the separated identification address data and the stored peripheral addresses, means coupled to said separated address data storing means for combining the separated identification address data with each data frame o:E
the data message to be transmitted serially at a later time by the peripheral when said comparing means detects a predetermined relation between the separated identification address data and the stored perlpheral addresses, and means responsive to said comparison Eor instructing the peripheral associated with said at least one interEace to respond to the received data message at a la-ter time when the separated identification address data bears said predetermined relation to the stored peripheral addresses.
To the accomplishment of the above and such objects as may hereinafter appear, the present inven-tion relates to a peripheral lnterface substantially as defined in the appended claims and as described in the following specifica-tion as considered wi-th the accompanying drawings in which:
FIGURE 1 is a schematic block diagram illustrating one application of the interface of the invention;
FIGURE 2 is a schematic block diagram of the peripheral interface in accordance with an embodiment of the present invention;
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FIGURE 3 is a block diagrarn of the address recognition circuit of the interface of Fig. l;
FIGURE ~ is a schematic logic diagram of the comparator of Fig. 4;
FIGURE 5 is a flow diagram of the transmit control portion of the interface of Fig. l;
FIGURE 6 is a diagram of a typical computer message format that can be processed by the peripheral interface of the invention; and FIGURE 7 is a schematic block diagram of the receive control and zero strip logic circuit of the peripheral interface of Fig. 1.
Fig. 1 illustrates one possible application of the controller or interface circuit of the invention. As therein shown, the inter~ace of the present invention generally designated 10, i5 connected intermediate a central computer .~
(not shown), which may be an IBM computer that transmits data to the peripherals on an IBM twinaxial bus or cable in IBM 5250 protocol, and a host microprocessor 12 which is associated with a peripheral unit, such as a terminal or printer (not otherwise shown), it being understood that in a typical data communication network a plurality, typically up to seven, of different peripherals each having its own microprocessor and interface, are all connected for bilateral data communication with the computer.
As shown, interface 10 is connected to the computer by means of a cabl~ 14, which, as noted, may be an IBM twina~ial cable. A static RAM 16 is connected both to the microprocessor 12 and to interface 10 as well as to a s~stem bus 18. A per se conventional arbitration logic circuit 20 provides signals to the RAM 16 and receives and sends signals to the microprocessor 12. An also per se conventional address decode logic 22 13~0~
decodes address and control signals from the system bus and provides read and write signals to the arbitration logic. As is per se conventional, data is communicated between the computer over the cable 14 to the peripheral via its associated microprocessor 12. The data communication between the computer and the peripheral is in the protocol associated with the computer and is bidirectional but only in one direction at a given time. Tha` is, after the computer sends a message to a particular peripheral, the peripheral sends a message to the computer in response. When the computer sends a message destined to a pa~.ticular peripheral, no other peripheral may respond to that message. The peripheral which finds a match between the three-bit address of the message and its own address (or one of its addresses) when responding, must include the same three bit address in the outgoing message. This is to allow the computer to do some form of checking and address verification.
In the exemplary embodiment of the invention herein described, the computer with which the interface 10 is designed to operate transmits messages in accordance with the protocol or format illustrated in Fig. 6. As therein shown, each message includes a 5-bit synchronization portion and a 3-bit frame synchronization portion, which together constitute the transmission start sequence of the message. The frame sync position is followed by a sync bit which is, in turn, followed in time sequence by an 8-bit data/command word, a 3-bit address, a parity bit and a 3-bit zero fill.
The computer can transmit messages, such as in the format illustrated in Fig. 6, to any one of the peripherals with which it is in network communication. Each of the peripherals is characterized or identified by a unique address, i32~
and the selection of the particular peripheral for which the message is directed is achieved in accordance with -the particular 3-bit address contained in the message. It is the function of the interface 10 of the inventlon to facilitate communication between the central computer and the peripheral host microprocessor, particularly with respect to -the manner in which the address information from the message received from the computer is processed, and in which the address data is inserted into the message sent from the peripheral to the computer.
As shown in Fig. 2, the interface 10 of the invention comprises a receive block 24, a transmit block 26 and a microprocessor interface block 2B. A data signal RX is received by the receiver block 24 in a digital filter 30, which, in a per se conventional manner, removes or filters noise from the input signal.
The output of digita:l filter 30 is applied to a digital phase-locked loop and control circuit 32, which also receives a reference frequency signal, here shown as 16 MHz (Fig. 1~ from a crystal oscillator 3~. The digital phas0-locked loop 32 separates the clock and data from the incoming data stream and generates synchronized clock and data. Several digital phase-locked loops are known and may be used in the circuit of the invention. The clock and data pulses generated by digital phase-locked loop 32 are applied to the remaining portions of the receive block.
The output of digital filter 30 is applied to a frame sync and line idle detect circuit 36, which detects the frame sync bits of the incoming message while ignoring the preceding bit synchronization portion of the message, and provides a filtered input signal to the digital phase-locked loop 32. A
receive control and zero strip logic 38, described in greater ~32~g~
detail below with reference to Fig. 7, receives the output of the frame sync detector 36. Circuit 36 also detects when there is no message activity on the line and generates a line idle signal to control circuit 38. Receive control logic 38, as described below, identifies the various subsections or portions of the message to determine the frame sync, data address and parity portions of the message and produces, as described below, an address time and parity signal at the occurrence of the corresponding address and parity bits of the message.
The address time signal generated in the control logic circuit 38 is applied to an eleven-stage receive shift register 42, in which the 8 data bits and three address bits oE the message are stored. The three address bits of the received message which are stripped and initially stored in register 42, are transferred to and stored in a present address register 4~.
In accordance with the present invention, the three-bit address stripped from the incoming message received from the computer in the manner just described is returned to the computer only if the peripheral with which the interface circuit o~ the invention is associated has to respond to the received messa~e, that is, if there is a match between the three-bit received and stripped address and the address or one of the addresses of the peripheral stored in the address select register ~6 that is included in the microprocessor interface block 28 of the interface circuit, and into which, according to a preferred embodiment of the invention, the reference address or addresses of the peripheral are written from the microprocessor.
In a data communication network that includes a plurality of attachments or peripherals each having its own uni~ue address, stored in its address select register, each peripheral will receive a data message transmitted by the computer that is directed to one of these peripherals. Each of 132~
the peripherals that has an interface circuit of the invention as illustrated in Fig. 2 will receive that messaye, but only the one peripheral to which the message is directed will Lespond. All of the interface circuits will strip the three-bit address from the received message and store it in their respective present address register. However, since the stLipped three-bit address will match for only one of the peripherals, the one to which the message is intended, only that peripheral will initiate the transmission of a return message to the computer. Significantly, and in contrast to the prior art, the microprocessor associated with that peripheral will not have to supply any address inforrnation to the outgoing message, since tnat information will be provided from the address information that was stripped from the received message and stored in th~ present address register 44 of the addressed peripheral's interface circuit.
To -this end, as shown in Fig. 3, which illustrates the address recognition circuit in greater detail than in Fig. 2, the three-bit signal stored in the present address register 44 is applied to ths inputs of a 3-to-8 line encoder 48 which converts the 3-bit address to a 7-bit address signal. That signal, in turn, is applied to the seven-bits (AO-A6) of a 7-bit comparator 50, illustrated in greater detail in Fig. 4, where it is comp~red to the contents of the address select register 46. To this end comparator 50 receives at its other set of inputs BO-B6. When a match is detected between any corresponding bits A and B in the comparator 50, an address match signal is ~enerated at the output of the comparator.
In an alternate design contemplated by the present invention, the camparison of the contents may be read by the peripheral's microprocessor, which can then compare that address against the peripheral's address under the control of ~32~8~
appropriate software in which the reference address is employed in the cornputer ^outine. When a comparison between the reference address and the address stripped from the received message is positive, e.g., when an address match signal is generated in comparator 50, that information is applied to the associated microprocessor.
If the result of the comparison of the address removed from the incoming message and the stored address is positive, as described above, the associated peripheral will analyze the data portion (bi s DO-D7) of the received message frame and respond accordingly. That is, after the peripheral microprocessor raceives the incoming message it will analyze it and perform an a?propriate operation on the incoming data, e.g., send a message back to the computer.~
If, on the other hand, the comparison is negative, the peripheral miGroprocessor ignores the entire message until a new message, which may include the peripheral's address is received from the computer.
~ eturning to the case in which the address comparison is positive, the address match signal places an address match bit in the interrupt status register 52 which causes an interrupt control 54 to send interrupt signals INTl or INT2 to the microprocessor. The interrupt signals when received at the microprocessor thus cause an interruption in the procedure or routine that is then being carried out at the peripheral microprocessor and, in accordance with the microprocessor's software control, causes the microprocessor to respond to the received message from the computer, which, in accordance with the positive address comparison mode, is directed for that particular peripheral.
~L 3 2 ~
~ eturning to the receive block 24 of the interface circuit of the invention, the data bits D0-D7 from the incoming message frame are removed from the incoming message frame and stored in one level of a two-level buffer register designated as the receive FLFO 58. The received data bits are applied through a bus 60 and a bus 61 and through an I/0 buffer 63 to the microprocessor. The receive control logic 38 also provides the parity bit from the received frame to a parity check frame check 62 which compares the incoming parity bit with an internally generated parity bit (from the receive shift register 42) to determine the validity of the incoming message frame. The result of the parity check carried out in parity circuit 62 is stored in a receive status register 64. The bit stored in register 6~ is sent to the microprocessor 12 via bus 61.
The function of the transmit block 26 of the interface circuit is to reconstitute a frame or message for transmission to the computer having the same protocol or standard as the received message frame illustrated in Fig. 6. To this end the microprocessor 1.~ transmits via buses 60, 61 to a zero fill register 66 the required number or count of the zero fill bits, here shown as three. That count is used to initialize a counter contained in a zero fill logic 68, which counts down and then transmits the zero fill bit to transmit shift register 70.
The shift register also receives the eight data bits to be included in the message to be transmitted from the addressed peripheral to the computer. Those data bits are received from the microprocessor 12 through buffer 63 and over buses 60, 61 to a transmit bu~er 72 from which the data bits to be included in the transmitted message frame are applied to transmit shift register 70.
1~2~
A transmit control 74 executes a procedure, as described below with reference to Fig. ~ and controls a parity and frame genera~ion circuit 76, which generates the required frame sync, sync bit and parity bits transmit control also sends a status bit to a two-bit transmit status register 78, which stores tha~ information and communicates it to the microprocessor to advise the latter of the readiness of the circuit to transmit a new message to the computer.
The outputs of the present address register 44 (three address bits of '_he peripheral), transmit shift register 70 (the zero fill and data bits), and the parity and frame generation circuit 76 (the frame sync , sync and parity bits) are combined in a multiplexer 7~, when a message in the desired format and including the zero fill data is formed and employed to the input of a Manchester encoder 80. Encoder 80 receives timing or clock signals from a bit rate generator 82, which receives a clock signal from the cr~stal oscillator 34. The output of the en~oder 80 is conveyed to a transmit-retiming and control circuit ~, which generates from the encoded signal it receives from the Manchester encoder 80, a true and a delayed inverted message signals TX and DTX, as well as the enabling signal TXE~ which enables the drivers in the cable 14 as shown in Fig. l, thereby to allow for transmission of the data message on cable 14 to the computer.
Turning now to Fig. 5, there is shown in flow ~hart or flow diagram form the control sequence performed by transmit control 74 with respect to the transmission of a data message from the peripheral to the computer. In Fig. 5, the states (or collection of few states) are labeled with an "S" and certain states have two-way branches (decision) where an input condition is checked to determine the next state.
~2~
SO is the idle state. Since it has two arrows coming out of this state, it is a decision-making state. The input condition checked is Data Available (meaning that data is to be transmitted because the external microprocessor has supplied new data). If data is available, then the sequences go to the next state (Sl). If data is not available, go to SO (meaning the next state is the same as the present state so that the transmit control is to keep checking for data a~ailable). This state is one clock long.
Sl is the transmit five ones state. The five one's ~l's) of the transmit start or bit synchronization sequence are transmitted in this state. This state is five clocks long. S2 is the transmit :rame sync pattern state. The frame sync pattern of the transmit start sequence is transmitted in this state. This state is three clocks long. S3 is the transmit sync bit state. The s~vnc bit (a one) is transmitted in this state. This sta e is one clock long.
S4 is the transmit data state. The eight data bits (DO-D7) are transmitted in this state. At the end of the last data bit (D7) a decision is made based on data available to determine the next state. If more data is available, then the three bits of the present address register 44 are transmitted.
If no more data is available, then an end of message (111) signal is transmitted. This state is eight clocks long. If no more data is available, the sequence goes to the S5a state which is the transmit end of message (111) state during which the 111 pattern is transmitted. The S5a state is three clocks long.
The sequence then goes to the S6a state which is the transmit parity state during which the parity bit of the frame is transmitted. This state is one clock long. The next state is S7a which is the transmit three zero bits state during which ~32~8~
the three zero bits of the frame are transmitted. At the conclusion of this state, the sequence goes to state SO and the entire process is repeated. The S7a state is three clocks long.
If, on the other hand, more data is available for transmission to the computer, the sequence from state S4 goes to the S5b state~. which is the transmit present address state during which the three bits of the present address register ~4 are transmitted. This state is three clocks long.
The next state is the routine S6b which is the transmit parity state, during which the parity bit of the frame is transmitted. This state is one clock long. S7b is the transmit zero bits state during which the three zero bits of the frame along with the interframe zero fill bits are transmitted. ~t the conclusion of this state, the routine or sequence goes to state S3 and transmits the next frame. This state is three plus clocks long depending on the number of zero fill bits transmitted.
As shown in Fig. 7, the receive control circuit 38 includes an in-progress flip-flop 86 which receives a frame sync detect signal at its CLK input from the frame sync detect circuit 36. Flip-flop 86 also receives -the Line Idle signal from circuit 36 at its inverted CLR input and a logic "1" at its D input. Th~ output of flip-flop 86 at its Q terminal is the In-Progress signal.
Also included in receive control circuit 38 is a sync bit detected flip-flop 88, which receives the Receive Data and Receive Clock si3nals from the digital phase-locked loop 32.
The Receive Data signal is applied to the D input and the Receive Clock signal is applied to the CLK input of flip-flop 88. The output of flip~flop 88 at the Q terminal is the S~nc Bit Detect signal.
1320~
The In-Progress signal from flip-flop 88 and the Sync Bit Detect signa: from fllp-flop 88 are respectively applied to the enable and clear inputs of a bit counter 90, which also receives the ReceiYe Clock signal at its CLK input. The outputs of the counter are applied to a decoder 92, which receives and decodes the outputs of the bit counter 90 and produces the Add-ess Time, Parity Time, and Zero Time Signals.
The latter is ap~lied to the inverted CLR terminal of flip-flop 8~.
Flip-flop 86 produces an In-Progress signal to enable the bit counter 90 upon the detection of a frame sync, which occurs when a message packet reception process is occurring.
When the message is terminated or when there is no message activity on the line, the Line Idle signal clears flip-flop 86 and removes the In-Progress signal. The Sync Bit Detect signal produced in flip-flop 88 clears bit counter 90 as an indication of the beginning of a new message frame so as to cause bit counter 90 to start counting from an initial count.
The counting operation of bit counter 90, which counts the number of bits within a received message frame, begins when a sync bit is de ected. Bit counter 90 continues to count u~til the count of 13 is reached at which time a Zero Time signal is produced; that signal is, as noted, applied to the inverted CLR terminal of flip-flop 88 to remove the Sync Bit Detect signal from the CLR terminal of the bit counter 90, to cause bit counter 90 to stop counting, and to remain doing so until a new frame sync bit is detected.
During the counts of 1 through 8 of bit counter 90 the interface receiver is receiving the eight data bits DU-D7 of the message frame; during the counts of 9-10-11, the receiver is receiving the address bits AO-A2; at the count of 12 it is parity time during which the receiver is receiving the parity bit P; and a count of 13 is zero time. To this end, the count 1~20~$~
in bit counter 90 is decoded in decoder 92, which generates an Address Time signal for a detected count of 9, 10 or 11, a Parity Time signal for a count of 12, and a Zero Time signal for a count of 13.
During the count of 1 through 8, no signal is produced by decoder 90 which causes the eight data bits to be transferred to the 8-bit section of receive shift register 42.
During the Address Time, which occurs the ne~t 3 counts, the three address bi s are transferred and stored in the other 3-bit section of receive shift register 42, as described above. The Parity Time signal is applied to parity check circuit 62, and, as described, the Zero Time signal is returned to the flip-flop 88 to thereby carry out the zero strip logic function in circuit 38.
It will be appreciated from the foregoing description of a preferred embodiment that the peripheral interface of the invention provides improved communication between a computer and a peripheral. It will further be appreciated that modifications to the described embodiment may be made without necessarily departing from the spirit and scope of the appended claims.
Claims
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. An interface arrangement for use in facilitating serial data communication between a computer and a plurality of peripherals located remote from the computer, a plurality of interfaces in respective operative association with each of said peripherals, each of said peripherals being assigned a plurality of unique peripheral addresses, wherein a data message including a plurality of data frames is transmitted from the computer to one of said peripherals, each of said data frames including identification address data uniquely associated with the peripheral to which the data message is directed, at least one of said interfaces including means for receiving and separating the identification address data from each frame of a received serial data message, means for storing said unique peripheral addresses, means coupled to said separating means and to said peripheral addresses storing means for storing the separated identification address data, means for comparing the separated identification address data and the stored peripheral addresses, means coupled to said separated address data storing means for combining the separated identification address data with each data frame of the data message to be transmitted serially at a later time by the peripheral when said comparing means detects a predetermined relation between the separated identification address data and the stored peripheral addresses, and means responsive to said comparison for instructing the peripheral associated with said at least one interface to respond to the received data message at a later time when the separated identification address data bears said predetermined relation to the stored peripheral addresses.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10715987A | 1987-10-13 | 1987-10-13 | |
| US107,159 | 1987-10-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1320589C true CA1320589C (en) | 1993-07-20 |
Family
ID=22315147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000579456A Expired - Fee Related CA1320589C (en) | 1987-10-13 | 1988-10-06 | Twinax interface circuit |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH01243743A (en) |
| CA (1) | CA1320589C (en) |
| GB (1) | GB2211006B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2255477A (en) * | 1991-03-21 | 1992-11-04 | Grey Cell Systems Ltd | Apparatus for the connection of computers and associated peripherals |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3573741A (en) * | 1968-07-11 | 1971-04-06 | Ibm | Control unit for input/output devices |
| US3833930A (en) * | 1973-01-12 | 1974-09-03 | Burroughs Corp | Input/output system for a microprogram digital computer |
| US4183084A (en) * | 1977-06-06 | 1980-01-08 | Digital Equipment Corporation | Secondary storage facility with serial transfer of control messages |
| EP0116098B1 (en) * | 1983-01-31 | 1988-06-22 | Unisys Corporation | Peripheral controller for i/o subsystem using slow devices |
-
1988
- 1988-09-28 GB GB8822698A patent/GB2211006B/en not_active Expired - Lifetime
- 1988-10-06 CA CA000579456A patent/CA1320589C/en not_active Expired - Fee Related
- 1988-10-12 JP JP63256871A patent/JPH01243743A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01243743A (en) | 1989-09-28 |
| GB2211006B (en) | 1992-06-03 |
| GB2211006A (en) | 1989-06-21 |
| GB8822698D0 (en) | 1988-11-02 |
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