CA1309160C - Sub-range type decoder - Google Patents

Abstract

ABSTRACT
This invention relates to a subrange-type decoder equalizing A/D converter used for a transmission system that samples a television signal at a specified sampling frequency. The system first transmits a sampled value and a test signal for detecting the transmission characteristics of a transmission path. The system then decodes the sampled value with a decoder and equalizes the transmission characteristics of the transmission path using the test signal.

Description

sUB--R~NGE TYPE DECODER 1 3 0 9 1 6 a This is a division of copending Canadian Patent Application Serial No. 577,859, which was filed on September 20, 1988.
BACKGROUND OF THE INVENT~ON
FIELD OF THE INVENTION
This invention relates to a decoding equalizer for a sampled value transmission system of high definition television signal, such as MUSE (Multiple Sub-Nyquist Sampling Encoding) system, and to a subrange-type A/D
converter us~d for the decoding equalizer and suited to implement the automatic e~lalization of the transmission characteristics of the transmission system.
DESCRIPTION OF THE RELATED ART
The conventi~nal technique for equalizing the transmission path characteristics for the transmission of sampled values produced by offset sampling, such as in the MUSE system, employs standard rece.ivers on the part of the receiver and implements pre-egualization by an encoder on the part of the transmitter so that the receivers have satisfactory reproduction characteristics. However, this technique fails in the achievement of effective pre-equalization if there exists the variability of characteristics among the standard receivers. Another problem is that it necessitates distinct equalization when supplying a signal to different information media such as a BS (broadcasting satellite) system and a 22 GHz ground , 1 3~7 1, ~o system.
In the technique of automatic equalization of transmission characteristics for the analog signal transmission of high definition television signal, in which a certain unit impulse signal is inserted as a test signal in the television signal and the characteristics of t~e transmission path is detected through the subsequent signal processing as disclosed in JP~A-62-172~26, it necessitates an A/D converter of 16.2 MXz clock rate for the trun~ system and an A/D converter of 32.4 MHz clock rate for the equalizing system.

SUMMARY OF T~E I~ENTION
An object of this invention is to provide a decoding equalizer capable of equalizing an offset sampled signal to meet invaria~ly satisfactory characteristics on the part of the receiver.
Another ob;ect of this invention is to provlde a decoding equalizer which is simple in circuit arrangement and easy in circuit design.
A further obiect of this invention is to provicle ,~.
subrange-type A/D con~erter used for the above-mentioned decoding equalizer and operative to implement both ~he A/D
conversion o~ the television signal and the A/D conversion of the test signal ~or automatic equa1ization without , ' . .

1 3~q 1 60 increasing the complsxity of the circuit arrangement.
According to one aspect of the invention there is provided a subrange-type decoder equalizing A/D
converter used for a transmission system which samples a television signal at a specified sampling frequency, transmits a sampled value and a test signal for detecting the transmission characteristics of a transmission path, decodes the sampled value of a decoder, and equalizes the transmission characteristics of the transmission path using the test signal, the subrange-type A/D converter comprising A/D converters connected sequentially in a plurality of stages, a fore-stage A/D converter having a driving clock frequency which is a multiple of a driving clock frequency of a back-stage A/D converter.

BRIEF DESCRIPTION OF THE DRAWINGS
The present invention taken in conjunction with the invention disclosed in copending Canadian Patent Application Serial No. 577,859, which was ~iled on September 20, 1988, will be described hereinbelow with the aid o~ ~he accompanying drawings, in which:
Fig. l is a block diagram showing the first embodiment of the inventive decoding equalizer;
Fig. 2 is a block diagram showing the second embodiment of the inventive decoding equalizer;
Fig. 3 is a flowchart showing the operation of ~ 13(~t~)0 the CPU shown in Figs. 1 and 2;
Fig. 4 is a diagram explaining the sampling rate required for the equalization of MUSE system;
Fig. 5 is a waveform diagra~ showing, as an example, the test signal;
Figs. 6A and 6B are block diagrams showing, as examples, the arrangement of the e~ualizing filter;
Fig. 7 is a block diagram showing the overall arrangement of the subrange-type A/D converter suitable 1 3~9 1 ~)0 1 Lor the inventive equalizer;
Figs. 8 and 9 are block diagrams showing circuit sections added to the subrange-type A/D con-verter;
Fig. 10 is a waveform diagram showing, as an example, the unit impulse waveform signal for equalization; and Fig. 11 is a waverorm diagram showing, as an exampLe, the reception conversion waverorm ror equaliza-tion.

DESCRIPTION OF T~E PREFERRE3 EMBODIMENTS
Embodiments of this invention will be described in detail with reference to the drawings.
The embodiments will be described by taking an example of the MUSE transmission system developed for the high definition television signal, which i5 àn analog signal transmission system for transmitting the analog signal obtained by offset sampling between rames, fields and lines.
Fig. ~ is a block diagram showing an embodi-ment of the inventive decoding equalizer. In Fig. 1, indicated by 1 is an A/D converter which samples the input analog signal in MUSE system at a frequency of 32.4 MHz. 2 is a sub-sampling circuit which converts the output signal o~ the A/D ocnverter 1 into a signal of a trunk sampling clock rate of 16.2 ~l~z (or Ms/s:
mega-samples per second). 3 is a delay circuit, and 1 3~q 1 60 1 4 is an adder. 5 is an equalizing filter with a variable tap, and is used to produce an equalization correction value. 6 is a VIT signal extraction circuit which extracts the VIT (Vertical Interval ~est) signal with an impulse response waveform for measuring the distortion of the transmission path by being inserted in advance in the trun.~ system signal. 7 is a CPU
which receives signal waveform data provided by the signal extraction circuit 6 and compares it with stored ideal waveform data to evaluate the distortion, and controls the variable tap of the equalizing filter 5 so that it produces the equalization correction value.
The correction value is added to the trunk system signal by the adder 4, and the transmission characterictics or the transmission line are equalized.
The trunk system of MUSE system has a sampling clock rate of 16.2 ~Hz, while the equalization system operates at a sampling clock rate of 32.4 MHz. Fig; 4 is a diagram explaining the sampling clock rate neces-sary for the equalization of MUSE mode. As shown inFig. 4, sampling at 16.2 M~z with the intention of producing the 8.1 ~IHz roll-off characteristics (a) will result in a fold-over of the higher range above the cutoff frequency 8.1 MHz on the characteristics (b) as shown by hatching. This fold-over can be avoided by the sampling at 32.4 MHz which is twice the 16.2 M~z, and the sampling rate required for equalization is accomplished.

139~160 1 Fig. 2 is a bloc~ diagram showing another embodiment of the inventive decoding equalizer. In Fig.
2, components identical to those of Fig. 1 are referred to by the same symbols, and their explanation will not be repeated. ~ndicated by 8 is an A/D converter which samples the input signal at 16~2 MHz, and its output signal is used for the trunk system. 9 is an A/D
converter which samples the input signal at 32.4 MHz, and it is used as a circuit component of the equalization system The arrangement shown i.n Fig. 2 allows the A/D converter 9 for the equalization system, which is formed as a branch path of the trunk system, to have a resolution of 6 bits at most. The equalization filter 5 is conceivab].y re~uired to have the ability for processin~ a 6-bit si~nal a~ most, provided that it does not conduct a d.c. component. A problem seems to arise in the phase difference between the A/D converter 9 for the equalization system having a 6-bit resolution and the A/D converter 8 or the trunk system, but it is avoided completely through the adoption of the iterative correcting operation in the equalization system loop and by suppressing the phase difference below 1/5 of clock period. The above-mentioned iterative method enables equalization on the part of the decoder ; to have less equalization volume, and provides the characteristics of digital circuit arter equalization that are dee~ea ideal, whereby the arxangement is 1 30~ 1 60 1 simplified considerably.
Fig. 3 is a flowchart showing the process carried out by the CPU shown in Figs. 1 and 2. Tn the flowchart of Fig. 3, step S1 reads data in the VIT
signal by means of the VIT signal extraction circuit 6, and the data is delivered to the CPU 7. Step S2 subtracts the extracted data from data of ideal impulse response, which has been stored in advance in the CPU
7, to evaluate the error. Step S3 causes the variable-tapped equalizing filter 5 to have a center-tap coeffi-cient equal to the sum of errors of other than the center tap. Step S4 multiplies -1 to the errors of these taps. Consequently, the equalizing filter S has a zero gain, and it does not make a d.c. variation in the trunk system. Step S5 multiplies (~1~ to the error values or obviating the possibility of oscilla~
tion in the equalizing operation. Step S6 subtracts the error from the filter coefficien~ which has been evaluated previously. Step S7 sends the error data to the variable tap o equalizing filter to control the filter, At step S8, the above operations are repeated until the error value is smaller than the predeterm.ined value ~. The state of convergence is determined solely on the basis of the error of the 16.2 MHz data, as indicated in the step S8, i.e., the sampled value which is read originally as a signal of MUSE mode.
The ~IT signal will be described in more detail. Fig. 5 is a waveform diagram showing, as an 130916~
e~ample, the VIT signal of MUSE signal. Shown by (A) in Fig. 5 is the impulse response waveform for the n-th frame, while (B) is that for the n 1 th frame. The waveform of (A) has a peak (mar~ed by x) at the center s point M, and the amplitude of oscillation decreases progressively as the position goes right or lert away from the M point. The response characteristics have zero-cross pOiIlt at a constant interval on the horizontal axis as indicated by marks "x".
The waveform of (B) have maximum ~alues at two positions in the central portion in correspondence to the "x" positions of (A) and have peaks of amplitude for the remaining "x" positions, as indicated by marks "o".
Accordingly, by combining the waveforms of (A) and (B) in Fig. 5, data which is sampled at 32.4 ~IHz is obtained. A signal with a completely equal waveform is reproduced i. the transmission system has no distortion. The presence of distortion in the trans-mission system creates a distortion in the impulse response waveform and creates error in the values at the "x" and "o" positions.
The VIT signal extraction circuit 6 in Figs 1 and 2 supplies the impulse response wavefcrm data to the CPU 7, which controls the equalizing filter 5 for the waveform equalization.
By the way, in the embodiment shown in Fig. 2 for example for implementing the equalization on the part of the decoder, the follcwing two points of _ g _ .

, .................... . .

, ' 13~ql60 1 ~ractical problen~ must be overcome.
(1) Conflict in equalization between the decoder and the encoder when it is carried out on the part of the encoder (2) Creation of flaw in the trunk system signal when loading data from CP~ 7 into equalizing filter S
As regards item (1), an iteration flag indicative of equalization in progress on the part of the encoder is provided so that the equalizing opera-tion does not take place on the part of the decoder while it is in progress on the part of the encoder.
As regards item (2), there are two possible methods. One is that two sets of equalizing filters S
are prepared, with data being preloaded to the one unused for the trunk system, and the fil~ers are switched such that the loaded e~ualizing filter is inserted in the trunk system. The other is that the output of the equalizing filter is made zero and equa-lization is inhibited while data is being loaded.
Although the latter method involves a momentary period in which equalization is suspended during data loading, this does not cause the d.c. level to vary and therefore it is virtually unnoticeable.
Figs. 6A and 6B are blo k diagrams showing, as an example, the arrangement of the variable-tap equalizing filter 5 shown in Figs. 1 and 2. The circuits of both figures in unison form a single circuit by being connected ~hrou~h terminals ~ to ~ .

1 30q 1 60 1 In Figs. 6A and 6B, indicated by 101 is an input terminal and 102 is a line receiver. 103-106, 113, 114, 131-146, 154 and 157 are flip-flops each used ~o delay the signal by one 32 MHz clock period. 107-110 and s 123-130 are 3-state buffers, providing the output of "0", "1" or "open". 111 and 112 are delay circuits used to delay the signal by three 16 MHz clock periods.
115-122 are 11-bit RAMs, 147-153 and 156 are adders, and 155 is a delay circuit for delaying the signal by n 16 MHz clock periods (n ~ 128). 158 is an AND gate and 159 is an output terminal. 160 is a counter which generates the write address for the RA~s 115-122.
The RAMs, 3-state buffers, flip-flops and adders are combined ~n groups, e.g,, 121, 129, 137, 145 and 151, and connected in series to form a basic s~ructure o a variable-tap equalizing fil~er as the whole, The flltering characteristics are determined by the coefficients of the RAMs 118-122, and the variable-tap filter has its characteristics variable by changing the RAM coeficients with the CPU 7.
Through the detardation for one 32 l~lHz clock period by the flip-flop 104 in Fig. 6A, taps T2, T4, T6, T8, T10, T12, T14 and T16 on the upper section are separated ~rom taps T1, T3, T5, T9. T11, T13 and T15 on the lower section, and they operate at a 16 MHz clock, The delay circuit 155 and adder 156 are combined to produce a delay of n 16 MHz clock periods ~ (n ~ 128), and the timing relation between the trunk :

1 30~ 1 60 1 ~ystem and equalizing filter system can be adjusted.
Namely, the CPU 7 controls such -that the center tap (T8 or T9) of the filter is placed at the point where the VIT signal waveform has a maximum ringing.
The counter 150 generates the address for loading data from the CPU 7 into the R~s 115-122. When the CPU 7 is loading data into the R~Ms, the AND gate 158 produces a low output to invalidate the outout of the equalizing filter 5, and equalization or the trunk system is inhibited temporarily.
As described above, the equalizing filter of this embodiment has less number of bits (6 bits) for the input, and therefore it is relatively simple. A
11-bit RA~I is used for two taps, and the filter having a total of 16 tAps is formed. Taps dealing with the central portion of the VIT signal have 6~bit inputs, while taps for the remote portions have S-bit inputs.
In this embodiment, it is possible to choose the tap positions for the central portion of the equalizing filter, allowing the use by setting the tap position to be corrected.
Figs. 7, 8 and 9 show, as an example, the arrangement of the subrange~type A/D converter suitable for the foregoing decoding equalizer. The conventional subrange~type A/D converter generally includes two A/D converters of 16 MHz clock rate and 32 MHz clock rate, whereas the inventive subrange~type A/D converter co~ers the A/D conversion for both the VIT signal and 1 high definition television signal, resulting in a smaller scale of circuit.
Generally, each A/D conversion stage of the subrange~type A/D converter needs to operate fastex than the operating speed of the overall converter. It is relatively easy to design a high-speed A/D converter with a relatively low resolution, e~g., bits or less.
Accordingly, a high-resolution A/D converter of around 10 bits used ror the subsampling transmission of high definition television signal is arranged favorably in the subrange type with each A/D conversion stage having a resolution of 6 bits or less, whereb~l a high-speed, high-resolution A/D converter is realized relatively simply.
The subrange-type A/D convexter of this embodiment utilizes the above-mentioned advantages of subrange type. As sho~n in Fig. 7, the fore-stage A/D
converter 20g for converting the high-order 6 bits out o 10-bit conversion output dicJital signal, for e~ample, has its driving clock rate set to 32.4 MHz twice the television signal sampling clock rate 16.2 ~IHz for the trunk system, and the back-staye A/D converter 212 for converting the low-order S bits has its driving clock rate left unchanged at 16.2 MHz, so that the 32.4 ~Hz A/D converter 204 is used commonly for the conversion of upper digits of television signal and the formation of the signal for correcting the transmission charac-teris~ics. Accordingly, the A/D converter or this .. , ~ ~ .

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.. . : :

-:

130ql60 embodiment is capable of high-speed A/D conversion at as high resolution as around 10 ~its, for example, and the accuracy of A/D conversion is determined from the input to the back-stage A/D converter 212. Eventually, the accuracy is determined by the A/D converter 212 driven at a 16.2 MHz clock rate, and therefore it is identical to the conventional subrange-type A/D
converter operating at a 16.2 MHz clock rate for both the fore stage and bac~ stage.
Next, the arrangement and operation of the A/D converter shown in Fig. 7 will be explained. Clock pulses of 32.4 ~IHz and 16.2 MHz for driving the upper and lower conversion stages, respectively, are produced as shown in Fig. 8. A clock generator (not shown) provides on a terminal 219 a clock of 16.2 MHz having a duty cycle below 50~, which is fed to an exclusive-OR
gate 211 directly and also through a delay element 200, and a 32.4 MHz clock is produced at the output of the gate 221. The 1~.2 MHz clock is delivered through another exclusive-o~ gate 222. The 32.4 MHz and 16.2 ~SHz clocks are ed through respective OR gates 223 and 225, and led out o~ the converter on output terminals 224 and 226 for external uses, as shown i.n Fig. 9.
In the subrange-ty~e A/D converter shown in Fig. 7, an analog input signal such as the high defini--tion television signal on the input terminal 201 is introduced to a sampler 202, by which the signal is : sampled by the 32.4 MHz clock supplied on the clock .. ,--- : , -` 1 30q 1 60 l terminal h. The sampled signal level held by a capacitor 203 for one sampling period is fed to the A/D converter 204, by which the voltage level is converted into a high-order 6-bit digital signal by being driven by the 32.4 ~IHz clock supplied on the clock terminal h. The high-order 6-bit digital signal is led out through an OR gate 205 on an output terminal 206 as a digital test waverorm signal at a 32.4 MHz clock rate made up of unit impulses as shown in Fig. 10 which is an example of the digital test waveform signal against the analog test signal having a waverorm shown in Fig. 11 applied to the input terminal 201.
~ he high-order 6-bit conversion output signal of 32 . a ~IHz provided by the fore-stage A/D converter 204 ls fed to a flip-flop 207 driven by the 16.2 MHz clock so that the signal is converted to have a 16. 2 MHz clock ra~e, and it is con~erted back to an analog signal by a D/A converter 208 and fed to a subtractor 211.`
The subtractor 211 has another input receiving a signal which is derived from the analog input signal on the input terminal 201, which is sampLed at the 16.2 MHz clock by a sampler 209 and held by a capacitor 210 for one sampling period. Accordingly, the subtractor 211 produces a differential analog signal which is the analog input signal subtracted by the analog signal equivalent to the high-order conversion digital signal, and the differential analog signal is fed to the back-stage A/D converter 212 driven by the 16. 2 MHz clock ' , ' ~:
. .
., , . , ' - .

1 30~ 1 60 supplied on the cloc~ terminal ~, thereby producing a 5-bit low-order conversion digital signal.
In the illustrated circuit arrangement, which is intended to convert an analog input signal into a s 10~bit digital signal, it is sufficient for the lower conversion stage to produce a low-order 4-bit digital signal left aside from the 6-bit conversion output produced by the upper conversion stage. However, there is little difference in the complexity and easiness of fabricating each A/D conversion stage of up to 6 bits, and thererore the A/D converter 212 is designed to have a 5-bit resolution, with its low-order 4 bits providing the lower conversion output at a 16.2 MHz clock rate through an OR gate 213 and output terminal 214 and with its highest 1 bit providing a carrier or borrower to an adder 216. The adder 216 also receives the output o~' the flip-flop 207 through another flip-flop 215 driverl by the 16.2 ~ z clock. The 6-bit high-order digital signal at the 16.2 MHz clock rate added ; 20 by the carri.er or borrower bit from the A/D converter 212 is fed to an OR gate 217 togethex with an overflow bit OF from the adder 216, and the OR gate 217 delivers the high-order 6-bit conversion output digital signal at 16.2 MHz clock rate to the output terminal 218.
The subrange-type A/D converter arranged as described above, in fact, rorms an arrangement which embodies the circuit section of the A/D converter 1 .

1 30~1 ~a 1 and subsamplin~ circuit 2 included in the decoding equalizer shown in Fig. 1. ~he subrange-type A/D
converter has on its terminals 214 and 218 the output signals at the trunk system sampling rate delivered s to the delay circuit 3, and the output signal at the equalization system sampling rate on the terminal 206 is delivered to the equalizing filter S.
It is possible for the A/D converter shown in Figs. 7, 8 and 9 to be modified variously as in conventional subrange-type A/D converters. For example, in the illustrated arrangement, the output digital signal from the fore-stage A/D converter is converted to the low-rate digital signal with the flip-flop 207 and then converted back to the analog signal with the D/A converter 208, whereas the high-order output digital signal of 32.4 MHz from the A/D converter 204 may be converted back to the analog signal directly with the D/A converter 208. Instead of subtracting the analog signal produced by the D/A converter 208 from the input analog signal on the input terminal 201 with the subtractor 211, the back-converted analos signal is added to the reference level of the A/D converter 212 and, in this state, the i.nput analog signal on the input terminal 20l is fed directly to the A/D converter 212 so that their difference is rendered A/D conversion.
For the bac~-stage AJD converter 21Z, five bits are used to obtain the low-order 4-bit conversion output, i.e., the dynamic ranqe twice as needed, and conceiva~ly '~:

'~

q 1 60 such an excessive range need not be afforded.
As regards the clock rate, only the low-rate cloc~ is supplied and it is multiplied within the converter as shown in Fig. 8, but instead both the 16.2 MHz and 32.4 MHz clocks may be supplied from separate clock sources, although the illustrated scheme is more preferable for the avoidance of possible influence of the phase relation between the clocks on the conversion characteristics. The number of stages of A/D converters is not confined to two stages, but any plurality oE stage is possible.

Claims

CLAIMS:
1. A subrange-type decoder equalizing A/D
converter used for a transmission system which samples a television signal at a specified sampling frequency, transmits a sampled value and a test signal for detecting the transmission characteristics of a transmission path, decodes the sampled value with a decoder, and equalizes the transmission characteristics of the transmission path using the test signal, the subrange-type A/D converter comprising A/D converters connected sequentially in a plurality of stages, a fore-stage A/D converter having a driving clock frequency which is a multiple of a driving clock frequency of a back-stage A/D converter.
2. A subrange-type A/D converter according to claim 1, wherein the multi-stage A/D converters consists of two stages.
3. A subrange-type A/D converter according to claim 2, wherein the fore-stage A/D converter has a 32.4 MHz driving clock frequency and the back-stage A/D
converter has a 16.2 MHz driving clock frequency.
4. A subrange-type A/D converter according to claim 1, wherein the back-stage A/D converter is provided with resolution in excess of minimum resolution needed theoretically, the excessive resolution being used for correcting a total conversion output digital value.