CA1297992C - Computer bus - Google Patents

Abstract

Abstract of the Disclosure A computer bus having two paths, each path capable of transmitting 32 bits of data, 5 bits of function code, 8 bits of identification information, 5 bits of parity information, 2 bits of acknowledge codes, and four bus acquisition signals.

Description

~g~79~

_OMPUTER B US

Background of the Invention The present invention pertains to a computer system and, in particular, a bus system for use therein.
Computer systems exist which use a bus system to route signals from a central processing unit to Pither a memory device or peripheral equipment and vice versa.
A needs exists for a bus system which enables multiple central processing units to interface with each other and with memory devices, input/output devices and input/output device controllers. In addition, the need exists for such a bus system which can also interface several computer systems, each using a bus system, to provide multitask-multisystem integrated computers for network and taskcoordination.

Summar of the Invention Y

The present invention pertains to a computer bus system which enables multiple central processing units to interface with each other and with memory devices, input/output devices and input/output device controllers.
In addition, the bus system also interfaces several computer systems, each using a separate inventive bus system, to provide multitask-multisystem integrated computers for network and task coordination.
The inventive bus comprises having two paths with each path being ca~able o transmitting 32 bits of data, 5 bits of function code, ~ bits o~ identification information, 5 bits of parit~ for~atlon, 2 bits of acknowledge codes, and ~our bus acquisition signals.

~7~

Brief Description of the Drawin~

Ajcomplete understanding of the present invention may be gained by considering the following detailed description in conjunction with the accompanying drawing, in which:
FIG. 1 shows a block diagram of module interfaces to paths on the inventive bus system;
FIG. 2 shows a block diagram of bus path acquisition 10 circuitry for the inventive bus system;
FIG. 3 shows a block diagram of a backplane of the in~entive bus system;
FIG. 4 shows a block diagram of clock distribution circuitry for the inventive bus system; and FIG~ 5 shows a memory module for use with the inventive bus system.
To facili-tate reader understanding, identical reference numerals are used to designate elements common to the figures.
etailed Description The inventive, hi~h-performance synchronous bus system will be described in the context of its use in a Model 25 3280MPS computer system manufactured by Concurrent Computer Corporation, hereinafter referred to as the disclosed embodiment. This bus system, hereinafter re~erred to as the S-bus, interconnects various modules of the computer system, such modules being computer processor units (CPU), 30 input/output channels (I/O), and memories.
In general, the S-bus routes messages between modules on two distinct 32~bit data paths, a "To" or T-path and a "From" or F-path. The T-path transfers addresses and data "to" memory modules from other modules. The F-path 35 trans~ers data read "from" memory modules to other modules.
The F-path is also used (1) to route inter-processor messages; (2) to control dlrect inpUt/output (I/0), i.e.

31 2g 79~2 where an I~O device operates directly under the control of a CPU (this is contrasted with I/O that occurs under the control of a channel, otherwise known as DMA); and (3) to broadcast interrupts to modules other than memory.
FIG. 1 sho~s a block diagram of a system which uses an S-bus and the modules interconnected thereby. S-bus 10 comprises F-pa ~h 1 and T-path 2 . For purposes of simplicity, FIG. 1 only shows an overview of the interconnections between the modules which use the S-bus system and does not show the bus control and acquisition circuitry.
F-path 1 and T-path 2 are connected to various modules of the computer system. CPUs 1021 to 102n are connected to S-bus 10 by means of connections which allow bi-directional information transfer between the CPUs and F-path 1. The bi-directional connection is required because F-path 1, in addition to transferring data from memory modules to the CPUs, also transfers inter-processor messages, direct I/O
and broadcast interrupts from the CPUs to other modules.
Composite Memory Modules (CMM) lOll to 101n, to be described in detail hereinbelow, are connected to S-bus 10 by means of connections which only allow uni-directional information transfer to ~-path 1 and T-path 2. Only a uni-directional connection is required because addresses and data are transferred over T-path 2 to memory modules, whereas data read from memory modules is transferred to other modules over F-path 1.
I/O channel 105, sometimes referred to as a DMA
interface, is con~ected to S-bus 10 by means of connections which allow bl-directiunal in~ormation transfer to F-path 1 and only uni-directional information transfer to T-path 2.
M~le 106 is an interface circuit for connecting "compa-tible" I/O devices to S--bus 10, in a similar manner to the connection of I/O channel 105. "Compatible" I/O
devices are devices which interfaced to prior computer systems, i.e., prior to the Model 3280MPS. Module 106 allows bi-directional information trans~er to F-path l and uni-directional in~ormation transfer to T-path 2.
In addition to the above, S-bus Exchange circuits (SBX) 110 and 210 connect S-bus 10 to S-bus 20. SBX llO and SBX 210 are each connected to paths on the respective S-buses by means of connections which allow unidirectional informati~n transfer and are connected to each other by S-bus cable 107. This provides the means for modules connected to S-bus 10 to interact with modules connected to S-bus 20.
S-BUS OVERVIEW

T-Path (TO):
.
Processors and I/O channels initiate memory operations by sending addresses and data to memory modules on T-path 2. This is the only function of the T-path.

F-path (FROM):

Data read from any of the memory modules is returned to requesting processors and I/O channels on F-path 1. F-path 1 is also used for communica-tions between processors and I/O channels.
F-path 1 and T-path 2 each contains 50 data lines, each data line carrying one bit of informatlon. The bits, represented by the data lines, are divided, as listed below, into ~our groups or fields which comprise a bus data "item":
1) S~bit function field, 2) 8-bit identification (ID) field, 3) 32-bit data field, and 4) 5-bit parity field.
In addition to the 50 data lines used to transmit information, F-path l and T-path 2 each contains six acquisition lines and two acknowledge lines. As will be explained in detail below, the acquisition lines ~or each path are used to control path acquisition by the modules and the acknowledge lines for each path are used to control the interaction between modules by transmitting signals which indicate the receipt of data items.

Communication Among Modules Connected to the S-bus I D :

1 - Modules such as processors and I/O channels make similar use of the S-bus and are identified by 8-bit unit ID numbers. On T-path 2, the unit ID number identifies the re~uesting module. For example, each module puts its unit ID number on T-path 2 when it initiates a memory operation to identify itself as the requesting unit. Memory modules latch the unit ID number on T-path 2 and echo it on F-path 1 when responding with read data. The requesting module recognizes its unit ID number when it receives responses on F-path 1.
The ID appearing on F-path 1 addresses the destination module. Each module compares that ID with its own ID and latches all messages which match.
An exception to the above for the disclosed embodiment occurs for a broadcast interrupt; here the sender ID
appears on F-path 1. The broadcast message is received by all processors, regardless of whether the ID matches.
However, for any other F-path bus data item, only the addressed unit will respond.
2 ~ Memor~ is referenced solely by memory address;
i.e. memory modules do not have unit ID numbers. Each memory modulè recognizes the addresses of the memory locations it contains.

-` ~%~9~

Interaction Amon~ Modules Connected to the S-bus 1 - Modules such as processors initiate rnemory operations on the I'-path by specifying a memory operation in the 5-bit function field of a bus data item and placing a memory address in the 32-bit data field of the bus data item. For data writes, the data to be written into the memory module is sent to the memory module during subsequent bus operation cycles. For memory reads, the addressed memory module performs the read and then returns the data to the requesting module on the F-path. The disclosed embodiment provides four different memory reads and and four different writes for reading or writing from one to four words from memory.
2 - Modules such as processors and I/O channels communicate directl~ by means of the F-path. Inter-processor messages transfer interrupts and three data words from any processor or I/O channel to another designated module. Such messages are used (l) to coordinate processors in multiprocessor systems; (2) to initiate I/O channel operations, and (3) to reschedule tasks when I/O operations are completed.
3 - Messages can be sent from one module, such as a processor, to interrupt another module, such as a di~ferent proceSsor-~ - An interrupt can be broadcas~ to all processors simultar~eously. This allows an operating s~stem to pre-empt lower priority processes. In the disclosed embodiment, processors receive and act upon all broadcasts regardless of their ID. Broadcasts are no t acknowledged on the F-path.
5 - A processor can directly access an I/O channel to perform "Direct" Input/Output operations.
6 - Multiple S~buses may be interconnected to form larger computer systems by using two SBX circuits --one on each S-bus, e.g. SBXs llO and 210 in FIG. 1-- and a "System ; ~able" --e.g. cable 107 in FIG. l. Modules can thereby access memory in okher computer sys~ems by using real ;

addresses or by sending messages to other modules by unit ID numbers. An S~X monitors both the T-path and the F-path for messages addressed to the remote computer system. On the T-path, the SBX responds to selected memory addresses which are stored as a bit map in a random access memory (RAM) contained therein --in the disclosed embodiment, a 64K x ~ bit RAM stores four bits for each 64K byte block in the S-bus 4G by~e real address space. On the F-path, the SBX responds to selected unit ID numbers --in the disclosed 10 embodiment, these unit ID numbers are stored as a bit map in a 256 x 4 bit RAM. The messages intended for the remote computer system are acknowledged, buffered, and forwarded by the local SBX to the remote SBX. The remote SBX acquires the appropriate corresponding path in the remote computer system and echos the message.
The module which is given access to a path on the S-bus is called the "master" and the module which responds to requests from the master is called the "slave." The master of each path, T or F, can send one bus data item during 20 each bus operation cycle. The master enables its bus drivers when it gains control of a path and disables them when it relinquishes control to another module. The bus operation cycle is long enough to allow time ~or:
a. clock slew;
b. propagation delays of control flops (clock output~; -c. enable/disable times of bus path drivers (data propagation through the drivers is faster than enable/disable);
d. bus path propa~ation and settling time; and e. set~up time o~ bus path receivers and registers.
Every module receives every message. A bus data item is decoded during the cycle follo~ing its receipt; no logic delays are allowed during the transfer itself. Then, each module determines whether or not it is addressed: (1) if it is addressed, it becomes a slave and (2) if it is not addressed, or if the function code of the bus data item is "idle," it takes no further action. A slave che~ks the sæ

parity of each bus data item it receives, the parity of "idle" cycles is ignored.
A slave acknowledyes each bus data item it receives after that item was sent. In the disclosed embodimen-t, the acknowledge occurs two cycles after the bus data item was sent, i.e. on the cycle after the slave decoded ~he information. This pipelining of acknowledges permits high transfer rates. However, a master contains logic circuitry which enables the master to repeat the entire command n~essage if the "busy" acknowledge response is signalled by a slave.
The acknowledge lines in the disclosed embodiment are driven with open-collector gates and the acknowledge signal is the logical-OR of all slaves responding. Normally only one slave will respond, but a parity fault or improper configuration can cause two modules to respond to the same message. The fault code can be aliased if one of these boards is busy. The information conveyed by the acknowledge signals is given as follows:

AK1 AKO Meanin~
-O O No response - Idle cycle or module not present O 1 Here - Slave is present and accepted the item 1 O Busy - Slave is presen-t but did not accept item 1 1 ~ault - Slave detected a parity error The acknowledge l~nes merely ac~nowledge the receipt 3 o~ a bus data item. Thus, the acknowledge response "here"
does not mean that the rec~uested operation can be performed.
In the disclose(~ embodiment, when the slave sends a "busy" acknowledge response, this means that the slave's 35input buffer is full. For proper system operation, the slave must empty its buffer expeditiously.

When the master receives a "busy" acknowledge response, it must relinquish the bus and repeat the entire operation later. In the disclosed embodimen-t, .in order to prevent undue congestion, a module gets to keep the bus upon receiving two consecutive "b~lsy" responses. Memory and other modules should assert "busy" only on address cycles, i.e. when a master is attempting to create a slave. Thus, a module should assert the "here" acknowledge response only when it can accept the entire operation. On both the T- and 10 F-paths, one bit in the bus da-ta item --the most significant bit of the function code-- is set to to l for an address cycle and to 0 for a data cycle.
The "fault" acknowledge response indicates a hardware mal~unction.
As described above, parity bits accompany the data, function and ID fields in the bus data item. In the disclosed embodiment, the parity bits are used to detect errors which alter an odd number of bits. The parity bits are generated by the master and checked by the slave. A
20 parity error is detected when the parity check bit differs from the bus parity bit.
If a slave detects a parity error, it sends a "fault"
acknowledge response to the master and the bus data item is ignored.
All operations on the S-bus are deferred response.
This means that a master releases the bus after issuing a command and waits for an acknowledge response. The immediate acknowledge response assures the master that the command was received. }lowever, a master must include time-30 out logic to handle missing res~onses due to, for example a hardware ~aul-t.
In the disclosed embodiment, memory operations should complete within 25 usec. Longer delays are faults.
Responses to channel I/O commands can be delayed 35 indefinitely due to long mechanical delays, ~ueuin~, or human interaction. The so~tware must determine and implement its own time-outs.

OVERVIEW: ~US ACQUISITION AND PRIORITY

The operation of the inventive S-bus is synchronous with a system clock, shown in the disclosed embodiment to be a 10-megahertz clock. A module must request access to a path and then be given that access, i.e. become a master, before the path can be used to transfer information. The master has temporary control of the path. Addresses and data are transferred on the path from the master to a slave during one or more bus operation cycles.
Bus allocation operates in parallel with transfers on the S-bus. The next master of a path is determined at the end of each bus operation cycle.
The T-path and the F-path have identical, but independent circuitry, which allocates a path on the S-bus between -the modules connected thereto. This circuitry comprises a "bus acquisition circuit" within each module and a "priority encoder" circuit on the backplane. Also, as will be described hereinbelow, a priority scheme allows more urgent requests to be given priority over less urgent ones. In combin~tion, the "bus acquisition circuit" and the "priority encoder" circuit determine the sequence in which requests ~or a path on the bus are granted.
Priority Schemes for the Disclosed Embodiment 1. Positional Priority Each slot in the backplane o~ the system using the S-bus has a physical location number. In the disclosedernbodiment, modules connected to slots having lower location numbers have priority over modules connected to - slots having higher location numbers; with slot 0 having the highest priorit~. This ~eature is re~erred to as positional priority. When con~iguring a system which uses an S-bus, processors should be given high positional priority, i.e. be placed in low -numbered slots to avoid g7~

system degradation which results when a processor must wait for the bus.

2. Overlays on the Positional Priority Scheme When a module makes a request to acquire a path on the bus, its circuitry specifies the priority of the request as follows:
a) high priority - the bus acquisition circuitry will grant each bus acquisition request which specifies a high priority before granting lower priori-ty requests;
b) round-robin priority - modules in lower positional slots, i.e. those having higher positional priority, have priority over those in higher positional slots, but each may ac~uire a path only for one bus operation cycle until all modules requesting round-robin priority have had access. This priority scheme is provided because a high-performance processor can monopolize the bus during periods of high memory usage and cause lower priority processors to stall if they cannot acquire the bus. Thus, round-robin priority permits modules to share the bus more equally; and c) simple priority - I/O channels normally operate with low priority because they buffer data and can normally tolerate some delay without penalty. However, when extended delays cause the I/O channel buffer capacity to be exceeded, an operation will be aborted. To avoid this, and the resulting lose of data, the I/O channel will make a high priorit~ bus acquisition request to avoid losing data.
Within an~ priority level, positional priority determines wh:Lch request is granted first. But, wi-thin the round-robln priority level, acquisition re~uests are selectiv~ly enabled to providè access to rotate through the connected modules.

~2~

-12~ CS 3511 BUS ACQUISITION CIRCUITRY

FIG. 2 shows bus acquisi-tion circuitry for the disclosed embodiment. This circui-try is duplicated in -the system for the F-path and the T-path. Module bus acquisition request circuit ( MBARC ) 30 is present within each module that interfaces to the S-bus. MBARC 30 generates appropriate bus acquisition request signals and keeps track of whether the module has acquired the bus.
Priority encoder circui-t 40 is part of the system backplane. It responds to bus acquistion re~uest signals generated by all the modules connected thereto by boards plugged into the backplane. It determines which module is to be given access to the path and then it distributes that access information to all the modules connected thereto.

Nomenclature:
_ Signals are labelled with a postfix minus to indicate the complement of a signal which is "active" when the condition named by its mnemonic is true.

logic true signal complement SIG SIG-signal activ~ logic 1 logic 0 signal inactive logic 0 logic l In the disclosed embodiment, signal voltages are assigned positive-true logic levels:
lo~ic_ _ _ voltage levels logic 0 low volta~ (0.0 volts to 0.8 volts) logic l high voltage (2.0 volts to 5.5 volts) In FIG. 2:

(a) D flip-flop 309 within MsARC 30 generates bus request signal RQ to request acquisition of the path in response to a "set request" signal on lead 305 from the module upon w~ich MBARC 30 is situated. For each path, every module is allotted one bus request signal.
(b) JK flip-flop 308 within MsARC 30 generates acquisition master signals MINE and MINE-. When ~INE is true, the module has been given access to the path. The module whose request for a path acquisition has been granted is known as the path's master. During each bus operation cycle, there is only one master for each path, therefore the "MINE" flip~flop, i.e. flip-flop 308, must be reset in the MBARC of all modules which are not the master.
(c) JK flip-flop 310 within MBARC 30 generates round-robin priority path acguisition signals RREN and RREN-.
(d) D flip-flop 311 within MsARc 30 generates high-priority path acquisition signal HPEN in response to a "set high priority" signal on lead 306 from the module upon which MBARC 30 is situated.
Each of the above-described flip-flops is triggered by clock signal SCLK which is generated on a terminator card connected to t~e backplane. SCLK is subsequently transferred to all modules through the backplane in a manner to be described hereinbelow.
Note that MBARC 30 shown in FIG. 2 uses all the priority features describes hereinabove. ~lowever, a module need not use all the priority ~eatures generally available.
For e~ampl~, any modul~ not requiring high priority bus access t~ay delete the corresponding circuitry, starting with D ~l~p-flop 311.
On each module: (a) MINE is applied to NAND 301; (b) MINE- is applied to NAND 302; (c) RQ is applied to NANDs 302-304 and to AND 312-314; (d) RREN is applied to NAND 303 and to AND 312; (e) RREN- is applied to AND 312; and (f) HPEN is applied to NAND 304 and to AND 314. The outputs o~

~97~9~

NANDs 301-30~ from all modules connected to the S-bus are wire-ored in the backplane, in priority encoder circuit 40, to produce signals KEEP-, REQ-, RREQ-, and HREQ- on leads 341-34~, respectively. If no module has made a bus acquisition request, the signal on a lead is high, whereas if one or more modules have made a bus acquisition request, the signal on the lead is low. In the disclosed embodlment, KEEP-, REQ-, RREQ-, and HREQ- are open collectox signals, and each of the lines 341-344 is connected to a "pullup resistor."
RREQ-, ~REQ-, KEEP- and REQ- are each terminated by 150 ohm 2% resistors 361, 362, 351 and 352, respectively, to a +5 volt source (not shown). These resistors and their connections to the 5 volt source appear on a card called the S-bus terminator card. The terminator card is connected to the backplane and is described in further detail hereinbelow. Since the open collector signals are not driven above the loyic threshold, the rise time is determined by the RC constant of the circuit. The use of a 5 volt pullup improves the rise time of the open collector signal to a level above the logic threshold.
The wire-or of the output from NAND 303 on each module, i.e. round robin priority request signal RREQ-, is applied to AND 312 on each module. The wire-or of the output from NAND 304 on each module, i.e. high priority request signal .~REQ-, is applied to ANDs 312-313 on each module. F'ur-ther, on each module, the outputs from ANDs 312-31~ are applied to NOR 315. The output ~rom NOR 315 is module bus acguisition reguest signal RQn-, where n is the slot number on the backplane.
RQn~ is applied to bus allocation positional priority circuit 316 which, in the disclosed embodiment, comprises a priority encoder designated 381 and a decoder designated 382. ~us acguis~tion re~uest signal RQn- is active low and pullup resistor 371, taken to be 1000 ohms in the disclosed embodiment, in circuit ~0 assures that the reguest lines of ~2~7~

empty slots remain inactive. Thus, in the disclosed embodiment, ~nused request lines may be left unconnected.
Bus acquisition request si~nal RQn is determined by the circuitry shown in FIG. 2 to be equal to:

RQn=(RQ*~PEN)high priority (AND 314) + (RQ*RREN*HREQ-) round-robin, unless inhibited (AND 313) + (RQ*RREQ-*HREQ-*RREN-) simple, unless inhibited (AND 312) Positional priority encoder 316 has one input, i.e.
RQn-, and one output, GRn-, for each S-bus slot. Positional priority encoder 31~ determines which module has the highest priority request pending and grants it control of the path for the next cycle by means of "bus path grant"
signal GRn-. The "bus path grant" signals of all other modules rernain inactive, i.e. high, and the other modules must wait. As shown in FIG. 2, a "bus path grant" signal GRn- for each slot is sent back to the corresponding module on lead 391 to lndicate whether the path was ac~uired for the next bus operation cycle. The number of slots in the disclosed embodiment is 22, hence, encoder 381 comprises three 74F1~8 priority encoders and decoder 382 comprises three 7~F13~ decoders. Further, each RQn- signal presents one 74F unit load plus lK ohms from pullup 371 at the encoder input, and each GRn- can drive 20ma at 0.~ volts.
In addition, REQ-, produced by the wire-or o the outputs from NAND 302 ancl KEEP-, produced by the wire-or of the outputs of NAND 302 are used to pass the path to another module for the next bus operation cycle or to keep it for the module which presently has access. A module may want to ret~n a~¢~ss t~ the path for more than one bus operation cycle because a particular operation may require more than one bus operation c~cle to be completed. For ~7~

example, some memory reads or writes in the disclosed embodiment require more than one bus opera-tion cycle.
When a module gains access to a path, it sets signal MINE which is output from JK flip-flop 308. If the module needs to maintain the path for another bus operation cycle it sets a "more data" signal on lead 382, which signal is applied to NAND 301 along with MINE. The output of NAND 301 is wire-ored on the backplane to form signal KEEP- which is then applied to NAND 321. The output of NAND 302, to which RQ, requesting a bus path acquisition, and MINE- have been applied, is wire-ored on the backplane to form signal REQ-.
REQ- is inverted in inverter 320 and applied, along with KEEP-, to NAND 321. The output of NAND 321, signal PASS-, is applied, along with "bus path grant" signal GRn-, to NOR
385. PASS- is also applied, along with the output of NOR
385, to NOR 386. When "more data" on lead 388 is set and MINE is set, the module retains control of the path, notwithstanding the fact that the "bus path grant" signal for another module has been made active.
Thus, in summary, the following signals are generated by the modules, in conjunction with the backplane, in order to acquire each path on the bus --The prefix for a signal indicates a signal generated for T-path or F-path acquisition:
Bus acquisltion si~
T-path F-path TRQn- FRQn- bus path acquisition request siynal:
-one signal per path for each module TGRn- FGRn- bus path grant signal;
-one signal per path for each module ~9~2 TKEEP- FKEEP- keep bus path for the next cycle signal;
-wire-or of signals from each module (open collector in disclosed embodiment) TREQ- FREQ- request bus path signal;
-wire-or of signals fro~ each module (open collec-tor in disclosed embodiment) TRREQ- FR~EQ- round-robin request signal;
-wire-or of signals from each module (open collector in disclosed `embodiment) THREQ- FHREQ- high priority request signal;
-wire-or of signals from each module (open collector in disclosed embodiment) Step l: l'he module does not have the bus and wishes to a~guire it.

MINE is inactive, i.e. equal to 0 and MINE~ is equal to 1 ~ a) A regular priority re~uest for the bus is made by setting RQ, output from flip-flop 309, to active, i.e. 1.
Thus the output o gate 302, signal REQ-, will be 0, i.e.
active.
REQ=RQ*MINE-(b) In addition to setting RQ from flip-flop 309 to be active, a round-robin request for the bus is made by setting RREN from flip-flop 310 active.
RREQ=RQ*RREN

, .

~97~

-18- CS 351~
(c) In addition to setting RQ ~rom flip-flop 309 to be active, a high priority request for the bus is made by setting HPEN from flip-flop 311 active.
HREQ=RQ*HPEN
HREQs have priority over RRENs and both have priority over other "simple" requests. These signals oper~te by inhibiting, and thus delaying, requests from modules with a lower level of priority. When HREQ is active, only high-priority requests are enabled. When RREN is active, simple requests are disabled. Since the "round-robin"
control line RREN permits processors to share the bus more equally, processors typically request their first operation with both REQ and RREN. This gives them priority over simple requests. When several processors have pending requests, RREN stays active until each gets one operation.
A processor which requests a second cycle while RREQ is still active must assert only REQ. This is a low priority request. When RREQ goes inactive, all processors may again use RREQ. Memory modules use RREQ to share F-path equally.
Processor messages and direct I/0 should also use RREQ.

Step 2: The module has the bus a~d wishes . . . ~
to retain it for the next cycle.

~5 MINE is active, i.e. equal to 1. When an operation requires more than one bus operation cycle, "more data" is set to be aCtive, i.e. equal to 1.
KEEP=MINE*"more data"
The master of a path, i.e. the module having MINE=1, asserts ~<EEP during operations which require two or more cycles. This prevents loss of the bus in the middle of an operation. ~lowever, KEEP must not be used to retain the bus for consecu~iv~ operations. KEEP must be inactive during idle cycles and the last cycle of any operation.

~7~1~2 -l9- CS 3511 Step 3: The bus ~s passed to a new master KEEP is inactive, i.e. equals 0. XEQ from this module is inactive, i.e. equal to 0, because RQ is inactive, i.e.
equal to O and REQ=RQ*MXNE-. ~owever, since some other module is requesting the bus, and REQ is the wire-or of the REQ signal from all the boards, REQ for the bus is active, i.e. equal to 1. Thus, PASS is active, i.e. equal to 1.
PASS=KEEP-*REQ
As a result, the bus is lost and MINE is set to inactive.
LOSEBUS=PASS*GRn-Here GRn- is inactive, i.e. equal to 1 because this module did not make a bus request, and therefore, no grant is made. Note, that unless another request is made, tllis module does not lose the bus. This is because REQ would be inactive, i.e. equal to 0 and hence, PASS would be equal -to 0.

Step 4: The bus is obtained.

PASS is active, i.e. equal to 1, because KEEP is inactive and KEEP- is therefore equal to l. REQ is active and equal to 1, and therefore, PASS is active, i.e. equal to 1. In addition, GRn- is active, i.e. equal to 0, because the bus is to be given to this unit or module.
GETBUS=PASS*GRn GETBUS sets flip-flop 308 so that MlNE is active and it se-ts flip-flop 310 so that RREN is active.
SUMMARY: Open Collector_Bus Si ~

In the di.sclosed embodiment, each of the two bus paths uses 6 open collector signals: four for acquisition control and two for acknowledge. The acquisition control signals are driven by each module requesting a path on the bus. The outputs from each module are lo~ically wire-ored, i.e., a ~7~Z

signal is active low if any board asserts it. The acknowledge signals are usually driven only by the slave, however, a parity error or an improper configuration can result in several modules responding at once.
The lines transmi~ting acknowledge signals TAK1, TAKO, FAKl, ~`AKO and acquisition control signals TKEEP, FKEEP, TREQ and FREQ are terminated with 150 ohms to 5 volts on the backplane by the S-bus terminator card. The 5 volt pullup improves rise time to above the logic threshold, for example 1.6 volts is a typical logic threshold for 74F
logic obtained from Fairchild Camera and Instrument Corporation, Digital Products Division, hereinafter referred to as Fairchild. These lines need not be exactly matched to bus impedance, and a diode clamp to 0.6 volts (not shown) reduces nega-tive overshoots.
Bus ac~usition signals TRREQ, FRREQ, THREQ and FHREQ
use 150 ohm 2% pullup resistors to provide ~ast rise times.
In addition, Fairchild 74F38 buffer gates are required to drive these signals fast enough to overcome the extra delay involved in driving inputs to priority encoder 316 and to Fairchild 74F64 NOR gate 315.
FIG. 3 shows S-bus backplane 29 and a portion of terminator card 50 for T-path 2.
Signals input to and output from backplane 29 are generally collected above designation 1717. For purposes of discuss$on, let us focus on a module board installed at slot O of bac~plane 29. The 32 T-path data signals T31:00 are input to 32 pins on backplane 29, the pins all being represented in FIG. 3 by pin 501. The 32 lines on backplane 29 that connect T-path 2 to pln 501 are all represented in FIG. 3 by lin~ 601. Each of the 32 lines represented by line 601 is termina~ed by a 150 ohm resistor, the resistors all being rep~esented in FI~. 3 by resistor 651. Resistor 651 is ~onnect~ to a ~3 volt source (not shown) on terminator card 50. In similar fashion, T-path signals TFN4:0, TID7:0, and TPAR4:050 are input to backplane 29 at pins represented by pins 502-50~, respec~iv~ly, and each of ~7~2 the lines connecting T-path 2 to pins 502-50~ is represented by lines 602-604, respectively. Each of the lines represented by lines 602-604 is terminated by a 150 ohm resistor represented by resistors 652-654, respectively, which resistors are connected to a +3 volt source (not shcwn).
In addition, the six open collector signals, TAKl:O, TKEEP-, TREQ-, TRREQ-, and THREQ- are applied as input signals to pins represented by pins 505-509, respectively.
The lines on backplane 29 connecting T-path 2 to pins 505-509, respectively, are represented by lines 605-609, respectively. Each of the lines 605-609 is terminated by a 150 ohm resistor represented by resistors 655-659, respectively. Each of the resistors 655-659 is connected to a +5 volt source ~not shown) on terminator card 29.
Bus path acquisition re~uest signal TRQn- from the module board is applied as input to pin 510 and is terminated by a 1000 ohm pullup resistor (not shown) on termina-tor card 50. The TRQn- signals from all the modules are input into priority encoder 381. The outputs from priority decoder 382 are applied to the module boards as TGRn- signals. This is shown illustratively ~or slot 0 in FIG. 3 by the connection between the output of priority decoder 382 and pin 511.
Circuit 50 shown in FIG. 3 represents a portion of the S-bus terminator card referred to hereinabove. It provides the proper pull-up resistors for the open collector signals discussed above. In addition, as described hereinbelow with respect to ~ig. ~, the terminator card contains circuitry for generating clock signals which are distributed to a clock distribution board.
FIG. 3 also shows the inter~ace, throuyh the backpanel, between clock dis-tribution board 55 and the modules (clock distribution board 55 being responsible for distributing clock signals to the modules). As shown in FIG. 3, clock signals OSC- and CL~- are distributed -to the module board in slot 0 at pins 498 and 499, respectively.

~2~7~Z

_-BUS CLOCKS

Bus timing is synchronous with a 10.00 megahertz (mHz) timing signal, i.e. clock SCLK. SCLK is generated on each module from two timing signals which are distributed radially on the S-bus backplane. ~he two timiny signals are 20.00 megahertz oscillator clock signal OSC- and 2.000 megahertz oscillator clock signal CLK-. More specifically, in the disclosed embodiment, (1) OSC- is a 20.00 +,- 0.001 m~lz oscillator having a 50 nsec period with less than 2 nsec jitter and a 50~ 10% duty cycle at its output connector and (2) CLK- is a 2.00 mHz signal, derived from OSC-, which is active for one OSC period (50 nsec) every 500 nsec.
In the disclosed embodiment, bus timing is taken relative to the falling edye of OSC- on the backplane --the rising edge of OSC- is imprecise and ~hould not be used for any bus operation. Timing slew, defined to be the dif~erence in timing between separate clock signals, from OSC- to SCLK must be minimized.

Clock Distribu-tion-.

All S-bus timing is derived from a sinyle 20mhz cr~stal oscillator. Its output is buffered and radially distributed to each board in the S-bus b~ means of a terminator card. Radial cables minlmize clock slew and waveform degradation.
The cloclc distribution is shown in FIG. 4. All signals are referenced to the ~al~-ing ~dge of OSC- at the backplane pin 498. For the disclosed embod:l~ent, it is preferrable that slew be less than ~,- 6 nsec between boards in a chasis and less than ~,- lO nsec between chasises.
~5 In the disclosed embodiment, oscillator 401 on S-bus terminator card 50 provides clocks to its chasis usiny a coax cable and a 4-pin connector. Oscillator 401 can also ~2~79~2 provide clocks to a second chasis via coax cable. To minimize slew, the electrical length of the cables should be equal.
Signal OS~, output from oscillator 401, is inverted in inverter 420, for example a Texas Instrument 7~AS1000 buffer, to provide OSC-. OSC- is then applied to divide-by-2 circuit ~Q3. One output from divide-b~-2 circuit 403 is applied to divide-by-5 circuit 404, ~or example a Fairchild 74F163 synchronous presettable binary counter, to provide, in conjunction with NAND 421, 2 M~z signal CLK-. Signal CLK- comprises one 50 nsec pulse every 100 nsec and is used to synchronize the S-bus at 100 nsec cycles (10mhz). NAND
421 is repeated once for each chasis which needs CLK-.
OSC is inverted in inverter 408, for example a Texas Instrument 74AS1000 buffer, to provide OSC-. CLK- and OSC-are applied to clock distribution board 55 by coaxial cable 467.
Clock OSC- is received on clock distribution board 55 by buffer 410 which, in turn, drives buffer 411. One input to buffer 411 is ground, applied through inverter 409, for example a Fairchild 74F04 hex inverter. This reduces the electromagnetic interference if no module board is plugged into the slot driven by buffer 411. Buffer ~11 drives one module board with OSC- at pin 498. Thus, buffer ~11 is repeated, for example by buffer 412, for each module board -that is driven.
Clock CI,K- is input into JK flip-flop 477 on clock distribution board 55 along with the output of buffer 410.
The ouptut from JK flip-flop 477 is buffered in buffer ~13, for example a Texas Instrument 74AS1000 buffer. Buffer 413 drives three module boards with CLK- at pins 499, 469 and 479, respectively. Thus, buffer 413 is repeated, for example by buffer 414, for each three module boards that are driven. In the disclosed embodiment, traces are le.ss than 6 inches and are not terminated.
In the disclosed embodiment, each S-bus module board, like module board 89, may put one 74F load on CLK~ w i th a ~2~

maximum of 1 inch trace stub length. Each S-bus module board, like module board ~9, ma~ put a maximum of 5 74F
loads on OSC- with a maximum of 10 inches of trace stub length terminated by a 100 ohm resistor. Signal OSC- from backplane 29 is inverted in inverter ~50 on module board 89 and applied, along with signal CLK- from backplane 29, to JK 1ip-flop 406 (or to logic that acts like a JK flip-flop) to produce module clock signals SCLK and SCLK- on lines 491 and 492.

TRANSFER OF INFORMATIO~ USING THE S-BUS

Notation Signals are represented by mnemonics composed of capital letters, the postfix numbers identify individual signals within a field. A field is labelled, along with its bit range, by using a colon, i.e., T31:00 represents the 32 bit signals T31 through T00. The most significant bit is listed first. A postfix minus indicates the complement of a signal which is "active" when the condition named by its mnemonic is true.
A "word" is 32-bits wide, a "halfword" is 16-bits wide, a "byte" is 8-bits wide and a "nibble" is 4-bits wide. Binary values are represented in hexadecimal notation, thus, each nibble has a value of 0 to 9 or A
(=10) to F (=15).
"Power-of-two" notatlon is used to number bits within a field. Thus, T31 is the most significant bit in the data field, TFN~ is the most significant bit in the function field, TID7 is the most si~nificant bit in the ID field, and so ~orth. Bit 0 is the least significant bit ln a field. The weight of each bit "n" is "2**n", i.e. 2 to the power n. However, bytes and halfwords are numbered "left to right," i.e. byte 0 is the most significant and byte 3 is the least signirican-t.

~2~

SIGNAL DEFINITIONS

T-path and F-path signals are identical. All T-path signals have "T" prefixes and all F-path signals have "F"
prefixes.
TO-path FROM-path Signal Definition Message fields:
T31:00- F31:00- 32-bit data field TFN4:0- FFN4:0- 5-bit function select 10 TID7:0- FID7:0- 8-bit unit identification number Parity bits on Message:
TPA~4- FPAR4- even parity bit for ID and FN
fields TPAR3- FPAR3- even parity bit for data bits 31:24 TPAR2- FPAR2- even parity bit for data bits 23:16 TPAR1- FPAR1- even parity bit for data bits 15:8 TPAR0- FPAR0- even parity bit for data bits 07:00 DEFINITIONS OF THE CODES OF THE FUNCTION FIELD

On the T-path and the F-path, the 5-bit function field specifies what is on that path during each cycle. For a memory write or an I/O write, the data cycles must immediately follow the address cycle. Other data cycles, such as the memory read and I/O read, are separate.
Function "0" specifies an idle cycle during whiCh there is no transfer. The other fields, includin~ parity, are ignored. As a consequence, the master must drive the function code to zero durlng idle cycles and the other fields need not be driven.

~29~

T-path Function field Codes The T-path is used solely to initiate memory operations. TFN4 is 1 for address cycles and O for data.
For the disclosed embodiment:

TFN4:0 _ Mnemonic Operation 00 00000 IDL Idle bus cycle 01-03 * (reserved) -----Data-----04 00100 DWO Data word, end a-t byte O
05 00101 DW1 Da-ta word, end at byte 1 06 00110 DW2 Data word, end at byte 2 07 00111 DW3 Data word, end at byte 3 15 08-OF (reserved) -----Read-----10000 MR1 Memory Read: 1 word 11 10001 MR2 Memory Read: 2 words 12 10010 MR3 Memory Read: 3 words 20 13 10011 MR4 Memory Read: 4 words , -----Write-----14 10100 MW1 Memory Write: 1 word 15 10101 MW2 Memory Write: 2 words 16 10110 MW3 Memory Write: 3 words 25 17 10111 MW4 Memory Write: 4 words -----Special-----18 11000 MRS Memory Read and Set 19 11001 MRR Memory Read and Reset lA 11010 MRI Memory Read and 30 Increment lB 11011 MRD Memory Read and Decrement lC 11100 MRW Memory Read and Write Word 35 lD 1~101 MW~ Memory Write Diagnostic lE-lF * (reserved) ~9~

F-path Function field Codes The F-path is used for memory read data, direct I/O, broadcast interrupts, and messages between units. The ~our "broadcast" functions are received and decoded by all units whereas the memory read data, direct I/O, and the four "message" func-tions are decoded only by the unit addressed by FID7:0.

10 F 4:0 Mnemonic Operation 0000000 IDL Idle bus cycle ~ -Direct I/O Response-----0100001 ATN Attention (compatible I/O
~ interrupt lines 15 0200010 IOK I/O acknowledge, data okay 0300011 IER I/O acknowledge, data error -----Memory Response-----04 00100 MDCOMernory Read, word 0, disable cache 20 05 00101 MDC1Memory Read, word 1, disable cache 06 00110 MDC2Memory Read, word 2, disable cache 07 00111 MDC3Memory Read, word 3, disable cache 08 01000 MOKOMemory Read, word 0, data correct 09 01001 MOK1Memory Read, word 1, data correct 30 OA 01010 MOK2Memory Read, word 2, data correct OB. 01011 MOK3Memory Read, word 3, data correct OC 01100 MEROMernory Read, word 0, data error OD 01101 MER1Memory Read, word 1, data error ~2~

-28~ CS 3511 0E 01110 MER2 Memory Read, word 2, data error OF 01111 MER3 Memory Read, word 3, data error -----Direct I/O-----10000 IOR Input/Output Read 11 10001 * (reserved) 12 10010 IOW Input/Outpu-t Write 13 10011 FDAT F-path Data ~ollows IOW or MSGn -----Broadcasts~
14 10100 PRE "Pre-empt" broadcast interrupt 10101 DVA "Delete Virtual Address"
broadcast interrupt 16 10110 SYNC "Start real time clock"
broadcast interrupt 17 10111 * (reserved) broadcast interrupt -----Messages-----18 11000 MSG0 Message 0 19 11001 MSG1 Message 1 lA 11010 MSG2 Message 2 lB 11011 MSG3 Message 3 25 lC-lF (reserved) IOW and FDAT must be sent as pairs of consecutive items, each MSGn must be ~ollowed by two FDAT items and the other items may be sent singly.
IOK and IER are responses to IOR and IOW commands.
MOKn, MERn and MDCn are reSponses for memory read operations. The responses for a multiple word read operation will llsually oCcur on sucCessive cycles, but this is not re~uired.
T~e responses ~OK, IER, MOK, MER, and MDC send one item to acknowledge completion of a direct I/O or memory operation. All direct I/O is acknowled~ed, this signals the processor to proceed.
For IOR, read data is returned on F31:00.
Memory reads are acknowledged with the read data returned on F31:00.
Each word of a quadword memory read is sent, MOK, MER
or MDC, and acknowledged separately. The memory module ma~
retain the bus for all four words.
For memory writes, there is no response on the F-path, i.e. the processor does not wait.

ELECTRICAL SPECIFICATIONS

The S-bus uses four types of signals. As has been described above, the logic signals are driven, OSC-, CLK-, TGRn-, FGRn-, or received, TRQn-, FRQn-, by circuits on the backplane. Bus signals connect to all module boards on the S-bus. The backplane terminates the bus lines, but does not send or receive signals.
S-bus Logic Signals:

1. OSC- and CLK- clocks are radially distributed to each module;
2. Bus request signals TRQn- and FRQn- are generated on each module board, and, in the disclosed embodirnent, are Fairchild 7~F logic signals; and 3. Bus ~rant signals TGRn- and FGRn- are generated on the S-bus backplane and are distributed to each module board, and, in the disclosed embodimen-t, are Fairchild 74F
logic signals.
S-Bus Signals:
1. Tri-s-tate bus signals T31:00-,TFN4:0-, TID7:0-, TPAR5:0-F31:00-,FFN~:0-, FID7:0-, FPAR5:0-2. Open collector bus control signals TKEEP-, TREQ-, TRREQ-, THREQ-, TAKl:0-TKEEP-, TREQ-, TRREQ-, THREQ-, TAKl:O-In the disclosed embodiment, the logic used conforms to the Fairchild 7~F logic levels and loading, i.e.:
Bus Line Receivers: Input-High > 2.0 volt with I-IH < 0.04ma -Low < 0.8 volt with I-IL < 0.6 ma Bus Line Drivers: Output-~igh > 2.7 volt @ 1 ma -Low < 0.5 volt @ 20 ma Tri-State Bus Signals:
.

As described above, the F-path and the T-path each uses 50 tri-state bus signals. These bus signals are driven by thè module that is presently the master of the bus path synchronously with SCLK at 100 nsec cycles. In the disclosed embod;ment, these tri-state bus signals are pre~errably driven and received with edge-triggered D-type registers. Each slave receives the bus signals during every bus opera-ti0n cycle and decodes its address or ID.
In the disclosed embodiment, the master must drive the ~unction signal lines, TFN for the T-path or FFN for the F-path, during every bus operation cycle for which it is themaster oP the bus path. If the module does not use the bus path, it must drive the unction code to zero, i.e. high.
The lines for the other fields are allowed to float high to save power since the bus termination ~issipates significant power only Por low si~Jnals. Since tri-stated lines rise slowly, the~ Ploat hiyh too slowly to guarantee an adequate logic high; so the other ~ields are ignored.
The tri-state signals, as shown in FIG. 3, are terminated through 150 ohms to 3 volts on the S-bus terminator card~ A series-pass voltage regulator (not shown) is used to produce 3 volts on the terminator card.
ThiS termination has an a. ~. response similar to a split resistor terminator, but dissipates little power for inactive (high) signals.
Terminator power for T-path or F-path for the resistors shown in FIG. 3 is given by:
50 tri-state bus lines * 20 ma = 1000 max, 500 average 2 fast Open Collector * 35 ma = 70 35 i.e. ~REQ- and HREQ-4 slow Open Collector * 22 ma = 90 45 i.e. KEEP-, REQ-, and AKl:0 10TOTAL 1160 max,580 average In addition, a diode clamp (not shown) on terminator card 50 to 0.6 volts reduces negative excursions of the open collector signals.
The bus is terminated at one end only because double-ended termination requires too much drive current and dissipates substantially more power. Signal edges are absorbed by the terminator, but reflect at the far end.
Thus, bus timing allows 20 nsec ( > 2nsec/ft * 1.5 ft * 4) for settling. Thus, the timing for the bus is determined from the following:
delay SCLK to drivers disabled 15 nsec typical delay SCLK to drivers disabled 25 nsec maximum delay SCLK to drivers enabled 30 nsec typical delay SCLK to drivers enabled 45 nsec maximum 25 bus settling time20 nsec maximum bus setup time25 nsec maximum clock skew 10 nsec maximum total 100 nsec Tri-state drivers provide cleaner, faster switching speeds than open-collector. ~lowever, severe noise problems can result whenever two opposing drivers are enabled simultaneously. A slight overlap of a few nsec is acceptable if the drivers are properly clecoupled. Every driver should have an adjacent 0.1 uf decoupling capacitor.
Any overlap increases system noise, but comparable currerl-t spikes occur when switching a high capacitance bus.
However, consistent overlaps greater than 5 nsec must be avoided. Each module board must reduce tri-state conflict by delaying bus enable versus bus disable by 10 nsec.

Positional Priority Signals:
As discussed hereinabove, each positional priority encoder such as encoder 316 in FIGs. 2 and 3, has one input, TRQn- or FRQn-, and one output, TGRn- or FGRn-, for each path for each S-bus module slot. In the disclosed embodiment, as previously described, each encoder circuit 316 comprises three Fairchild 74F148 priority encoders and three Fairchild 74F138 decoders. The maximum delay from any RQn- to any GRn- is 20.5 nsec. Each RQn- signal provides an input load of one Fairchild 74F unit, e.g. NOR 315 in FIG.
2, plus a lK ohm pullup resistor, e.g. resistor 371 in FIG.
2. The lK ohm pullup resistors hold unused inputs inactive high. Thus no jumper changes are needed when boards are inserted or removed.
~us path acquisition request and bus path grant signal timing is given by the following:
delay SCLK to RREQ-, HREQ-15 nsec max settling time 30 nsec max delay RREQ-, HREQ- to RQn-10 nsec max delay RQn- to GRn-20 nsec max sèttling time GRn- to LCI,K15 nsec max clock skew 10 nsec max total100 nsec Bus Capaeitance:
Bus eonneetions have high distributed capacitance.
This a~fects signal transmission by lowering the characteristic impedance and slows the rise time on the open collector signals.

~7~

per board: multiwire 3pf/inch x3" = 10pf, x 1.5" = 5p input 74F 5 74F 5 output 74F 5 74F38 10 connector, pins, etc 5 5 TOTAL per board 25 25 x 22 boards = 550pf 550pf backpanel: multilayer 2 pf/inch x 17" = 35pf TOTAL per line 585pf 585pf Hold Times:

Data is transferred from a source register to a destination register during one bus operation cycle. The worst case delays and necessary setup times determine the cycle time (100 nsec nominal). In effect, clock skew shortens the cycle to 100-10 = 90 nsec.
Hold times are more difficult since the clock skew is comparable to the minimum delay path. Extra timing margin is desirable. Input registers are clocked on every cycle.
Output clocks are gated and may have an extra gate delay.

clock Skew:

OSC- is radially distributed to each board in the system. It has a nominal 50% duty cycle, ~- 10% or 5nsec.
The high and low periods can nominally vary between 20 and 30 nsec. ~lowever, pulse width becomes less certain with each buffer. Only the fall~ng edge of OSC- may be used for timing.
MEMORY OPERATIONS OVERVIEW

S-bus memory comprises one or more memory modules, each containing a controller an~ an array of semiconductor memory chips. MGdules are selected by memory address using decoders on each board. Different size and speed modules can be mixed on the same buS.

~az97~z There are three types of memory operations which can be perormed in a memory module: read, write and special.
The special operations combine a read-modify-write operation into a primitive command.

Interleaving:

Burst transfers ~rom or to memory are divided into quadword block transfers. Each memor~ module interleaves four rows of d~namic RAM on quadword boundaries to ma-tch bus bandwidth for a quadword -transfer. Dynamic RAMs require a precharge time before they can be accessed again. The cycle time for a quadword read for any row, including a precharge time of 200 nanoseconds (ns), is ~00 ns ~or the disclosed embodiment. The memory module activates another row while a row that had just been accessed precharges.
This means that successive quadword accesses are overlapped by 200 ns, thereby reducing the effective cycle time for these operations to 600 ns. However, one module cannot match the bandwidth of both buses. Also, byte, halfword, and special operations are slower than bus speed.
Improved bandwidth is possible when there are two or more memory modules to share the wor~. These memory modules share the bus most effectively when bus operations alternate between modules. Thus, two or four modules can be interleaved by ~uadwords. Burst transfers access each module cyclically, with successive quadwords being sent to different modules in turn. Module interleaving is determined by address decoders in each module.
Each module contains an input buffer which stores addresses and data received while the module is busy performing previous operations. The buffer improves performance by allowing more effective sharing of the bus.
However, buffer size is limited to pruvide adequate access times for high-priority read operations --in the disclosed embodiment, operations already in the buffer are completed first.

~2~

The buffer preserves the sequence of operations to any given memory location. Otherwise, memory values could be uncertain. Operations to different addresses proceed in any order; the queue on any module is independent of the other modules.

Address Space:

32-bit memory addresses are transferred on T-path.
This provides a 4-gigabyte real address space.

Memory Read Operations-The four memory read commands MRl, MR2, MR3, and MR4 read 1 to 4 words from memor~ without altering the contents of memory. MR1 reads one fullword, but it can be used for byte and halfword reads as well. Bytes and halfwords have the same alignment on the bus as in memory, i~e. the byte select bits of the data address, A01:00, are ignored by the memory modules.
MR4 reads an entire quadword, whereas, MR2 and MR3 read two or three words -from the same quadword. Words are selected by memory address bits 03:02. The addressed word is transferred first; the remaining words are transferred in cyclic order: 0, l, 2, 3, 0, 1, 2, etc. The 2-bit word address is returned with eaah word as part of the F-path function code.
The sequence of a read operation is:
bus-op 0 cycle I 1 ][ 2 ~[ 3 ]~ ~ ] ... [ 5 J[ 6 ][ 7 ][ 8 ]
[ ][ ]<---memory-read-------~T-pth[ rq ][ A ][ ][ ak ] [ ][ ~[ ][ ]
F-pth~ J[ ][ ][ ] [ rq ][ D ][ J[ ak ]
cycle 1. source module, e. g. a processor, acquires T-path (rq) ~7~

cycle 2. address cycle (A) - the source module, e.g. processor:
(1) puts read function on TFN~:O
(MRl, MR2, MR3, MR4 (2) puts source unit ID onto TID7:0 (3) puts memory address onto T31:00 All memory modules latch T-path data every cycle. The source module then releases the bus after only the address (A) has been sent. 0 cycle 3. each memory module decodes the memory address todetermine if it contains the addressed word. If not, it takes no further action. Parity is checked. The selected memory module begins the memory operation. 5 cycie 4. the selected memory module acknowledges (ak) the read message.
The memory module reads the requested data from the memory array and prepares to send it to the source module which requested it.
cycle 5. The memory module acquires the F-path (r~
cycle 6. data transmission cycle (D) - the memory module:
(1) puts response function on FFN4:0 "MOKn" or "MDCn" indicates the data is valid "MERn" indicates an uncorrectable memory error "n" = O, 1, 2 or 3 indicates which word this is, within a quadword block. "n" is bits ~03:02 of the address for the word on the bus.
(2) puts the source unit ID latched in cycle 3 onto FID7:0 (3) puts a data word on F31:00 The memory module release~ F-path during the last data word transferred. Usually, all requested words are transferred on consecutive cycles. However, memorv data errors can slow or interrupt the transfer. The memory controller in th8 disclosed embodiment is allowed to ~7~9;~:

request the F-path before it has checked the data for validity. If there is an error, the next cycle is wasted and the corrected data word is sent on a later cycle.
Each module, such as processors and so forth, latch data on the F-path during every cycle.
cycle 7. each module, s~lch as processors and so forth, match FID to its own ID. If unequal, the module takes no further action. The source module checks the data ~or proper parity.
cycle 8. the source module acknowledges the item with either "here" or "fault." In the disclosed embodiment, the source modules are not allowed to respond "busy" or "not present" to memory operations they request. Any response other than "here" is a malfunction.
Cycles 6 to 8 are repeated for each additional word accessed. For example~ an MR~ transfers four words on F-path:
cycle ... [ 5 ][ 6 ][ 7 ][ 8 ][ 9 ][ 10 ][ 11 ]
read---->]
F-path [ rq ~[ DO ][ D1 ][ D2 ~[ D3 ][ ][ ]
ack. [ ][ ][ ][ dO ][ dl ][ d2 ][ d3 ]

Memory Write O~erations:
Memory write operations write byte, word, or multi-word data into memory. The data word(s) immediately ~ollows the address on the T-path. F-path is not used.

The sequence of a write operation is:
cycle ~ 1 ~C 2 ][ 3 ~C 4 ][ 5 ][ 6 ][ 7 ~[ 8 ]
[ ][ ]<---memory-write----------> quadword~-->
T-path [ rq ][ A ][ D1 ~[ D2 ][ D3 ][ D4 ][ J[ ]
ack. [ ]~ ][ ][ a ][ dl ][ d2 ][ d3 ][ d4 ]
D2, D3 and D4 are used only in quadword operations The sequence of a write operation is:

cycle 1. source module, e. g. a processor, ac~uires T-path (rq) cycle 2. address cycle - this is the same as in a read operation except that the function code specifies a write: MW1, MW2, MW3, or MW4. The source module retains the bus by asserting TKEEP.
cycle 3. data c~cle - the source module:
(1) puts write data onto T31:00 (2) puts its unit ID onto TID7:0 (3) puts a data code on TFN4:0, i.e. DWO, DWl, DW2, or DW3 During the last data cycle of the normal memory writes, function DWn specifies that writing ends on byte "n." This is used for byte, halfword or other partial word writes-Function code DW3 must be used for other write datacycles and for all special memory data on T-path.
Meanwhile, each memory module decodes the memory address to determine if it contains -the addressed word. If not, it takes no further action. Parity is checked. The selcted memory module begins the memory operation.
cycle 4. The selected memory module acknowledges the address cycle.
cycle 5. The selected memory modules acknowledges the data cycle.
For MW2, MW3, and MW4, additional data is sent in cycles 4, 5, and 6. Each item is checked and decoded on the cycle after it is sent; then acknowledged on the following cycle: 6, 7, and ~.
_ltiple- ord Wri-te Operations:

The multiple-word operations (MWl-MW4) write a string of data into a memory quadword. The string begins at the addressed byte. Lower bytes, i.e. to the left, in this word are not written. During the last word, the function code TFN4:0 se~ects the last byte t~ ~ writt~n.

Words are cyclic within a quadword. Writing begins at the addressed word and continues in cyclic order: 0, 1, 2, 3, O, 1, 2, and so forth. The entire quadword can be written starting with any word.
Partial quadword writes are useful for string operations and for burst transfers which begin or end on non-aligned addresses. Data bytes are aligned on the bus as in memory. Unused bytes are ignored except ~or parity checking. When only one word is transferred, the address and TFN both limit which bytes are written.

First word control Last word control ddress bytes written TFN4:0 function bytes written T01:00=000,1,2,3 DWO 00100 0 1501 1,2,3 DWl 00101 0,1 2,3 DW2 00110 0,1,2 11 3 DW3 00111 0,1,2,3 ,.
Bytes written when only one word is transferred (MWl):
Function code with data word address DWO DWl DW2 DW3 . _ . . _ .
... 00 0 01 012 0123 ... 01 none 1 17, 123 ... 10 none none 2 23 25 ... 11 none none none 3 Byte _ Halfword Operations:

Byte and halfword operations are performed as partial word wrl~es ~ith on~ data word, MWl; they are special cases of part~al word writes, as described above. The memory address specifies the first byte written; DWn specifies the last byte. The other bytes are not altered. Bus timing is the same as a fullword write; memory timing uses longer read-modify-write cycles because the error correction codes are computed on fullwords. Each byte to be written must be properly aligned within the data field; the memory controller does not shift data bytes. Unused bytes are ignored.
Byte Operations Halfword Operations Byte TOl:OO TFN4:0 Halfword (bytes) TOl:OO TFN4:0 _ O OO 00100 DWO O O,l OO OO101 DWl 1 Ol OO101 DWl 2 lO OOllO DW2 1 2,3 lO OOlll DW3 3 11 OOlll DW3 Special Memory Operations:

Special memory operations facilitate multiprocessor interaction. These operations are indivisible primitives which operate as read/modify/write cycles. They combine write and read data transfers on the S-bus. The original unmodified memory value is read and sent on F-path. Several types of operations are supported in the disclosed embodiment:
1. bit operations MRS and MRR set or reset any ona bit witin a data word. The number of this bit is selected by the write data value T04:00.
2. Exchange words MRW swaps a word with memory. The addressed word is read and returned on F-path; then the T-path data word is written.
3. Semaphore operations MRI and MRD increment or decrement the addressed word. The T-path data word is not used. By convention in the disclosed embodiment, all write messages are at least two words long.
The sequ~nce of any special operatiorl is:
cyc[ 1 ]C 2 ][ 3 ]~ ~ ][ 5 ] ~ ][
[ ][ ]<~ --read/moc~ify/write cycle------->
Tph[ r~ ]~ ~ ][ DW ~lak-A][ak-D]
Fph~ ]~ ]~ ]~ r~ ][ DR ][ ][ ak]

T-path operates as A memory write and F-path operates as memorY read--41- CS 35~1 _st-and-Set Operations:

Test-and-Set (T&S) memory operations are used to coordinate activity within mul-ti-tasking systems. T&S
provide race-proof interlocks for allocating acc~ss to devices, tables, or other resources. The memory system performs an indivisible operation which: reads the interlock word, tests the specified bit, then sets it, and writes the word. This function is performed by the MRS
command.

DI~ECT TRANSFE~S ON F-PATH OVERVIEW

In addition to memory read data described above, the F-path is used for inter-processor messages, broadcast interrupts, direct I/O and compatible I/O.

Interprocessor Messaqes:

Inter-processor "messages" transfer interrupts and three data words from any processor or channel to another designated processor or channel. Such messages are used by system designers to coordinate processors in multiproceesor systems, to initiate channel operations, and to reschedule tasks when I/O operations are completed.
In the disclosed embodiment, channels perform input/output tasks according to "channel command blocks"
(CCB) stored in memory. CCB's contain informa-tion for selècting device~, Eunctions, memory buffers and so forth connected with a particular I/O operation. The processor sends a message to an I/O channel to initiate the operation of a CCB. The message includes the CC9's address in memory.
The channel then accesse.s the CCB using memory operations described hereinabove and performs the required functions.
Data is transEerred directly to or ~rom memory. The channel can chain data buffers and commands under the dir~ction of the CCB. The channel reports its status to the processor by sending messages thereto.
In the disclosed embodiment, the interprocessor messages are: (a) "start I/0" command which is sent from a processor to a channel to initiate a CCB, (b) "halt I/0'1 command which is sent from a processor to a channel to halt execution of a CCB, (c) "end I/0" interrupt which is sent from a channel to a processor to interrupt the processor after a CCB is completed, or (d) "processor" interrupt which is sent from a first processor to a second processor.
Although the source and destination modules are either processors or channels, these designations are flexible.
For example, an I/0 processor could accept messages as a channel or a channel could request I/0 operations from another channel.
The interprocessor message is three words long:

word FFN _ FIDF31 - F00 1 18 unit-dlevel, unit-s, parameter #1 20 2 13 unit-dparameter #2 3 13 unit-dparameter #3 where:
FID, i.e. FID7:0, is the ID of the destination module, unit-d; unit-s is the ID of the source module; level sets the "priority" of the CC~ operation or interrupt, for example in the disclosed embodiment 0 is the highest priority, and parameter #1 is a halfword, parameters #2 and #3 are fullwords whose meaning is defined by software convention.

The sequer.ce of a message is:
cycle [ 1 ][ 2 ][ 3 ][ ~ ][ 5 ]
F-path [ rq ][ MSG][ Dl ][ D2 ~[ ][ ]
ackn [ ][ ][ ][a-MS][a-Dl}~a-D2~
cycle 1. source module requests and acquires F-path (rq) 97~

-~3- CS 3511 cycle 2. source unit puts word 1 on the F-path (MSG):
(1) puts function code MSGn on FFN4:0 (2) puts the destination unit ID on FID7:0 (3) puts level, source uni~ ID and param~ter #1 ~ on F31:00 All processors and channels latch F-path data every cycle cycle 3. source unit puts word 2 on the F-path (Dl) (1) puts function code FD~T on FFN4:0, "data word"
(2) puts destination unit ID on FID7:0 (3) puts parameter #2 on F31:0 cycle 4. source unit puts word 3 on the F-path (D2) (1) puts function code FDAT on FFN4:0, "data word"
(2) puts destination unit ID on FID7:0 (3) puts parameter #3 on F31:0 (4) destination module acknowledges word 1.
cycle 5. destination module acknowledges word 2.
cycle 6. destination module acknowledges word 3.

Broadcast Interrupts~

Broadcasts are interrupts which are sent simultaneously to all processors within an S-bus system.
Processors receive all broadcasts regardless of their ID.
Two broadoast interrupts used in the disclosed embodiment are "Pre-empt" (PRE) and "Start Real Time Clock" (S~NC).
Broadcasts are not acknowledged on the F-path. Thus, processors must use the broadcast when it is received, i.e.
they cannot respond with a "busy" acknowledge to request that the message be repeated.

The sequence of a broadcast interrupt is:
cycle ~ 1 ][ 2 ]~ 3 ][ 4 F-path [ r~ ][ FN ]~ ][ ]
ackn [ ][ ][ ][ ]

'75'~;~
-~4- CS 3511 cycle 1. source unit re~uests and acquires F-path (rq) cycle 2. BROADCAST: the module (1) puts function code (PRE or another defined codes) on FFN4:0 (2) puts zero in FID7:0 (3) puts the broadcast message on F31:0 All processors and channels latch F-path data every cycle.
cycle 3. All processors decode the broadcast message.
Broadcasts are not acknowledged.
"Start Real Time Clocks" is used to synchronize clocks within a multiprocessor system. In the disclosed embodiment, every processor includes a 64-bit "real time"
clock which keeps precise time by counting system bus operation cycles. Once initialized, all clocks within the system will keep exactly the same time. SYNC does not send any data, i.e. bits F31:00 are ignored. However, the sender will place its ID into bits F23:16 for use by bus monitors.
The following procedure is used to initialize clocks:
step 1: One processor send.s messages to all processors instructing them to stop their real-time clocks and to reload them with the 64-bit time contained in parameters ~2 and #3 of words 2 and 3 of the interprocessor message.
step 2: the one processor waits for 100 microseconds to provide time for each other processor in the system to acknowledge its message interrupt and to reload its real-time clock.
step ~: the one processor issues SYNC on the F-path.
This broadcast message is decoded by hardware within each processor and all processors start their clocks within two cycles to provide precise synchronization.
SYNC is a 1-word message whose format is:
FFN is ~16; FID is sender's ID (used for a broadcast message to be decoded by all processors and channels on the S-bus system); and F23: 16 is sender ID.

~Z9~

Direct Input/Output:

Direct I/O allows a processor to read or write a word from a selected device or ch~nnel. The complexities of channel I/O are avoided, but the processor must wait ~or a response. Direct I/O is useful f~r cc~municating with test equipment.
The processor can read (IOR) or write (IOW) data to a selected device. IOR sends one word and IOW sends data in a second word. The destination module resp~nds with either an IOK, the operation was completed succe~sfully, or an IER, error. Read data is returned with IOK

The sequence of direc~ I/O is:
cyc[ 1 ][ 2 ]L 3 ][ 4 ]~ 5 ] ...[ 6 ][ 7 ][ 8 ][ 9]
[ ][ ]<---input/output------>
Fph[ rq ][ IOR~[ ][ ak ][ ]... [ rq ][ IOK][ ][ak]
or [ rq ][ IOW][ D ][ak-W][ak-D]... [ rq ][ IOK][ ][ak]
cycle 1. processor acquires F-path (rq) cycle 2. select cycle - the processor:
(1) puts IOR or IOW on FFN4:0 (2) puts destination module unit ID on FID7:0 (3) puts subfunction/device on F31:00 as follows:
F31:28 (4-bits) subfunction F27:24 ~-bi~s,~ lluJt used F23:16 (3-bits) sender unit ID
F15:00 (16-bits) channel/device number cycle 3. data write cycle - IOW only - the processor (1) puts FDAT on FFN4:0 "data word"
(2) puts destinatlon unit ID on FID7:0 (3) puts write data on F31:00 cycle 4. destination ~nodule ~cknowledges select cycle (ak) cycle 5. destination module acknowledges data write cycle, IOW only (alc-W) [I/O unit does a data trans~er]

cycle 6. destination module acquires the F-path (rq) cycle 7. IOK or IER cycle - the destination module:
(l) puts IOK or IER on FFN4:0 (2) puts processor unit ID on FID7:0 (3) puts data on F31:00 - response to IOR only cycle 8. processor decodes and checks item received cycle 9. processor acknowledges (ak) Compatible I/O
.

Compatible I/O operations are provided in the disclosed embodiment by a "Direct Memory Interface" (DMI) board to provide compatible 3200-series MUX and EDMA I/O
buses. A processor uses direct I/O operations to access -the DMI and a subfunction determines whioh specific MUX-bus operation is performed.

Multiple S-bus Systems:

Two or more S-bus systems can be interconnected to operate to~ether. Processors can access memory in other systems by using real addresses or by sending messages to other modules using unit IDs.
Two S-buses are connected by a system cable which symmetrically joins "system-bus expansion" board ~SBX) interfaoes in each S-bus. Each S-bus can have a separate power supply, diagnostic system and clock distribu-tion means.
An SBX monitors both the T-path and the F-path ~or operations addressed to the remote system. On the T-path, an SBX responds to selected memory addresses which are stored, ir~ the disclosed embodiment, as a bit map in a RAM.
For example, using a 64~ x 4 bit RAM, one stores four bits ~or each 64K byte block in the S-bus 4G byte real address space. On the F-path, an SBX responds to selected unit IDs.
These are stored, in the disclosed embodiment, as a bit map in a 256 x 4 bit RAM.

~7~

Messages received by a local SBX are acknowledged, buffered, and forwarded to a remote SBX. The remote SBX
acquires the corresponding remote path and echos the message. The two SBX's reverse roles for operations from the remote system.
SBX operations on T-path and F-path are independent of each other, except for the fact that in the disclosed embodiment they share the same cables. F-path transfers have priority for the cable.
An SBX uses an entire bus operation cycle to decode an address. Thus, it can use fast RAM memories to store a bit map of each unit ID and eac~ lM-byte memory block to be accessed in the remote system. If desired, the SBX can only allow access to a subset of the remote system. Unit IDs and addresses are not translated by the SBX and messages are echoed without modification.
An SBX uses four unit ID's so that it can overlap memory reads. It substitutes one of these for the ID of each remote memory operation it receives. The original ID
is not put on T-path, but is saved and returned with the read data. Thus, the IDs used to access memory do not need to be unique system-wide. The unit ID coming from a memory request is not matched against the ID RAM.

System Cable:

FI~. 1 shows an SBX 110 being connected to a system cable which comprises data paths 117 and 118. Data paths 117 and llB are similar to T-path and F-path. Messages ~rom S-bus 10 or 20 are sent by SBXs 110 and 210 onto a data path from a connection labelled CT and messages ~or S-bus 10 and 20 are received by SBXs 110 and 210 from a data path at a connection labelled CF. System cable 107 connects each CT connection of a local SBX, e.g., SBX 110, to the CF
connection of a remote SBX, e.g., SBX 210.
The signal definitions are similar to that on the S-bus. An extra signal indicat~s which path each meSSage is ~97~

from: CTT=1 selects T-path; CTT=O selects F-path. Note that CTT is received by the remote SBX as CFT.

S-cable Signal definitions:
CT CF
transmitted received as Signal definition . . .
CT31:00- CF31:00- 32-bit data fi.eld CTFN4:0- CFFN4:0- 5-bit function select CTID7:0- CFID7:0- 8-bit unit ident. no.
CTPAR5:0- CFPAR5:0- parity bits control signals:
CTT- CFT- T path (1) or F-path (0) mess.
CTAK1:0- CFAK1:0- Acknowledge CTRDY- CFRDY- Ready for more data Each SBX transmits a continuous clock CTCLK from the CT connection; all items are synchronous with this clock.
However, a remote SBX must be able to receive this clock, as CFCLK, asynchronously to its own clocks, because the remote system may operate on a different oscillator.
However, an SBX should also be able to operate synchrously when S-buses operate synchronously.

DESCRIPTION OF COMPOSITE MEMORY MODULE
Composite Memory Module (CMM) 1000 is a combination storage control module and memory control].er on one board for the Model 3280MPS computer system manufactured by Concurrent Computer Corporation. Several CMMs in a computer system may be interleaved on ~uadword boundaries in either 2-way or 4-way mode.
As shown in FIG. 5, CMM 1000 contains l, 2, or ~
arrays of dynamic memory 601-604, each consisting of 156 dynami~ RAMSs ~6~K x 1 or 256~ x 1) organized into ~ rows by 39 bits~ ~his allows for 32-bit data storage with a 7-bit error-check-and-correct (ECC) code that provides single bit error detection and correction, double bit error 9~2 detection and some multiple bit error detection. Data storage capacity for CMM lO00 is 1, 2, or 4 megabytes using 64K x l dyna~ic RAMs and 4, 8, or 16 me~abytes using 256K x 1 dynamic RA~s.
Packaging is accommplished using quad-sinyle-in-line packages, QSIPs, which are ceramic substrates with 22 pins on 0.1 inch centers. Four RAMs are mounted on each and the QSIPs are mounted vertically on CMM 1000. This approach allows for four arrays of memory. It is possible to depopulate this board to either 1 or 2 arrays.
As shown in FIG. 5, memory arrays 601-604 are each 64K
x 1 bit dynamic RAMs with a nibble mode. In one embodiment, nibble mode provides high speed serial access of 2, 3, or 4 bits of data. Whenever a RAM is activated, it internally accesses 4 bits of data as selected by the 8 row address bits and the most significant 6 bits of the column address.
The 2 least significant bits of the column address, designated A3 and A6, select 1 of the 4 nibble bi-ts for the initial access. The remaining nibble bits can then be accessed by toggling the CAS control signal on lines 605 high and then low while the RAS control signals on lines 605 stay low. Toggling C~S on lines 605 causes A3 and A6 to be incremented internally while all other address bits remain unchanged. If more than 4 bits are accessed during a nibble mode access, the address sequence repeats. If any bit is written during a nibble access, the new value will be read on any subsequent nibble access. 256K x l RAM chips produced by some manu~acturers provide a slightly different nibble mode than that described above. In one instance, the 4 bits o data are selected by the 8 least significant bits of both the row and column addresses, and the most si~nificant bit of both the row and column address are used to select 1 of the 4 nibble bits for the initial access.
Data to be written into memory is supplied to memory arrays 601-604 through write data register (WDR) 610. Data read from memory is taken from memory arrays 601-60~ and is buffered through the read data buffer (RDB) 612 and loaded therefrom into read data register ( RDR) 613. The address for the data in memory arrays 601-604 is held in address latch (AL) 614. The memory address is supplied to memory arrays 601-60~ by means of address multiplexer (AMX) 616.
The 4 rows in each memory array are interleaved on quadword boundaries under the control of sisnals RASO: 3- on lines 605. Any time a row is activa-ted, up to 4 words can be accessed by taking advantage of nibble mode. This allows high speed quadword access while only having 1 row of memory active.
All commands for memory operations are initiated on CMM 1000 by supplying a master ID, function code, and 32-bit address on the T-path. AS described above, transfers on the S-bus are performed at a lOMHz rate which is derived from OSC- and kept in sync by CLK-. OSC- and CLK- are supplied to CMM 1000 over lines 619 to clock drivers 620.
CMM 1000 accepts commands by constantly monitorin~ the 50 leads comprising T-path on line 621. This is done by sampling the T-path at every bus operation cycle with input latch (IL) 622. IL 622 comprises seven octal latches which receive data from the T-path. The output of IL 622, i.e.
all 50 input bits, are transmitted to parity check circuit (PCC) 671. PCC 671 computes the parity of the 50 bits and compares it with the transmitted value, TPAR4:0. If an error occurs, a parity error signal is sent to T-path FIF0 624 and to T-path acknowledge (TPA) 673. In addition, 19 bits --T31:20, T05:0~, and TFN~:0-- are sent from IL 622 to board select logic (BSL) 672 over line 627. BSL 672 uses bits TFN4:0 to determine whether the command is a memory operation and uses bits T31:20 and T05:0~ to determine whether the addr~ss o the memory operation is to be found within the memory arrays 601-60~ which comprise CMM 1000.
If both conditi~ns are true, ~SL 672 sends a signal over line 62~ to TPA 673. In response, TPA 673 applies the appropriate acknowledgc response TAK1:00 to line 625.
In addition, when the function code of the received bus data item signifies that a memory operation is required ~7~9;~

and an address match occurs for CMM 1000, 45 bits from SL
622 --T31:00, TFN4:0, TID7:0-- are sent over line 623 to FIF0 624. As described above, any write data, up to 4 words, accompanying a write command will ollow on consecutive cycles on the T-path. This subsequently sent write data is also stored in FIFO 624. In the disclosed embodiment, FIFO 624 is 15 words deep and will accept commands until ll locations are filled. CMM 1000 does not accept commands after FIF0 624 has 11 locations filled 10 because 5 locations in FIFO 624 are required for a quadword write command. When FIF0 624 can no longer accept commands, a signal is sent to TPA 623 and TPA will transmit a "busy"
acknowlsdge response as TAK1:0- on line 625. In the disclosed embodiment, T-path FIF0 624 comprises thirteen 15 16K x 4 RAMs. The data signals entering FIFO 624 is neyative-true and positive-true leaving, i.e. the data signals are inverted.
Command signals in FIF0 624 are fed over line 630 to command latch (CL) 631 to start a memory operation: master 20 unit ID TID7:0, memory operation function code TFN4: 0 and status information. At the same time, the address of the memory operation in FIFO 624 is fed over lines 701 to address latch (AL) 614.

READ OPERATIONS
. . . ~ .

P~fter CL 631 and AL 614 are loaded with a read command, a row of RAMs in one of memory arra~s 601-604 is activated, as selected by CL 631 and AL 614, by signalling 30 array drivers 47 to assert the proper RASn- signal on lines 605 low. AMX 616 first receives a row address for the data from AL 614 over line 705. Then, AMX 616 is switched to provide a aolumrl address to the arrays, which column address is received from AL 614 over line 706. CAS- is ther asser-ted over line 605. Data is then read out of the selected row in memory arrays 601-604 over lines 635. The data is buf~ered in RDB 612 and .~tored in RDR 613. The 979~

contents of RDR 613 are then transmitted to error-check-and-correct circuit (ECC) 640 for checking. If ECC 640 does not detect an error, the da-ta is transmitted for storage to data output register (DOR) 645. F-path control circuit 57 acquires F-path and a bus data item is output over the 50 leads of -the F-path by (l) placing the read data in DOR 645 on line 646, (2) placing the ID of the master which requested the operation in DOR 656 on line 660, the ID having been previously forwarded from CL 631 over line 665 to DOR 656, (3) placing the response code from DOR 658 on line 662, and (4) placing parity from DOR
657 onto line 661, the parity having been generated by the parity generation circuit (PGC) within special function gate array 59.
If additional words, up to three more, are to be accessed, signal CAS-, applied over line 605, is toggled by array control line driver 47.

WRITE OPERATIONS
A write operation starts exactly like a read operation through the time signal CAS- is first asserted over line 605. Write data is then sent from FIFO 624 over line 666 for storage in data input register (DIR) 667. The contents of DIR 667 are transmitted to ECC 640. Check bits are generated by ECC 6~0. The check bits and write data are then stored in WDR 610. Array control line driver 47 then asserts signal WE- to cause the write data in WDR 610 to be stored in memory arrays 601-604. If additional words are to be written into memory, up to three more, these words are taken from FI~O 6~4, loaded into DIR 667, stored into WDR
610, and written into memory by keeping signal WE- low and toggling signal CAS-.
Byte, halfword, and string write operations are performed using the above-described write operation and by supplying apprpriate proper function codes and addresses to CMM 1000 in the incoming bus data item. For the first word 97~2 of any write opera~ion, the 2 least significant bits of the address of the command are used to determine how many bytes of the first word are to written into me~ory: 00 means write bytes 0-3, 01 means write bytes 1-3, 10 means write bytes 2 and 3, and 11 means write byte 3. Bytes are ordered with byte 0 in data bits 31-24, byte 1 in data bits 23-16, byte 2 in data bits 15-8, and byte 3 in data bits 7-0. For the last word o~ any write operation, the accompanying function code determines how many bytes of that word are written into memory: 00100 means write byte 0, 00101 means write bytes 0-1, 00110 means write bytes 0-2, and 00111 means write bytes 0-3. The combination of the 2 least significant address bits of the MW1 command along with the function code in the write data portion of the MW1 command, many different partial writes can be performed.
Whenever a part of a word has to be written into memory, CMM 1000 first reads the word at the desired location out of memory into RDR 613, checks for errors, replaces part of the data in RDR 613 with write data from DIR 667, generates new check bits, stores the modified word and the new check bits into WDR 610, and writes the contents of WDR 610 into memory.

SPECIAL OPERATIONS
In the disclosed embodiment, CMM 1000 performs 6 special operation~s. The first 5 of these read data out of memory, place the data on the F-path, modi~y the data, and write it back into memory.
The memory read and set, MRS, an~ the memory read and reset, MRR, start out exactly like read operations up through the time data is placed on the F-path. At that time, the data is latched into yate array 675. A 5-bit select code is then read from FIFO 624 and sent to gate 35 array 59. This cod~ ts derived ~rom T04:00- on the cycle immediatel~ following the MRS/MRR command on T-path. Gate array S9 then either sets or resets 1 of 32 bits in the ~Z97~2 -5~- CS 3511 latched word. The modified word is then read ou-t of the gate array and into ECC 640, new check bits are generated, the data bits and the check bits are stored in WDR 610.
Then, the contents of WDR 610 are written into memory.
Memory read and increment, MRI, and memory read and decremen~, MRD, are performed exactly like MRS/MRR except ~or the fact that no 5-bit code is taken from FIF0 624, and gate array 59 increments or decrements the word read out of memory by 1.
The memory exchange operation, MEX, is per~ormed exactly like an MRS/MRR except for the fact that instead of using gate array 59 to modify the word read out of memory, a new 32-bit word is placed in DIR 667 from FIF0 624 and this new word is written into memory.
The sixth special operation, memory writ~ dia~nostic, MWD, does not place any data on the F-path. MWD reads a word out of memory, discards the 32-bit data, supplies a new 32-bit data through DIR 667 from FIFO 624, and writes the new word with the old check bits into memory through WDR 610. This makes it possible to force errors on a subsequent read to the same location.

ECC
.

ECC 64~ is implemented in the disclosed embodiment by use of the Texas lnstrument TI 74ALS632 32-bit ECC chip.
ECC 640 has the ability to detect and correct all single-bit errors in memory, detect all double-bit errors, and detect some multiple-bit errors.
If a single-bit error i.s detected during any memory operation, ECC 640 will latch the bad data off internal data bus 640 from RDR 613, correct the data, store the corrected data in WDR 610, and move data from WDR 610 to RDR 613. In the case of a read operation, new check bits are generated for the new data in RDR 613, the data and the check bits are stored in WDR 610, an~ the contents of WDR
610 are written into memory. Write and special operations ~55~ CS 3511 continue normally after the corrected data has been placed in RDR 613.
When double or multiple-bit errors are deteced, CMM
1000 sends the bad data out on the F-path wi-th the proper response code during a read or special operation, 0xcept for MWD. In the case of a write operation, when a partial word is being written, CMM 1000 overwrites the addressed location with an all ones pattern. This will force a multiple-bit error condition back to the requesting master while performing a write operation. The data in memory is not modi~ied if a multiple-bit error occurs during a read or special operation. Memory errors canno-t occur during a MWD operation because the data read out of memory is not checked.
Clearly, those skilled in the art recognize that further embodiments of the present invention may be made withou-t departing from its teachings.

Claims (63)

1. A synchronous priority positional bus in conjunction with a pull up resistor and a bus allocation positional priority encoder for transmitting data, function codes, identification codes and parity information between modules connected thereto which comprises:
at least one path which comprises:
(a) 32 path lines for transmitting path data;
(b) 5 path lines for transmitting path function codes;
(c) 8 path lines for transmitting path identification codes;
(d) 5 path lines for transmitting path parity information;
(e) 4 path acquisition lines for transmitting path acquisition signals; and (f) 2 path acknowledge lines for transmitting path acknowledge codes.
means for interfacing modules to at least one path;
path system acquisition means comprising:
(a) means, responsive to path module signals -56a-generated on at least one module, for generating the path acquisition signals; and (b) means, responsive to path module acquisition request signals generated on at least one module in response to the path acquisition signals, for generating path module acquisition grant signals.
path module acquisition means, disposed on at least one module, comprising:
(a) means for generating the path module signals;
(b) means for generating the path module acquisition request signals in response to the path acquisition signals; and (c) means for determining whether at least one module has acquired the path in response to the path module acquisition grant signals.

2. The bus of claim 1 wherein the path system acquisition means further comprises means for assigning positional priority to the modules and for giving preferential access to a path to modules having higher positional priority.

3. The bus of claim 2 wherein:
(a) a path module acquisition means further comprises means for generating a "simple bus request" signal as one of the path module signals; and (b) the path system acquisition means further comprises means, in response to the "simple request" signals from the modules, for generating a composite simple request , REQ-, signal as one of the path acquisition signals.

4. The bus of claim 3 wherein the path module acquisition means for determining whether at least one module has acquired access to the path in response to the path acquisition grant signal comprises means for generating a MINE and a MINE- signal having a first and a second logical value, respectively, if the at least one module has access to the path and having the second and first logical values, respectively, if the at least one module does not have access to the path.

5. The bus of claim 4 wherein a path module acquisition means comprises means, in response to a signal from at least one module, for generating a bus request signal RQ having the first logical value if a module wants to acquire access to the path and a second logical value otherwise.

6. The bus of claim 5 wherein the path module acquisition means comprises means, in response to the MINE-and RQ signals, for generating the simple bus request signal which has the second logical value when at least one module wants to acquire access to a path and the path is not already accessed by a module, i.e., when RQ and MINE- have a first logical value, and which "simple bus request" signal has the second logical value otherwise.

7. The bus of claim 6 wherein the path system acquisition means further comprises means for ORing the "simple bus request" signals from the modules to generate the composite simple request signal, REQ-, on one of a first path acquisition lines.

8. The bus of claim 7 wherein the path module acquisition means further comprises a flip-flop for generating the RQ signal in response to a signal from the at least one module.

9. The bus of claim 3 wherein:
(a) the path module acquisition means further comprises means for generating a "keep access to the path" signal as one of the path module signals: and (b) the path acquisition means further comprises means, in response to keep access to the path signals from modules, for generating a composite keep access to a path signal, KEEP-, as one of a path acquisition signals, whereby modules having access to the path and requiring a path to complete a task may get to retain access to a path for the next bus operation cycle.

10. The bus of claim 7 wherein the path module acquisition means further comprises means, responsive to the MINE signal and to a more data signal from the at least one module having a first logical value when the module requests a path access for more than a single bus operation and a second logical value otherwise, for generating a keep access to a path signal having the second logical value when the module seeks to retain access to a path and the first logical value otherwise.

11. The bus of claim 10 wherein the path system acquisition means further comprises means for ORing the keep access to the path signals from modules to generate a "composite keep access to the path" signal, KEEP-, on one of the path bus acquisition lines.

12. The bus of claim 11 wherein a path module acquisition means further comprises means, responsive to the KEEP- and REQ- signals, for generating a PASS- signal having the second logical value when any module does not seek to retain access a path and the first logical value otherwise.

13. The bus of claim 12 wherein the path module acquisition means further comprises means, responsive to RQ, for generating the path module acquisition request signal.

14. The bus of claim 13 wherein the path module acquisition means further comprises means, responsive to the PASS- and one of the path module acquisition grant signals, for generating GETBUS and LOSEBVS signals, having a first and second logical values, respectively, when at least one module has obtained access to a path and the second and first logical values, respectively, otherwise.

15. The bus of claim 14 wherein the path module acquisition means further comprises means, in response to signals GETBUS and LOSEBUS, for generating signals MINE and MINE-.

16. The bus of claim 9 wherein:
(a) the path module acquisition means further comprises means for generating a round-robin request signal as one of the path module signals; and (b) the path system acquisition means further comprises means, in response to the round-robin request signals from modules, for generating a composite round-robin request signal, RREQ-, as one of a path acquisition signals, whereby modules requesting round-robin priority will be given access to path for one bus operation cycle until all modules requesting round-robin priority have had access.

17. The bus of claim 15 wherein a path module acquisition means further comprises means for generating round-robin request signals RREN and RREN- having a first and second logical values, respectively, when a round-robin request is desired and having second and first logical values, respectively, otherwise.

18. The bus of claim 17 wherein a path module acquisition means further comprises means, responsive to the RQ and RREN signals, for generating a round-robin request signal which has the second logical value when a module is seeking round-robin priority access to the path and a first logical value otherwise.

19. The bus of claim 18 wherein the path system acquisition means further comprises means for ORing the round-robin request signals from modules to generate a composite round-robin access signal, RREQ-, on one of the path acquisition lines.

20. The bus of claim 19 wherein the path module acquisition means further comprises means, responsive to the RREQ-, RQ, RREN, and RREN- signals, for generating the path module acquisition request signal.

21. The bus of claim 20 wherein the path module acquisition means further comprises:
(a) means to AND the RREN and RQ signals;
(b) means to AND the RQ, RREQ- and RREN- signals;
and (c) means to NOR the outputs of ANDs to provide the path module acquisition request signal.

22. The bus of claim 16 wherein:
(a) the path module acquisition means further comprises means for generating a high priority request signal as one o the path module signals; and (b) the path system acquisition means further comprises means, in response to the high priority request signals from modules, for generating a composite high priority request signal, HREQ-, as one of a path acquisition signals, whereby modules requesting high priority will be given preferential access to the first path over modules having a lower priority, the high priority requests being granted in order of positional priority.

-62- Cs 3511

23. The bus of claim 20 wherein a path module acquisition means further comprises means for generating a high priority signal HPEN having a first logical value if a module is seeking a high priority access to the path and a second logical value otherwise.

24. The bus of claim 23 wherein a path module acquisition means further comprises means, responsive to the HPEN and RQ signals, for generating a high priority request signal which has a second logical value when a module is requesting high priority access to the path.

25. The bus of claim 24 wherein the path system acquisition means further comprises means for ORing the high priority request signals from modules to generate a composite high priority signal, HREQ-, on one of the path acquisition lines.

26. The bus of claim 25 wherein the path module acquisition means further comprises means, responsive to the RREQ-, HREQ-, RQ, RREN, RREN- and HPEN signals, for generating the path module acquisition request signal.

27. The bus of claim 26 wherein the path module acquisition means further comprises:
(a) means to AND the RREQ-, HREQ-, RQ, and RREN-signals;
(b) means to AND the HREQ-, RQ and RREN signals;
(a) means to AND the RQ and HPEN signals; and (d) means to NOR the outputs of ANDs to provide the path module acquisition request signal.

28. The bus of claim 20 wherein the path module acquisition means further comprises a flip-flop, in response to signals RREQ- and GETBUS, for generating signals RREN and RREN-.

29. The bus of claim 26 wherein the path module acquisition means further comprises a flip-flop for generating signal HPEN in response to a signal from a module.

30. The bus of claim 29 wherein signals REQ- and KEEP- are open-collector signals.

31. The bus of claim 19 wherein signal RREQ-is an open-collector signal.

32. The bus of claim 25 wherein signals HREQ- is an open-collector signal.

33. The bus of claim 13 which further comprises means for inverting RQ to provide the path module acquisition request signal.

34. The bus of claim 15 wherein the path module acquisition means further comprises a flip-flop, in response to signals GETBUS AND LOSEBUS, for generating signals MINE and MINE-.

35. The bus of claim 1 wherein the path acknowledge codes are open-collector signals.

-63a-

36. The bus of claim 35 wherein the path data are tri-level signals.

37. A synchronous priority positional bus in conjunction with a pull up resistor and a bus allocation positional priority encoder path acquisition circuit for modules connected to a bus path which transmits data, function codes, identification codes and parity information between modules connected thereto, which bus path acquisition circuit interfaces with a path system acquisition circuit which generates path acquisition signals and path module acquisition grant signals, the bus path acquisition circuit comprising:

(a) means for generating path module signals, in response to which path module signals the path system acquisition circuit generates the path acquisition signals;
(b) means for generating path module acquisition request signals, in response to which path module acquisition signals the path system acquisition circuit generates the path module acquisition grant signals; and (c) means for determining whether a module has acquired a path in response to the path module acquisition grant signals.

38. The bus path acquisition circuit of claim 37 wherein a path system acquisition circuit further includes a circuit for assigning positional priority to the modules and for giving preferential access to the path to modules having higher positional priority and a means for generating a composite simple request signal, REQ-, as one of the path acquisition signals, the bus acquisition circuit further comprising means for generating a simple bus request signal as one of the path module signals, in response to which the path system acquisition circuit generates the composite simple request signal.

39. The bus path acquisition circuit of claim 38 wherein the means for determining whether the module has acquired access to a path in response to the path acquisition grant signal comprises means for generating a MINE and a MINE- signal having a first and a second logical value, respectively, if a module has access to the path and having the second and first logical values, respectively, if the nodule does not have access to the path.

40. The bus path acquisition circuit of claim 39 com-prising means, in response to a signal from a module, for generating a bus request signal RQ having the first logical value i' the module wants to acquire access to a path and the second logical value otherwise.

41. The bus path acquisition circuit of claim 40 com-prising means, in response to the MINE- and RQ signals, for generating the simple bus request signal, which signal has the second logical value when the module wants to acquire access to the path and the path is not already accessed by the module, i.e., when RQ and MINE- have the first logical value, and which simple bus request signal has the second logical value otherwise.

42. The bus path acquisition circuit of claim 41 wherein the path system acquisition circuit further includes a circuit for ORing simple bus request signals from modules to generate the composite simple request signal, REQ-, the bus path acquisition circuit comprising a flip-flop for generating the RQ signal in response to a signal from a module.

43. The bus path acquisition circuit of claim 41 which further comprises means, responsive to the MINE signal and to a more data signal from a module having the first logical value when the module requests a path access for more than a single bus operation and a second logical value otherwise, for generating a keep access to a path signal having the second logical value when the module seeks to retain access to the path and the first logical value otherwise.

44. The bus path acquisition circuit of claim 43 wherein the path system acquisition circuit further includes a circuit for ORing keep access to A path signals from modules to generate a composite keep access to the path signal, KEEP-, the bus path acquisition circuit comprising means, responsive to the KEEP- and REQ-signals, for generating a PASS- signal having a second logical value when any module does not seek to retain access to a path and the first logical value otherwise.

45. The bus acquisition circuit of claim 44 which further comprises means, responsive to RQ, for generating the path module acquisition request signal.

46. The bus acquisition circuit of claim 45 further comprises means, responsive to the PASS- and one of the path module acquisition signals, for generating GETBUS and LOSEBUS signals, having a first and second logical values, respectively, when a module has obtained access to the bus and the first and second logical values, respectively, otherwise.

47. The bus acquisition circuit of claim 46 further comprises means, in response to signals GETBUS AND LOSEBUS, for generating signals MINE and MINE-.

48. The bus path acquisition circuit of claim 40 which comprises means for generating round-robin request signals RREN and RREN- having a first and second logical values, respectively, when a round-robin request is desired and having a second and first logical values, respectively, otherwise.

49. The bus path acquisition circuit of claim 48 further comprises means, responsive to the RQ and RREN
signals, for generating a round-robin request signal which has the second logical value when a module is seeking round-robin priority access to a path and the first logical value otherwise.

50. The bus path acquisition circuit of claim 49 wherein the path system acquisition circuit further includes a circuit for ORing the round-robin request signals from modules to generate a composite round-robin access signal, RREQ-, the bus acquisition circuit comprising means, responsive to the RREQ-, RQ, RREN, and RREN- signals, for generating the path module acquisition request signal.

51. The bus acquisition circuit of claim 50 which comprises:
(a) means to AND the RREN and RQ signals;
(b) means to AND the RQ, RREQ- and RREN- signals, and (c) means to NOR the outputs of the ANDs to provide path module acquisition request signal.

52. The bus path acquisition circuit of claim 48 further comprises means for generating a high priority signal HPEN having the first logical value if a module is seeking a high priority access to a path and the second logical value otherwise.

53. The bus path acquisition circuit of claim 52 further comprises means, responsive to the HPEN and RQ
signals, for generating a high priority request signal which has the second logical value when a module is requesting high priority access to the path.

54. The bus path acquisition circuit of claim 53 wherein the path system acquisition circuit further includes a circuit for ORing a high priority request signals from modules to generate a composite high priority signal, HREQ-, the bus acquisition circuit further comprising means, responsive to the RREQ-, HREQ-, RQ, RREN, RREN- and HPEN signals, for generating the path module acquisition request signal.

55. The bus acquisition circuit of claim 54 which comprises:
(a) means to AND the RREQ-, HREQ-, RQ, and RREN-signals:
(b) means to AND the HREQ-, RQ and RREN signals;
(c) means to AND the RQ and HPEN signals; and (d) means to NOR the outputs of ANDs to provide the path module acquisition request signal.

56. The bus acquisition circuit of claim 50 further comprises a flip-flop, in response to signals RREQ- and GETBUS, for generating signals RREN and RREN-.

57. The bus acquisition circuit of claim 52 further comprises a flip-flop for generating signal HPEN in response to a signal from a module.

58. The bus acquisition circuit of claim 45 which further comprises means for inverting RQ to generate the path module acquisition request signal.

59. The bus acquisition circuit of claim 47 further comprises a flip-flop, in response to signals GETBUS AND
LOSEBUS, for generating signals MINE and MINE-.

60. A module which interfaces with a synchronous priority positional bus in conjunction with a pull up resistor and a bus allocation positional priority encoder comprises:
a first bus acquisition circuit for interfacing with a first path;
a second bus acquisition circuit for interfacing with a second path;
means disposed on a module for generating 32 bits of path data, 5 bits of path function code, i.e. the function field, 8 bits of path identification code, i.e.
the ID field, 5 bits of path parity information and 2 bits of path acknowledge code wherein a parity bit is an even parity bit for the ID and function fields, a second of the parity bits is the even parity bit for data bits 31 to 24, a third of the parity bits is the even parity bit for data bits 23 through 16, a fourth of the parity bits is the even parity bit for data bits 15 through 8, and a fifth of the parity bits is the even parity bit for data bits 7 though 0.

61. The module of claim 60 which further comprises means for receiving, on a path, function codes for reading and writing data from memory means disposed on said module and reading or writing data, the function codes comprising following five bits for a read:
10000 Memory Read: 1 word 10001 Memory Read: 2 words 10010 Memory Read: 3 words 10011 Memory Read: 4 words and the function codes comprising the following five bits for a write:
10100 Memory Write: 1 word 10101 Memory Write: 2 words 10110 Memory Write: 3 words 10111 Memory Write: 4 words.

62. The bus of claim 1 wherein at least one module further comprises means for generating acknowledge signals to bus operation cycles after a bus data items was sent on at least one path.

63. A module for interfacing with a synchronous priority positional bus in conjunction with a pull up resistor and a bus allocation positional priority encoder path wherein the bus path transmits data, function codes, identification codes and parity in formation between modules connected thereto which bus path includes:
at least one path which comprises:

(a) 32 path lines for transmitting path data;
(b) 5 path lines for transmitting path function codes;
(c) 8 path lines for transmitting path identification codes;
(d) 5 path lines for transmitting path parity information;
(e) 4 path acquisition lines for transmitting path acquisition signals; and (f) 2 path acknowledge lines for transmitting path acknowledge codes, The module comprising means for generating acknowledge signals two bus operation cycles after a bus data item was sent on a path.