CA1275463C - Multipurpose digital integrated circuit for communication and control network - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A low cost, multipurpose digital integrated circuit (IC) is used as the basic building block in establishing a network communication system over a desired communication link. The digital IC can function as an addressable microcomputer interface between the network line and a remotely located microprocessor which may, for example, comprise any microprocessor based controlled product. In such mode, the digital IC's function is to take data from the network and pass it on to the remotely located microcomputer upon command from the central controller and to transmit data from the microcomputer to the central controller. The digital IC may also function as a nonaddressable microcomputer interface between the central or master controller and the network line. In such case the digital IC's function is to continuously take data from the central controller and place it on the network and take data from the network and pass it back to the central controller. The digital IC may also function as an addressable load controller associated with an individual remote controlled device and responding to shed or restore load commands from the central controller over the network line. When so used the digital IC may also be commanded to transmit a reply message back to the central controller giving information as to the status of the controlled device, thus enabling the central controller to monitor a large number of remotely located controllable devices.

Description

1 51,930 MULTIPURPOSE DIGITAL INT~GRATED CIRCUIT FOR
COMMUNICATION AND CONTROL NETWORK

CROSS REFERENCE TO_RELAT~D APPLICATION

The invention disclosed herein relates to two-way communication and control systems. The following commonly assigned Canadian patent application relates to such communication and control systems; Serial number 484,817 file~ June 21, 1925, by Leonard C. Vercellotti, William R. Verbanets Jr. and Theodore H. York entitled "Digital Message Format for Two Way Communication and Control Network .

BACKGROUND OF THE INVENTION

A. Field of the~ Invention The present invention relates generally to information communication networks and, more particularly, to communication networks by means of which a large number of remotely positioned controllablP
devices, such as circuit breakers, motor overload relays, lighting systems, and the like, may be controlled from a central or master controller over a common network line which may comprise either the existing AC power lines, or 2 51,930 a dedicated twisted pair line, or in some instances a fiber optic cable.
The invention particularly relates to a low cost, multipurpose digital integrated circuit (IC) which can be used as the basic building block in establishing a network communication system over a desired communicatior, link. The digital IC can function as an addressable microcomputer interface between the network line and a remotely located microcomputer which may, for example, comprise any microprocessor based controlled product. In such mode, the digital IC's function is to take data from the network and pass it on to the remotely located microcomputer upon command from the central controller and to transmit data from the microcomputer to the central controller. The digital IC may also function as a nonaddressable microcomputer interface between the central or master controller and the network line. In such case the digital IC's function is to continuously take data from the central controller and place it on the network and take data from the network and pass it back to the central controller. The digital I~ may also function as an addressable load controller associated with an individual remote controlled device and responding to shed or restore load commands from the central controller over the network line. When so used the digital I~ may also be commanded to ~ransmit a reply message back to the central controller giving information as to the status of the controlled device, thus enabling the central controller to monitor a large number o~
remotely located controllable devices.

B. Descri~tion of the Prior Art Various communication and control systems have been heretofore proposed for controlling a group of remotely located devices from a central controller over ~z~
3 51,930 a common network line. Control systems for controlling distributed elec~.rical loads are shown, for example, in Miller et al's U.S. patents Nos. 4,167,786, issued September 1979, 4,367,414, issued January 1983, and 4,396,844, issued August 1983. In such systems a large number of relatively comple~ and expensive transceiver-decoder stations, each of which includes a microprocessor, are interconnected with a central controller over a common party line consisting of a dedicated twisted pair for bidirectional comrnunication between the central controller and all transceivers.
Each of the transceiver-decoder stations is also of relatively large physical size due to the fact that a substantial amount of hardware is required, in addition - to the micro-processor, to receive and transmit signals.
Also, both the hardware and microprocessor consume substantial amounts of power. In fact, in Miller et al's U.S. patent No 4,167,786 it is necessary to provide a powersaver mode in which the major portion of the circuitry at each remote station is de-energized to reduce power consumption during intervals when load changes are not being actuated.
Each of the transceiver-decoder stations controls a number of loads which must be individually connected to a particular transceiver by hardwiring, these interconnections being quite lengthy in many instances. In such a system, all transceivers can initiate messages at any arbitrary time in response to control input from the associated switches. Accordingly, it is not uncommon for two or more transceivers to simultaneously sense a free common party line and begin simultaneous transmission. This requires a special bus arbitration scheme to cause all but one of the interfering transceivers to drop out of operation while permitting one selected transceiver to continue its data transmission. Also, in such a system transmission from ~ ~7~i~63 4 51,930 the transceiver to the central controller is very limited and consists meraly of an indication of a manually operable or condition responsive switch or analog sensors such as a thermistor or other analog sensing device. In the load distribution control system shown in the above referenced prior art patents, the arbitration technique is dependent on the impedance levels of the active and inactive ~tates of the data line. If the data line becomes s-tuck in a low impedance state, due to the failure of one of the connected transceiver decoders, fur~her communication over the network line is prevented until the mal-~unctioning transceiver is physically disconnected from the data line.
In the communication and control syskem described in the above identified Miller et al patents a message transmitted over the network includes a preamble portion of a minimum of four bits. These preamble bits comprise 50~ square waves which are utilized by the transceiver decoders to permit a phase lock loop circuit in each transceiver to lock onto the received preamble bits. The use of a minimum of four bits to provide phase loop lockon reduces the overall throughput of such a system. Also, in order to capture the preamble bits, it is necessary to provide the phase lock loop circuit initially with a relatively wide bandwidth of about 5KH7 and then narrow down the bandwidth after the phase lock loo~ circuit has locked onto the preamble bits. Such an arrangement requires addltional circuitry to accomplish the necessary change in bandwidth. Also, the relatively wide bandwidth necessary to capture the preamble bits also lets in more noise so that the security and reliability of the system is reduced in noisy environments.
SU~MARY OF THE INVENTION
According to one aspect of the invention, there is provided, in a communication and control ~.~'7~
5 51,930 network, the combination of a digital integrated circuit device coupled to a common net,work line and adapted to store plu~al bit messages transmitted over said line, said device having first and second control output terminals. A variable interval timer external to said device has a reset terminal connected to said first control terminal and a clock inhibit terminal connected to said second control terminal. A controlled element external to said device is connected to said second control terminal. The variable timer has a decode output which is low when said timer is reset and is connected to an input terminal of said device. Means in said device is responsive to the reception of a message which includes a shed load instruction for pulling both said first and second control output terminals low, thereby to cause said controlled device to shed load and said timer to start counting, said decode output of said timer going high a predetermined time interval after starting said counting. Means in said device is responsive to a high on said input terminal for pu1ling said second control output terminal high, thereby causing said controlled element to restore load at the end of said predetermined interval.
In preferred embodiments of the communication network a small low cost digital integrated circuit is employed which can be readily adapted by merely grounding different input terminals of the IC to perform all of the different functions necessary to the compon0nt parts of the completer communications network. Thus, in one pin configuration of the digital IC it can function as an addressable load controller, responding to shed or restore load commands from the central controller and replying back to the central controller with status information regarding the state of the controlled load.
This mode of functioning of the digital IC is referred to as a stand alone slave mode of operation. In the stand i 3 6 51,930 alone slave mode the digital IC is arranged to be directly associated with each ccntrol device i.e. circuit breaker, motor controller, lighting control, etc. and may, if desired, communicate with the master controller over the same wires which are used to supply power to the controlled device. This substantially reduces the amount of wiring required to connect a number of controlled devices to the common communication network.
The central controller may also issue block shed and block res~ore commands to a group of stand alone slaves to which command they will all simultaneously respond.
Also, the central controller may issue a "scram" command to shed load which causes all stand alone slaves (which may number as high as 4,095) to simultaneously shed their respective loads.
In another pin configuration of the digital IC
it can function as an addressable microcomputer interface. In this so called expanded slave mode of operation the digital IC provides an interface between the communication network line and a remote microcomputer which may, for example, wish to transmit data over the communications network to the central controller. In the expanded slave mode of the digital IC the micro-computer interface is disabled until the central controller enables it by sending an enable interface command addressed ~o the expanded slave. After the microcomputer interface is enabled the central controller and the remote microcomputer can communicate back and forth through the expanded slave digital IC~
The digital IC may also be pin configured to function as a nonaddressable microcomputer interface, such functioning being referred to as the expanded master mode of functioning of the digital IC. In the expanded master mode the interface with an associated microcomputer is always enabled and any network transmissions that tha digital IC receives may be read by ~ 27~
7 51,~30 the interfaced microcomputer. Also, the interfaced microcomputer may transmit data onto the network at any time throuyh the expanded master type of digital IC.
Accordingly, when the digital IC is operated in this mode the interfaced microcomputer may comprise the central controller of the communications network.
The digital IC which may be adapted to perform all of the above described functions, may also be arranged so that it can be used with different types of data lines. Thus, in one embodiment the digital IC i5 adapted to transmit messages to and receive messages from a network line consisting of the conventional AC power line of a factory, office building or home. Because of the significant ~hase disturbances associated with such power lines, data is transmitted over the network by means of on-off keying of a high frequency carrier.
Preferably this high ~requency carrier has a frequency of 11~.2 KHz and the digital IC is arranged to transmit data at the rate of 300 bits per second (300 baud~ over conventional power lines. The choice of a 115.2 kHz carrier is based on empirical results of spectrum analyses of typical power lines and the 300 baud bi~ rate is based upon desired system performance and acceptable error rates.
2~ The digital IC may comprise a crystal controlled oscillator operating at a frequency many times higher than the carrier frequency. The carrier signal is derived from this crystal oscillator. The crystal oscillator is also used as a source of timing signals within each digital IC to establish predetermined baud rates for the transmission of data over the network.
Accordingly, the frequency of the carrier signal employed to transmit messages over the network can be readily changed to avoid an undesired interfering fre~uency by 3~ simply changing the crystals in the crystal oscillator associated with each digital IC. Such a change in 8 51,930 carrier -frequency will also change the baud rates at which the communica-tion system operates, as described in more detail hereinafter.
The fre~uency of the crystal oscillator in each digital IC preferably is highly stabilized so that the carrier frequencies developed by the digital IC's at the central controller and remote stations are very close to the same frequency although a received carrier signal may drift in phase relative to the timing signals produced in the digital IC which is receiving a message.
As a resu~t, it is not necessary to transmit a number of preamble bits and provide a phase lock loop circuit which locks onto the received message dur1ng the preamble bits, as in the above described Miller et al patents. In embodiments of the present invention the individual digital IC's may operate asynchronously but at substantially the same frequency so that any drift in phase does not interfere with detection of the received carrier signal, even at relatively low baud rates and noisy environments.
In order to provide further noise immunity when using noisy power lines as the common network data line, the digital IC may be arranged to compute a 5 bit BCH error code and transmit it with each message transmitted to the network. Also, each message received from the network by the digital IC includes a five bit ~CH error code section and the digital IC computes a BCH
error code based on the other digits of the received message and compares it with the BCH error code portion of the received message.
In order to provide still further noise immunity when operating over conventional power lines, the digital IC may include a digital demodulator which has high noise rejection so that it can detect on-off carrier modulation on power lines which have a relatively high noise level. Empirical results show that the l.Z~S~-3 9 51,930 digital demodu~ator portion of the digital IC can receive messages with a bit error rate of less than 1 in 100,000 for power line s-ignal to noise ratios of approximately 5 db at a 300 Hz bandwidth. Also, ~uch digital demodulator can receive error free 33 bit messages at a 90% success rate in a power line noise environment of only 4 db signal to noise ratio.
When -it is desired to use a dedicated twisted pair line as the common data line for the communication network, which usually has a lower noise level than power lines, th~ digital IC may be adapted t~ transmit data to and from such twisted pair line at 4 times the data rate mentioned above i.e. at 1200 bits per second (1200 baud).
Such adaptation of the digital IC can be readily accomplished by simply grounding a different one of the input terminals of the digital IC.
~he digital IC may also be pin configured to accomplish all of the above described functions in a high speed communication network in which tha common data line is a fiber optic cable. In this mode of operation of the digital IC the digital demodulator portion is bypassed and the ramaining logic is adapted to receive and transmit data messages at the extremely highrate of 38,400 bits per second (38.4 k baud). In such a fiber optic cable communication system the data is transmitted as base band data without modulation on a higher frequency carrier.
The digital IC preferably is arranged to transmit and receive messages over the common network in a specific message format or protocol which permits the establishment of the above described microcompuker inkarface so that different microcomputers can communicate over the common network while providing maximum security against noise and the improper addressing of individual digital IC's by the master controller. Specifically, the message format consists of ~ 27S~
9 A 5 1 , 9 3 0 a series of 33 bits, the first two bits of which comprise start bits having a lcgic value of "I". The start bits area followed by a control bit which has a logic value "1" when -the succeeding 24 message bits signify the address of the digital IC and instructions to be performed by the digital IC. When the control bit has a logic value oF "O" the next 24 message bits contain data intended for the interfaced microcomputer when the digital IC is operated in an expanded mode. The next five message bits contain a BCH error checking code and the last message bit is a stop bit which always has a logic value of "O".
When a 33 bit message is received by the digital IC the first 27 bits thereof are supplied to a BCH code computer portion of the digital IC which computes a 5 bit BCH error code based on the first 27 7 -bits of the received message. The computed BCH code i5 then compared with the succeeding 5 bit BCH error checking code of the received mes~age, on a ~it by bit basis, to ensure that the received message has S been received and decoded properly.
In a similar manner when data is to be transmitted onto ~he network either as a reply mes-sage in the stand alone slave mode, or from the in-terfaced microcomputer to the network through the di-gital IC, the BCH computer portion of the digital ICcomputes a 5 bit error chec~ing code based on the data to be transmitted and adds the computed BCH
error checlcing code at the end of the stored data bits as the 33 bit message is being formatted and transmitted out of the digital IC to the communica-tion networ~. 8y thus employing BCH error code com-puter logic in the digital IC for both receivea and transmitted messages, the assurance of transmitting valid, error free 33 bit messaqes in ~oth directions on the networ~ is greatly increased.
The digital IC which accomplishes all of these functions is of small size, is readily manufac-tured at low cost on a mass production basis and con-sumes very little power. Accordingly, the overall cost of the communication and control system is much less than that of the a~ove described prior art patents while providing all of the addititional fea-tures discu~sed above. Of particular importance is the feature of providing a low cost interface to microprocessors associated with controlled devices, such as circuit breakers, motor starters, protective relays and remote load controllers, so that tnese microprocessors, which are busy with other tasks, can be selectively interruptea and two-way communication establi~hed between the central controller and the selected microprocessor at a remote station.

:~ Z`7~ 3 ~ The invention, both as to its organization and method o~ operation, together with further objects and advantages thereof, will best be under-stood by reference to the following specificationta~en in connection with the accompanying drawings in which:
Fig. 1 is an overall block diagram of the described communication syqtem;
Fig. 2 is a diagram of the message ~it for-mat employed in the system of Fig. 1 for a message transmitted ~rom the central cont~oller to a remotç
station;
Fig. 3 shows the coding of the instruction ~its in the message of Fig. Z;
Fig. 4 is a message ~it format for a reply message transmitted ~ac~ to the central controller from a remote station;
Fig. S is a message ~it format of a message transmitted from the central controller to an inter-faced microcomputer;
Fig. 6 is a diagram of tne pin configura-tion of the digital IC used in the disclosed cystem;
Fig. 7 is a block diagram illustrating the use of the digital IC with a power line at 300 baud rate;
Fig. R is a block diagram showing the use of the digital IC with a twisted pair line at 1200 ~aud rate;
Fig. 9 is a ~lock diagram of the digital IC
used with a fi~er optic ca~le transmission sys~em a~
38.4k baud rate;
Fig. 10 is a ~loc~ diagram showing the use of the digital IC in a stand alone slave mode;
Fig. 11 is a ~lock diagram howing a modi-fication of the system of Fig. 10 in which varia~le time out is provided;

12 51,930 Fig. 12 is a block diagram of the digital IC
in tne stand alon~ slave mode and illustrates the operation in response to a shed load instruction;
Fig. 13 is a block diagram of the digital IC
5in the stand alone slave mode in transmitting a reply message back to the central controller;
Fig. 1~ is a block diagram of the digital IC
in an expanded slave mode in responding to an enable interface instruction;
10Fig. 15 is a flow chart for the microcomputer associated with the digital IC in the disclosed system;
Fig. 16 is a detailed schematic of the coupling network employed with the ~igital IC in the disclosed communications system;
15Fig~ 16a is a diagrammatic illustration of the coupling transformer used in the coupling nekwork of Fig.
16;
Fig. 17 is a detailed schematic diagram of an alternativ~ coupling network embodiment;
2CFigs~ 18-33, when arranged in the manner shown in Fig. 34, (which is located after Figure 6), comprise a detailed schematic diagram of the digital IC used in the disclosed communications system;
Fig. 35 is a block diagram of the digital 25demodulator used in the digital IC of the disclosed communication system;
Fig. 36 is a timing diagram of the operation of the carrier confirmation portion of the digital demodulator of Fig. 35;
30Fig. 37 is a series of timing waveforms and strobe signals employed in the start bit detection and timing logic of the digital IC of the disclosed communication system;
Fig. 38 is a graph showing the bit error rate 35of the digital demodulator of Fig. 35 IC in different noise environments;

Fig. 39 is a schematic dia9ram of a local override circuit employing the digital IC of the dis-closed communications system;
Fig. 40 is a series of timing diagrams il-lustrating ~he operation of the digital ~C in thetand alone slave mode;
Fig. 41 i~ a chart of the respon~e times at different ~aud rates of the signals shown in Fig. 40;
Fig. 42 is a series of timing diagram~ of the digital IC in an interface mode with the micro-computer; and Fig. 43 is a chart showing the operatlon times of the waveforms in Fig. 42 at dif~tent ba~d rates.
_~ ~ ~ ~
Referring now to FIG. 1, there is shown a general ~loc~ diagram of the communication network wherein a central controller indicated generally at 76 can transmit messages to and receive mes~ages from a large num~er of remote stations over a conventional power line indicated generally at 78. The ~asic ~uilding ~loc~ of the communicatron network is a small, low cost digital IC, indicated gener~lly at 80, which is arranged to ~e connected to the power line 7~ so that it can receive messages from the central controller at 76 and transmit messages to the central controller over this line.
The digital IC 80 is extremely versatile and can ~e readily adapted to different modes of operation by simply establishing different connec-tions to two of the external pins of this device.
More particularly, as shown at remote stations ~1 and #2 in FIG. 1, the digital IC 80 may ~e pin configured to operate in a stand alone slave mode in which it is arranged to control an associa~ed relay, motor con-troller or other remote control device, indicated generally at 82, by sending a control output signal ~If.i7~ 3 (COUT), to the controlle~ device 82. In the stand alone slave mode, the digital IC 80 can also respond to an appropriate command from the central controller 76 by transmitting a message back to the controller S 76 over the power line 78 in which the status of 2 terminal~ associa~ed with the controlled device 82, identified as STAT 1 and STAT 2, are given. Each of the digital IC's 80 is provided wi~h a 12 bit address field so that as many a~ 4,0~5 of the devices 80 may be individually associated with different relays, motor controllers, load management terminals, or other controlled devices at location~ remote from the central controller 7~ and can respond to shed load or restore load commands transmitted over the power line 7~ ~y appropriately changing the potential on its COUT line to the controlled device 82.
The digital IC ~0 is also arranged so that it can be pin configured to operate in an expanded slave mode as shown ,at station ~3 in FIG. 1. In the expanded slave mode the digital IC is arranged to respond to a particular command from the central con-troller 76 ~y esta~lishing an interface with an as-sociated microcomputer indicated generally at 84.
More particularly, the expanded slave device 80 re-sponds to an enable interface instruction in a mes-sage received from the central controller 76 by pro-ducing an interrupt signal on t~e INT line to the microcomputer 84 and permitting the microcomputer 84 to read serial data ou~ of a buffer shift resister in the digital IC 80 over the bi-directional DATA line in response to ~erial clock pulses transmitted over the SCR line from the microcomputer 84 to the digital IC 80. The digital IC 80 is also capable of resp~nd-ing to a signal on the read write line (RW) from the microccmputer 84 ~y loading serial data into the ~uf-fer shift regis~er in the device 80 from the DATA
line in coordination with serial cloc~ pulses suppli-~.Z`',s~6~3 ed over the SC~ line from the microcomputer 84. Tnedigital IC 80 is then arranged to respond to a change in potential on the RW line by th~ microcomputer ~4 by incorporating the data supplied to it from tne microcomputer 84 in a 33 ~it message which is format-ted to include all of the protocol of a standard mes-sage transmitted ~y the central controller 76. This 33 bit message in the correct forma~ is then trans-mitted by the IC ~0 over the power line 78 to the central controller. As a result, the expanded slave device 80 enables bi-directional communication and transfer of data between the central controller 76 and the microcomputer 84 over the power lin~ 78 in response to a specific ena~le interface in~truction initially transmitted to the expanded slave device ~0 from the central controller 76. nce the interface has ~een established between the devices 80 and 84 this interface remains in effect until the digital IC
receives a message transmitted from the central con-troller 76 which includes a disable interface in-struction or the expanded slave device 80 receives a message from the central controller- which includes a command addressed to a different remote station. In either ca~e the interface between the network and the microcomputer 84 is then disabled until another mes-sage ls transmitted from the central controller to the expanded slave device 80 which includes an ena~le inter~ace instruction. ~he expanded slave device 80 al~o sends a busy signal over the ~USYN line to the microco~pu~er 84 whenever the device 80 is receiving a message from the network 7~ or transmitting a mes-sage to the network 78. The BUSYN signal tells the microcomputer 84 that a message is ~eing placed on the network 78 ~y the central controller 76 even though control of the ~uffer shift regiRter in the ex-panded slave device 80 has ~een shif~ed to the ~icro-computer 84.

The digital IC 50 may also be pin configur-ed to operate in an expanded master mode as indicated at station #4 in FIG. l. In the expanded master mode the device 80 is permanently interfaced with a micro~
computer 86 so that the microcomputer 86 can operate as an alternate controller and can send shed and re-store load messages to any of the stand alone slaves 80 of the communication networ~. The microcomputer 86 can also establish communication over the power line 78 with the micrcomputer 84 through the expanded slave IC device 80 at station t3. To ectabl~sh such two way communication, the microcomputer 86 merely transmits data to the expanded ma ter device 80 over the ~idirectional DATA line which data includes the address of the expanded slave device 80 at sta,tion ~3 and an enable interface instruction. The expanded master 80 includes this data in a 33 ~it message for-matted in accordance with the protocol required ~y the communication network and transmits this message over the power line 7~ to the expanded slave 80 at station #3. The expanded -clave 80 at this station re-spond~ to the ena~le interface inst~uction by esta~-lishing the above descri~ed interface wi~h the micro-computer 84 after which the bidirectional exchange of data between the micrcomputers ~4 and 86 is made pos-sible in the manner de~cribed in detail heretofore.
A digital IC 80 which is pin configured to operate in the expanded master mode may al~o be u ed a~ an interface ~etween a central control computer 88, wh~ch may comprise any microcomputer or main frame computer, which is employed to control the re-mote stations connected to the central controller 76 over the power line 78. Since each of the digital IC's 80 puts out a BUSYN signal to the associated computer when it is either receiving or tran~mitting a message the present communication and control system permits the use of multaple masters on the same ~1 2 ~
17 5193~
network. Thus, considerin5 the central controller 76 and the alternate controller at station ~4 which is operating in the expanded master mode, each of these masters will ~now when the ol:her is transmitting a message by monitoring his BUSYN line.
It will thus ~e seen that the digital IC 80 is an extremely versatile device which can be used as either an addressa~le load controller with status reply capability in the stand alone slave mode or can be used as either an addressable or non addressa~le interface ~etween the network and a microcomputer so as to ena~le the bidirectional transmission of data between any two microcomputer control units such as the central controller 76 and the remote stations ~ 3 and ~4.
Networ~ Co~munica ions _ ormat All communications on the network 78 are asynchronous in nature. The 33 bit message which the digital IC ~0 is arranged to either transmit to the network 7~ or receive from the networks 7~ is speci-fically designed to provide maximum security and pro-tection against high noise levels ~n the power line 78 while at the same time making po~sible the estab-lishment of interfaces between different microcompu-ters as described heretofore in connection with FIG.}. The 33 bit message has the format shown in FIG. 2 wherein the 33 bits B0-B32 are shown in the manner in which they are stored in the shift register in the digital IC 80 i.e. reading from right to left with the lea~t significant ~it on the extreme right. Each 33 3it message begins with 2 start ~its B0 and Bl and ends with 1 stop bit B32. The start bits are defined as logic ones "1" and the stop bit is defined as a logic ~0~. In the disclosed communication and con-trol 3ystem a logic 1 is defined a~ carrier pre~entand a logic 0 is defined a-q the absence of c~rrier for any of the modulated carrier ~aud rates.

~a~J5~ 3 The next ~it B2 in the 33 ~it message is a control bit which defines the meaning of the succeed-ing message bits B3 through B26, which are referred to as buffer bits. A logic ~1~ control ~it means that the buffer bits contain an a~dress and an in-struction ~or the digital IC 80 when it is configur-ed to operate in either a stand alone slave moae or an expanded slave mode. A logic n 0~ con~rol bit B2 means that the buffer bits B3 through B26 contain data intended for an interfaced microcomputer such as the microcomputer 84 in FIG. 1.
The next four bit3 B3-B6 after the control bit 2 are instructisn bits if and only if the pre-ceeding control ~it is a ~1~. The instruction bits lS 83 - B6 can ~e decoded to give a number of different instructions to the digital IC 80 when operated in a slave mode, either a stand alone slave mode or an expanded slave mode. The relationship ~e~ween the in~truction ~its 33 - B6 and the corresponding in-struction is shown in FIG. 3. Referring to thisfigure, when instructions bits 83, B4 and BS are all ~9R a ~hed load instruction is indi~-ated in which the digital IC 80 res~ts its COUT pin, i.e. goes to logic zero in the conventional sense so that the controlled device 82 is turned off. An X in bit position B6 means that the shed load instruction will ~e executed independently of the value of the B6 ~it. However, if B6 i~ a ~1~ the digital IC 80 will reply bac~ to the central con~roller 76 with in~ormation regarding the ~tatus of the lines STAT 1 and STAT 2 which it receives from the controlled device 82. The format of the reply message is shown in FIG. 4, as will ~e described in more detail hereinafter.
When instruceion bits B3-B5 are 100 a re-store load instruction is decoded in response towhich the digital IC 80 ~etc its COUT pin and pro-vide~ a logic one on the COUT lin~ to the controlled 19 ~ 3 51930 device 82. Here again, a ~1" in the B6 bit instructs the deYice 80 to reply back with status information ~ram the controlled device 82 to indicate that the command has been carried out.
When the instruction bits B3-B5 are 110 an enable interface instruction is decoded which in-structs an expanded slave device, such as the device 80 at station t3, to e~tablish an interface with an associated microco~puter such as the microcomputer 84. The digital IC 80 responds to the enable inter-~ace instructior. by producing an interrup~ ~ignal on ~he INT line after it has received a message from the central controller 76 which contain~ the enablc in-terface instruction. Further operation of the digi-tal IC ~0 in esta~lishing this inter~ace will ~e de-scri~ed in more detail hereinaf~er. In a i~ilar manner, the instruction 010 instructs the digital IC
80 to disable the interface to the microcomputer 84 so that this microcomputer cannot thereafter communi-cate over the networ~ 78 until the digital IC 80 again receives an enable interface instruction from the central controller 76. In the disable interface instruction 3 ~1~ in the B6 bit position indicates that the exp~nded lave device ~0 should transmit a reply back to the central controller 76 which will confirm to the central controller that the micro interface has been disa~led ~y ~he remote device 80.
The B6 bit for an enable interface instruction is always ze~o so that the digital IC ~0 will not trans-mit b~ck to the central controller data intended for the microcomputer 84.
If bits 83-B5 are 001 a block shed instruc-tion is decoded. The block shed instruction i~ in-tended for s~and alone slaves and when it iS received the stand alone ~lave ignores the four LSB's of its addre~s and executes a shed load operation.
Accordingly, the block shed in truction permit the central controller to simultaneously control 16 stand alone slaves with a single transmitted message so that these slaves simultaneously d.s~31e their asso-ciated controlled devices. In a similar manner if the instruction bi~s B3-a5 are 101 a bloçk restore in~truction is decoded which is simultaneously inter-preted ~y 16 stand alone slaves to restore a load to their respective controlled devices. It will ~e noted that in the bloc~ shed and bloc~ restore in-structions the B6 bit must be ~0~ in order for the instruction to be executed. This i~ to prevent all 16 of the instructed stand alone qlaves to attempt to reply at the same time.
If the B3-BS bits are 011 a ~cr~m instruc-tion is decoded. In response to the scram instruc-tion all stand alsne slaves connected to the networ~
7~ disregard their entire addres and execute a shed load operation. Accordingly, by transmitting a scram instruction, the central controller 76 can simultane-ously control all 4,0~6 stand alone slaves to shed their loads in the event of an emergency. It will be noted that the scram instruction can only be executed when the B6 bit is a "on.
If the B3-BS bits are all "1" a status in-struction is decoded in which the addressed stand alone slave ta~es no action with respect to its con-trolled device but merely transmits bac~ to the cen-tral controller 76 status information regarding the associated controlled device 82.
Returning to the message bit format shown in FIG. 2, when the received message is intended for a stand alone slave, i.e. the control ~it is ~
~its B10-B21 constitute address bits of the address assigned to the stand alone slave. In thi~ mode bits B7-B9 ~nd bi~s B22-a26 are not used. However, when an enable interface instruction i~ given in the ex panded mode, bits B7-B9 and B22-~26 may contain data 5~

intended for the associated microcomputer 84 as will be des¢ri~ed in more detail hereinafter.
Bits ~27-B31 of the received message con-tain a five bit 8CH error checking code. This BCH
code is developed from the first 27 ~its of the 33 bit received message as these first 27 ~its are stored in its serial shift register. The stand alone slave device 80 then compares its computed BC~ error code with the error code contained in bits B27-B31 of the received message. If any ~its of the BC~ error code developed within the device 80 do not agree with the corresponding bits in the error code contained in ~its ~27-B31 of the received message an error in transmission is indicated and the device RO ignores the message.
FIG. 4 shows the message format of the 33 bit message which is transmitted by the stand alone slave 80 back to the central controller in response to a reply request in the received meQsage i.e. a ~1~
in the B6 bit position. ~he stand alone slave reply message has the identical format of the received mes-sage shown in FIG. 2 except that ~its B2s and B26 correspond to the status indication on STAT 1 and STAT 2 line~ received from the control device 82.
However, since a2s and B26 were not used in the re-ceived me~Qage whereas they are employed to transmit information in the reply message, the old BCH error checking code of the received ~essage cannot be used in transmitting a reply ~ack ~o ~he central control-ler. The ~tand alone slave device 80 recomputes afive bit 8CH error code based on the first 27 bits of the reply message shown in FIG. 4 as these bits are being shipped out to the network 78. At the end of the 27tb bit of the reply message the new HCH error code, which has been computed in the device 80 ~ased on the condition of the statu~ bits B25 and B26, is then added on to the transmitted message ~fter which 22 ~ Z~ 51930 a stop bit of 0 is added to complete the reply mes-sage back to the central controller.
Fig. 5 shows the forrnat of a second message transmitted to a digital IC 80 operating in an exp-anded mode, it being assuming that the first messageincluded an enable interface as discussed previously.
In the format of Fig. 5 the control ~it is ~o" WhiCh informs all of the devices 80 on the power line 78 that the message does not contain address and in-struction. The next 24 ~its after the control bitcomprise data to be read out of the ~uffer shift reg-ister in the device ~0 ~y the associated microcompu-ter 84.

In the illustrated em~odiment the digital IC 80 is housed in a 28 pin dual in line pac~age.
Preferrably i~ is constructed from a five micron silicon gate CMOS gate array. A detailed signal and pin assignment of the device 80 is shown in FIG. 6~
It should ~e noted that some pins have a dual func-tion. For example, a pin may have one function in the stand alone slave configuration and another func-tion in an expanded mode configuration. The ~ollow-ing is a ~rief description of the terminology assign-ed to each of the pins of the device ~0 in FIG. 6.
TX-the transmit output of the device ~0.
Transmits a 33 bit message through a sui~a~le coupl-~ng network to the common data line 78.
~ X the receive input of the device RO. All 33 bit network transmissions enter the device through this pin.
RE~TN-the active low power on reset input.
Resets the internal registers in the device 80.
Vdd-the power supply input of +5 volts.
Vss-the ground reference.
XTALl and XTAL2 - the crystal inputs. A
3.6864 mHz + 0.015~ crystal oscillator is required.

23~ 51930 Baud O and 8aud l-the baud rate select in-plJtg-A0-A8 - the least significant address Dit pins.
As/cLK - dual function pin. In all but the test modes this pin is the A9 address input pin. In the test mode this pin is the cloc~ strobe output of the digital demodulator in the device 80~
A10~D~MOD - a dual function pin. In all but the test mode this pin is the Al~ address input pin.
In the test mode this pin is the demodulated output ~DEMOD) of the digital demodulator in the device ~0 All/CD - a dual function pin. In all pu~
the test mode this pin is the All address input pin.
In the tes~ mode this pin is the receive word detect output (CD) of the digital demodulator in the device B0.
BUSYN/COUT - a dual function output pin.
In ~he expanded slave or expanded master modes this pin is the BUSYN output of the micro interface. In the stand alone slave mode this pin is the switch control output (COUT).
INT/TOUT - a dual function output pin. In the expanded master or expanded slave modes this pin is the interrupt output (INT) of the micro interface.
In the stand alone slave mode ~his pin is a timer control pin (TOUT).
SC~/STATl - a dual function input pin. In the expanded master and expanded slave modes this pin is the erial cloc~ (SCK) of the micro interface. I,n the qtand alone slave mode it is one of ~he two statu~ input~ (STATl).
~W/ST~T2 - a dual function input pin. In the expanded master or expanded slave mode this pin is the read-write control line of the micro inter-face (RW). In the stand alone slave i~ is one of the two status inputs ~STAT2).

L'~ 3 DATA/TIMR - a dual function pin. In the expand~d maYter or expanded slave modes this pin is the bidirectional data pin (DATA) of the micro inter-face. In the stand alone 31ave mode thiS pin is a timer contLol line (TIMR).
All input pins of the device ao are pulled up to the +5 five volt supply Vdd by internal 10~
pull-up resistors. Preferably these internal pull-~p resistors are provided by suita~ly biased transistors within the device 80, a~ will ~e readily under tood by those skilled in the art.
As discussed generally heretofore the digi-tal IC ~0 is capable o~ opera~ion in several differ-ent operating modes by simply changing external con-nections to the device. The pin~ which control themodes o~ operation of the device 80 are pins 1 and 27, identified as mode 1 and mode 2. The relaeion-ship between these pins and the selected de i as follows-0 0 expanded slave 0 1 stand alone ~lave 1 0 expanded master 1 1 test When only the MODE 1 pin is grounded the MODE 0 pin a~sume~ a logic ~1" due to it~ internal pull up re~i~tor and the digital IC 80 is operated in the stand alone slave mode. In this pin configura-tion the digital IC 80 acts a~ a ~witch control with status feed ~ack. The device 80 containc a 12 ~it addres~, a switch control output (COUT~ and two status inputs (STAT1) and (STAT2). The addressed device 80 may ~e commanded to set or reset the 8Wi tch control pin COUT, reply with status information from it~ two Rtatus pins, or both. The device 80 ~ay be addre ~ed in blocks of 16 for one way swltch control commands.

When ~oth the MODE 1 and MODE 0 pins are grounded the device 8 i5 operated in an expanded slave mode. In this pin configura~ion the device 80 contains a 1~ bit address and a microcomputer inter-face. This interface allows the central controller 76 and a microcomputer 84 tied to the device 80 to communicate with each other. The interface is dis-a~led until the central controller 76 enablec it by sending an enable interface command to the addressed digital IC 80. The central controller and microcom-puter communicate by loading a serial shift register in the digital device 80. The central controller does this ~y sending a 33 bit message to the device ~0. This causes the microcomputer interface ~o in-terrupt the microcomputer 84 allowing it to read the shift register. The microCompu~er 84 communicates with the central controller 76 by loading the same shift register and commanding the device 80 to trans-mit it onto the network.
When only the mode 0 pin is grounded the MODE 1 pin aQSUmeS a logic "1" due to i~s internal pull up re~istor and the device 80 is operated in the expanded ma~ter mode. In this mode the device 80 operateQ exactly like the expanded slave mode except that the micro interface is always ena~led. Any net-work transmis~ion~ that the digital device 80 receives produce interrupt3 to the attached microcomputer 84, en~bling it to read the serial shift register of the device 800 Also the microcomputer may place data in the shi~t regi~ter and force the device B0 to trans-mit onto the network at ary time.
When both the MODE 1 and MODE 0 pins are ungrounded they assume ~logic~ value~ of "1~ and the device 80 is configured in a test mode in which some of the external signals in ~he digital demodulator portion of the device 80 are ~rought out to pins for test purposes, as will be described in more detail~

1. ~ f Sg~ 3 As discussed generally heretofore the digi-~al IC 80 is adapted to transmit messages to and re-ceive messages frcm different types of communication ne~work lines such as a conventional power line, a dedicated twisted pair, or over fi~er optic cables. When the digital IC 80 is to work s~ith a conventional AC
power line 78, this device is pin configured so that it receives and transmits data at a baud rate of 300 ~its per second. Thus, for power line applications the ~inary ~its consist of a carrier of 115.2 kHz which is modulated by on-off keying at a 300 baud ~it rate. This bit rate is chosen to minimlze bit error rates in the relatively noisy environment of the power line 7~. Thus, for power line applications the digital IC #0 is configured as shown in FIG. 7 wherein the ~aud 0 and baud 1 pins of ~he device 80 are ungrounded and assume logic values of ~1" due to their internal pull up resistors. The RX and TX pin~
of the device 80 are coupled through a coupling net-work and amplifier limiter 90 to the power line~ 78,this coupling network providing the desired i~olation ~etween transmit and received mess~ges so that two way communication ~etween the digital IC 80 and the power line 78 is permitted, as will ~e descri~ed in more detail hereinafter. When the device 80 is pin configured as shown in FIG. 7 it is internally ad-justed so that it will receive modulated carrier mes-s~ges at a 300 baud rate. It i~ also internally con-trolled 30 that it will trdnsmit messages at this sa~e 300 ~aud rate.
In Fig. 8 the digital IC ~0 is illustrat-ed in connection with a communication networ~ in which the common data line is a dedicat~d twisted pair 92. Under these conditlons the baud 0 pin of the device 80 is groundea whereas the baud 1 pin a~-~umes a logic value of ~1~ du~ ~o it~ internal pull up resistor. When the device 80 i pin configured as shown in FIG~ 8 it is arranged to transmit and re-ceive ~odulated carrier me~ages at a 1200 baud rate.
The 1200 baud bit rate is possible due to the less nol~y environment on the twisted pair 92. In the configuration of Fig. 8 the coupling network 90 is al~o required to couple the device 80 to the ~wisted pair 92.
For high speed data communication the digi-tal IC 80 is also pin configura~le to transmit and receive unmodulated da~a at the rela~ively high ~it rate of 38.4R ~audO When so configured the device 80 is particularly suita~le for operation in a communi-cations system which employ~ the fi~er optic ca~les 94 (Fig. 9) as the communication network medium.
More particularly, when the de~ice 80 is to function with the fi~er op~ic cable~ 94 the baud 1 terminal is grounded and the ~aud 0 terminal aqsumes a logic value of ~1~ due to it~ internal pull up resiseor, as shown in FIG. 9. In the f i~er optic cable ~ystem o~
FIG. 9 the coupling network 90 is not employed.
Instead, the receive pin RX of the device 80 directly connected to the output of a fiber optic receiver 96 and the tran~mit pin TX is connected ~o a fiber optic tran~mitter 9~. A digi~al IC ~0 in the central controller 76 is also in~erconnected with the f$ber optic cables 94 ~y a suita~le transmitter receiver p~ir 100. The fi~er optic receiver 96 and tr~n~mitteE 98 may comprise any suita~le arrangement in which the RX terminal is connec~ed to a suitable photodetector and amplifier arrangement and the TX
terminal i5 connected to a ~uitable modulate~ light source, such as a photodiode. For example, the Hewlett Pac~ard H~BR-1501/2502 transmitter receiver pair ~y ~e employed to connect the digital IC 80 to the fi~er optic cables 94. Such a transmitter-receiver pair operateQ at TTL compati~le logic levels ~ ~-" !7 ~ 3 which are satisfactory ~or direct application to the ~X and.~X terminals of the device 80.
Stand Alone Slave Mode In Fig. 10 a typical configuration is shown for the device 80 when opera~:ed in the ctand alone slave mode. Referring to thi~ figure, plu~ 5 volts DC iq applied to the Vdd terminal and the Vss terminal is grounded. A crystal 102 operating at 3.6864 -0.015~
mHz is connected to the OSCl ænd OSC2 pins of the de-vice 80. Each side of the crystal is connected toground thro ~h a capacitor 104 and 106 and a resistor 108 is connected across the crystal 102. Prefer-rably, the capacitors 104, 106 have a value of 33 picofarads and the resistor 108 ha-~ a value of 10 megohms. The baud ra~e at which the device 80 i5 to operate can be selected by mean of the baud rate switches 110. In the em~odimen~ o~ FIG. 10 these switches are open which means that the device 80 i~
operating at a baud rate of 300 ~aud which is suit-able for power line network communication. The MODE1 terminal i 9 grounded and the MODE 0 terminal $s not connected so that the device 80 i~ operating in a stand alone 31ave mode. A 0.1 microfarad capacitor 112 is connected to the RESETN pin of the device 80~
When power is applied to the Vdd terminal of the device 80 the capacitor 112 cannot charge immediately and hence provide~ ~ re~et signal of "O" which is employed to re~et v~rious logic circuits in the digital IC 80.
A130, a power on reset signal forces the COUT output of th~ device 80 to a logic "1~. As a result, the controlled device, such as the relay coil 114, is en-ergiz~ through the indicated transictor 116 whenever power is applied to the digital IC 80. The condition of the relay 114 ic indicated by the status infor~a-tion switches 118 which are opened or closed inaccordance with the signal supplied to the controlled relay 114. Two status information witches are pro-~.~ f~ 3 29 519~0 vided for the two lines STATl and STAT2 even thoughonly a single device is controlled over the COUT con-trol line. Accordingly, one stat~s line can be connected to the COUT line to confirm tha~ the COUT
5 signal was actually developed and the other statusline can be connected to auxiliary contacts on the relay 114 to confirm that the load in~truction has actually been executed.
A series of twelve addreYs switches 120 may ~e selectively connected to the address pins A0-All -~o as to prov;de A digital input signal to the address co~parison circuit in the digitz-l IC 80. Any address pin which is ungrounded by the switche~ 120 assumes a logic "1~ value inside the device ~0 L5 through the us~ of internal pull up resistor on each address pin. In this connection it wilL be understood that the device 80, and the external components as-sociated wi~h it, including the coupling networ~ 90 may all be assembled on a small PC board or card which can be associated directly with the controlled device such as the relay 114. Furthermore, the digi-tal IC 80 and it8 associated componehts can ~e of ex-tremely small size so that it can be actually located in the bousing of the device which it controls.
Thus, if tne device ~0 is employed to control a relay for a ho~ water heater or freezer in a residence, it may be aQ-soclated directly with such relay and re-ceive mes~ages for controlling the relay over the hou~e wiring of the re~idence. If tne controlled de-vice does not include a five volt source for poweringthe digital IC 80, the coupling network 90 may pro-vide such power directly from the power line 78, as will ~e de~cribed in ~ore detail hereinafterO
In some situations it is desiraDle to pro-35 vide a variably timea shed load feature for particu-lar stand alone slave ~pplication. For exa~ple, if the digital IC ~0 is employed to control a hot w~ter he~ter or freezer, it may be controlled from a cen-tr~l controller so that the freezer or hot water heater may be turned off (shecl load instruction~ dur-ing pe~ load periods in accordance with predetermin-ed time schedules. Under these condition~ it would ~e desirable to provide a varia~ly timed facility for restoring power to the controlled freezer or hot water heater in the event that the central controller did not transmit a message instructin~ the digital IC
~0 to restore load. Such a varia~ly timed shed load feature may be provided in a simple manner by employing the arrangement shown in FIG. 11 wherein a varia~le timer 130 is associated with the digital IC
80. The varia~le timer 130 may comprise a commercial type MC14536 device which is manufactured by Motorola Inc and others.
In the arrangement of FIG. 11 the COUT line of the digital IC 80 is connected to the reset pin of the variable timer 130 and is also connected to an internal NOR gate U625 of the device 80 whose output is inverted. The TOUT outpu~ line of the device 80 i5 connected to the cloc~ inhibit-pin of the timer 130 and the decode output pin of this timer is connected ~o ~he TIMR input pin of the device 80.
The device 80 in Fig. 11 is also conencted in the stand alone slave mode of FIG. 10 in which mode the TOUT and TIMR lines are enabled~ In the em~odiment of FIG. 11 the controlled relay 114 is connected to the TOUT line rather than ~o the COUT pin of the device 80. The timer 130 has an in~ernal cloc~ whose frequency can be determined by the external resistors 132 and 134, and the capacitor 136 as will ~e readily understood ~y those skilled in the art. In addition, the timer 130 has a num~er of timer input terminals A, B, C and D to which shed time elect cwitches 13~
may ~e selectively connected to egta~li3h a desired varia~le timer interval.

3~ 7~ 51330 When power is applied to the di9ital IC 80 in FIG. 11 a power on reset produces a logic ~1" (re-store load state) on the COUT pin. This signal is applied to the reset terminal of the timer 130 forc-ing the timer to reset and its decode output pin low.This decode output pin is connected to the ~IMR line of ~he device 80 which is internally connected to the NO~ gate U625. Since the T~UT pin is the loglcal OR
Or COUT and the decode output of the timer 130, upon power on reset TOUT is a logic 1 and the relay 114 i9 in a restore load state. When the COUT line i re-set, in response to a shed load lnstruction to the device 80, the ~imer 130 is allowed to start counting and the TOUT pin is a lo~ic ~0~ causing the load t~
5 De shed. When the timer 130 counts up to a num~er determined by the shed time select switches 138 its decode out pin goes high forcing TOUT high i.e. back to the restore load state and inhi~iting the timer clock. Accordingly, if the central controller for-gets to restore load to the relay 114 by mean of anetwork message transmitted to the device 60, ~he timer 130 will restore load autom&tically after a predetermined time interval.
In FIG. 12 the main component parts of the digital IC 80 are shown in block diagram form when the device 80 $s operated in the stand alone slave mode and i~ ~rranged to receive a message transmitted over tbe network 78 which includes a shed load in-struction. The incoming message is amplified and li~ited in the coupling networ~ 90, as will ~e de-scri~ed in more detail hereinafter, and is applied to the RX terminal (pin 63 of the digi~al IC 80. It will be understood that the incoming meYsage is a 33 ~it message signal having the format descri~ed in de-tail heretofore in connec~ion with Fig. 2. This in-coming message is demodulated in a digit~l demodu-lator 150 whicn also include the start ~it detection ~ ~7546'3 and framing logic necessary to esta~lish the bit in-tervals of the incoming asynchronous message trans-mitted to the devie 80 over the ne~work 7~. The digi~l demodulator and its accompanying framing logic will be d2scri~ed in more detail hereinafter in connection with a description of the detailed schema-tic diagram of the device 80 shown in FIGS. 18 to 33.
The output of the demodulator 150 is sup-plied to a serial shift register indicated generally at 152. The serial ~hift register 152 comprises a series of 26 serially connected stage~ the first 24 of which are identified as a buffer and store bit~ B3-B26 ~Fig. 2) of the received me3~age. The next ~tage is the control bit regi~ter U528 which s~ores the control bit B2 IFig. 2) of ~ne received message. The final stage of the serial shift register 152 is a start ~its reqister US41 which -~tores bits ~0 and Bl (Fig. 2) of the received mes~age. In this connection it will be recalled that the two start bits B0 and Bi of each message both have a logic value of ~1~ and hence constitute a carrier signal which extend~ over two ~it interval-~ so that both bits may be registered in the single register U641. In this connection it should be noted that all logic components having U
numbers re~er to the corresponding logic element shown in detail in the overall schematic of the digi-tal IC ~0 ~hown in FIGS. 18 to 33. The serial shift register 152 is loaded from the left by the demodu-lated output of the demodulator 150 which is applied to the data input of the register 152, this data ~e-ing cloc~ed into the register 150 by means of ~uffer shift clock pulses (BSHFCLK) developed by the demodu-lator 150 at the end of each ~it in~erval in a manner described in more detail hereinafter. ~ccordingly, the incoming message is shifted through the regi~ter 152 until the start bits regi~ter U641 i3 set ~y the two ~tart ~its B0 and 81 to a logic ~1~ v~lue. In ~his connection it will De noted that the ~its of the incoming mes~age are stored in the Duffer portion of the regi~ter 1~2 in the manner shown in FIG. 2 with the lea~t significant bit B3 ~tored in the regicter next to the control ~it register U528.
As the demodulated data bit~ are thus being loaded into serial shift register 152 they are also simultaneou~ly supplied to a ~CH error code computer indicated generally at 154. More particularly, the DEMOD output of the demodulator 150 is supplied through a switch 156 to the input of the ~C~ error code computer 154 and the output of this computer is connected to a recirculating input through the.switch 158. The BCH error code computer 154 compri~es a series of 5 serially connected shift regi ter stages and when the ~witches 156 and 158 are in the position shown in FIG. 12 the computer 154 computes a S ~it error code based on the first 27 message ~itg which it receives from the de~odulator 150 as these ~its are being stored in the serial shift register 152.
The clock pulses on the BSHFCLK line, which are used to advance ~he serial shift regi~ter 152, are also supplied to a message ~it counter 160. The counter 160 is a ~ix stage counter which develops an output on itR end-of-word (EOW~ output line when it counts up to 32. In this connection it will ~e noted that by using two logic "1~ start ~it which are counted a~ one, the total message length may be counted by digital logic while providing increased nol~e immunity ~y virtue of the longer start bit in-terv~l.
The ~essage ~it counter 160 also se~s a latcb at the end of the 26th me~age ~it and devel-opes an enabling signal on it~ G~26 (greater than 26) output line. The GT26 signal control the switches 156 and 158 ~o that after the 26th mescage ~t the DEMOD output of the demodulator 150 is 3upplied to a ~4 51930 BCH comparator 162 to which comparator the output of the BC~ error code computer 154 is also supplied. At the same ~ime the switch 158 is opened by the GT 26 signal 50 that ~he BCH error code computed in the com-puter 154 re~ains fixed at a value corresponding tothe first 26 bits of the received message. Since the demodulator 150 continues to supply BSHFCLK pulses to the computer 154, the BCH error code developed in the computer 154 is then shifted out and compared ~it by bit with the next 5 ~its of the received me sage i.e.
B27-B31 (Fig. 2) which constitute the BCH error code portion of the incoming received message and are QUp-plied to the other input of the BCH comparator 162.
If all five bits of the BCH error code computed in the computer 154 correspond with the five ~itC of the BCH error code contained in ~its ~27-B31 of the re-ceived message the comparator 162 develops an output on i~s BCHOK output line.
The digital IC 80 also includes an address decoder indicated generally at 164 which comp~ise~ a series of 12 exclu~ive OR gates and associated logic.
It will ~e recalled from the previo~s description of FIG. 2 that bits Bll-B22 of a received me~sage con-tain an address corresponding to the particular stand alone slave with which the central controller wi~hes to communicate. Also, it will ~e recalled from the preceed$nq de~cription of FIG. 10 that ~he address select switches 120 are connected to the address pins A0-All of the digital IC 80 in accordance with the addre~ as~igned to each particular stand alone slave. The addre~s decoder 164 compares the setting of the address select switche~ 120 with the address stored in ~its Bll-B22 of the ~uffer portion o~ the serial shift register 152. If the two addresses co-incide the decoder 164 developes an output on its ad-dres3 OK (ADDOK) output line.

The digital IC 80 also includes an instruc-tion decoder 166 which decodes the outputs of the buffer stages corresponding to bita B3-B6 (Fig. 2) which contain the instruction which the addressed stand alone slave is to execute~ Assuming that ~its ~3-B5 all have a logic value of ~0~, a shed load in-struction is decoded, as hown in FIG. 3, and the in-struction decoder 166 produces an output on its shed load line (SHEDN).
10As discussed generally heretofore, the con-trol ~it B2 of a message intended for a stand alone slave always has a logic value of ~1~ indicating th~t bits B3-B26 of this message include address ~its and instruction bits which are to be compared and decoded 15in the decoders 164, 166 of the digital IC 80. When the control ~it register U528 in the serial shift register 152 is set an ena~ling qignal is supplied over the CONTROL output line of the register U528 to the execute logic circuits 170. The BC~OK output 20line of the comparator 162, the EOW output line of the message bit counter 160 and the ADDOK output line of the address decoder 164 are also supplied to the execute logic circuits 170. Accordingly, when the message ~it counter 160 indicates tnat the end of the 25message has been reached, the comparator 162 indi-cates that all bits of ~he received BCH error code agreed with the error code computed by the computer 154, the address decoder 164 indicate that the mes--~age i~ intended for this particular stand alone 30slave, ~nd the control bit register U52~ is set, the logic circuits 170 develo~ an output signal on the EXECUTE line which is anded with the S~EDN output of the instruc~ion decoder in the NAND gate U649 the output of which is employed to reset a shed load 35latch U651 and U6~2 so that the COUT output pin of the ditigal IC 80 goes to a logic value of ~0~ and power is removed fro~ the controlled dev$ce 32 (Fig.

t~

1). The stand alone slave thus executes the instruc-tion cPntained in the reçeived message to shed the load of the controlled device 82. As discussed gen-erally heretofore when power is applied to the digi-tal IC 80 the shed load latch is initially reset ~ythe signal appearing on the PONN line so that the COUT line goes high when +5v. power is applied to the device 80.
When the message ~it B6 (Fig. 3) has a logic value of "1" the stand alone slave not only executes a shed load instruction in the manner de-scribed in connection with FIG. 12 ~ut al o is ar-ranged to transmit a reply message bac~ to the cen-tral controller as shown in FI5. 4. In this reply, message ~its B25 and 326 contain the two status in-puts STATl and STAT2 which appear on pins 26 and 25, respectively, of the digital IC ~0. Considered very generally, this reply message is developed ~y ~hift-ing out the data which has ~een stored in the serial shift register 15~ and employing this data to on-off ~ey a 115.2 kHz carrier which i~ then supplied to the TX output pin of the device 80. However, in accord-ance with an important. aspec~ of the disclosed system, the status signals appearing on the STAT 1 and STAT 2 inpu~ pins of the device 80, which repre-sent the condition o the controlled relay, are not e~ployed to set the ~tatus bits ~25 and B26 of the reply me~sage until after 15 ~itq have been read out of ~he serial shift register 152. This gives consid-30 era~le time for the relay contacts to settle down ~e-fore their status is added to the reply message being transmitted ~ack to the central controller.
In Fig. 13 the operation of the ~tand alone slave in for~atting and transmitting such a reply message ~ac~ to the central controller i5 shown in block diagram form. Referrlng to this figure, it is assumed that a message ha~ ~een received from the 37 l.Z75~6~ 51930 central controller and has been stored in the serial ~hift register 152 in the manner descri~ed in detail heretofore in connection wi~h Fig. 12. It is further a~um~d ehat the control ~it B2 of the received mes-~age has a logic value of ~1" and that the messagebit B6 s~ored in the ~uffer portion of the register 152 has a logic value ~1~ which ins~ructs the stand alone slave to transmit a reply me~sage ~ac~ to the central controller. When the B6 ~it has a ~1~ value the instruction decoder 166 produces an output signal on its COM 3 output line. Also, at the end of the received message ~he execute logic circuits 170 lsee Fig. 12) produce an EXECUTE 3ignal when the cond~-tions descri~ed in detail here~oore in connection lS with Fig. 12 occur. When an EXECUTE signal i5 pro-duced a reply latch 172 provides an output which is employed to set a status latch 174. The ~tatus latch 174 provides a control signal to the status control logic 176. However, the condition of the status pins STAT 1 and STAT 2 is not employed to set corre~pond-ing ~tages of the buffer portion of the serial shift regi3ter 152 until after 15 bits have ~een shifted out of the register 152. At that time the message ~it counter 160 provide~ an output on its ~15~ output line which is employed in the status control logic 176 to ~et tbe corresponding stages of the ~uffer portion of the register 152, these stages correspond-ing to the location of bits B25 and B26 in the reply ~e8~age after 15 bit~ have ~een shifted out of the register 152.
Con5idering now the manner in which the re-ceived me ~age which has been stored in the serial shift register 1S2 is shif~ed out to form a reply me~sage, it will ~e recalled that a mes~age which is tran~mitted over the network 78 requires two start bits having a logic value of ~lW. ~owever, when the message was received it was initially d~te~ted by de-, ~1~
38 ~ `3 51930 tecting the pre~ence o~ carrier on the network 78 for a dura~ion of 2 bits and, hence, the two start bits of the received me age are stored as a single bit in the start ~its register U641. When a reply message 5 is to be transmitted over the networ~ it is necessary to provide a modulated carrier of two bits duration in re~ponse to the single start ~it stored in the re-gister U641. To accompli~h this, a transmit strobe signal (TXSTB) is derived from the reply latch 172 and is coupled through the NOR gate U601 to reset a one bit delay flip-flop 178 which haq its D input connected to the five volt ~upply Vdd. As a re~ult the QN output of the f lip-f lop 178 i~ inverte~ to provide a transmit strobe A (TXS~BA) signal which sets a transmit control latch 180. Wben the latch 180 is set it provides a transmit on (TXONN) signal which is e~ployed to relea~e the framing counters in the demodulator 150 so that they begin to provide BSHFCLK pulses at one bit intervals.
For the first 26 ~its of the reply message the output of the start bit regi~ter U641 is con-nec~ed throuigh a switch 190 to a t-ransmit flip-flop 182 which is al30 get by the TXST~A signal and is held in a ~et condition so that it does not respond to the first BSHFCLR pulse which is applied to its clock input. At the same time the QN output of the one bit del~y flip-flop 178 is com~ined with the first BS~FC~ pulse in the NAND gate U668 so as to provide a signal which set~ a transmit enable latch 184. When the transmit enable lat~h 184 is set it provide~ an enabling signal to the modulator 186 to which is al~o ~upplied a carrier signal having a fre-quency of 115.2 ~Hz. fro~ the digital demodulator 150. When ~he transmit fllp-flop 1~2 is initially set by the TXSTBA line going low, it provides a 1 on its Q output to the modulator 186. Accordingly, when the tran~mit ena~le latch 184 provide~ an enabling ~ ~!' tSi L~ ~ ~

signal to the modulator 186 a carrier output is sup-plied to the TX output pin of the device 80 anZ is supplied to the networ~ 78. During this initial tran~mission of carrier during the first sta;t bit interval the data in the serial shift register 152 is not shifted out because BS~FCLR pul~es to the cloc~
input of the register 152 are ~locked by the NAND
gate U697. The NAND gate U69~ has as it~ second inpu~
a signal from the GT26N output line of the mes3age ~it counter 160 which i~ high until 26 bits have been shifted out of the register 152. Howeve~, a third input to the NAND gate U697 is the TXSTBA line which went low when the 1 bit delay flip-flop 178 wa~ re-set. Accordingly, the first BSHFCLR pulse is not ap-plied to the cloc~ input of the register lS2 although this pulse does set the transmit ENABLE latch 18~ and enable carrier outpu~ to be supplied to the TX output pin for the first bit interval. However, a ehort in-terval after the first BS~FCLR pulse, a delayed shift cloc~ pulse ~DSHFHCLK), which is also developed in the framing logic of the demodulator 150, is supplied to the clock input of the 1 ~it delay flip-flop 178 so that the TXST8A line goe~ high shortly after the first BSHFCLK pul~e occur When the TXSTBA line goes high the ~SHFCLK pulses pass through the NAND
gate U697 and shift data out of the register 152 and the ~erially connected tranqmit flip-flop 1~2 to the modulator 186 so that the ~ingle start bit ~tored in the register U641 and the remaining bit~ a2-~26 of the receiv~d mes age control the modulation of the carrier supplied to the TX output pin. in this connection it will be noted that the BSHFCLK pulses are also upplied to the cloc~ input o the transmit flip-flop 182 so as to permit the ~erial shift of da~a to the TX output pin. However', as discu~sed above, when the TXS~3A line i8 low it hold~ tbe flip-5 ~ ~

~lop 182 5et so that it does not respond to the firstBSHFCLK pulse.
Considering now the man..er in which the STAT l and STAT 2 status signals fro~ the controlled device are added to the reply mess2ge, it will ~e re-called that the buffer stages are not set in accord-ance with the signals on the STAT 1 and STAT 2 pins until 15 ~its have been snifted out of the register 152 in order to allow time for the relay contacts of the contro~led device to assume a final posi~ion. It will also be recalled that the B25 and B26 bits of the received message are reserved for status ~it~ to ~e added in a reply ~essage so that the last active bit in the received message is B24. When the B24 bit lS has been shifted 15 times it appears in the B9 stage of the bu~fer portion of the serial ~hift regis~er 152. Ac~ordingly, the conditions of the statu pins STAT 1 and STAT 2 can be set into the ~10 and Bll stages of the buffer after the l5th shift of data in the register 152. To this end, the message bit counter 160 develops a signal on the ~15~ output line which is ent to the s~atus control-logic 176. This logic was enabled when the statu~ latch 174 was set in response to a COM 3 signal indica~ing that the reply was requested. Accordingly, tne status control logic then responds to the ~15~ signal by setting the ~10 and Bll tages in accordance with the poten-tials on the STAT 1 and STAT 2 pins. In this connec-tion it will be underctood that the B10 and Bll st~ge~ of the buffer initially contained part of the address in the received message. However, after the received message has been shifted 15 bits during transmission of the reply message the stages 810 and Bll are free to be set in accordance with the status pin~ STAT 1 and STAT 2 and this status will be trans-mitted out a~ a part of the reply message in the B25 and B26 bit positions.

s~ 3 As discussed generally heretofore, it is nece~ry to compute a new BC~ error code for the re-ply ~essage which is transmitted back to the central controller due to the fact that the ~tatus bits ~25 and B26 may now contain status information whese they were not u~ed in the received message. As ~oon as the transmit control latch 1~0 is set the TXONN ~ig-nal controls a switch U758 so that the DEMOD output of the demodulator 50 i~ removed from the data input of the BCH error code computer 154 and the ouptut of the serial shift register 152 i~ connected to this input through the switch 156. However, during the initial 1 ~it delay of the flip flop 178 BS~FCLR
pulses are bloc~ed from the cloc~ input of the com-para~or 154 ~y the NAND gate U672 the other input of which is the TXST8A line which is low for the first start bi~. After the first BSHFCLK pulse the TXST~A
line goes high and succeeding BSHFCLK pulses are 5up-plied to the computer 154. The two start bits of the transmitted message are thus treated as one ~it ~y the computer 154 in the same manner as the two ~tart ~iteivs of a received messa~e are dec~ded as one bit for the register U641.
As the data stored in the register 152 is shifted out to the transmit flip-flop 182, this data is also supplied to the data input of the ~CH error code computer 154 through the switch 156. Also, the recirculating input of the computer 154 is connected through the switch 158, as descri~ed heretofore in connection with Fig. 12. Accordingly, as ~he 2Ç
~it stored in ~he register 152 are shifted out of this register, the computer 154 i~ computing a new 8C~ error code which will eake into account the status informa~ion in bits B25 and ~26 thereof.
After the 26th bit has been ~hifted out of the regi~-ter 152 a new five bit error code is then pres~nt in the co~puter 154. When the mes3age bit coun~er 160 produces an output on the GT26 line the switches 156 and 158 are opened while at the same time the output of the computer 154 is connected through the switch 190 to the input of the transmit flip-flop 182 in S place of the output from the serial shift regi ter 152. Since BSHCLK pulse-~ are ~till applied to ~oth the BC~ error code computer 154 and the transmit flip-flop 182 the five ~it error code developed in the computer 154 i5 succeR9ively clocKed through the transmit flip-flop 182 to the modulator 186 so as to con~titute the BCH error code portion of the trans-mitted reply message.
When the switch 156 i~ opened after the 26th ~it, a zero is applied to the data input of the BCH error code computer 154 30 that as the five ~it error code is shifted out of the BCH error code computer 154 the shift register stages are ~ac~
filled with zeroes. After the five error code bits have been shi f ted out, the next BSHFCLK pul~e clocks a zero out of the computer 154 and tbrough the transmit flip-flop 182 to the modulator 186 to con3titute the 832 stop bit which has a logic va~ue of ~0~. Thi~
completes transmi~sion of the 33 bit message onto the network 7~.
When the message counter 160 has counted to 32 bit~ its EOW line iq ~upplied to a transmit off flip-flop 192 ~o that a transmit off signal tTXOFFN) i~ developed by the flip-flop 192. The TXOFFN signal i~ e~ployed to reRet the status latch 174 and tne tran~mit control latch 180. When the transmit control latch 180 i9 reset it~ TXONN output line re-sets the transmit ENABLE latch 184. The reply latch lt2 is reset by timing pulse~ STBAD developed in the framing loqic of the de~odulator 150, a3 wili ~e dewribed in more detail hereinafter.

~ Z7~

~ . In Fig. 14 there is shown a block diagram of the digital IC 80 when operated in an espanded slave ~ode and showing the operation of the device 80 in respon~e to an ena~le interface inetruction. It will be recalled ~rom the pr~viouQ description tha~
in the expanded mode, pin 24 (~ATA~ of the digital IC
is used as a ~i directional cerial data line by means of which dat~ stored in the serial shift register 152 may ~e read out by an associated microcomputer, such as the microcomputer 84 (Fig. 1), or dat~ fro~ the microcomputer c~n be loaded into the register 152.
Also, pin 26 of the device 80 acts as a serial clock (SCR) input ~y means of which serlal cloc~ pulse~
lS supplied from the associatea microcomputer 84 may be connested to the cloc~ input of the regi~ter 152 to control the shift of data from this regi eer onto the daSa output pin 24 or the cloc~ing of data placed on the DATA pin into the regi~ter 152. Also, pin 25 of the device 80 (RW) is connected as a read-write control line which may be controlled by the as~ociated ~icrocomputer 84 to co~trol either the reading of data fro~ the register 152 or the writing of data into thl~ register from the microcomputer ~4.
The RW line i~ al~o used ~y the microcomputer 84 to force the digital IC 80 to transmit the data present in it~ regl~t~r 152 onto the networ~ 78 in the 33 ~it meQ~age fo~at of thi~ network. Pin 9 of ~he device functions as an interrupt line (INT) to the microcomputer 84 in the expanded moae and ~upplies an interrupt Rignal in res~nse to an ena~le interface instruction which informs the micro 84 that a me~Rage intended for it ha~ been stored in ~he register 152.
An interrupt signal is al-~o produced on the ~NT line afer the device 80 has transmitted data loaded ineo the regi~ter 152 onto the network. Pin 8 of the de-vice 80 supplies a bu~y ~ignal (~USYN) to the a~30-6~

clated micro 84 whenever a message is being received by the .device 80 or a mes3a~e is bein~ transmitted ~y thi~ device onto the network 78.
It will ~e under~tood that the block dia-S gram of Fig. 14 include3 only the circuit components and logic gates which are involved in setting up an interface with the a~sociated micro 84 and the bi-directional transmis-~ion of data and control signals between the micro 84 and the device 80. In Fig. 14 10 it is as~umed that a message has been rec~ived from the central controller which contain~ an in.truction to establish an interface witb the a-Rsociated micro-computer 84 in bit~ B3-85 of the mes~age and that the instruction decoder 166 has decoded thi instruction 15 ~y producing an output on it~ enable interf~ce output line (EINTN). Also, when the device 80 i8 operating in an expanded slave mode pins 1 and 27 are grounded and the expanded mode line EMN is high.
In the expanded mode of operation of the 20 digital device B0, a serial ~tatu~ register 200 i~
employed which include~ ~ BCH error register U642 and an RX/TX regi~ter U644. The BCH error register U642 i~ serially connected to the output sf the control Dit register U528 in the serial snift register 152 25 over ~he CONTROL line. The RX/TX register U644 is serially conn~ted to ~he output of the 8CH error re-gi~ter U642 and the output of the eegister 644 i~
supplied through an inverting tri-state output circuit U762 to the ~i-directional serial DATA pin 24.
~ 30 It will ~e recalled from the previous dis-cussion of Fiq. 12 that wben the di~ital device 80 receive~ a message from the central controller which includes an instruction it will not execute that in-struction unless tbe BCH comparatcr 162 (Flg. 12) 35 provides a 8CHOK output which indic~tes th~t e~ch ~it of the ~CH error code in the rec~ived me~age com-pares equally witb the BCH error code computed ln the a 3 5193~
device 80. The BCH error register U642 is set or re-set in.accordance with the ~CHOR output from the BCH
comp~rator 162. The BCH error register U642 is reset when the initial message i~ received req~esting that the interface be established ~ecau3e this instruction would not have been executed i~ it was not error-free. However, once this interface has ~een set up the central controller may send additional messages to the microcomputer 84. During receipt of each of these additlona1 ~essages the BCH comparator 162 com-pares the BCH error code contained in the received meSQa9e with the BCH error code computed ~y the CQm-puter lS4 and will indicate an error ~y holding the BCHOR line low if all ~it~ of the ~wo codes are not ehe same. If the BCHOK line is low the BCH error register U642 is set. However, ince the interfa¢e has already ~een set up, this second m~s-qage stored in the register 152, which contains an error, may b~
read out by the microcamputer 84 by quccessively clocking the SCK line and reading the DATA line. The presence of a logic ~1~ in the ~CH error regiQter po~ition (second bit~ of the data-read out by the microcomputer 84 indic~es to the microoomputer 84 that an error ln transmiscion has occurred and that the microcomputer may wish to as~ ~he central con-~roller to repeae the me~sage.
The RX/TX register V644 is employed to in-dicate to the microcomputer 84 whether or not the s~rial ~hift regi~ter 152 $R loaded or empty when i~c recelve~ an interrupt signal on the INT line. I the regl3t~r 152 has been loaded with a received me.~sage f rom the c~ntral controller the RX/TX register U644 is ~et. When the micro readQ ou~ ~he dat~ tored in tbe regi~ter 152, the serial shift register 152 and 35 the serial s~atus regi3ter 200 are back f illed with zesoe~ SQ that when the readout i~ complet~ly a zero will ~e stored in '~he RX/TX regl~ter U6~4. When data 46~ 51930 i~ then loaded into the registe!r 152 and transmitte~
out to the network this zero remains stored in the RX/TX register since it is not used during trans~is-sion. Accordingly, when an in~errupt is produced on the INT line after the message is transmitted, the RX/TX regi.~ter U644 remain at zero so as to the in-dicate to the microcomputer that the message has been sent and the register l.52 is empty.
When the digital IC 80 is arranged to re-ceive a me~sage ~rom the network 78, the switches U759 and U76Q have the position shown in Fig. 14 CO
that the output of the demodulator 150 is supplied to the data input of the serial shift regi3ter 152 and the received message may ~e cloc~ed into regiqter 152 ~y means of the BSHFCLK pulses applied to the cloc~
input of the register 152. However, a~ soon a~ an ena~le interface command has been executed in the IC
80 control of the register 152 switches to the a~so-ciated microcomputer ~4 by actuating the switches U759 and U760 to the opposite position. Thi~ insures that data which has been stored in the register 152 during the received message is preserved for tran~-mission to the microcomputer 84. It is important ~o switch control of the regi~ter 152 to the microcompu-ter 8~ immediately because the micro might not be a~le to re3pond immediately to its interrupt on the INT line and an incoming me~sage might write over the data in the register 152 ~efore the micro read~ out thi 9 data.
- 30 While the interface is esta~li hed to the microcomputer 84 no more network transmis~ion~ will be de~odulated and placed in the serial shift r~gis-ter 152 until the microcomputer 84 relinqui ~hes con-trol. However, after control is shif~ed to the microcomputer 84, the digital demodulator 150 conti-nues to demodulate networ~ message~ and wh~n a net work message is received produces a signal on its ~ ~ r~ r ~

RXWDETN output line. This signal is transmitted through the NAND gate U671. The outpu~ of the NAND
gzlte U671 i inverted ~o pcoduce a BUSYN ou~put ~ign~l to the a~ociated microcompu~er 84. The microcomputer ~ iq thu3 informed that the device 80 ha~ detected activity on the networ~ 78. Thi~
actlvity might ~e that the central controller is at-tempting ~o communicate with the microcomputer through the enabled slave mode digital IC 80. When the digital IC ~0 is tran~mitting a messaqe bac~ to the central controller over the networ~ as de cribed hereto~ore, the TXONN signal developed ~y the trans-mit control latch 180 (Fig~ 13) alRo ~upplie~ an ac-tive low signal to the BUSYN output pin to inform the lS microcomputer 84 tnat a message i being transmitted by the digital IC 80 to the central controller o~er the network 7~.
Considering now in more detail the manner in which control of the regi~ter 152 is shifted from the network to the microcomputer 84, when the ena~le interface command is decoded by the instruc~ion de-coder 166 it produces an ~IN~N out~ut which setc an enable interface laech 202. The low ou~pu~ of the latch 202 i~ com~ined with the master slave signal EMN, which is high in the expanded slave mode, in ehe NAND gate U749 ~o as to provide an active high ~ignal on the ENABLE output of the NAND gate U749 which is one inpu~ of the NAND gate U686. A~suming that the other input of the NAND gate U686 is al~o a 1, the ou~put of U6~6 goe3 low which i~ inver~ed in the in-v~rter U736 ~o tha~ the UPSLN line goes high. The UPSLN line is employed to control the switches U75~
and U760 and when it i9 high switche~ the data input of the regi~ter 152 ~o the ~i-directional serial DATA
line through inverter U547 and the cloc~ input of the regis~er 152 to the Rerial cloG~ SC~ line. M~re par-ticularly, the UPSLN line direc~ly control~ switch 4~ 51930 U760 80 that the SCK serial clocK line is connected to the clock input of the regiciter 152. Also, the UP5LN line through ~he inverter U547 i~ one input of the NOR ga~e g597 the other input of which 1~ the RW
line which is normally high due to an internal pull up resiRtor in the digital IC ~00 Accordingly, a high on the UPSL~ line cau~es the switch U75Y to dis-connect the demod output of the modulator 150 from the data input of the register 152 only when the RW
line i~ low.
When the microcomputer 84 wishes to re~d the data stored in the serial ~hift regi~ter 152 it does so by providing serial cloc~ pulses to th~ SCK
line. At the same time the RW line is high which control~ the tri-state output circuit U762 to connect the output of the RX/TX regis~er U644 to the ~i-directional DATA line. Accordingly the DATA pin will contain the state of ~he RX/TX register U644 which can ~e rea~ by the microcomputer 8~. When the UPSLN
20 liAe i5 high and the RW line iR also high the ou~put of the NAND gate U683 is low which is inverted by the inverter U~OO and applied a~ one input to the NAND
gate U801 the other input o~ which is the SCK line.
The ou~put of the NAND gate U~Ol is inverted by inverter U~02 and i5 supplied to tne clock inputs of th~ BCH error register U642 and the RX/TX register U644 30 t~t the~e regic~ters are also shifted ~y pul~e~ produced by the micro on the SCK line.
Accordingly, when the micro clocks the SCR pin once all of the data in the serial shift register 152 and the ~erially connected ~erial ~atus register 200 i5 shifted to the riyht o ehat the state of the 3CH er-ror regiseer U642 will be pre3ent at the DATA pin.
The ~icro can then read the DAT~ pin again to ohthin the 3tate of ~his register. Thi~ cloc~ing and read-ing process con~inues until the micro ha~ read out of the DATA pin all of the data in th@ serial ~hift g~.~`f ~

register 152 and the serial status regi~ter 200. In this connection it will be noted that the start bit regi~ter U641 is ~ypassed during the readout opera-tion since its information is used only in transmit-ting a message to the network. As indicated a~ove,the stage~ o the ~erial statu~ register 200 are in-cluded in the chain of data which may be shifted out to the microcomputer 84 because these stages contain information which i5 useful ~o the microcomputer Y4.
It will alsv be noted that when an enable interface signal is produced and the UPSLN lin~ is high, the RW line is also high which produces a zero on the output of U683. The fact that both the UPS~N
line and the RW line are high forces switch U75Y to the DEMOD position. However, since the ou~pu~ of U683 is low the data input to the serial shift regis-ter 152 will always be logic zeros. Accordingly, as data is ~eing read out of the register U644 on ~he DATA pin 24 the register 152 and the serial status register 200 are ~eing back filled with zeros. After the entire contents of these registers has ~een read out the RX/TX register U644 contains a zero so that a zero appears on the DATA pin thereafter. A~ indicat-ed a~ove, when the micro receives a second interrupt on the INT line after a mecsage has been transmi~ted the micro can read the DATA pin and verify that the ~essage ha~ been sen~.
Con3idering now the manner in which the ~tage~ of the serial statUC register 200 are set at th~ end of either a received message or a transmitted message to provide t~e a~ove-descr i~ed information ~o the micro, ae the end of a received message the mes-sage bit counter 160 (Fîg. 12) produces an EOW ~iq-nal wh~ch is cGm~ined with DSHFCLR pulse~ from the digital demodulator 150 in tbe NAND gate U647 ~Fig.
14) to provide a statu3 strobe ~ignal STSTB. The STST~ signal is com~ined with the ~CHOR signal in th~

,~ 1 r ~

~AND ~ate U660 so that the BCH error register U642 is re~et if the received message was error free. The BC~OR signal is inverted in the inverter U555 whose output is also combined with the STSTB signal in the NAND gate U65Y so that the BCH error register U642 is .et if the~e wa~ an error in the received message.
The STSTB signal is also com~ined with the E~lABLE
signal in the NAND gate U658 the output of which is supplied to one input of a NAMD gate U756 the other input of which is the TXONN line which is high when the device 80 is not transmitting a me~saqe. Accor-dingly, the RX~TX register U644 is et at the end of a received message.
When the device ~0 transmits a message to the network the TXONN line is low so that at the end of such transmission the STSTB signal does no~ set the regi ter U644. However, as indicated a~ove, ~he register U644 is ~ac~ filled with a zero a~ data i~
read out of the register 152. Accordingly, the micro can read the DATA pin, to which the output of the register U644 is connected, and determine that a mes-sage has been transmitted to tne network and the register 152 is empty. The register U644 is reset when power i5 applied to the device ~0 and when the in~erface is disabled and the ENABL~ signal disap-pears. This re-~et i accomplished through the NAND
ga~e ~657 ~nd inverter U725 which together act as an AND gat~ the inputs of which are the PONN signal and the ENABLE signal.
After the micro has read ou~ the data stor~
ed in the serial shift register 152 and the s~atus register 200 it can either switch control ~ac~ to the ne~work immediately or it can load d3ta into the ser-ial shift register 152 and then command tne device 80 to ~ransmit the data loaded into ~he regi~ter 152 on-to the network in a 33 ~it meq~age having the aDove descri~ed networ~ format. The micro s~itche~ control ~ J~ ~6 ~

back to the network immediately ~y pulling tne RW
line low and then high. However, the low to high transition on the ~W line, which is performea ~y the microcomputer 84, occurs asynchronously with respect to the framing logic in the demodulator 150. Accor-dingly, it is important to make sure that the device 80 sees the zero to one tran~ition which the micro-computer 84 place~ on ~he RW line. This transition is detected ~y a digital one shot 204 the two stages o~ which are clocked by the STBDD timing pulses from the framing logic in the demodulator 150. The stages of the one shot 204 are reset by the RW line so that during the period when the RW line i~ held lQw by the microcomputer 84 the o~tput line RWR o~ the one shot 204 remains high. However, upon the zero to one transition on the RW line the digital one qhot 204 is permitted to respond to the ST8DD pulses and produces an outpu~ pulse on the RWR line of guaranteed minimum pulse width due to the ~act that it is derived from the framing logic timing pulses in the demodulator 150. The RWR line thus goes low for a fixed interval of time in response to a zero to ~ne transition on the RW line.
When the RWR line goes low it sets a buffer control la~ch 206 the output of which is connected to one input of the NAND gate U753. The other input o~
~he NAND gate ic the RW line. Accordingly, after the zero to 1 tr~n~ition on the RW line this line is high so that the outpu~ of the NAND gate U753 is no longer a ~1~ and the UPSLN line goes from high to low. When this occurs the switche~ U759 and U760 are returned to the positions shown in Fig. 14 so that ~uffer con-trol 15 shifted from the micro bac~ ~o the networ~.
Considering now the situation where the micro wi~hes to load data into the serial shift regi3ter 152 and then command the device 80 to tran~-mit the data in the regist@r 152 onto the networK, 52 519 3n the micro f irst pulls the RW line low which ena~les da~a to ~e transmitted from the DATA line through the NO~ gate U5~B, the switch U~5~ e NAND gate U~82 and the inverter U730 to the dal:a input of the regis-ter 152. As stated previou~ly, a high on the UPSLNline has also caused the switch U763 to connect the SCR serial cloc~ line to the clock input of the register 152. Daea from the micro may now be placed on the DATA pin and clocked into the register 182 by 10 the positive clock edges of the SC~ clock pulses.
The data entering the register 152 begins with a control bit having a logic value of "o~ followed ~y the least significant bit of the buffer bit-~ B3~B26 and ends up with the most significant bit of the buffer bits. It should ~e noted that the micro does no~ load the start bitC register U641.
After this data has been loaded into the register 152 the micro pulls the R~ pin high. The low to high transition on the RW line after SCK
pulses have ~een supplied to the SC~ line is intes-preted ~y the device 80 as meaning ~hat data has been loaded into the regi ~er 152 and- that this data should now be transmitted out to the network in the 33 ~it message form~t of the network. To detect this 25 condi tion a transmit detect flip flop 20~ is employ-ed. More particularly, the cloc~ pulses developed on the SCK lin~ ~y the microcomputer 84, identified as BS~RCK pulces, are applied to the cloc~ input of the flip-~lop 208 and the RW line is connected to its D
input. When the RW line is low and a BSERCR pulse i~
tran3mitted over the SCX line from the microcomputer 84 the Q output line of the flip-flop 208 goes low.
This output is supplied to the NOR gate U628 ~he o~her input of which is the RWR line. Accordingly, when the RW line is again pulled high at ~he end of transmission of data into the register 152 th~ R~R
line goes low so that the outpu~ of the NOR gate U628 53 ~ 1930 goes high. This output is supplied as one input to a N(:~R gate U601 and passes through this gate so as to provide a low on the TXSTB line. A low on the TXSTB
line eau e3 the device 80 to transmit the data stored 5 in the serial shift reqister 1i2 onto the networ~ in the 33 bit network format in exactly the same manner as descri~ed in detail heretofore in connec~ion with Fig. 13 wherein the device 80 transmitted a reply message back to the central controller. However, since the micro doe~ not load data into the start bits regis~er U641, it is necessary to set this register before a message is transmitted. This is accomplished by the TXSTBA line which ~oeq low at the beginning of a transmitted message and sets the register stage U641 as shown in Fig. 13.
Accordingly, when the TXST8A line goe~ high at the end of the l bit delay provided ~y the flip-flop 178, the start bits regis~er U641 is se~ and its logic ~l~
can be shifted out ~o form the second half of the two ~it start signal of the transmitted message as described previou~ly.
When the transmit ena~le latch 1~4 (Fig.
13) is set at th2 start of transmission of this mes-sage, the output of the NAND gate U66~ (Fig. 13) is employed eo et the transmit detect flip flop 20~
through the NAND gate U664 the other inputs of which are the power on signal PONN and the ~NABL~ ~ignal.
When an STSTB signal is produced at the end of this trans~itted ~essage in response to the delayed clock pulses DSHFCLK the TXONN line is low so that the ou~-put o a NANG gate U68~, to which these two signals are inputted, remains high leaving the ~uffer control latch 206 se~. Thi~ means that buffes control, which wa~ switched to ~he networ~ at the ~eginning of ~rans-mission, remains that way.
In order to -ignal the a~e~ociated microcom-puter ~4 that an interface ig being ~et up between ~ 5~

~he expanded slave mode device 80 and the miero so that two way data transmission over the netwoc~ is ~k po~sible, the device 80 produces a high on the INT
pin 9 as soon a an ena~le inter~ace instruction is decoded ~y the decoder 166. More particularly, when the RX/T~ register U644 i5 se~ at the end of a re-ceived message containing the ena~le interface in-struction, as descri~ed previously, the output of the NAND gat~ U756 is supplied as one input to the NAND
gate U1000 the other input of which is the TXONN
line~ Since the TXONN line is high excep~ during transmission a clock pulse is supplied ts the ~nter-rupt flip flop 210, also identified as U643. The D
line of the flip-10p 210 is connected to the 5 volt supply so that when this flip-flop receiveq a cloc~
pulse its QN output ~oes low, which is inverted and supplied to the INT pin 9 of the device 80. This signals the associated microcomputer that an inter face has ~een established ~etween it and the expanded slave device 80 so that the micro may read the data s~ored in the serial shift register 152 from the DATA
pin and load data in~o th.s regist`er in the manner descri~ed in detail here~ofore. As ~oon a3 ~he micro produces the first pulse on the SCK line, either in reading da~a from the register 152 or writing data into the register 152, this SCK pulse reset3 the interrupt flip flop 210 and removes the interrupt signal from the INT line. More particularly, this SC~ pul~e is supplied to one input of a NOR gate U1002 the other input of which is the output of a NAND gate U657. The output of the NAND gate U657 i5 high when the interface is ena~led and power is on the device 80 so the f irst SCK pul~e reset~ the in-terrupt flip flop 210.
If the micro loadR the serial shift regi -ter 152 and instructs thé expand~d ~lave device 80 to transmit this message back to the networ~ the TXONN

~s~

line goe~ low during such transmission, as described in de~ail heretofore in connec:tion with Fig. 13.
During such transmission the NAND gates U756 and U1000 are blocked so that ehe RX/TX regis~er U644 is not ~et at ~he end o~ the transmitted message. How-ever, when the TXONN line goes high again after the message has been transmitted the interrupt flip-flop 210 is again clocked 50 that a signal is produced on the INT pin th~s signalling the micro that transmis-sion of a message back to the central controller hasbeen completed. The fact that transmission ha~ ~een completed can be verified by the micro by reading the ~ATA pin which is tied to the output of the RX/TX
register U644 and wculd show a ~0~ stored in thi3 re-gister. In this connection it will be noted that themicro can read the DA~ pin any time that the RW line is high to ena~le the tristate output U762, even though control of the register 152 has been shifted back to the network. Cloc~ing of the interrupt flip-flop 210 is timed to coincide with the trailing edgeof the BUSYN signal on pin 9 so that the INT line goes high at the ~ame time that the BUSYN line goes high.
While the microcomputer 84 may be program-med in any ~uitable manner to receive data from and transmit data to the expanded mode slave digital IC
80, in FIG. 15 there is shown a general or high level flow chart ~or the microcomputer ~4 ~y means of which it may re~pond to the interface and establish bi-dir~c~ional communication with and data transmission to the neSwork 7~ through the digital IC 80. Refer-ring to this figure, i~ is assumed that the associ-ated dlgital IC 80 has received a message which in-clude~ an en~ble intcrface command ~ut has not ye~
produced an interrupt on ~he INT line. under these condition~ the RW line is high and the SCK line is low, a~ indica~ed by the main micro progra~ bloc~
212. As soon as an interrupt occurs on the INT line the micro ~eads the DATA linel as indicated by the bloc~ 213 in the flow chart of Fig. 15. As described generally here~ofore, the RX/TX register U644 is set at the end of a received meqsage which includes an enable inter~ace command qo thal: the DATA line, under these conditions is high. Accordingly, the output o~
the decision block 214 is YES and the micro then read the contents of the register 152 in the digital IC ~0, as in~icated by the process bloc~ 215. As de-scribed generally heretofore, the micro perform~ this read out by cloc~ing the SCK line 27 times and read-ing the DATA line on the leading edge of each SCR
pulse~ ~fter the 27th SCK pulRe a zero will ~e stored in the RX/TX register U644, as described heretofore in connection with Fig. 14.
After it has read the con~ents of the re-gister 152 the micro has to decide whether it wi~hes to reply back to the central controller or whether it wishes to switch control of the register 152 ~ack to the network without a reply, as indicated ~y the de-cision block 216 in Fig. 15. ~ssuming first that ~he micro wishes to switch control ~ac-~ to the networ~
withou~ a reply, as indicated ~y the process ~locK
217, the micro accomplishes this by holdin~ the SCK
line low and pulling the ~W line low and then ~ack high. When control is ~witched ~ac~ to the network, the program returns to the main micro program to await the occurrence of another interrupt on the INT
line in response to a message from the central con-troller. In thi~ connection it will ~e recalled that as ~oon as the micro send~ one pulse over the SCR
line to read out the conten~s of the register 152 the interrupt FF U643 is reset and the INT pin goe low again.
After reading the contents of the register 152, the microcomputer 84 may wi~h to reply to the central controller ~y loading data into the register 7 1 ~s ~

152 and com~anding the digital l:C 80 to transmit a 33 blt me~3age ~ignal to the networ~ including this data. under -~uch conditions the c~tput of the deci-~ion block 216 is YES and ~he microcompu~er 84 can load data into ~he regis~er 152 as indicated by the process bloc~ 21~. A descri~ed hereto~ore, the micro loads data into the register 152 ~y pulling the RW line low and then serially placing data ~its on the DATA line and cloc~ing each bit into the register 152 by the positive clock edges of SCX pulses it places on the SC~ line. The data entering the chip begins with the control bit, followed by the least 5 igni f icant ~i t of the ~uf f er ~1 t~ and ends ~p wi th the mos~ significant ~it of ~he buffer bits. The SCR
line is thus cloc~ed 25 times to load the regi3ter 152.
A~ter the register 152 is loaded ~he micro reads the 8USYN line to determine whether it is high or low, as indica~ed by the decision block 220. It will ~e recalled that the BUSYN line goes low if a me~age on the networ~ i~ demodulated by the digital demodulator portion of the digital ~C 80 even though control of the register 15' has ~een shifted to the micro compueer 84. Also, a burst of noise may be in-terpreted by ~he demodulator 150 as an incoming signal. under the3e conditions the microcomputer 84 hould not command the IC ~0 to transmit a message onto the networ~. If the BUSYN line i~ high the micro then give~ a transmit command to the diqital IC
80, as indicated by the process ~loc~ 221. As de-scri~ed heretofore, ~his command is performed by pul-ling the RW line high after it has been held low dur-ing the loading of data into the digi~al IC 80. Con-trol is then returned to the main micro program, as indlcated in Fig. 15.
After the digital IC 80 ha~ tran~mitted the data whlch has ~een load~d into the register 152 onto ~ r ~ ; 3 the network 78 it produces an interrupt high on the INT line at the end of the transmitted message. In response to this interrupt the data line is again read by the micco as indicated by the block 213.
However, at the end o~ a transmitted message the data line is no longer high since the RX/~X register U644 contains a zero at the end of a transmitted message, as described heretofore. Accordingly, the output of the decision ~loc~ 214 is negative and the program pro-ceeds to the decision block 222 to determine whether~urther transmi~sion is required from the microco~pu-ter 84 to tne central controlle~. If such tr~n~mis-sion is required, further data i~ loaded into tbe re-gister 152, as indicated by the blOC~ 219. On the other hand, if no ~urther transmission is required the INT line is reset as indicated by the process block 222. As descri~ed generally heretofore, this is accomplished by holding the RW line high while ap-plying one SCK pulse to the SCR line. This single SCK pulse resets the interrupt flip flop 210 (FIG.
14) and re~oves the interrupt signal from the INT
line.
It will thus be seen that the present com-munication ~y~tem provides an extremely flexi~le ar-rangement for bidirectional communication between thecentral controller and the microcomputer 84 through the digital IC ~0. After the interface is set up the micro reads th~ message transmitted from the central controller to the IC 80 and can either switch cor~rol ~ack to the central controller to receive another me~s~ge or may transmit a me~sage of its own to the central controller. Furthermore, the micro can send a serieR of message~ to the central controller by succes~lvely loading data into the register 152 and commanding the digital IC 80 to transmit thi~ data ~ac~ to ~he central controller, a~ indicated ~y block 219, 220 and 221 in Fig. lS. In this connec-tion it will be ~nderstood that: a~ter the interfaceis initially set up in the first message transmi~ted by the central controller, subc;equent messages from thi~ central con~roller to the micro use all 24 ~uf-fer ~its a3 data ~itY a~d the control bit is a ~on.
All other devices 80 on the ~ame networ~, whether in the stand alone slave mode or the expanded mode, will interpret such a message as noe in~ended for them due to the fac~ that the control bit is reset, even though the data transmitted may have a pattern cor responding to the addre s of one of the~e other de-vices ~Q. The tranRmission cf data bac~ and forth ~etween the central controller and the microcomputer 84 continues until the central ^ontroller diRa~les the in~erface.
The interface may De disa~led by a direct disable interface instruction to the device 80 asso-ciated with the microcomputer, in which case the mes-sage transmitted by the central controller will have a control ~it set (~1") and will have address bits corresponding to the address of this device 80. The device 80 will respond to the disa~le interface in-struction by re~etting the enable interface latch 202 (Fig. 14). In the alternative, the central control-ler can disable the inter~ace implicitly ~y si,~plytransmitting a me33age over the network which i~ ad-dressed to another digital IC 80 in which ~he control bit i~ ~et. The interfaced digital IC 80 will al50 receive thiq message ~u~ will recognize the occur-re~ce of a control bit of ~1~ together with anaddress which i~ not its own and will di a~le the in-terface in response to this condition, as will ~e descri~ed in more detail hereinaf~er. However, in the expanded slave mode this implîcit mode of disabl-ing the interface will not be effective if a BC~error iR detected in the received me~sage. ~his is done because the received message might have been in-~ ~7~ 3 6~ 51930tended for the inter~aced microcomputer bUt a noise impul e caused the control bit to be demodulated as a Rl3 instead of a zero. Under these conditions, the BC~O~ line will not go high at the end of the receiv-S ed me~sage and this condition is used to maintain theinterface, as will be descri~ed in more detail here-inafter.

As discussed generally heretofore, the digital IC ~0 may also be pin configured to operate in an expanded master mode as indicated at station ~4 in FIG. 1. In the expanded master mode the device 80 i5 permanently interfaced with a microcompu~er 86 so that the microcompute~ ~6 can operate as an alternate controller and can send she~ and restore load signals to any of the stand alone slaves 80 of ~he communication networ~ if the central controller 76 is inactive and does not place any messages on ~he ne~work. This interface is permanently established when the MODEl pin 1 of the device 80 at station ~4 is ungrounded, as shown in Fig. 1, so that the ~MN
line in Fig. 14 is always low and the ENA~LE line is always held high through the NAND gate U749. The expanded master device 80 a~ station ~4 should have an address which is different from the address of any of the other device~ 80 on the line 78 so as to permit th~ central controller to communicate with the microcomputer 86.
The microcomputer 86 can also establish communication over the power line 7~ with the micr~computer 84 through the expanded slave IC device at station ~3. To esta~lish such two way communication, the microcomputer 86 merely transmits data to the expanded master device 80 over the bidirectional DATA line which data includes the addreq~ of the expanded sl~ve device 80 at ~ation ~3 and an enable inter~ace instruction. The expanded msster 80 includes this data in a 33 bit message formatted in accordance with the protocol required by 4 the communica~ion networ~ and transmits this message over the power line 78 to ~he expanded slave 80 at station t3. The expanded slave 80 at this station responds to the enable interface instruction by e~tablishing the above de~cri~ed interface with the microcomputer 8~ after which the bidirectional ex change of data ~etween the microcomputers ~4 and 86 is made possi~le in the manner descri~ed in detail heretoore.
A digital IC 80 which is pin configured to opera~e in the expanded master mode i~ also used as an interface ~etween the central control computer 88, which may comprise any microcomputer or main frame computer, which is employed to control the remote stations connected to the central controller 76 over the power line~ 78. ~he expanded master device 80 associated with the central controller 76 should also have an address assigned ~o it which is different from the address assigned to any of the other digital IC's on ehe line 78, including the ~igital IC ~0 at sta~ion 54 associated with the microcomputer 86.
This is true even though the interface to the central control computer 8~ is always ena~led as discussed previously in connection with the expanded master de-vice ~0 at station 44.
Since the expanded master digital IC's 80 a~ociated with the central computer 88 and the microc~mputec 86 each produces a BUSYN signal when-ever it is receiving a message from the network, the presently deYcri~ed communications and control system permit the use of multiple masters on the same net-wsrk line. If, for example, the microcomputer 86 wishe~ ~o send a message to any other point in the system, including the central controller 76, the microcomputer 86 can monitor it~ BUSYN line to see if ~.~'7~

any message is on the networK at that time. In ~he 3~me manner, the central controller 76 can monitor ~e it~ BUSYN line before sending a message to be sure the microcomputer 86 is not sending or receiving a message at that time.
l_ 9~
As will be recalled from the preceeding general discussion, the coupling networ~ 90 prQvides ~idirectional coupling between the network 78 and the digital IC ~0 which is tuned to the carrier freq~ency of 115.2kHz. The coupling network 90 also provides amplification of the received signal and limit thi.
signal in b~th the positive and negative directions to five volts peak to peak ~efore it is applied to the RX input terminal of the device ~0. The coupling network 90 also couples the transmi~er output termi-nal TX to the power line and drives it with suffi-cient power to provide a signal of 1 volt runs ampli-tude on the power line 7~ when the device 80 is transmi~ing a ~essage onto the network.
In FIG. 16 a coupling network 90 is shown which is particularly suitable or applications wherein the device 80 is to be asssciated with a con-trolled unit, such as a hot water heater or freezer, in a re~idence. In such applications a ~5V supply for the device 80 is not usually available and the coupling network Y0 of FIG. 16 is arranged to func-tion from the conventional power line and develop a ~uitable power Qupply for the device 80. Referring to this ~igure, the power lines 230 and 232, which may be a 240 volt AC line, supply power to a load 234, which may comprise a ho~ water heater or freezer in a residence, through a power relay indicatea generally at 236 wnich ha~ the normally closed power relay contacts 23~ and 240. A protective device 2~2 i3 connected ~etween ~he power line 232 and neutral, this voltage ,~ormally being 120 volts AC. A full 63 ~ ~ 7~3~ ~ 51930 wave rectifier 244 rectifies the AC voltage on the llne 232 and the output of the rectifier 244 is connected through a diode 250, a resis~or 248 and a filter capacitor 246 to ground so that a DC voltage of approximately 150 volts is developed acrsss the capacitor 246.
In order to provide a suitable voltage level for energizing the device 80, ~he voltage ac-ross the capacitor 246 is connected through a resis-tor 252 to a zener diode 254 across which a voltage of + 10 Y. is developed, a capacitor 256 heinq con-nected across the Zener diode 254 to provide addi-tional filtering. A v~ltage regulator, indic~ted generally at 258, is connected across the Zener diode 254 and is arranged to developed a regulated +5 volts at its output which is connected to the Vdd pin 28 of the device 80. The voltage regulator 25~ may, for example, comprise a type LM309 regula~or manufactured by Na~ional Semiconductor Inc.
A ~ransformer 260 is employed to provide ~idirectional coupling between the networ~ 78 and the device 80. The transformer 260 i~cludes a primary winding 262 and a secondary winding 264, the primary winding 262 being connected in -Qeries with a capaci-tor 266 ~etween the power line 232 and neutral. The two winding~ 262 and 264 of the transformer 260 are decoupled go as to permit the winding 262 to func-tion a~ a part of a tuned resonant circuit which in-clude~ the capacitor 266, this resonant circuit being tuned to the carrier frequency of 115.2 kHz. More particularly, as shown in FIG. 16A the core structure of the transformer 260 is formed by two sets of op-posed E shaped ferrite core sections 268 and 270 oppoQed E shaped ferrite core sectionC 268 and 270 the opposed leg-~ of which are sep~rated ~y a small air gap. Preferably~ these core sections are made of type 814E250/3E2A ferri~e material made by the Fesrox 4~ ^~

Cube Corp. The winding 262 is wound on the opposed upper leg portion3 272 of the sections 268 and 270 and the winding 264 is wound on the bottom leg sec-tion~ 274. The windings 262 and 264 are thus de-couple~ by the magnetic shunt formed ~y the opposedcenter leg~ of the core sections 268 and 270 so a~ to provide su~stantial decoupling between these wind-ings. The winding 262 has an inductance of 0.2 ~
lihenries and consists of 100 turns of AWG~36 wire.
The winding 264 has an inductance of 7.2 millihenries and consists of 600 turns of AWGJ40 wire. The turns ratio between the primary winaing 262 and the secon-dary 264 is thus 1:6. The air gaps ~etween the opposed legs of the core sections 26~, 270 are pre~
fera~ly 63 mils.
The upper end of the winding 264 is con nec~ed ~o ~he 150 volt potential developed across the capacitor 246 and the bottom end of this winding i5 connected to the collector of a high voltage NPN
transistor 280 the emitter of which is connec~ed to ground through a small resistor 282. Prefera~ly, the tran~istor 2~0 i a type MJE 13003 ~hich is manufac-tured by Motosola Inc. In the alterna~ive, a high voltage FET type IR720 manufactured by International Rectifier CQ. may be employed as the transistor 2~0.
The bottom end of the winding 264 is also connected through a c~pacltor 2~4 and a pair of reversely con-nected d~od~s 286, 288 to ground.
When a modulated carrier message i5 trans~
mitted over the power line 232 to the remote location of the device 80, ehe on-off keyed carrier signal may have an amplitude in the millivolt range if the mes-sage has been ~ransmitted a su~stantial distance over the power line. The winding 262 and capacitor 266 of the coupling networ~ ~0 act as a first resonant cir-cuit which is tuned to the carrier frequency of 115.2 kHz and ha~ a Q of approxima~ely 40. The winding 264 ;~ ~`7~

and the capacitor 2~4 also act as a reso~ant circuit which i~ tuned to the carrier frequency. Prefera~ly, the capacitor 266 is a polypropylene 400 V. capacitor having a capacitance of 0.01 microfarads. The capa-ci~or 284 preferably has a value of 270 picofarads.
If the signal on the line 232 has an amplitude of 10 millivolts, for example, approximately Q times the input voltage will ~e developed acros~ the winding 262 i.e. a signal of 400 millivolts amplitude. The signal developed across the winding 264 is increased by a fac~or of 6 due to the turnQ ratio of the tran~
former 260, and is coupled through the capacitor 2~4 to a filter network which includes the ~eries resi~-tors 2Y0, 292, and 2~4. A shun~ resistor 296 is con-nected between the resistors ~0 and 2Y2 and ground and a small capacitor 2~8, which prefera~ly has a value of 100 picofaads, is connected ~etween the junction o the resistors 292 and 294 and ground.
The output of this filter circuit is sup-plied to one input of a comparator 300 the other in put of which is connected to ground. The comparator 300 may, for example, comprise one section of a quad comparator commercial type LM239 manufactured by National Semiconductor, Inc. The comparator is energized from the + 10 V. supply developed across the Zener diode 254 and its output is supplied to the R% pin 6 of the device 80. Thi~ output is al~o con-nected through the resistor 302 to the f ive volt out-put of the regulator 25~. A small amount of positive feedback is provided for the comparator 300 ~y means of the resistor 304 which is connected between the output of the comparator 300 and the plus input ter-minal thereof, the resistor 304 preferrably havLng a value of 10 megohms. The slight positive feed~ac~
provided ~y the resistor 304 creates a small dead band at the input of the comparator 300 so tbat a signal of approximately 5 millivolts is required eo develop a signal in the output and noise voltages ~élow this level will not ~e reproduced in the outpu~
of the comparator 300. However, when the incoming signal exceeds a five millivolt level it i5 greatly amplified, due to the extremely high gain of the com-parator 300 so that an amplified carrier signal of five volts amplitude is developed across the resistor 302 and is applied to the RX i.nput terminal of the device 80.
Considering now the operation of the coupl-ing network 90 during the transmission of a mecsage from the device 80 to the networ~, the modulated car-rier signal which is developed on the TX pin lO of the device 80 is coupled through a capacitor 306 to the base of the transistor 2~0~ This Dase is also connected through a diode 308 to ground and through a resis~or 310 to ground. The transistor 280 is a high voltage NPN transistor so tha~ the collector of thi~
transistor can ~e connected through ~he transformer winding 264 to the lS0 volt supply appearing across the capacitor 246. The capaci~or 306 is provided to couple the TX output of the device ~0 to the base of the transistor 280 ~ecause when power is applied ~o thc device 80 the TX output pin 10 assumes a five volt potential which would destroy tne transistor 2B0 if the capacitor 306 were not provided.
The ~ran istor 280 is turned on and off ~y the ~odulated carrier signal which is couple~ to the base of thi~ transistor through the capacitor 306 and hence dcvelops a voltage of approximately 150 volts acro~ the winding 264 during the carrier on portions of the transmitted message. When the transistor 280 i8 turned off there is a substantial current being draws through the winding 264, which cannot change instantaneously, so that a large bac~ EM~ pulse is also developed across the winding 264. The reversely connected diodes 2~6 and 2~ protect the receiver in-5L~
~7 51930 put circuitry in both polarities from the high vol-tage pulses which are developed acros~ the winding 264 during the transmit mode. Ho~ever, it will 3e uslder~tood that the diodes 286 and 288 do not conduct for small amplitude signals and hence ~he received carrier signal may ~e coupled through the capacitor 2B4 to the comparator 300 without interference from the diodes 286 and 288.
The large carrier voltage developed acros~
the winding 264 is stepped down in the transformer 260 and drives the power line 232 ~o th3t the 33 bit rnessage developed by the device 80 may be trar~smitted over a substantial dis'cance to the central control-ler. At the carrier frequency the power line 232 will have a very low impedance of approximately 10 ohms whereas the reactance of the capacitor 266 is a~out 300 otDns at the carrier frequency. According-ly, the power line i5 essentially driven in a current mode.
Considering now 'che manner in which the de-vice 80 controls the relay 236 and its a~sociated load 234 in response to a shed loa~ instruction, the relay 236 iY provided with a high current coil 320 which controls the high current relay contacts 238, 240, the coil 320 t)eing connected in series with the normally closed contacts 322 and an SCR 324 to ground~ The other side of the relay coil 320 is con-nected to the unfiltered full wave rectified output of ~he rectifier 244. A relatively low current hold-ing ooil 326 i~ also connected from this point to the drain electrode of an FET 328 the source of which is connected through the resistor 330 to ground. The COUT pin 8 of the device 80 i connected to the gate electrode of an FET 332 the drain elec~rode of which i~ connected ~o the +5 V. supply through the resiqtor 334 and ~he source is connected to ground~ The drain of the FET source is connectea to the gate of the FET
328.
When power is applied to the device 80 the COUT pin goe high which causes the F~T 332 to con-5 duct and the voltage developed across the resistor 334 holds the FET 328 nonconductive. Accocdingly, there is no current flow through the resistor 330 and the SCR 324 is held off. When a shed load instruc-tion is received by the device 80 the COUT line goes low which turns off the FET 332 and causes the FET
328 to conduct. The voltage produced across tbe re-sistor 330 turns on the SCR 324 so that the relay coil 320 is energized and opens the main relay con-tacts 23~ and 240. At the same time, the normally closed contacts 322 in series with the coil 320 are opened. However, since the FE~ 328 i~ conducting the relay coil 326 is energized and holds the contacts 238j 240 and 322 open. However, the coil 326 has an impedance su~stantially greater than the coil 320 so that only a small current is required to hold the contacts of the relay 236 open. When a restore load instruction is received by the device 80, the COUT
line again goe~ high and the FET is cendered noncon-ductive so that the coil 326 is no longer energized and the normally closed contacts of the relay 236 are again clo ed. Since the relay 236 has no auxiliary contact-~ to provide status feedbac~, the STATl and STAT2 pins 26 and 25 are connected bac~ to the COUT
pin ~ of the device 80.
If it is desired to have a varia~le time out feature, a~ discuqsed in detail heretofore in connection with Fig. ll, the TOUT pin 9 and the TIMR
pin 24 of the device 80 in Fig. 16 may be connected in the manner shown in Fig. 11 to provide a variable time out feature in association with the relay 236.
It will be understood that the coupling networ~ ~0 can ~e of very small phy~ical ~ize due to ~.~7~

the fact that the coupling transformer 260 is rela-t~lvely small. The coupling network 90, the device 80 and the control devices 332, 32~ and 324 may all be loca~ed on a qmall circuit board which can be moun~ed s withln the housing of the relay 236 so as to provide an addressa~le relay in a ~i~ple and economical man-ner. Furthermore, existing relays can be conver~ed into addressa~le relays ~y simply installing such a ~oard and ma~ing appropriate connections to the power line.
It will be appreciated that in many in-stances the controlled device associated with the digital IC 80 will have a low voltage D.C. power ~up-ply which is provided for other logic circuits in the lS controlled devic~. In such instance, the coupling network of Fig. 16 can be modified as shown in Fig.
17 to operate directly from a low voltage D.C. power source. Referring to this figure, only the portions of the network of Fig. 16 are shown which are chang-ed from the arrangement of Fig. 16. Specifically, the upper end of the winding 264 is conneceed to a +24 volt supply (assumed to ~e available from the controlled device) and the bottom end of the winding 264 is connected through a resistor 340 to the drain electrode of an FET 342 the source of which is con-nected to ground. Preferably the FET is a power FET
commercial type 2N6660. The gate of the FET 342 is connected to ground through the diode 308 and through the capacitor 306 to the TX terminal of the device 80. The drain of ~he FET 342 is also coupled through a dlode 344 and a resi3tor 346 to a liqht emitting diode 34~. In the circuit of Fig. 17 the voltage regulator 258 and comparator 300 are of a suita~le com~ercial ~ype to ~e energized directly from the +24 V. ~upply. Since a lower D.C. voltage is availa~le in the circuit of Fig. 17 both of the wlnding~ 262 and 264 of the transformer 260 of Fig. 17 have the same number of turns, i.e. 100 turns of AWG ~36 wire, and the capacitors 266 and 284 are both 0.01 ufd.
cap~citors.
In operaeion, the circuit of Fig. 17 re~
ceives an on-off modulated carrier signal from the power line 78 which is coupled through the transform-er 260 without step up ~ecause ~oth windings 262 and 264 have the same number of turns. The signal deve-loped across the winding 264 is coupled through the capacitor 2~4 and the input filter and co~parator 300, as described in connection with Fig. 16, to the RX terminal of the device 80. In the transmit mode the modula~ed carrier signal on the TX terminal is supplied ~hrough the capacitor 306 to the gate of the FET 342 so as to turn this device on and of~ which produces a modulated carrier current in the transformer winding 264 which i~ transmitted to the power line 78. Since the wi~dings 262 and 264 have the same num~er of turns in the emDodiment of Fig. 17 there is no step down of the transmit~ed signal in pas~ing through the tran~ormer and hence ~he level of the transmitted message in the power line 7~ is a~out the same as the em~odiment of Fig. 17 even though the 24 V. supply is approximately one qixth of the +150 V. sup~ly in the embodiment of Fig. 16.
The LED 348 will indicate the periods during whicn the device 80 i5 transmitting a message to the ne~w~rk 78.

Figs. 18 to 33, inclusive, when arranged in the mænner shown in Fig. 34, comprise a detailed ~chematic diagram of the digital TC 80 descri~ed generally heretofore. Generally ~peaking, in this schematic diagram the logic signals which are deve-loped at the outputs of variouR portion~ of the schematic are given a letter abbreviation which ends with ~N" whenever that particular sig~al i8 an active 71 ~ 51930 low output, Oth@rwise the signal is active high.

Considering now in more detail the dlgital receiver-demodula~or 150 and its associated start ~it deeec~ion and framing logic, it should first ~e pointed out ~hat while this demodulator is particu-larly suitable for demodulating power line c~rrier information in high noise environments and lends it-self to implementaeion in digital large-scale inte-gration circuitry, such as the device 80, this de-modulator is of broad general application and can ~e used wherever it is required ts demodulate ASK
modulated binary data. ~he demodulator m~y ~e used ~y it~elf since it is readily implemen~ed in digital logic or may be used as a part of a larger sys~em as in the digital IC 80.
As discussed generally heretofore, the re-ceiver-demodulator 150 is arranged to demodulate da~a transmitted over a power line. Power line carrier signals are af fected Dy three types of noise:
Gaussian noise, coherent signals, and impul ive noise. The carrier signal plus noi~e is fed into tne digital demodulator 150 through the coupling networ~
~0 which includes an input filter which couples the device 80 to the power line 7~, as descri3ed in de-tail heretofore in connection with Fig. 16. This in-put filter produces oscillations (ringing) in re-spon~e to th~ impulsive noise inpu~s. On the one h~nd it is de~irable to reduce the noise power ~and w~dth of the input filter, i.e. hiqh Q, while at ~he same time there is a need for a relative low Q input filt~r to reduce the ring down time associaeed with inpul~ive noise. The filtering action of the digital demodulator 150 attempts to reconcile the e two con-flicting requirements.
As discussed generally heretofore, the car-rier modulation system e~ployed in ~he digital IC 80 is on-off keying o a carrier frequency of 115.2kHz at 300 baud. This modulation 3y~te~ was chosen in preference to phase shift modula~ion at the data rates required because of the significant phase dis-~urbances associated with the power line 78. Thecarrier frequency of 115.2~Hz i3 chosen ba ed upon spec~ural analyses of typical power line sy~tems and the 300 baud bit rate i5 choserl to provide maximum throughput with acceptable error rates.
The general approach in the digital demodu-- lator 150 is to require pha e coherence in the short term i.e. over one and a half carrier cycles, for frequency detection, and to sen-~e continued pha~e coherence in the longer term i.e., l/6th of a bit, or 64 carrier cycles at 300 ~aud, to di criminate aqainst impulsive noise. Impulsive noise also pro-duces frequenoy information that is coherent in the short term but is not perfectly coherent in the longer term. The reason that the longer term is not extended ~o an entire bit or a longer frac~ion of a bit is that the power line produces phase diYcontinu-ities ~hat are significant over the ~ime interval in-volved. An exa~ple of a phase discontinuity being produced on the power line is a line impedance dis-turbance cdused ~y rectifiers beginning to conduct orending conduct~on in association with a capaci~ative input filter. ~hese phase discontinuities are de-tected and lead to bit error~. By choosing the in-tegr~tion time of l/6th of a bit, each phase di tur-bance can lead only to a degrada~ion of 1/6~h of a~it.
The digital demodulator 150 thus senses both frequency and phase of an incoming signal over a 1/6th of a bit interval (approximately 556 micro-~econds at 300 baud). If the input frequency i~ cor-rect and maintains phase coherence for at le~t three fourths of the 1/6th ~i~ interval, a counter is 5 '~ ~

incremented. After six of these 1-5th bit inter~als are prQcessed, the counter contents are examined. If the counter counts up to ~our or more tassuminq that it ~tar~ed out at 0), the demodulator ou~puts a demodulated logic 1. If the counter conten~s are less than 4, the ~emodulator outputs a demodulated logic 0.
Referring first to the ~loc~ diagram of the digital demodulator 150 shown in FIG. 35, an oscil-lator and timing su~system 400 is employed to pro-vide all of ~he timing signals and stro~es for ~he other portions of the demodulator 150 . A 3 . 6864 M~z _0.015~ oscillator is employed to drive these timing circui~s. ~he carrier input ~ignal which is ampli-fied and limited in the coupling network ~0 and is applied to the RX inpu~ terminal of the device 80, i5 inputted to a pair of carrier confirma~ion circuits 402 and 404, these circuits wor~ing ~0 out of phase with respect to each other. Each of the carrier con-firmation circuits 402 and 404 examines tne input signal and determines if it is within an acceptable ~and of frequencies centered a~out tlle carrier. This i done on a cycle by cycle basis. Each carr ier con~
firmation circuit has two outputs. One output pro-duces a pul~e if the signal is within the pass ~and and the ~a~pled phase of the input signal is a logic 1. The other produce~ a pulse if the signal is with-in the pa~s b~nd and the sampled phase of the input signal is a logic 0. The four outputs of the carrier confirmati~n circuits 402 and 404 are used as cloc~
inputs to a 3eries of four phase counter~ 406, 408, 410, 412 which are reset every 1-6th of a bit. At 300 baud each ~it contain 384 cycle3 of the 115~2kHz carrier. Therefore, a ixth of a bit contains 64 carrier cycles. Should any one of the phase counters 406-412 count up to 48 or more, there~y indicating phase conerence over three four~hs of the -~ixth bit interval, a loglc 1 is produced at the output of a four input OR gate U166, the four inputs of which are the outpu~s of the phase counter 406-412~
The output of the OR gate U166 is connected S to the start bit detection and framing loglc indicat-ed gen2rally at 414. Considered generally, the first logic 1 input to the circuit 414 triggers the start ~it detector. The start ~it detector then releases ~he reset on a coun~er and increment it at intervals of one sixth of a ~it. This counter then counts 11 more sixth bit intervals. At the end of each sixth ~it interval the output of the OR gate U166 stroDed and causes this same counter to increment if it is a logic 1. At the end of the 12th in~erval, lS the counter is examined. If the counter contents are 8 or more, two valid start bi~s are assumed. The counter then resets and six one-sixth bit intervals are counted off. At the end of each interval again the output of the OR gate U156 is strobed and incre-ments the counter if it is a logic 1. The counter isexamined at the end of each six one-sixth bit inter-vals. If the counter indicates 4 ;-~r more a demodu-lated logic 1 is provided on the demod output line.
If the counter indicates less than 4 a logic zero is demodulated. This process is repeated 30 more times ~o yield a complete word of 32 bits (including ~he two start ~lts)~ If in the ~eginning the counter do~ not count up to eight over a two bit interval, the ~tart bit logic 414 re~ets itself and looks for the next loglc 1 out of the OR gate U166.
Considering now in more detail the carrier confirmation circuit~ 402 and 404, each of these cir-cuit sample~ the carrier input at twice the carrier frequency of 115.2kHz. The only difference between the two circuits is in the phase of ~he sampling, the circuit 402 sampling 90 out of pha~e witb respect to circuit 404~ Referring to Fig. 36, the 0 ~tro~e 75 ~ 51930 sample~ of the carrier confirmation circuit 402 are indlcated by the downwardly directed arrows relative to the incominq carrier and the 90 stro~e samples of the carrier confirmation circuit 402 are indicated by the upwardly directed arrows. It can be seen from Fig. 36 that because of the quadrature samplinq of the circuits 402 and 404 the uncertainty of sampling the carrier input signal around its edges is eli~i-nated ~ecause if one of the circuits 402 or 404 is sampling tAe carrier sïgnal in the area of transition from high to low the other circuit is sampling the carrier signal in the middle of th~ square wave car-rier input. Accordingly, ~y simultaneously counting the outpu~s of both of the carrier confirmation cir-cuits 402 and 404 one can ~e sure that one of them is sampling the incoming carrier square wave signal away from its edgesO
Each o~ the circuits 402 and 404 store~ itsthree most recent samples, each sample representing a half cycle strobe of the incoming carrier. After every other sample the circuit will produce a pulse on one of two outputs provided the ehree storea sam-_ples form a one-zero-one or a zeso-one-zero pattern.
The pulse wlll appear at one output if the most re-cent sample is a logic 1 and will appear at the otherif the most recent sample i~ a logic 0. It can thus be seen that ~n output pulse will occur on one output on each of the circuit~ 402 or 404 every ~.68 micro-seconds should the alternating pattern of half cycle sample~ continue. By requiring 3 consecutive samples of the input to ~e opposite in phase, the demodulator lS0 places a more strict criterion on accep~ance of an input 2S the valid carrier signal than would a clrcuit which looks only at the two most recent half cycle sample~. This technique of requiring three conYecutive samples of the input to ~e opposite in phase has been found to be very effec~ive in reject-` i 3 ing noise in the intervals with no signal present and the carrier confirmation circuits 402 and 404 are ef-fective in rejec~ing all frequencies except the od~
harmonic multiples of the carrier frequency.
Considering now the details of the carrier confirmation circuits 402 and 404, and referring to Figs. 18 and 19 wherein these circui~s are shown in the detailed schematic diagram of the device 80, the 3.6864MH~ oscillator signal which is develsped by the crystal oscillator connected to pins 3 and 4 of the device 80 is divided down in the divider tage U102 and U103 so as ~o provide a 921~6~H~ ~ignal which is used to clock a two stage Johnson counter compri3ing the stages U104 U105. The Q and QN outpu~s of the stage U105 comprise oppositely phased square waves of a frequency twice the carrier frequency of 115.2kHz.
These outputs are supplied through the inverters Ul~
and U40 to act as cloc~ signals for the carrier con-firmation circuits 402 and 404. However, the circuit 402 is clocked when U18 goes positive and U40 goes negative whereas the circuit 404 is cloc~ed when U18 goes nega~ive and U40 goes positive so that the cir-cuits 402 and 404 stro~e the incoming carrier 90 apart on the carrier wave.
In order to provide a circuit which stores the 3 mo~t recent samples of the incoming carrier a two stage shift register is clocked at ~wice carrier frequency. Thus, considering the carrier confirma-tion circuit 402, the shift register ~tages U113 and U114 are cloc~ed at twice the carrier frequency, as described heretofore, the output of each ~tage being exclusively ORd with its input ~y means of the ex-clu~ive O~ gates U133 and U134, respectively. The exctusive-OR outputs of the gates 133 and 134 are anded in the NAND gate U137 the output o~ which is inverted in the inver~er U35 and applied to the D
ir.put of a register stage U115. The incoming carrier 77 ~ 930 on the RX pin 6 is applied through the inverter U25, the NAND gate U139, and the inverters U16 and U39 ~o the D input of the first regi!3ter stage U113. The other input of the NAND gate [J139 is controlled by the TXONN signal 30 that no carrier input is supplied to the carrier confirmation circuit~ 402 and 404 while the device 80 is transmittingO
Assuming that a one-zero-one pattern exists on the D input to shift register stage 113, the Q
output of this ~tage and the Q output of register stage U114, this mean~ that the past sample, which is zero, is stored in U113 and the sample ~efore that, which is a one, i~ stored in U114. However, the pre-sent sample on the D input of U113 has not yet been storea. Under these conditions, the outputs of the exclusive OR gates U133 and U134 will ~e one, the outpu~ of the NA~ ga~e U137 will ~e a zero which is inverted and applied to the D input of ~he regi~ter s~age U115. On the next cloc~ pulse the Q outpu~ of V115 will be a one. If, at the time of this cloc~
pulse the D input to U113 remains a one, this one i5 clocked into U113 so that its Q output is a one which represents the stored pre~ent sample at the time of this cloc~ pulse. The Q Output of the stage U115 is supplied as one input to the NAND gates U15~ and U15~
and the Q output of the stage U113 is supplied directly a~ another input to the NAND gate U15~ and through the inverter U36 as another input of the NAND
gate U15~. .
A stro~e signal occurring at carrier fre-quency is applied as a third input to the NAND gates U158 and U159. More particularly, the stages of the Johnson counter U104 and U105 are com~ined in the NOR
g2te~ U66 and U65 to provide twice carrier frequency signal. which are applied to a ripple counter com-pris~ng the s~ages U106-UllO. The input and output of the f irst s cage U106 is com~ined in NO~ gate U130 to proYide a strobe at carrier frequency for ~he NAND gate~ U158 and U159. In this connection it will be noted that the Q output of the stage 115 is always a 1 irrespective of the 101 or 010 patterns set up at the inpu~s and outputs of the stages U113 and U114.
~owever, the Q output of the st:age U113 i~ supplied direcely to the NAND gate U15~ and through the in-verter 136 to the NAND gate U159. Accordingly, only one of these NAND gates will ~e enabled depending upon the condition of the Q output of the stage U113~
~hen this output is a O the NAND gate U159 will pro-duce a pulse on the ZEROA output line whereas when the Q o~tput of the stage U113 is a one the NAND gate U158 will produce a pul~e on the ONEA output line.
It will thus be seen that the pulse on either the ONEA output or the ~EROA output of the carrier confirmation circuit 402 means that over the relatively short term of one and a half carrier cycles the input carrier is generally in pha~e with the tim~ng signals estaDlished in the device 80 through the crystal oscillator 102. The term gener-ally is used because a given pattern may continue to ~e produced even though the incoming carrier shifts in phase by a substantial amount; as shown by the dotted llne in Fig. 36. If the same pattern con-tinues, thus indicatin~ that ~he incoming signal con-tinues to be in phase with the timing circuits of the davlce 80, an output will continue to ~e produced on either the ONEA output or the 2EROA output of the circuit 402 each carrier cycle.
The carrier conf irmation circuit 4G4 oper-ates su~stantially identically to the circuit 402 ex-cept that it is cloc~ea opposite to 402 so that the incoming carrier signal is stro~ed at a 90 point relative to the carrier conf irmation circuit 402.
Thus, if the circuit 402 i~ 3tro~ing the lncoming carrier near t~e edges of the carrier, and hence may 79 ~.2~ 51930 not give a reliable 101 or 010 pattern, the carrier confirmation circuit 404 will ~e strobing the incom-ing carrier mldway between i~s edges so that a reli-able pattern is ob~ained ~y the circuit 404.
As de~cri~ed genera].ly heretofore, t~e phase counters 406-412 are employed separately to coun~ the num~er of pulses developed on the four out-puts of the confirma~ion circuits 402 and 404 during a time interval eq~al to l/6tn of a bit. If any of these counters reaches a count of 48 during the 64 carrier cycles which occur during a l/6th bit inter-val at 300 ~aud, or 12 out of 16 at 1200 ~aud, it is assumed that a valid carrier signal exi~ted for ~hat 1/6th bi~ interval and an ou~put is ~upplied to the OR gate U166. More particularly, referring to Figs.
19 and 20 wherein the counters 406-412 are shown in detail, and consideriny the phase counter 406, the ONEA output of the carrier confirmation c~rcuit 402 is supplied thrOugh the NAN~ gate U140 as the clocK
and notclock input to 2 ripple counter comprising the stages U71-U76. ~ 300 baud, when the counter 406 reaches a count of 48 the Q outputs of tne ~16~ stage U75 and the "32" stage U76 are com~ined in the NAND
gate U141 the zero output of w~hich is supplied to the NAND ga~e U166 which ORs the zeroes outputted ~y the counter~ 406-412 and corresponds to the OR gate U166 of Fig. 26. When the counter 406 reaches a count of 48 the output of the NAND gate U141 is supplied bac~
to the other input of the NAND gate U140 ~o disa~le the input of ~he coun~er 406 during the remainder of the 1/6th ~it interval. In a similar manner, the phase counter 40~ counts the pulses developed on the 2EROA output of the carrier confirmation circult 402, the phase counter 410 counts the pulses on the ONEB
output of the carrier confirmation circuit 40q and the phase counter 412 count~ the pulse3 on the ~EROB
output of the circuit 404.

~.~`7~ 3 ~0 51930 The diyital demoàulator 1;0 is thus capable of recelving a transmitted message even though the seceived carrier signal drifts continuously by a sub~tan~lal ~mount throughout a recelved message S transmitted at 300 ~aud. This is achievea by providing the phase counting channel5 406-.412 all of which only counts over an interval of one s~xth ~it.
The received message may drift ~ufficiently relative to one of these channels during one sixth of a bit to alter the 101 or 010 pattern of one of the carrier confirmation circuits 402 or 404 but the other will not have the pattern altered over this lnterval.
ThuR, referring to Fig. 36, if the receiv~d oarrier drifts to the left ~y a su~stantial amount as indicated by the dotted line in Fig. 36, the 101 pattern of the 0 samples will not change ~ut the 90 sample pattern changes ~rom 101 to 010 ~y viztue of this carrier drift. The 0 samples will thus glve a valid one sixth ~it .coun~ with this amount of carri*r drift even though the ~0 samples will not. By ORing the outputs of all of the phase connector~ 406-412 several one sixth bit intervals may be successively counted through different phase counters and thereby accommodate su~s~antial drift ~in either direction ~etween the received carrier and the sampling strobes developed in the demodulator 150. As a result, the 33 bit received message may be demodulated without ehe use of a pha~e loc~ loop or other synchronizing c~rcuit and even though the crystal oscillators at the central controller and the remote station are operating asynchronously and at slightly d~fferent frequencles.
As discu~sed generally heretofore the phase counterR 406~412 also count the phase coherences of the carriet confirmation circuits 402 and 404 over only a 1/6th ~it interval so as to avoid any pha~e d~3tur-~ances which may ~e produced on the power line used ~.~7'~ 3 ~1 519 30 as the network transmission medium. Accordingly, the phase counters 406-412 are reset after each l/6th bi~ interval. More particularly, the output of tne rlpple counter Ul06-110, the input of which is cloc~ed at twice carrier frequency, is supplied through the swLtch U122, the inverters U873 and 874, the switch U128 and the inverters U867 and U17 to a two stage Johnson counter comprising the stages Ulll and U112.
The output of this counter is a signal at 1/64th car-rier frequency which is equal to a 1/6th bit interval at a 300 baud rate. Accordingly, the output of the inverter U15, which is connected to the Q output of the s~age U112, is employed to reset th~ pha e counters 406-412. More particularly, the output of the inverter U15 is ,supplied as a clock input to the flip flop U172 the D input of which is connected to the +5V supply. The ~ output of the stage U172 is coupled through the inverters U20 and U50 to the RSTPHAS line (reset phase counters) ana resets all of ~he phase counters 406-412. The stage U172 is reset by the output of the NOR gate U65 which is delayed with respect to the outpue of the NOR gate U66 which controls the ripple counter U106-U110.
Considering now in more detail the start ~it detection and framing logic portion of the demod-ulator 150, the Johnson counter comprising the stages Ulll and U112 is employed to develop a num~er of tim-ing signal~ which are employed in the start bit de-tection and framing logic circuits. More particular-ly, the inputs and outputs of the stages Ulll and U112 are combined in a series of NOR gates U67-U70, U132 and U200 to provide a num~er of s~ro~e signals.
The nomenclature and timing of these stro~e signals is shown in Fig. 37 wherein ~he waveform 37~a) is the 3; output of the switch U128 which occurs at 24 times bit rate at 300 ~aud.~ ~he output of the ~OR gate U67 is identified as STBAD and is shown in Fig. 37(b).
.

Jl . ~ ~ .5 ~ ~: 3 The output of the NOR gate U132, identified a~ STBB, i shown in Fig.. 37(c). The output of the NOR gate US8, identified as STBBD, is showr in Fig. 37(d).
The output of the NOR gate U69, identified as STBCD
is shown in Fig. 37(e). The o~ltput of tne NOR gate U200, id~ntified as STBD, is shown in Fig. 37(fJ and the ou~put of the NOR gate U70, identified as STBDD, is shown in Fig. 37(9J.
Should one of the phase counters 406-412 counts to 48 during a 1/6th bit interYal and the OR gate U166 produces an output, a bit framing counter 420 (Fig. 22) has its reset released and is incremented by one. The ~it framing counter 420 is initially set to count 12 1/6th bit intervals to pro-lS vide a frame of réference to determine whether ~he incoming signal comprises two start blts ~oth having logic ~1" values. At the same time a demodulator counter 422 ~Fig. 21) is employed to count the num~er of outputs produced ~y the OR gate U166 from any of the phase counters 406-412 during the two ~it inter-val esta~lished by the bit framing counter 420. If the demo~ulator counter 422 counts to 8 or more dur-ing thls two bit interval a valid start ~it is assum-ed~ On the other hand, if ~h~ counter 422 has a count of less than Y when the counter 420 has counted to 12 the framing logic is reset and waits or the next logic 1 out of the OR gate U166. More particu-larly, when the OR gate U166 produces an output it is suppl~ed through the switch U12~ to the D input of the flip flop U95 (Fig. 22) which is clocked by the output of the Johnson counter stage U112 near the end of each l/6th ~it interval. When the flip ~lop U~5 goe~ high it cloc~ a flip flop Ull9 the D input of which 18 connected to the +5V Supply so ~hat the QN
output of Ull~ goes low. This Oueput, through the NAND gate U162, the inverter U53, the NOR qate Ul76 and the invercer U54, controls the bit reset line ~3 51930 (~ITRST~ so thàt the reset on ~oth of l:he counters 420 an~ $22 i~ released. Also, the ~it framing counter 420 i~ incremented ~y 1 ~y means of the STBAD
pulse (Fig. 37~b)) which is ~upplied through the in-s verter U~65 to cloc~ the first C;tage U98 of the coun-ter 420~ Also, when U95 goes high it is anded with the STBAD pul~e in the NAND gate U155 which incre-ments the demodula~or counter 422 by 1.
When the bit framing counter 420 has count-ed to 12, which occurs two bit interval~ lateri the "4" and "8" output stages U100 and U101 thereof are supplied to the NOR gate U131 the outpue of which sets a frame latch comprising the NOR gate~ V169 and U170. This latch produce~ an output on the FRAME
line which is anded with the STBB pulses (Fig. 37(c)) in the NAND gate U153 ~he output of which is inverted in the inverter U58 and supplied as an input to the NAND gate U152. The o~her input of the NAND gate U152 is the Q output of the last stage U121 of the demodulator counter 422. Accordingly, if during the first two ~it interval the demodulator counter 422 has received 8 or more cloc~ pulses from the flip flop U95, which indicates tha~ the phase counters 406-412 have collectively produGed an output for ~ of the 12 1/6th ~it intervals corresponding to the two s~art ~its of a received message, the Q output of the last stage U121 will ~e high and the output of the NAND gate U152 is employed to set a received word detec~ latch U151 and U165. When this la~ch is set the RXWDETN line, which is the inverted output of ~his latch, goeC low for ~he remainder of a received message. This RXWDETN signal passes through the NAND
gate U171 to one input of a three input NAND gate U163 the other two inputs of which are the frame out-put of the latch U169, U170 and the STB~D ~tro~e pulses (Fig. 37 (d) ) . Accordingly, when the ~WI)E~N
line goes low af ter the frame latch has been set the NAND ~ate U163 produces an output which is inverted in the.inverter U567 to produce shift register clock pulses on the BS~FCLK line. The output of the demo~-ulator counter 422 passes through the NOR gate U29 and ~he inver~er U63 to the DEMOD output line as soon a. the counter 422 counts 8 1/6th bit intervals.
However, the demodulated data is not clocked into ~he serial shi~t register 152 until BSHFCL~ pulse~ are produced at the end of the two start bit framing in-terval when the output of the NAND gate U163 goeslow. After the BSHFCLR pulses are produced the S~BDD
pulses are combined with the FRA~E signal in the NAND
gate U164 so as to produce delayed shift regi~ter clock (DSH~CLKJ pulses which ocour after the BSHFCLK
pulses and are used at various points in the d~vice 80, as descri~ed heretofore. The DEMOD output line of the demodulator I50 is supplied througn the switch U758 ~Fig. 31) to the input of the BCH error code computer 154 so as to ena~le this computer to compute a BCH error code based on the first 27 bits of the received message. The DEMOD output is al50 supplied through the switch U75~ (Fig. 27) to the input of the seri21 shift register 152~ as will ~e descri~ed in more detail hereinafter. The DEMOD output is also supplied to the dual function pin 22 of the device ~0 when this device i~ operated in a test mode, as will be descri~ed in more detail hereinafter, The RXWDETN line also controls resetting of the counters 420 and 422 since when this line goes low it indicates that a valid start ~it of two bit intervals length has ~een received. More particular-ly, the RXW~ETN llne is supplied thrQugh the NAND
gate U162 and the inverter U53 to one input o~ a three Input NOR gate U176. The STBCD stro~e pulses are anded with the frame signal in tne NAND gate U150 and inverted in the inverter U55 to supply another input ~o ~he NOR gate U176. The third input of this ~1930 NOR gate is the internal reset line INTRES which is normally low. Accordingly, an output is supplied from the NOR gate U176 in cesponse to the low output produced by U150 which is inverted in the inverter U54 and supplied to the bit reset line BITRST to reset ~he ~it framing counter 420 and the demodulator counter 422.
After a valid start bit has been received, which lasted for two bit intervals, it is necessary to adjust the ~it framing counter 420 50 that i~ will count up to only 6 to set the frame latch U169, U170.
This is acsompli~hed ~y combining the ~XWDETN signal, which passes through the NAND gate U201 and the inver-~ers U202 and U~61, with the STBAD pulse which are supplied as the other input to a N~ND gate U~62 through the inverter U866. As a re~ult, th~ NAND
gate U~62 ~upplies a clock signal through the NAND
gate U854 to the second ~tage U99 of the bit framing counter 420 while the output of the first stage U~
is bloc~ed ~y the NAND gate U860. Accordingly, the stages Uln0 and U101 of the counter 420 are com~ined in the NOR gate U131 to set the frame latch U16~, U170 at a count of 6 for the remaining bits of the received message.
With regard to the demodulator counter 422, it will be recalled that if this counter counts to four during the next ~it interval, i.e. the phase counters 406-412 have collelctively produced an output for four l/6~h bit intervals during the next full bit interval, it is assumed that a logic 1 has been received~ Accordingly, the Q output of the stage U120 is also connected through the NOR ga~e U29 to the DEMOD line. In this connection it will be understood that while the stage U120 produces an ou~put during the start ~it framing interval before a count of 8 i9 reached in the counter 422, this output appearing on ~he DEMOD line is no~ used to load the shift register 152 because no BSHFCLK pulses have been produced at that time. The STBD3 strobe pulses (Fig. 37(9)), which occur at the end of a 1/6th ~it intervalt are used to reset the frame latch U169, U170 at the end of either the initial two start bit framing cycle or ae the end of each succeeding ~it interval.
If ~he bit framing counter 420 counts to 12 during the initial two start bits interval and the 1~ demodulator counter 422 does not count up to 8 or more during this period it is assumed thae two valid start ~its hav~ not been received and the ~lip flsp Ull9 is reset as well as the counters 420 and 422.
More particularly, if the counter 422 does not count to 8 or more the RXWDETN line is high whiCh appears as one input to the ~AND gate U149. The other input of this NAND gate is a one when the ST8CD stro~e pulse is nanded with FRAME So that the output of the NAND gate U164, iden~if ied as RSTWORD goes high ana reset~ the flip flops U~5 and Ull9. When tnis occurs the Q not output of Ull9 goes high and the output of NAND ga~e U162 goes low whiCh passes through the NQR gate U176 and causes the BITRST line to go high whlch resets the counters 420 and 422.
8 At the end of `a 33 bit message the EOW
line from the message ~it coun~er 160 goes high and sets the lacch U167, U16~ so that the output of this latch, which iS one input of the NAND gate U148 goes high. Upon the occurrence of the STBD pulse to the other input of the NAND gate U14~ the RXWDETN latch U151, U16S is reset So that the RXWDETN line goes hlgh indicating ~he end of a message. Also, a low on the output O~ the NAND gate U148 produces a high on the outpue of the NAND ga~e U164 whlch resees the flip flops UY5 and Ull~.
From the a~ove detailed descrip~ion of the digital demodulator 150, it will ~e evident that this ~ 27.5~
8, 51930 demodula~or is particlarly suita~le for receiving and ~emodulating on-o~f keyed carrier messages transmit-~ed over a power line which rnay have phase distur-bances which produce large holes in the received mes-~age. This is ~ecause the pnase counters 406-412 can detect a valid l/6th ~it when 16 out of the 64 car-rier cycles are missing from the recelved signal.
Also, the demodulator counter 422 can indicate a valid n logic l n when 2 out of the six 1/6tn bit in-tervals are missing in the received message. In Fig.
38 there is shown the test results of the digital de-modulator 150 when used in different noi~e environ-ments. Referring to this figure, the a~cissa is a linear scale of signal to noise ratio in DB an~ the ordinate is a linear scale of the bit error rate.
For example, a ~it error rate of 10-3 is 1 ~it error in the detection o~ 1,000 bits. The curve 424 in FIG. 38 s~ows the bit error rate of the digital de-modulator 150 when an input signal amplitude of 100 milivolts peak to pea~ is mixed with different ampli-tudes of white nois2 to provide different signal to noise ratios. This 100 milivolt input signal plus noise was applied to the input of the coupling net-work 90 (in plac~ of tne power line 232 (FIG. 16)) and the signal to noise ratio was measured at the -- junctions of capacitor 284 and the diodes 286 and 2~8 in the coupling networ~ of Fig. 16 with a spectrum analyzer having a bandwidth of 300 Hz. The curve 424 hows that at a signal to noise ratio of 17 ~3 a bit error rate cf 1 in 100,000 is achieved. At a ~ignal ~o noi e ratiO of 9 a bit error rate of 1 in 1,000 is achieved. For comparison, the curve 426 ~how~ the theoretical ~it error rate curve for a differentially coherent phase shift ~eyed sig.nal witA white noise.
Curve 42~ in Fig. 3~ shows the bit error rate oÇ tne demodulator 150 when used on a powe line in~tead of ' with a white noise geherator. 5ince it was not 8~ 51930 po~sible to vary the noise level o~ tne power line, d1fferen~ values of signal input were employed, point A on the curve 428 being ob~ained with a signal input of 30 milivolts peak to peak and poin~ B on the c~rve 428 being obtained with a signal input o~ 60 mili-volts peak to pea~.
By co~paring curves 424 and 4~, it will ~e seen that ~he digital demodulator 150 provides su~-stan~ially ~etter performance i.e. lower ~it error rates when used with the power line tnan when the input signal is mixed with white noise. This is ~ecause the power line noise is primarily impulsive whereas the white noise signal is of uniform distribu~ion through-out all frequencies. The digital demodulator 150 is particularly designed to provide error free bit detec~ion in the presence of impulsive noise, as discussed in detail heretofore.
The bandwidth of the digital demodulator 150 has also ~een measure~ ~y applying a sweep generator to the RX input pin of the device 80 and sweeping through a ~and of ~requencies centered on the carrier frequency of 115.2 kHz. It was founc that the demodulator lSO totally rejec~s all frequencies greater than 1.2 kH2 away from the carrier frequency (115.~ k~z) except for odd harmonies of the carrier the lowest of which is 3 times the carrier frequency.
As discussed generally heretofore, the di-gital IC 80 can be pin configured to operate at a 1200 baud rate when the device 80 is to ~e used in le~s noisy environments such as the dedicated twisted pair 92 shown in F$g. ~. In accordance wieh a fur-ther aspec~ of the disclosed system this modification is accomplis~ed in the digital demodulator 150 by simply reset~ing ~he phase counters 406-412 every 16 cycles of carrier rather than every 64 cycles of c~r-rier. Also, the input to the Johnson counter Ulll, U112 is stepped up by a factor of 4 so tha~ all of ~ ~J~
~9 51930 the strobe signals (Fig. 37) develo~ed in the output of this counter, which repeat at a l/6th ~it rate, are increased by a factor of 4. More particularly, when the BAUD0 pin 2 of the device 80 is grounded a low signal is coupled through the inverters U24 and U49 to contrcl the switch U122 so that the outpuS of the stage U10~ in the ripple counter U106-UllO is supplied to the Johnson counter U111~ U112 through ~he swi~ch U12~. At the same time this signal con-trols the switches ~123, U124, U125 and U125 (Fig.
19) to delete the first two stages of e~ch of the phase counters 406-412 f~om their respective counting chains so that theqe counters now have only to count up to 12 during a 15 carrier cycle bit interval in lS order to indicate a valid 1/6th ~it pulse on the ou~-put line thereof. However, all of th* dig~tal circuitry, descri~ed in detail heretofore in connec-tion with the operation of the demodulator 150 at a 300 ~aud rate, continues to function in the same man-ner for input data received at a 1200 ~aud rate whenthe baud zero terminal is grounded. Also, all of the other circuitry of the di~ital IC 80, which has ~een described gene~ally heretofore, functions prope~ly to receive messages from the networ~ and transmit mes-sages to the networ~ at the increased ~aud rate of1200 baud by simply grounding the BAUD0 pin 2 of the device 80.
As discussed generally heretofore, tne digiSal IC 80 may also be pin configured to accept unmodulated ~se band aata dt the extremely high ~aud rat~ of 38.4K baud. To accomplish this the baud 1 pin 7 of the device 80 is grounded so that ~he output of the inverter U12 (Fig. 18), which is identified as TEST in the detailed schematic, goes high. When this occurs the ~witch U12~ i5 switched to its A input so that the 921.6~Hz signal from ehe John~on counter U102, U103 is applled directly to the input of the 3Ohnson counter Ulll, U112. This later Johnson coun-ter thus operates to produce the above descri~ed ~trobe pulses at a frequency of 6 times the ba~d rate of 38~4k~zo At the same time the carrier confirma-tion circuits 402, 404 and the p~ase counters 406-412 are bypassed ~y supplying the B,aud 1 signal to the switch U12Y so that this switch is thrown to the B
position in which the RX input is supplied direcely to the D input of the flip flop U~5. All of the start bit detection and framing logic descriDed in detail heretofore in connection with the operaeion of the demodulator 150 at a 300 baud rat~, will now function at the 38.4k baud rate.
When the device ~0 i5 operated at a 3~.4k ~aud rate tne ~aud 1 signal line is also used to con-trol the switch U761 (Fig. 25) so that the QN output of ~he transmit flip flop U640 is supplied to the TX
output pin 10 of the device 80 through the inver~ers U733, U740 and U745. Accordingly, all of the digital circuitry in the device ~0 is capaDle of receiving messages from a low nolse environment, such as a fiber optic ca~le,-executing all of the instructions heretofore de~cribed including interfaclng with an associated microcomputer, ~and transmi~ting messages ~ac~ to the networX all at the elevated ~aud rate of 38.4k baud~

Considering now in more detail the serial shift register 152, this regis~er comprises the seri-ally connected stages U536, U537, U535, U515-51~, U533, U534, U529-532, U521, U500, U501, U53B, U$22, U523, U526, U524, U525, U527, U52~ and U641 tFigs.
26-29). A~ discussed generally heretofore the stage U528 stores the control bit of the reeeived mes~age and the 3~age U641 ~tores a logic "1" for the two start bit~ of the received message. The ~emodulated da~a of the received message is transmitted through ~.z~

the switch U75Y, the NAND gate U6~2 and the inverter U730 to the D input of the first stage U536 of the reglster 152, this input ~eing identified as BUFDATA.
The BSHFCL~ pulses developed in the demodulator 150 are supplied as one input to a NAND gate U6Y7 (Fig.
29). The other two inputs of ~he N~ND gate U69~ are the TXSTBA line and thP GT26N line both o which are high at the beginning of a received message. Accor-dingly, the B~HFCLK pulses are inverted in the inver-ter U727 and appear on the ENSHF line which is sup-plied through the switch U760 (Fig. 26~ and the in-ver~ers U540, U543, U544 and U545 to the BU~CK ClocK
line of the register 152 and through the inverter U546 to the BUFCKN line, these lines forming the main cloc~ lines of the register 152. The regiseer 152 is reset from the internal reset line INTRES through the inverters 734 and 575 (Fig. 27). The manner in which data may be read out of the register 152 ~y an asso-ciated microcomputer or loaded into this register by a microcomputer has been descri~ed heretofore in con-nection with Fig. 14.
A~lec~ 3e~o~
Referring now to the detailed circuitry of the addre~s decoder 164, this decoder comprises the exclusive OR gate U57~-U5~ (Figs~ 27 and 2~) which compare the outputs of 12 stages of the register 152 with the 12 address pins A0-All, the A0 pin ~eing compared with the output of the 16th stage U500 and the output of address pin All Delng compared with the output of tne fifth tage U516 of the register 152.
The exclusive OR gate outputs are com~ined in the NOR
gates U595, U5Y3, USY5 and USY2, the output~ of which are further combined in the four input NAND gate U636 (Fig. 2~. If bits Bll-B22 of the receiYed message, which are ~tored in ~he indicated stag~s of the re-gister 152 all compare equally with ~he 3et~1ng of the address select switches 120 (Fig. 10) which are connected to the address pins A0-All, the output of the NA~D gate U636 goes low, as indicated ~y the ADDECN ou~put line of ~his gate.

Considering now in more detail the instruc-tion decoder 166, the Q and QN outputs of the regis-ter stages U5~7, U525 and U524 (Fiy. 2~, are coupled through inverters to a series of NAND gates U691, U6Y0, U6 Y, U6~8, U639, U63~ and U637 (~ig. 30) the outputs of which provide the decoded in~truction. de-scribed in detail heretofore in connection with Fig.
3.
The manner in which a shed load instruction is carried out has been described in detail hereto-fore ln connection with Fig. 12. However, lt is pointed out that the SHE~N output of the lns~ruction decoder 166 is supplied as one input to a 3 lnput NAND gate U698. The other two inputs of this NAND
gate are the SCRAMN .instruction and the bloc~ shed instruction BLSHEDN. Accordingly, when ei~her of these other two instructions are developed they are combined with the execute function in the NAND gate U649 and set the Yhed load latch U651 and U692.
As discueeed generally heretofore, the central controller ~can issue ~lock shed or bloc~
restore in~tructions in response to which a group of sixteen stand alone.slaves will simultaneously shed or restore their loads. More particularly, when a bloc~
~hed instruction is decoded the ~LSHEDN line goes low and when a bloc~ réstore instruction is decoded the BLRESN line goe~ low~ These lines are inputted to a NAND gate U752 whose output i5 high when either of these instruction i5 decoded. The output of U752 is supplied as one input to the NOR gate U634 the other input of which is the output of U592 corresponding to the four LS8'~ of the addreqs decoder 164. The NOR
gate U63~ thus produces a zero even though the four LSB's of the decoded address do not correspond to the addres a~signed to these stand alone slaves. The output of U634 is inverted in U566 and provides a one to U63~ so tha~ the ADDOK qoes high and a Rhed load or restore load operation is performed in all sixteen stand alone slaves~
With regard to the ena~le interface in-struction EINTN, this signal is inverted in the in-verter U699 and com~ined with the execute function in the NAND gate U652 so as to set the enaDle interface latch U654 and U693. As discus~ed generally hereto fore, when the device 80 is in the expanded ~lave mode and an enable inter~ace instruction i8 received this device esta~Lishes the a~ove descri~ed interface iS with the microcompu~er ~4 which i5 maintained until a disable ineerface in.qtruction is supplied rom the master which re~ets the enaDle interface latch U654, U693. More particularly, a disaDle interface in-struction DINTN is inverted in the inverter U700 (Fig. 2Y) and supplied through the NAND gates U633 and U680 to re~et the latch 654, 693.
It is also possi~le for the master to dis-a~le the interface indirectly and without requiring the master to send a disa~le i~terface instruction to the device 80 which has already esta~lished an inter-face. More particularly, the master can accomplish the disabl$ng of the interface implici~ly ~y trans-mit~ing a me~sage on the network which i5 addressed to a digital IC at a dif ferent remote st~tion, t~is mefisag~ including ~a c~ntrol ~it which i set. When this occurQ~ ~oth devices will receive the message transmitted ~y the master. However, the device ~0 which has alrea~y established an inter~ace, will recogni~e that ehe address of the received message is not his own, in which caYe the ADDOK line (Flg. 2~) will ~e low. This signal i inverted in the inverter U564 so a to provide a high on one input of the NAND

gate U681~ When the execute sttobe signal EXSTB goes high the other input of the NAND gate U681 will be ~k high so tha~ a low is supplied to the other inpu~ of the NAND gate U680 which resets the latch U654, U693 in the same manner as would a disable interface in-struction. When ~he ADDOK line is low, the NAND gate U812 is not ena~led so that no F:XECUTE instruction is produced in response to the message addre.qsed to a different digital IC ~0. The ena~le interface latch is also reset when power is applied to the device ~0 over the PONN line.
Considering now the logic circuits 170 ~Fig. 12) employed. to provide the EX~CUTE ~ignal, wnen the ADDECN line goes low it pa ses through the lS NAND gate U~10 to .one input of the NAND gate U#12.
It ~ e recalled from the previous g~neral de-scription that if the control ~it register 52~ is set, the BCH comparator indicates no error in tran~-mission by producing a high on the BCHOK line, and the end of a word is reached, all three lines EOW, CONTROL, and ~CHOK are hlgh. These three signals are inputted to a NAND gate U74~ (Fig. 32~ and pass through the NOR gate U604 so as to provide a hlgh on the execute strobe line EXSTB. This line is supplied through the inverter U1005 (Fig. 29) and the NOR gate U1006 to the other inpu~ of the NAN~ gate U812 the output of which is inverted in the inverter U735 to provide a high on the EXECUTE line.
A~ discussed generally neretofore, the expande~ mode slave device ~0 will not disa~le the interface to the associated microcomputer 84 in re~ponse to a received message with a different address, if a BCH error i9 indica~ed ln the received message. This restriction is established ~ecause the received message might have ~een intended for the e~panded mode slave but the controL bit wa~ garbled into a nl~ by a noise impulse. More particularly, if a ~.~ 7 ~

BCH error is noted in the received message the BCHO~
line will not go high and no high will be produced on the EXST~ lineO Accordingly; even though the ADDOK
line i~ low the NAND ga~e U68:L will not produce an output and the ena~le interface latch U654 and U693 rem~ins set so that ~he interface is not disahled.

Considering now in more detail the message bit counter 160, this counter comprises the six ripple counter stages U503 and U510-U514 (Fig. 31) which are clocked by the B5HFCLK pulse~ develo2ed by the demodulator 150. As descri~ed generally here~o-fore, the mes age bit counter 160 counts these pulses rom the demodulator 150 and when a count of 32 ls reached provides an output on the EOW line which is the Q output of the .last stage U514. The counter 160 also provides a strobe pulse for the status latch at a count of 15 and provides both positive and negative GT26 and GT26N signals upon a count of 26.
Considering first the manner in which the ~15u stro~e is pro~uced, the Q outputs of the first and third stages 50~ and 511 are com~ined in the NAND
gate U869 and the 4 outputs of the second and fourth stages are com~ined in thP NAND gate U~70, the out-puts of these two ga~es ~eing AND~D in tne MOR gate U871 to provide an output on the FIFTEEN line when the indicated stageS of the counter 160 are all high~
Con~idering how the GT26 signals are devel-oped, the 9 outputs of the second stage V510, the fourth stage U512, and the fiftn stage U513 are com-bined in the NAND gate U696 so that on a count of 26 this gate produces an output which goes to the NOR
gate U747. The second input to the NOR gate U747 is a Com~inatiQn o~ the Q outputq of s~ages U503 and U511, which must both ~e zero for a valid count of 26, in the ~OR gate U630. The third input to the NOR
gate U742 is the BSHFCLK pulse which, after ~ count ~27~ 3 of 26 in the counter 660 sets a latcn comprising the NOR gates U631 and U632. When this latch is set the ~T26 line goes high and the GT26N lines goes low.
It will ~e recalled from the previous gen-eral description that the message bit counter 160 isemployed during both ~he recep~ion of a message and the transmission of a message to count ehe bit inter-vals to determine t~he end of a word. However, when the de~ice ~0 is neither receiving a message or transmitting a message this counter should be reset.
Also, it will ~e recalled from ~he previou~ general escription that the BUSYN output pin 8 of the device 80 goes low when the device 80 is either receivlng a message or transmitting a message to inform the in-terfaced microcomputer of ~his condition. Consider-ing first the manner in which the BUSYN output is produced, when tne device ~0 is receiving a word the ~XWDETN line is low and when the device ~0 transmit-ting a message the TXONN line is low. These lines are ORed in ~he NAND gate U671 the output of which is supplied over the ~USYN line and through the B eermi-nal of the switch U~53 (Fig. 32), and the inverters U70~, U741 and U746 (Fig. 33) to the BUSYN pin 8 of the device 80. Accordingly, a negative signal is produced on pin 8 when the device 80 is either re-ceiving or tran~mitting a message.
Considering now the manner in which tne message bit counter 160 is reset, it will be recalled from tne previous general descrip~ion of FIG. 13 that during a transmit message a TXSTBA signal is produced by the one blt delay flip flop U646 so as to provide a two ~it interval wide Start pulse at the ~eqinning o~ the message while proYiding only a count sf 1 for ~oth start bits. Accordingly, it is nece~sary to hold the message ~it counter 160 reset during the time period of ~he firs~ start ~it. Thi~ 1~ accom-plished ~y the TXSTBA signal which is suppliea as one ;1~5463 input to a NAND gate U6~5 ana is low auring the ~irst s~art ~it. The other two inputs of the NAND gate U695 ~re the power PONN signal which resets the mes-sage bit counter 160 when power is applied ~o the device 80 but is otherwise normally high~ and the ~USYN line which is high whenever a message is being either received or transmitted i.e. a perioa when the counter 160 should count the bits of the message.
Accordingly, aftec the first transmitted start ~it the TXSTBA line goes nigh and the reset is released on the counter 160.

Considering now the BCH computer 154 in more detail, this computer is in tructed ~ased on '~he polynomial x5~x2+1 an~ hence comprises the five stage shif t register U505~U509 ~Fig. 32~, as will ~e readi-ly understood by those s~illed in the art. In this connection, reference may ~e had to the ~ook Error Correcting Codes ~y Peterson and Weldon, MIT Ptess ~nd. Ed. lY~2, for a detailed description of the func-tioning and instruction of a ~CH error correcting code. The shift register s~ages U505-U509 are cloc~-ed by the BS~FCLK pulses developed by the demodulator 150 which are applied to one input of the NAND qate U672 the other input of which is the TXSTBA signal - which is high except during the first start ~it of a transmi~ted me-qsage. The output o~ the NAND gate U672 is inverted in the inverter U711 eo provide clock pulses for the BCN shift register U5~5-U503.
The demo~ulated data of the received mes-Qase is sup-plied through the switch U75~ (Fig. 31) and the NAND
gate U673 (Fig~ 32) an~ the inverter U712 to one in-put of an exclu~ive OR gate U577 the output of which is connectea to the D input of the first stage U505.
The other input of the exclusive OR gate U577 is the output of a NOR ga~e U603 having the GT26 line a~ one input and the yN output of the last s~age U50g as the 98 ~5~6~ 51930 other input. During the first 26 message ~it the NOR
gate U~03 and exclusive OR gate U57~ act as a recir-culating input from t~e output to the input o~ the computer 154. Also the D input of the first stage 505 and the Q output of tne second stage U506 provide inputs to an exclusive OR gate U590 the output of whi~h is connected to the D input of the third stage U507. Accordingly, during the recep~ion of the first 26 message ~its the computer 154 computes a five ~it BCH error code which is stored in the stages 'J505-U509. The stages U505-509 of the BCH error code com-puter are reset concurrently with the message bit counter 160 by the output of the inverter U~31.

It will be recalled from the previous gen-eral description that following reception of the 25 message ~its the BCH error code computed in computer 154 i~ compared with the error code appearing as the me~sage ~its B27-B31 of the received message in the BCH comparator 162. More particularly, the Q output of the last stage U509 is one input of an exclusive OR gate U5~1 (Fig. 32) the other input of which is the DEMOD data from the output of the switch U758.
As soon as the GT26 line goes high at the end of 26 mesqage ~ies the NOR gate U60~ bloc~s tne recircula--- tion connection from the QN output of stage 509 to the exclusive OR gate U577. The gate U603 thus func-tions as the switch 158 in Fig. 12. At the same time the GT26 line is inverted in the inverter U713 and supplied as the second input to the NAND gate U673 so as to remove DEMOD data from the input to the compu-ter 154. The gaee U673 thu~ performs the function of the switch 156 in Fig. 12. Accordingly, u~sequent BSHFCLK pulses wili act to shift the BCH error code stored in the register U505-509 sut of this register for a bi~ by bit comparison in the exclusive ~OR gate U591. The output of-this NOR gate is supplied as one ~Z.~59~3 input to a NAND gate U755 (Fig. 33) the other input o~ whlch is the QN output of a BCHOK flip flop U520.
The flip flop U520 is held reset during transmission by ~he TXONN line which is one input to a NAND gate U750 the o~tput of which is connecte~ to the reset terminal of U520. U520 is also reset through the other input of U750 when ~he co~nters 160 and 154 are reset. The flip-flop U520 is cloc~ed ~y BSHFCLK
pulses through the NAND gate U676 (FigO 32) only after the GT26 line goes high at the end of tne 26th message bit. When ~he flip flop U520 is reset its gN
output is a one which is supplied to the NAND gate U755. When the two inputs to the exclusive NOR ga~e USYl agree this gate produces a one so that ~he outp~t of U753 is a 2ero to the D input of U520 so that lts QN output remains high. If all five ~its of the tws BCH error codes agree the QN outp~t of U520 remains high to provide a high on the BCHOK line.
If the two inputs to U5~1 do not agree, say on a comparison of the second bit in each code, the output of U591 will be a zero and the output of U755 will be a one which is cloc~ed into the flip flop U520 on the next BSCHFC~K pulse. This cau~es the QN
output of U520 to go low which is fed bac~ to U755 to cause U755 ~o ptoduce a one at~its output regardless of the other input from the exclusive NOR gate U5~1.
Accordingly, even though the third, fourth and fifeh ~lts compare equally and the gate U591 produces a one for these comparisons, the flip flop U520 will remain with a one on its D input S9 that the QN input of U520 will be low at the end of the five bit comparison and indicate an error in the receivea message.
Status Control 176 Considering now in more detail the manner in which the status signals on pins 26 and 23 ~STATl and STAT2) are added to a reply message transmitted ~ac~ to the central controller as ~its 25 and 26, it will be recalLed from the preceding general descrip-tion that a period of time equal to fifteen bits is allowed ~or the controlled relay contacts to settle ~efore the status o~ these con~acts is set in~o the register 152. More particl~larly, when fifteen bits of data have ~een shifted ou~ of the register 152 during a transmitted reply messaga, the data pre-viously stored in stage U535 has ~een shifted beyond the s~ages U500 and U501 and hence these stages may be set in accordance with the signals on STATl and STAT2. The STATl signal is supplied to one input of a NAND gate U820 (Fig . 2~) the output of which ~etq stage US00 and through the inverter U825 to one lnput of a NAND gate U~21 the output of which resets the stage U500. Also, the STAT2 signal is applied to one inpu~ of a NAND gate U822 the output of which sets the stage U501 and through the inverter U~26 to one input of a NAND gate U823 the output o~ which resets the stage U501.
It will ~e recalled from the previous des-cription of the message bit counter 160 that after this counter has counted to 15 the output of ~he NOR
gate U871 goes high. This signal is supplied as one input to a NAND gate U6~5 (Fig. 23J the other input of which is the DSHFCLK pulses so that the ou~put of the NAND gate U685 goes low near the end of the bit in-terval after a count of 15 is reached in the counter 160. A~suming that the sta~us la~ch U662 and U663 has been set in response to a reply instruction, as descri~ed previously in csnnection with FIG. 13, the two inputs to the NOR gate U599 will be zero 80 tha~
a 1 is produced on tne output of this gate which is supplied as one input to ehe NOR gate U678 (Fi9. 29) the other input of which is the INTRES line. The output 3f ~he NOR gate U67~ is inYerted in the inver-ter U570, whio~ is supplied to the other input of all four of the NAND gates V~20-U823. Accordingly, in response to the FIFTEEN signal the stages U500 and U~01 are set or reset in accordance with the signals on the STATl and STAT2 lines.
T~5L
As discussed generally heretofore, a digital IC 80 may be pin configured to operate in a test mode in which the outputs of the digital demodu-lator 150 are ~rought out to dual purpose pins of the device 80 so that test equipment can ~e connec~ed there~o. More particularly, the digital IC ~0 is pin configured to operate in a test mode by leaYing both the mode 1 and mode 0 pins ungrounded so that they ~oth have a ~1~ input due to the internal pull up re-sistors within the device 80~ The ~1~ on the mode 1 Line is supplied as one input to the NAND gaee U838 (Fig. 18) and the 1 on the mode 0 pin 27 is inYerted in the inverters U~27 and U~2~ and applied as the other input of the NAND gate U838 the output of which goes low and is inverted in tne inverter U~46 so that the OIN line is high in the test mode. The OIN line controls a series of 3 tristate output circuits U~55, U~56 and U~57 (Fig. 26) connectea rsspectively to ~he address pins All, A10, and A~. The RXWDETN output line of the demodulator 150 is spuplied througn tne inverter U831 to the input of the tristate output circuit U855. The ~EMOD output of the demodulator 150 is supplieà through the inverter 830 to the input of the tristate U856 and the B5HFCLK pulse line from the demodulator 150 is supplied through the inverter U829 to the input of the tristate U~57. The OIN line also control3 the All, A10 and A9 addres~ lines so that these lines are set at "1" during the test oper-ation and hence the signal~ supplied to the dual pur-pose add~es~ pins P21 22, and 23 during test will not interfere in the address decoder portion of the device 80.

The portlon of the digital IC 80 beyond the demodulator 150 can be tested at the 38.4k ~aud rate by applying a test message to the RX pin 6 at 33.4k ~aud. This message may, for e!xample, test the re-sponse of the device dO to a message including a shed load command and the COUT output line can be chec~ed to see if the proper response occur3. This portion of the digital IC 80 may thus ~e tested in les-~ than millisecond due to the ~act that the 38 . 4 ~ ~aud rate is utilized. In this connection ie will be noted that the baud 1 pin 7 of the device 80 grounded Eor the test mode so ~hat the switch U12Y
(Fig. 20) bypasses the digital demodulator 150.
Also, this TEST signal controls the switch U761 (Fig.
25) so that the TX out pin 10 is connected direc~ly to the QN ou~put of the transmit flip flop U640, as in the 3~.4k ~aud rate transmit and receive mode.
The digital de~odulator 150 of the dev~ce 80 may be tested ~y con~iguring the ~aud O and ~aud 1 pins for the desired baud rate of either 300 or 1200 and supplying a test message at that baud ra~e to the RX input pin 6 of the device 80. rl'he DEMOD, RXWDETN
signal and the BSCBFCLR pulses which are produced ~y the demodula~or 150 may be chec~ed by examining the dual function pins 21, 22 and 23 of the device 80.

A8 discussed generally heretofore, the di-gital IC 80 is designed so that whenever +5V is ap-plied to the Vdd pin 28 of the device 80 the COUT
line i~ pulled high even though no message i sent ~o the device to restore load. This feature can ~e em-ployed ~o provide local override capa~ility as shown in FIG. 39. Referring to ~hi~ figure, a wall switch 440 is ~hown connected in series with a la~p 442 and a set of normally closed relay contact~ 444 across the 115 AC line 446. A digital IC 80 which i~ oper-ated in the s~and alone slave mode i5 arranged to ~2t~5~3 control the relay contacts 444 in response to mes-5ag@~ received over the power line 446 from a central contsoller. More particularly, the COUT line of the digital IC 80 is connected to the gate electro~e of an FET ~48, the drain of whicn is connected ~o ground and the source of which is connected through a resis-tor 45~ to the +5v. supply output of the coupling networ~ 90. 1 The source of the FET 448 is also con-nected to tne gate electrode of a second FET 452 the drain of which is connected to ground and the source of wnich is connected to a reLay coil 454 which controls the relay contacts 444, the upper end of the relay winding 454 Deing also connected to the +5v.
supply.
The coupling network 90 shown in FIG. 39 is substantially identical to the coupling network ~hown in detail in FIGS. 16 except for the ~act that AC power for the coupling network 90, and specifically the rectifier 244 thereof, is con-nected to the bottom contact of the wall switch 440 so that when the wall switch 440 is open no AC power is supplied to tne coupling networK ~0 and hence no plus five volts is developed by the regulated five volt supply 258 (Fig. 16) in the coupling netwOrK ~0.
In thi connection it will be understood that the portions of the coupling network ~0 not shown in Fig.
39 are identical to tne corresponding por~ion of this net~or~ in Fig. 16.
In operdtion, the relay contacts 444 are normally closed wnen the relay coil 4S4 is not energized and the wall switch 440 controls the lamp 442 in a conventional ~anner. During periods when the wall switch is closed and the la~p 442 is energized AC power is supplied to ~he coupling net-work 90 o that it is capa~le of receiving a mes~age over the power line 446 and supplying tnis me sage ~o the RX input ~erminal of the digital IC 80. Accord-5~i3 10~ 519~0 ingly, if the central controller wishes to turn off the lamp 442 in accordance witll a predeteEmined load schedule, it transmits a shed lsaa message over the power line 446 which is received ~y the digital IC ~0 and tnis device responds to the shed loaa instruction by pulling the COUT line low. The FET 448 is thus cut off so that the gate electrode of the FET 452 goes high and the FET 452 is ren~ered conductive so that the relay coil 454 is ene~gized and the contacts 444 are opened in accordance with the shed load instruction. However, a local override function may ~e performed ~y a person in the vicinity of the wall switch 440 ~y simply opening this wall switch and then closing it again. When the wall switch 440 is opened AC power is removed from the coupling networ~
and the +5v. power 5upply in thi~ network ceases to provide 5 volt power to the digital IC 80.
Also, power is removed from the FET's 448 and 452 so that the relay coil 454 is deenergized so that the normally closed relay contacts 444 are closed. When the wall switch 440 is again closed five volts is developed by the supply in the co~lpling networ~ Y0 and supplied to pin 2~ of the digital IC 80 which responds ~y powering up with the COUT line high.
When this occurs the FET 44~ is rendered conductive and current through the resistor 4 50 holds the FET
452 off ~o that the relay 454 remains deenergized and the contacts 444 remain closed. If the digital IC ao powered up with the COUT line low then the relay coil 454 would be energized on power up and would open the contacts 444, thus preventing the local override feature. It will thus be seen that when power is re-moved from a particular area which includes the lamp 442, in accordance with a preprogrammed lighting schedule, the shed load ins~ruceion from the central controller can ~e overriden ~y a per~on in the room in which the lamp 442 is loca~ed by 5imply opening 105 ~2~463 51930 the wall switch 440 and then closing it again. This local override function is accomplished substantially i~mediately and without requiring tne digital IC ~0 ~o transmit a message back to the c2ntral control-ler and having the central controller send hack amessage to the digi~al IC 80 t:o restore load. In prior art systems such as ~hown in ~he aDove mention-ed prior ar~ patents No~. 4,367,414 and 4,396,844, local override is accomplished only by having the re-mote device send a request for load to the cen~ralcontroller which request is detected ~y polling all of the remote devices, tne central controller then sending back a message to thak particular re~ote station to restore loaa. Such a process take-~ many seconds during which time the per~onnel located in the room in which the lamp 442 has been turned off are in ~he dar~.
The coupling network 90, the digital IC ~0.
the FET's 448, 452 and the relay 454 may all be 20 mounted on a small card which can ~e directly associ-ated with the wall switch 440 qo as to provide an ex-tremely imple and low cost address&~le relay sta~ion wi~h local override capa~ility.

In Figs. 40 and 4~ tnere is shown a series of timing diagramc which illustrate the time required to accomplisb various functions within tne dlgl~al IC 80. In the ac~ompanying Figs. 41 and 43, the time required to accomplish these functions at each of the baud rates at which the digital IC 80 is arranged to operate are al~o givenO All time interval~ given in Figs. 41 and 43 are maximum values unless otherwise indicatsd. Referring to Fig. 40, the timing diagrams in this Fig. relate to the operation of the digital IC ~0 when in a stand alone ~lave mode. Thu~, ~$9. 40(a~ ~hows ~he l~ngth of a received network message ~TM~ and also how3 the 1~7S463 delay between the end of the received message and a ch~nge. in potential on the COUT output line of the di~ital IC 80 (~ig. 40b). Fig. 40(c) illustrates the additional delay TR which is experienced between the time the COU~ line is changed and the start of a transmitted mesRage when a reply is requested ~y the central controller. This Fig. also shows the length of time TST from the start of the tran-~mitted reply message to the time at which the signals on the STATl and STAT2 lines are stro~ed into the serial shift register of the digital IC 80~ Figure 40(d~
shows the reset pulse which is either developed in-~ernally within the device 80 ~y the Schmidt trigger U130 (Fiq. 18) or may be sent to the device 80 from an external controlling device, this pulse having a minimum width o~ 50 nanoseconds for all three baud rates. A comparison of Figs. 40(~) and 40(d) also shows the time (TCR) required to reset the COUT out~
put line in response to the reset pulse shown in Fig.
40(d).
Referring now to FIG. 42, this figure ~hows the various timing diagrams in connection with the digital IC 80 when operated in an expanded moae in setting up the interface with an associate~ microcom-puter and in reading data from the serial shift reg-ister of the device 80 and loading data into this register. In FIG. 42(a) the time delay ~etween the receipt of a m~ssage from the central controller and the time the BUSYN line goes low ~Fig. 42(~)), which i~ iden~ified as the delay TBD, is shown. The time fro~ the end of a received me~sage to the time the BUSYN line is brought high again is shown by the in-terval TIBD, when comparing Figs. 42(a) and (b).
Also, this same delay is produced in developing an interrupt pulse on the INT line, as shown in FIG.
42(c).

S~i3 A comparison of FIGS . 42 ~a1 and 42 (f ) shows .~
the time TDM between the end of a received message ~k and the time data i~ available on the DATA pin of the digital IC 80. A comparison of Figs. 42(c) and (e) shows the time delay TIRST between the leading edge o the first serial clock pulse produced on the SCK
line ~y the microcomputer and the time at which the device 80 causes the INT line to go low.
Figure 42le) shows the width TSCR of the serial clock pulses supplied to the SCR line ~y the microcomputer, these pulseq having a minimum width of 100 nanoseconds for all baud rateC. A compari~on of Figs. 42(e) and 42(f) show~ the maximum timo TSD
availa~le to the microcomputer to apply an SCK pulse to the SCR line in reading data out of the 3erial shif~ register of the digital IC 80. A compari~on of these Figs. also shows the set up time TWSU required be~ween ~he time the microcomputer puts data on th~
DATA line and the time when the microcompute~ can thereafter cloc~ the SCK line reliably. Ac shown in Fig. 43 this time is a minimum of 50 nanoseconds for all three ~aud rates. A comparison of Figs. 42(d) and tg) show the time TT required after the RW line is pulled higb after it has ~een low for the digital IC 80 to start transmitting a message onto the net-work. A compariqon of Figs. 42(b) and (d) shows the ti~e TBT required ~etween the time the RW line is pulled high and the time tbe digital IC 80 responds by pulling the ~USYN line low.
Obviou~ly, many modifications and varia-tion~ of the present invention are po sible in light of ~he above teachings. Thu-~ it is to ~e understood that, within the scope of the appended claims, the invention may be practiced otherwi e than as speci-fically described hereinabove.

Claims

108 51,930 WE CLAIM
1. In a communication and control network, the combination of a digital integrated circuit device coupled to a common network line and adapted to store plural bit messages transmitted over said line, said device having first and second control output terminals, a variable interval timer external to said device having a reset terminal connected to said first control terminal and a clock inhibit terminal connected to said second control terminal, a controlled element external to said device and connected to said second control terminal, said variable timer having a decode output which is low when said timer is reset and is connected to an input terminal of said device, means in said device and responsive to the reception of a message which includes a shed load instruction for pulling both said first and second control output terminals low, thereby to cause said controlled device to shed load and said timer to start counting, said decode output of said timer going high a predetermined time interval after starting said counting, and means in said device and responsive to a high on said input terminal for pulling said second control output terminal high, thereby causing said controlled element to restore load at the end of said predetermined interval.

2. The combination of claim 1, including means for adjusting said predetermined time interval.

3. The combination of claim 1, wherein said timer has a plurality of inputs which may be selectively grounded to vary said predetermined time interval.

9 51,930L

4. The combination of claim 1 , wherein said device is operable in an expanded mode to establish an interface to an associated microcomputer in response to the reception of a message which includes an enable interface instruction, and means utilizing said first and second control output terminals as a part of said interface in said expanded mode.

5. The combination of claim 4, wherein said input terminal of said device also forms part of said interface in said expanded mode.