CA1274293A - Multipurpose digital ic for communication and control network - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A low cost, multipurpose digital IC is used as the basic building block in establishing a network communication system over a desired communication link. The digital IC can function as an addressable microcomputer interface between the network line and a remotely located microcomputer which may, for ex-ample, comprise any microprocessor based controlled product. In such mode, the digital IC's function is to take data from the network and pass it on to the remotely located microcomputer upon command from the central controller and to transmit data from the microcomputer to the central controller. The digital IC may also function as a nonaddressable microcomput-er interface between the central or master controller and the network line. In such case the digital IC's function is to continuously take data from the cen-tral controller and place it on the network and take data from the network and pass it back to the central controller. The digital IC may also function as an addressable load controller associated with an indi-vidual remote controlled device and responding to shed or restore load commands from the central con-troller over the network line. When so used the di-gital IC may also be commanded to transmit a reply message back to the central controller giving infor-mation as to the status of the controlled device, thus enabling the central controller to monitor a large number of remotely located controllable de-vices.

Description

`` 3L~74~

1 51,930 MULTIPURPOSE DIGITAL IC FOR
COMMUNICATION AND CONTRQL NETWORK

- CROSS REFERENCE TO RELATED APPLICATIONS

The invention disclossd herein relates to two-way communication and control systems. Canadian patent :: application number 484,817 filed June 21, 19~5, entitled "Digital MessagQ Format for Two-Way Gommunication and Control Network", inventors Leonard C. Vercellotti, : William R. Verbanets Jr. and Theodora H. York, relates to such communication and control systems.

BACKGROUND OF THE_INVENTION

A. Field of the Invcntion The presant invention rslates gsnerally to information communication networks and, more particularly, to communication networks by means of which a large number oF remotely positioned controllable : devices, such as circuit breakers, motor overload relays, lighting systems, and the like, may bs controlled from a 742~33

2 51,g30 central or master controller over a common network line which may comprise either the exi~ting AC power 1ines, or a dedicated twisted pair line, or in some instances a ~iber optlc cable.
The invention particularly relates to a low cost, multipurpose digital IC which can be used as the basic building block in establishing a network communication system over a desired communication link.
The digital IC can function els an addressable microcomputer interface between the network line and a remotely located microcomputer which may, for example, comprise any microprocessor based controlled prodwct. In such mode, the digital IC's function is to take data from the network and pass it on to the remotely located 1~ microcomputer upon command from the central controller and to transmit data from t~e microcomputer to the central controller. The digital IC may also function as a nonaddressab7e microcomputer interface between the central or master controller and the network line. In such case the digital IC's function is to continuous1y take data from the central controller and place it on the network and take data from the network and pass it back to the cantral controller. The digital IC may also function as an addressable load controller associated with an individual remote controlled device and responding to shed or rastore load commands from the central controller over the network line. When so used the digital IC may also be commanded to transmit a reply message back to the central controller giving information as to the status of the controlled device, thws enabling the central controller to monitor a large number of remotely located controllable devices~

a. Descri~tion of the Prior Art Various communication and control systems have ~L27~93

3 51,930 been hereto~ore proposed for controlling a group of remotely located devices from a central controller over a common network line. Control systems for controlling distributed electrical loads are shown, for example, in Miller et al's U.S. patents Nos. 4,167,786, issued September 19791 ~ 7 367,414, issued January 1933, and

4,396,844, issued August 1983. In such systems a large number of relatively complex and expensive transceiver-decoder stations, each of which includes a microprocessor, are intsrconnected with a central controller over a common party line consisting of a dedicated twisted pair for bidirectional communication between the central controller and all transceivers.
Each of the transceiver-decoder stations is also of relatively large physical size due to the fact that a substantial amount o~ hardware is required, in addition to the micro-processor, to receive and transmit signals.
Also, both the hardware and microprocessor consume substantial amounts of power. In fact, in Miller et al patent No 47167,786 it is necessary to provide a powersaver mode in which the maior portion of the circuitry at each remote station is de-energized to reduce power consumption during intervals when load changes are not being actuated.
26 Each of the transceiver-decoder stations controls a number of loads which must be individually connected to a particular transceiver by hardwiring, these interconnections being qwite lengthy in many instances. In such a system, all transceivers can initiate messages at any arbitrary time in response to control input from the associated switches. Accordingly, it is not uncommon for two or more transceivers to simultaneously sense a free common party line and begin simultaneous transmission. This requires a special bus arbitration scheme to cause all but one of the ~7~3 4 51,930 interfering transceivers to drop out of operation while permitting one selected transceiver to continue its data transmission. Also, in such a system transmission from the transceiver to the central controller is very limited and consists merely of an indication of a manually operable or condition responsive switch or analog sensors such as a thermistor or other analog ssnsin~ device. In the load diskribution control systern shown in the above re~erenced prior art pakents, the arbitration technique is dependent on the impsdance levels of the active and inactive states of the data line. If the data line becomes stuck in a low impedance state, due to the failure of one of the connected transceiver decoders, further communication over the network line is prevented until the malfunctioning transceiver is physically disconnected ~rom the data line.
In the communication and control system described in the above identified Miller et al patents a ~ message transmitted over the network includes a preamble ; 20 portion of a minimum o~ ~our bits. These preamble bits comprise 60% square waves which ars utilized by the transceiver decoders to permit a phase lock loop circuit in each transceiver to lock onto the received praamble bits. The use o-~ a minimum of four bits to provide phase loop lockon reduces the overall throughput of such a system. Also, in order to capture the preamble bits it is necessary to provide the phase lock loop circuit initially with a relatively wide bandwidth of about 5KHz and then narrow down tha bandwidth after the phase lock 3U loop circuit has locked onto the preamble bits. Such an arrangement requires additional circuitry to accomplish the necessary change in bandwidth. Also, the relatively wide bandwidth nacessary to capture the preamble bits also lets in more noise so that the security and 3S reliability of the system is reduced in noisy environments.

51~3 ~ `~
In the presently described communication network a small low co~t digital I~ is employea which can be readily adapted by merely grounding different input terminals o~ the IC to perform all of the dif-ferent function~ necessary to the component parts of the complete communications network. Tbus, in one pin configuration of the digi~al IC it can function as an addressable load controller, responding to shed or restore load commands from the central controller and replying back to the central controller with status information regarding the ~t~te of the con-trolled load. This mode of functioning of the digi-tal IC is referred ~o as a stand alone slave mode of operation. In the stand alone sl~ve mode the digital IC is arranged to ~e directly associated with ~ach control device i.e. circuit ~reaker, motor control-ler, ligh~ing control, etc. and may, if desired, com-municate with the master controller over the same wires which are used to supply power to the control-led device. This substantially reduces the amount of wiring required to connect a number of controlled de-vices to the common communication ne~work. The cen-tral con~roller may alco issue ~lock shed and ~loc~
restore commands to a group of stand alone slaves to which com~and they will all simultaneously resp~nd.
Also, the central controller may issue a "scræm" com~
mand ~o shed load which causes all stand alone slaves Iwhich may num~er as high as 4,0~5) to simultaneously shed their respective loads.
In another pin conf iguration of the digital IC it can function as an addressa~le microcomputer interface. In this so called expanded slave mode of operation the digital IC provide~ an interface ~e-tween the communica~ion network line and a remotemicrocomputer which may, for example, wish to trans-~L~74~9~3 6 51~30 mit data over the communications network to the cen-tral controller. In the expanded slave mode of the digital IC the micro computer interface is disabled until the central controller enables it ~y sending an enable interface command addressed to the expanded slave. After the microcomputer interface is enaDled the c~ntral con~roller and the remc,te microcomputer can communicate back and forth through the expanded slave digital IC.
The digital IC may also be pin configured to function as a nonaddressa~le microcomputer inter-face, such functioning ~eing referred to as the ex-panded master mode of ~unctioning of tbe diqital IC.
In the expanded master mode the interface with an as-sociated microcomputer is always ena~led and any net-work transmissions that the digital IC receives may be read by the interfaced microcomputer. Also, the in~erfaced microcomputer may transmit data onto the network a~ any time through the expanded master type of digital IC. Accordingly, when the digital IC is operated in this mode the interfaced microcomputer may comprise the cen~ral controller o the communica-tions network.
The digital IC w~ich may be adapted to per-form all of the a~ove described functions, is also arranged so that it can be used with different types of data line Thus, in one pin configuration of the digital IC it is adapted to transmit messages to and receive messages from a networ~ line consisting of 3U tne conventional AC power line of a factory, ofice building or home. Because of the significant phase disturbances associated with such power lines, data is transmitted over the networ~ ~y means of on-off keying of a high frequency carrier. Preferably this high frequency carrier has a frequency of 115.2 ~H2 and the digital IC i5 arranged to transmit data at 7 51~30 the r~te of 30G bit~ per second (300 baud) over con-ventional power lines. The choice of a 115.2 kHz carrier is based on emplrical results of spectrum analy~es of typical power lines and tne 300 baud bit rate is based upon de~ired system per~ormance and ac-c~ptable error rates.
In tne pre3ently descri~ed communication system, the digital IC haY a crystal controlled os-cillator operating at a frequency ma:ny times higher than the carrier frequency. The carrier signal is derived from this crystal osciallator. The crystal oscillator i5 also used as a source of. timing ~ignals within each digital IC to esta~ h predetermined baud rates for the transmi~sion of data over the net-wor~. Accordingly, the frequency of the carrier sig-nal employed to transmit messages over the networ~
can be readily changed to avoid an undesired in~er-fering frequency by simply changing the crystals in the cry~tal oscillator associat~d with ea~h digital IC. Such a change in carrier frequency will also change the baud rates at which the communica~ion system operates, a8 described in more dëtail hereinafter.
The frequency of the crystal oscillator in each digital IC is highly sta~ilized so that the car-rier frequencies developed by the digital IC~s at thecentra} controller and remote stations are very close to the same frequency although a received carrier ignal may drift in phase relative to the timing sig-nals produced in the digital IC which is receiving a 30 message. As a result, it is not necessary to trans-mit a number of preamble ~its and provide a phase lock loop circuit which locks onto the received mes-sage during the preamble bits, as in the a~ove de-scrit:~ed Miller et al patents. In the presently 35 de~cri~ed communicatlon and control system the indivi-dual digital IC:'s operate asynchronOUsly ~ut at su~-~ ~74~

8 ~1930 stantially the ~ame frequency so that any drift in phase does not interfere with detection of the re-ceived carrier signal, even at relatively low baud rates and noisy environments.
In order to provide further noise immunity when using nolsy power lines as the~ common netwoxk data line, the digital IC is arranged to compute a 5 bit BCH error code and transmit it with each message transmitted to the network. Also, each message re-ceived from the network by the digital IC in~ludes a five bit BCH error code section and th~ digital IC
computes a BCH error code Dased on the other digits of the received message and compar~s it with the BC~
error code portion of the receivea message~
In order to provide still further noise immunity when operating over conventional power lines, the digital IC include~ a digital demodulator which bas high noise rejection so that it can detect on-of~ carrier modulation on power lines which have a relatively high noise level. Empirical resul~s show that the digital demodulator portion of the digital IC can receive messages with a ~it error rate o~ less than 1 i~ lU0,000 for power line signal to noise ratios of approximately 6 db at a 300 Hz bandwidtn.
Also, such digital demodulator can receive error free 33 bit mes~ages at a 90% success rate in a power line noise environment of only 4 d~ signal to noise ratio.
When i'c is desired to use a dedicated twi~ted pair line as the c~mmon data line for the communication network, which usually has a lower noise level than power lines~ the digital IC is adap-ted to transmit data to and from ~uch twisted pair line at 4 time~ the data rat2 mentioned above i.e. at 1200 bits per Qecon~ ( 1200 baud) ~ Such adaptation of the digital rc can ~e readily accomplished by simply grounding a di f ferent on~ of the input terminals of the d ig i tal IC .

~L~7~

The digital IC may also be pirl conf igured to accomplish all of the above descriDed functions in a high speed communication network in which the com~
mon data line is a fiber optic cable. In this mode S of operation o~ the digital IC the digital demodulat-or portion is bypa sed and the remaining logic is adapted to receive and tranqmit data messages at the extremely high rate of 38,400 bits pe.c second (38.4 k baud). In such a fiber optic cable co~munication system the data is transmitted as base band data without modulation on a higher frequency carr~er.
The digital IC is arranged to transmit and receive me sages over the common networ~ in a ~peci-fic message format or protocol which permits the es-ta~lishment of ~he a~ove described microcomputer in-terface so that dif ferent microcomputers can communi-cate over the common network while provi~ing maximum security against noise and the improper addressing of individual digital IC's by the master controller.
20 Specifically, the message format consists of a series of 33 bits, the first two bits of which comprise star~c bi~cs having a logic value of- "1". The start bits are followed by a control bit which has a logic value ~1~ when the succeeding 24 message ~its signify 25 the addres~ of the digi~al IC and instructions to be performed by the digital IC. When the control bit has a logic value of n o" the next 24 message bits contain ~ata i~tended for the in~erfaced microcom-pu~er when 'che digi~al IC is operated in an expan~ed 3Q mode, The next f ive message bits contain a BCH error checking code and ~he las~ message bit is a stop ~it whicn always has a logic value of n o~ .
When a 33 ~it message is received by the digital IC the f irst 27 bits thereof are supplied to a BC~ code computer portion of the aigital IC which computes a S bit BCH error code ~ased on the fir~t 27 bit of the received message. The computed BCH code is then compared wi~h the succeeding 5 bit BCH error chec~ing code o~ the received mes~age, on a ~it ~y bit basis, to ensure that the received message has S been received and decoded properly.
In a similar manner when data is to be transmitted onto the network either as a reply mes-sage in the stand alone slave mode, or from the in-terfaced microcomputer to the network through the di-gital IC, the BCH computer portion o:E the digital ICcomputes a 5 ~it error chec~ing code ba~ed on the data to be transmitted and adds the computed 3C~
error checking code at the end of the stored data ~its as the 33 ~it message is ~eing formatted and transmitted out of the digital IC to the communica-tion network. By thus employing BCH ~rror code com-puter logic in the digital IC for both received and transmitted messages, the assurance of transmitting valid, error free 33 bit messages in ~o~h directions on the ne~work is greatly increased.
The digital IC which accomplishes all of these functions is of small size, is readily manufac-tured at low cost on a mass production basis and con-sumes very little power. ~ccordingly, the overall cost of the commu~ication and control system is much less than that of the a~ove described prior art patents while providing all of the addititional fea-tures discussed above. Of particular importance i5 the feature of providing a low cost inter~ace to 3a microprocessors associated with controlled devices, such as circuit ~reakers, motor starters, protectiYe relays and remote load controllers, so that these microprocessors, which are busy with other tasks, can ~e selec~ively interruptea and two-way communication established ~etween ~he central controller and the selected microprocessor at a re~ote station.

~7~93 The inven~ion, both as to its organiza~ion and ~ethod of operation, together with Eurther objects and advantages thereof, will. best be und~r^
S stood by re~erence to the following speci~ication ta~en in connection with the accompanying drawlngs in which:
Fig. 1 is an overall bloc~ diagram of the described communication sy~tem;
Fig. 2 is a diagram of the message bit for-mat employed in the ~ystem of Fig. 1 for a mes~age transmitted from the central controller to a remote station;
Fig. ~ shows the coding of the instruction bits in the message of Fig. 2;
Fig. 4 is a message bit format for a r~ply message transmitted back to the central controller from a remote station;
Fig. 5 is a message ~it ~ormat of a me~sage transmi~ted from the central controll~r to an inter-faced microcomputer Fig. 6 is a diagræm of the pin configura-tion of the digi al IC used in the disclosed sy~tem;
Fig. 7 is a hloc~ diagram illustrating the use of the di~ital IC with a pow~r line at 300 ~aud rate ~ig. ~ is a block diagram showing the u5e of th~ digital IC with a twisted pair line at 1200 ~aud rate;
Fig. 9 is a ~loc~ diagram of the digital IC
u~ed with a fiber optic cable transmission Qy~tem at 38. 4k baud rate;
Fig. 10 is a bloc~ diagr~n showing the use of the digltal IC in a s~and alon~ ~lave mode;
Fig. 11 is a block diagram ~howing a modi-f ica~ion of the system o Fig. 10 in which varia~le time out i~ provided;

1~74~9~

12 61,930 Fig. 12 is a block diagram of the digital IC
in the stand alone slave mode and illustrates the operation in response to a shed load instruction;
Fig. 13 is a block diagram of the cligital IC
5in the stand alone slave mod0 in transmitting a raply messag0 back to the central controller;
Fig. 14 is a block diagram of the digital IC
in an expanded slave mode in responding to an enable interface instruction;
10Fig~ 15 is a flow chart for the microcomputer associated wtth the digital IC in the disclosed system;
Fig. 16 is a detailed schema~ic of the coupling network employed with the digital IC in the disclosed communications system;
15Fig. 1~a is a diagrammatic illustration of the coupling transformer used in the coupling network of Fig.
16;
Fig. 17 is a detailed schematic diagram o~ an alternative coupling network embodiment;
20Figs. 18-33, when arranged in the manner shown in Fig~ 34, (which is located after Fig~re 63~ comprise a detailed schematic diagram of the digital IC used in the disclosed communications system;
Fig. 35 is a block diagram of the dtgital 25demodu7ator used in the digital IC of the disclosed communication system;
Fig. 36 is a timing diagram of the operation of the carrier confirmation portton of the digital demodulator of Fig. 35;
30Fig. 37 is a series of timing waveforms and strobe signals employed in the start bit datection and timing logic of the digital IC of the disclosed communication system;
Fig. 38 is a graph showing the bit error rate 35of the digital demodulator of Fig. 35 IC in different noise environments;

, ~
" "

~7~9~ .

Fig. 39 is a schematic dia~ram of a local override circuit employing the digital IC of the dis-closed communica~ions system;
Fig~ 40 is a series of timing diagrams il-S lustrating the vperation of the digital IC in thestand alone slave mode;
Fig. 41 i3 a chart of the ~espon~e time~ at different baud rates of the ~ignals ~hown in Fig. ~0;
Fig. 42 is a ~eries of ti.ming diagrams of the digital IC in an interface mode wi~h the micro-computer; and Fig. 43 is a chart showing the oper~tlon times of the waveforms in Fi~. 42 at dlfferent baud rates.
~
Referring now to FIG. 1, there i~ sbown a general ~lock diagram of the co~munication ne~cwork wherein a cen~ral controller indicated generally at 76 can transmit messages to and receive m@ssages f rom 20 a large num~er of remote stations over a conventional power line indica~:ed generally at ~8. The ~asic building bloc~ of the communication network i5 a small, low co~t digital IC, indicated generally at 80, which is arranged to be connected to the power line ~ so ~hat it can receive mess~ges from the central controller at 76 and transmit messages to the central controller over this line.
The digital IC 80 is extr~mely versatile and c~n be readily adapted to different modes of 30 op@ration by simply establishing dif ~erent connec-tion~ ~o two of the external pins of this d~vice.
More particularly, as shown at remote tations ~1 and #2 in ~G. 1, the digital IC 80 may be pin conf igured to operate in a~s~and alone ~lave mode in which lt i5 35 arranged to contro~ an as~ociated relay, ~oto~ con-troller or other remote control devlce, indlcated generally at 82, by sending a c~ntrol output signal ~7~

(COUT), to the controlled deviGe 82. In the stand alone ~lave mode, the digital IC 80 can also respond ~o an appropriate command from the central controller 76 by transmitting a messaqe back to the controller 76 over the power line 7~ in which the statu~ of 2 terminals a~socia~ed wlth the controlled device 82, identi~ied as STAT l and STAT 2, are given. Each of the digital IC's 80 is provided with a 12 bit address field so that as many as 4,095 of the device 80 may ~e individually associated with different relays, motor controller~, load management terminals, or other controlled devices at location~3 remote from ~he central controller 76 and can re~pond to hed load or restore load commands transmitted over the power line 7~ by appropriately changing the potential on its COUT line to the controlled device 82.
The digital IC ~0 is al~o arranged so that it can be pin configured to operate in an expanded slave mode as shown at station ~3 in FIG. 1~ In the expanded slave mode the digital IC is arranged to respond to a particular command from the central con-troller 76 ~y esta~lishing an inte~face with an as-sociated microco~puter indicated generally at 84.
More particularly, the expanded slave device 80 re-sponds ~o an enAble int~rface instruction in a mes-sage reo~iYed from the central controller 76 by pro-ducing an lnterrupt signal on the INT line ~o the microcomputer 84 and permitting the microcomputer 84 to rea~ 3erial data out of a buffer shift register in 30 the dig~tal IC 80 over 'che bi-directional DATA line in respon~e to ~erlal clock pulses transmitted over the SCK line frc~a th~ microcomputer 84 to the digital IC 80. The digitaL IC 80 is al~o capable of respond-ing ~o a slgnal on the read wr~ te line ~ rom the 35 microcompu~er 84 ~y load~ng ~erial data into the ~uf-fer ~hif t regi3ter in the devic~ ~0 ~rom ~he DATA
line in coordination with serial cloc~ pulse~ suppli-9~

ed over the SCX line from the microcomputer 84. The digltal IC 80 is then arranged to respond to a change in potential on the RW line by th~ microcomputer ~4 by incorporating the data supplied to it from ~he microcomputer 84 in a 33 ~it message which is format-ted to include all of the protocol of a standard mes-sage transmit~ed ~y the central controller 76. This 33 bit message in the correct format is then trans-mitted by the IC 80 over the power line 78 to the central controller. As a result, the expanded slave devioe ao enables ~i-directional communication and transfer of data between the central controller 76 and the microcompute~ 84 over tbe power line 7~ in response to a specific ena~}e interface in3truction initially transmitted to the expanded ~lave device ~0 from the central controller 76. nce the interface ha~ ~een established between the devices 80 and 84 this interfacr remains in effect until the digital IC
receives a message transmi~ted from the central con-troller 76 which includes a disable interface in struction or the expanded slave device 80 receives 2 message from the central controller which includes a command addressed to a different remote sta~ion. In either case the interface between the network and the microcamput~r 84 is then disabled until another mes-sage i~ transmitted from the cen~ral con~roller to the expanded slave device 80 which includes an ena~le interface in~truc~ion. The expanded slave device 80 al~o Qend~ a busy signal over ~he BUSY~ line to the microcaDputer 84 whenever the device 80 i5 receiving a rnes3age from the network 78 or transmitting a mes-sage to the network 78. The BUSYN signal tells the microcomputer 84 that a message is being placed on the network 78 ~y the central controller 76 even though co~trol of the buffer shif~ register in the ex-panded slave device ~0 has ~een ~h$fted to the ~icro-computer 34.

74~~3 The digital IC ~0 may also be pin configur-ed to operate in an expanded master mode as indicated at station ~4 in FIG. 1. In the expanded master mode the device 80 is permanently interfaced with a micro-computer 86 so that the microcomputer 86 can operateas an alternate controller and can send shed 3nd re-store load messages to any of the st:and alone slaves 80 of the communication networ~. ~'he microcomputer 86 can also establish communication over the power line 78 with the micrcomyuter 84 through the expanded slave IC device 80 at station ~3. To establ~ h c~uch two way communication, the microcomputer 86 merely transmits data to the expanded ma~ter device 80 over the ~idirectional DATA line which data includes the address of the expanded slave device 80 at s~a~tion ~3 and an enable interface instruction. The expanded master ~0 includes this da~a in a 33 ~it meCsage for-matted in accordance with the protocol required by the c~mmunication network and transmits this message over the power line 7~ to ~he expanded slave 80 at station #3. The e~panded slave 8G at ~his station re-spond~ to the ena~le interface instruotion by esta~-lishing the a~ove descri~ed interface with the micro-computer 84 after which the ~idirectional exchange of data ~etween the micrcomputers ~4 and 86 is made pos-sible in the manner described in detail heretofore.
A digital IC 80 which i~ pin configured to operate in th e expanded master mode may also be used a3 an interface between a central control computer 88, which may comprise any microoomputer or main frame computer, which is employed to control the re-mote stations connected to the central controller 76 over the power line 78. Sinoe each of the digital IC' s 80 put out a BUSYN ~ignal to the associated 35 canputer when it i~ either receivinq or tran~mitting a message the present cc~mmunication and control 3y-~em permit~ ~he use of multipl~ ~a~ter~ on the same network~ Thu~, considering the central controller 76 and the alternate controller at station ~4 which is operating in the expanded master mode, each of these ma~ters will ~now when the other is transmitting a message by monitoring his BUSYN line.
It will thus ~e seen that the digital IC 80 is an extremely versatile device which can ~e used as either an addressable load control:Ler with status reply capability in the stand alone slave mode or can ~e used as either an addressable or non addr~able inte~face between the network and a ~icroGoMputer 50 as to enable the ~idirectional tran!3mis~ion of data between any two microcomputer control unitY ~uch as the central controller 76 and the remote stations ~ 3 and ~4.

All communications on the network 78 are asynchronous in nature. The 33 bit mes~age wh.ich the di~ital IC ~0 i5 arranged to either transmit to the network ~ or receive from the networks 7~ is speci-~ically designed to provide maxi~um security and pro-tection against high noise levels on the power line 7~ while at the same time making po~sible the esta~-lishment of interfaces between different microcompu-~ers a~ described heretofore in connection with FIG.1. The 33 bit message has ~he form~t shown in FIG. 2 whereln the 33 bitC ~0-B32 are shown in the manner in which they are stored in the shift register in the digital IC 80 i.e. reading frcm right to left with t~e lea~t ~ignificant ~it on the extreme right. Each 33 bit me~age begins with 2 start ~its B0 and al and end~ with 1 stop bit B32. The s~art bits are defined as logic ones ~1" and the stop bit i9 de~ined a~ a logic ~on. In the disclosed cGmmunication and con-trol sy~em a logic 1 i~ de~ined as carrier presentand a logic 0 is defined as the a~nce of ~arrier for any of the modulated carrier ~aud rates.

~7~ 3 The next bit B2 in the 33 bit msssage is a control bit which d~fines the meaning of the succeed-ing ~es~age bits B3 through B26, which are referred to as ~uÇfer bits. A logic ~1" control bit mean~
that th~ buffer ~its contain an a~dre~s and an in-qtruction for the digital IC 80 when it i~ con~igur-ed to operate in eith~r a stand alone slave moae or an expanded slave mode. A logic "0" control bit B2 mean~ that the buffer bits ~3 through B26 contain data intended for an interfaced microcomputer -~uch as the miceocomputer 84 in FIG. 1.
The next four bit~ B3 B6 af ter the control bit 2 are instruction bits if and only if the pre-ceeding control ~it is a "1~. The in~truction ~it B3 - B6 can ~e decoded to give a number of different instructions to the digital IC 80 when operate~ in a slave mode, either a st~nd alone ~lave mode or an expanded slave mode. The relationship ~etween the in truction ~its B3 - ~6 and the corresponding in-struction is shown in FI~. 3. Referring to thisfigure, when instructions ~its 83, B4 and ~5 are all ~0~ a shed load instruction is indi~ated in which the digital IC 80 rese~q it3 COUT pin, i.e. goes to logic zero in the conYentional ~ense so that the controlled device 82 i5 turned off. An X in ~it positisn B6 means th~t the shed load inctruction will be executed independently of the value of the a6 Dit. Bowever, if B6 ~ a "1~ the digital IC 80 will reply ~ck to khe c~ntral controller 76 wieh information regarding the ~tatu~ o~ the lines STAT 1 and STAT 2 which it receive~ fro~n the controlled device 82~ The format of the reply message is shown in FIG. 4, a~ will ~e described in more detail hereinafter.
When instruction bit~ B3-BS are 100 a re-s~o~e l~ad in~truction is decoded in r~ponse towhich the digi~al IC ~0 sets it~ COUT pin and pro-vide~ a logic one on the COUT line to the controlled 7~ 3 lg 51930 dPvice 82. Here again, a "1~ in the B6 bit instructs the deYice 80 to reply back with statu information from ~he controlled device 82 to indica~e that the command has been carried out.
When the in~truction bits ,B3-~S are 110 an enable interface instruction i5 decoded which in-structs an expanded ~lave device, such a5 the device 80 at station #3, to e~ta~lish an interface with an associated microcomputer such a~ the mierocomputer 84. The digital IC 80 respond to the enable inter-face instruction ~y producing an interrupt signal on the INT line after it has received a mes~ag~ f~om the central controller 76 which contain~ the enable in-terface instruction. Further operation of the digi-tal IC ~0 in esta~lishing 'ch~s in~erf ace will be de-scribed in more detail hereinafter. In a similar manner, the instruction 010 instruct~ the digital IC
80 to disable the interface to the microeomputer 84 so that thi s nticrocomputer cannot thereaf ter communi~
cate ov~r the network 78 until the digital IC 80 again receives an enable interface instruction from tha central contrs:)ller 76. In the- disa~le interface instruction a ~1" in the B6 bit position indicates that the exp~nded slave device ~0 should transmit a reply back to the central controller 76 which will conf irm to the cen~ral con~roller that the micro interface has b~en dis~bled ~y tb~ remote device 80.
The B6 ~it for an enable interface instruction is alway~ zero so ~hat the diqital IC ~0 will not trans-mit back to the central controller data in~cended for the microcomputer 84.
If bit~ B3-BS are 001 a blocl~ ~hed in~truc-~ion i~ decoded. The block shed in~truct~on i~ in-tended for ~tand alone 31ave3 and when it i~ received the stand alone slave ignoreq the foue LS3' s o its addre~3 and execu~e~ a ~hed load opeeation.
Accordingly, the block she~ instruction permit3 the ~.~7~3 central contro}ler to simultaneou~ly contro} 16 stand alone ~l~ves with a single transmitted message so :J~
that the~e slaves simultaneously d.âable their asso-ciated controlled devices. In a similar manner if the instruction bits ~3-B5 are 101 a bloc~ restore instruction i~ decoded which i~ simultaneously inter-preted ~y 16 stand alone slaves to re~tore a load to their respective controlled devices. It will be no~ed that in the bloc~ shed and bloc~ restore in-structions the B6 ~it mu~t ~e ~0" in order for the instruction to be executed. Thi~ is to prevent al}
16 of the instructed stand alone slaves to attempt to reply at the same ~ime.
If the B3-BS bits are 011 a ~cram instruc-lS tion is decoded. In response to the scram inatruc-tion ail stand alone slaves connected to the networ~
78 disregard their entire address and execute a shed load operation. Accordingly, ~y transmitting a scram instruction, the central controller 76 can simultane-ously control all 4,0~6 stand alone slaves to shed their loads in the event of an emergency. It will ~e noted that the scram instruction can only ~e executed when the B6 ~it is a "0~.
If the B3-BS bits are all "1" a status in-structiorl is decoded in which ~:he addre~sed stand alone slav~ take~ no ac~ion with respect to its con-trolled dev$ce ~ut merely transmits bac~ to the cen-tral controller 76 status information regarding the a~aociated controlled device 82.
Returning to the ~essage ~it format shown in FIG. 2, when the recelved me~sage is intended for a stand alone slave, i.e. the control bit i~
~its B10-821 constitute addres bitC~ of the addre3s assigned to the stand alone slave. In thi~ mode ~its 3~ B7-B9 and bit~ a22-a26 are not u~ed. However, when an enable interface instruc~ion i given in the ex-panded mode, bit~ ~7-B9 and B22-B26 may conta~n data 7~ ~3 intended for the a5sociated microcomputer 84 as will be des~ribed in more detail hereinafter.
Bits ~27-~31 of the received message con-~aln a five bit BC~ error checking code ~ This ~CH
S code i~ developed f rom the f irst 27 bits of the 33 bit received message as these first 27 ~its are stored in its serial shift register. The stand alone slave device 80 ~hen compares its computed BCH error code with the error code contained in bits B27-B31 of the received message. If any bits of the BC~ error code d~veloped within the device 80 do not agree with the corresponding ~its in the error code containedl in bits B27-B31 of the rec~ived message an .error in transmission is indicated and the device 80 ignores lS the message.
FIG. 4 shows the message format of the 33 bit messaqe which is transmitted by thc ~tand alone slave 80 back to the central controller in response to a reply request in the received message i.e. a "1"
in the B6 ~it position. The stand alone slave reply message has the identic~l format of the received mes-sage shown in FIG. 2 except that ~its B25 and B26 correspond to the status indication on STAT 1 and STAT 2 line~ received from the control device 82.
However, since B25 and ~26 were not used in the re-ceived me.~age whereas ~hey are employed to transmie information ln the reply message, the old BCH erro~
checking code of the received ~essage cannot be used in transmit~ing a reply ~ack to the central con~rol-ler. The stand alone slave device 80 reGomputes aive bit BCH error code based on the first 27 bits of the reply message shown in FIG. 4 as these bits are being shipped out to the network 7~. At the end of the 27th bit of the reply message ~he new BCH error 3S code, which ha~ been computed 1n tbe device 80 bas~d on the condition of the ~tatu~ bits 825 and B~6~ i5 then added on to the tran~mitted mesSage a~ter which ~7~2~

a stop bit of 0 i added to complete the reply mes-sa~e back to the central controller.
Fig. 5 show~ the format of a second message transmi~ted to a digital IC 80 operating in an exp-anded mode, it being assuming that the first messageincluded an enable interface as discussed previously.
In the format of Fig. 5 the control ~it is ~0" which informs all of ~he device~ 80 on t~le power llne 78 that the message does not contain address and in-struction. The next 24 ~its after the control ~itcomprise data to ~e read out of the ~ffer shift reg-ister in the device ~0 ~y the associated miceocompu-ter 84.

lS In the illustrated em~odiment the digital IC 80 is housed in a 28 pin dual in line package.
Preferrably it is constructed from a five micron silicon gate CMOS ga~e array. A detailed sigslal and pin a~signment of the device 80 is shown in FIG. 6.
It should ~e noted that some pins have a dual func-tion. For example, a pin may have one function in the stand alone slave configuration and another func-tion in an expanded mode configura~ion. The follow-ing is a ~rief d~cription of the terminology assign-ed to each of the pins of the device 80 in FIG. 6.
TX~thg transmit output of the device ~0.Transmits a 33 bit mes age th~ough a suita~le coupl-ing network ~o the common data line 78.
RX-the receive input of the device B0. All 33 ~i~ network transmission enter the device through thi~ p~n.
RESTN-the active low power on reset input.
Re3ets the internal regi~ters in the device 80.
Vdd-the power supply input of +5 volt~.
VS~-th~ ground re~e~en~e.
XTALl and XTAL2 th~ cry~tal input3. A
3.6864 mHz ~ 0.015~ crystal oscllla~or i9 requir~d.

~7~

Baud 0 and Baud l-the baud rate select in putg.
A0-AB - the }east signif icant address Dit pin~, A9/CLK ~ dual ~unction pin. In all ~ut the test mode~ this pin is the A9 addresc~ input pin. In the test mode ~hiC pin is the clock ~tro~e output of the digital demodulator in the device 80.
A10/DEMOD - a dual function pin. In all but the test mode this pin is the A10 alddress input pin.
In the test mode this pin is the demodulated output (DEMOD~ of the digital demodulator in the d~vice 80.
All/CD - a dual func~ion pin. In all put the test mode this pin is the All address input pin.
In the test mode this pin is the receive word de~ect output ~CD) of the digital demodulator in the device 80.
BU5YN/COUT - a dual function output pin.
In the expanded slave or expanded master mc~de~ this pin is the BUSYN output of the micro interface. I~
the stand alone ~lave mode this pin is the switch control su'cput (COUT).
INT/TOUT - a dual f unct ioi~ output pin . I n the expanded m~ster or axpanded slave mode~ this pln is the intarrupt output (INT) of the micro interface.
In the stand alone slave mode this pin is a ~imer control pin (TOUT).
SCR~STATl - a dual function input pin. In th~ expanded mas~er and expanded slave mode~ this pin i~ the 3erlal cloc~ ~SCK) of the micro interface. In the ~tand alone slave mode it is one o the two statu~ input~ (STA~
RW/STAT2 - a dual function input pln. In ~he expanded ma~ter or expanded slave mode this pin i~ the re~d-write control line of the micro inter-face ~E~). In the sl:and alone ~lave i~ i~ one of the two 9tz~tu3 inputs ~STAT2).

~7~9~3 DATA/TIMR - a dual function pin. In the expanded master or expanded slave mode~ this pin is the bidirectional data pin (DATA) of the micro inter-~ce. In the stand alone slave mode this p1n is a timec control line (TIMR).
All input pins o~ the devic:e ao ~re pulled up to the +5 five volt supply V~d by internal 10~
pull-up resistors. Preferably the3e internal pull-up resi~tor~ are provided ~y suitably bi~s~d tran~istors within the device 80, a~ will ~e readily und~r~tood ~y those skilled in the ~rt~
As discussed gener311y heretofore th~ d~gi-tal IC 80 is capable of operation in 3everal difer-ent operating modes ~y simply changing external con-nections to the device. The pins which control themodes of opera~ion of the device 80 are pin~ 1 and 27, identified as mode 1 and mode 2. The relation-ship between these pinq and the selected mode is a~
f~llows:
MOD~ 1 MODE 0 SELECTED MOD~
0 0 expanded ~lave 0 1 ~ stand aloneslave 1 0 expanded master 1 1 test When only the MODE 1 pin iS grounded the MODE 0 pin a~mes a logic ~1~ due to i~S in~ernal pull up r~ tor and th~ digital IC 80 is operated in the Rt~nd alone ~lave mode. In this pin configura-tion the digital IC 80 acts a3 a ~witch control with statuR fe2d ~ac~. The device 80 contain~ a 12 ~it addre~3, a switch control output (COUT) and two status inputs (STATl) and (STAT2). The addressed device 80 may be comm~nded to set or rese~ the 3witch control pin COUT, reply with ~tatu6 information from it~ two ~tatus pin~, or both. The devioe~ 80 may ~e addre~ed in blocks of 1~ for one w~y qwitch control command~.

~2~

When both the MODE 1 and MODE 0 pins are grounded the device 8 is operated in an expanded slav~ mode. In this pin configura~ion the device 80 contains a 12 bit address and a microcomputer inter-face. Thi~ interface allows the central controller 76 and a microcomputer 84 tied to the device 80 to communicate with each other. The interface is dis-a~led until the central con~roller 76 ena~les it by sending an enable interface command to the addressed digital IC 80. The central controller and microcom-puter communicate by loading a seria]. ~hift register in the digital device 80. The central control:Ler does this ~y sending a 33 ~it messag~ to the device ~0. This causes the microcomputer interface to in-terrupt the microcomputer 84 allowing it to read the shift register. The microcomputer 84 communicates with the central controller 76 ~y loading the same shift register and commanding the device 80 to trans-mit it onto the network.
When only the mode 0 pin is grounded the ~ODE l pin assumes a logic "1" due to its internal pull up resistor and the device 80 is operated in the expanded m~ster mode. In this mode the device 80 operates exactly like ~he expanded slave mode except that the micro interface is always ena~led. Any net-work transmi~Qion3 that the digital device 80 receives produce interrupts to the attached microcomputer 84, enabling $~ to read the serial shift register of the devic~ 80. Al~o the microcomputer may place data in the shift r~gi~ter and forc~ the device 80 to trans-mit onto the network at any time.
When both the MOD~ 1 and MODE 0 pins are unground~d ~hey assume "logic" values of "lq and the device 80 is conf igured in a test mod~ in which som~
of the external signals in the dlgital d~modulator portion of the device 80 are brought out to pins for te~t purposes, as will be de~cribed in more detail.

2~3 Ac discussed generally heretofore the digi-tal IC.80 is adapted to transmit messages to and re-ceive messages from different types of communication network lines such as a conventiona.l power line, a S dedicated twisted pair, or over fi~er optic cables. When the digital IC 80 i5 to work with a conventional AC
power line 78, this device is pin configured so that it receives and transmits data at a baud rate of 300 ~its per ~econd. Thus, for power line appllcations the ~inary Dits consist of a carri~er of 115.2 k~z which is modulated ~y on~off ~eying at a }00 ~aud bit rate. This bit rate is chosen to minimi2e ~it error rates in the relatively noisy enqironment of the power line 78. Thu~, for power line appLications 15 the digital IC 10 is conf igured aq shown in FIG. 7 wherein the ~aud 0 and ~aud 1 pins of ~he device S0 are ungrounded and assume logic value~ of Yl~ due to their internal pull up resistors. The RX and TX pins of the device 80 are coupled through a coupling net-work and amplifier limiter 90 to the power lines 78,~his coupling network providing the desired i301ation ~etween transmit and received mess~ges so that two way communication ~etween ~he digital IC 80 and the power line 7~ i permitted, as will ~e described in 25 more d~tail bereinafter. When the device 80 is pin configured as ~hown in FIG. 7 it is internally ad-justed ~o that it will receive modulated carrier mes-sage~ at a 300 ~aud rate. It i5 also internally con-trolled ~o that it will tr~nsmit messages at this 30 same 300 baud rate.
In ~ig. 8 the digital IC ~0 is illustr~t-ed irl connection with a communication network in which the common data 1 in~ i s a dedicated twisted pair 92. Under these condition~ the baud 0 pin of 35 the device 80 is groundea whereas the baud 1 pin as-~ume~ a logic value o ~1~ due to it~ internal pull up re~istQr. When the device ~0 i9 pin configu~ed a~

7 ~2 ~

~hown in FIG. B it is arranged to transmit and re ceive modulated carrier messages at a 1200 baud rate.
Th~ 1200 baud bit rate is pos3ible due to the less noi~y environment on the twi~ted pair 92. In ~he configuration of Fig. 8 the couplins3 network 90 is also required to couple the device 80 to the twisted pair 92.
For high speed data communication the digi-tal IC 80 is also pin configura~ o tran~mit and 10 receive unmodulated data at the relatively high bit rate of 38 . 4K ~aud. When 50 conf igured the device 80 is particularly suita~le for operation in a communi-cations system which emplsy3 the f ~er oE~tic c~les 94 ~Fig. 9) as the communication network medium.
15 More particularly, when the device 80 is to function with the f iber op~ic cable~ 94 the ~aud 1 terminal is grounded and the ~aud 0 terminal assumes a logic value of ~ln due to its internal pull up resi3tor, as shown in FIG . 9. In the f i~er optic cable system of 20 FIG. 9 the coupling network 90 is not employed.
In~tead, the receive pin RX of the device 80 i~
direc'cly connected to the output ~f a f iber optic receiver 96 and the ~ransmit pin TX is connected to a fi~er optic tran~mitter 9~. A digital IC RO in the 25 central controller 76 is also interconnected with the f iber optic cables 94 ~y a suita~le transmitter receiver p~ir lO0. The fi~er optic receiver 96 and tran~ t~r 98 may comprise any suita~le arrangement irl whlch the RX terminal is connected to a sui'cable photode~ector and amplifier arrangement and the TX
terminal i~ c3nnec~ed to a suita~le modulated ligh~
source, ~uch as a photodiode. For example, the Hewlett Pacl~ard H~BR-1501~2502 transmitter ~eceiver pair ~y ~e employed to connect th~ digi~al IC B0 to 35 the f iber optic cable3 9~. Such a trans~itter-receiver pair operate~ at TTL co~p~tible logic level~

~'7~

which are ~atisfactory for direct applica~ion to the RX ~nd.TX terminals of the device 80.

In Fig. 10 a typical configuration is shown S for th2 device 80 when operated in th~ stand alone slave mode. Referring to this figur.e, plu~ 5 volts DC i3 applied ~o the Vdd terminal and the V53 terminal is grounded. A cry~tal 102 operatin~ at 3.6864 -0.01S~
mHz is connected to the OSCl and OSC2 pin~ of the de-vice 80. Each side of the crystal is connected to ground thro ~h a capacitor 104 and 106 and a resi3tor 108 i~ connected across the crystal 102. Prefer-ra~ly, the capacitors 1040 106 have a value of 33 picofarads and the resistor 10~ has a value of 10 megohms. The baud rate at which the deYice 80 is to operate can be selected by means of the ~aud rate switches 110. In the em~di~ent of FIG. 10 the~e switche~ are open which mean3 that the device 80 iY
operating at a baud rate of 300 ~aud which is ~uit-able for power line network communication. The MODE
1 termin~ grounded and th~ MODE 0 terminal is not connected so that the device 80 i~ operating in a ~tand alone ~lave mode. A 0.1 microfarad capacitor 112 is conn~cted to the RESETN pin af the device 80.
When power is applied to the Vdd terminal of the device 80 the cap~citor 112 cannot charge immadiately and hence provide~ a ~eset ig~al of n o" which is employed to re~et v~riou~ logic circuit~ in ~he digital IC 80.
Al~o~ a powe~ on reset signal forces the COUT output of ~he de~ice 80 ~o a logic ~1~. As a result, the controll~d devlce, such a~ the relay coil 114, i~ en-ergiz~d through the indicated tran~istor 116 whenever power is applied to the digital IC ~0. The condition of tne relay 114 is indicate~ by the statu~ infor~a-35 tion ~witches 118 which are opened or c:losed in accordance with the ~gnal supplied to ~be contro}led relay 114. Two status infor~ation switche~ are pro-vid~d for th~ two lines STATl and STAT2 eve~ though only a.~ingle device is controlled over the COUT con-trol line. Accordingly, one status line can be connected ~o the COUT line to confir~ that the COUT
~ignal wa~ actually developed and the other status line can be connected to auxiliary contacts on the relay 114 to confirm that the load instruction has actually been executed.
A series of tw~lve address ~witches 120 may ~e selectively connected to the address pin~ A0-All so as to provide a digital input -Rignal to the address comparison circuit in the digital IC 80. Any address pin which i3 ungrounded ~y the switche~ :L20 assumes a logic "1~ value inside the deYice ~0 lS through the use of internal pull up re~istors on each address pin. In this connection it will b~ unders~ood that the device 80, and the extern~l compone~t~ a~-sociated wi ~h it, including the coupling networ~ 90 may all ~e as~embled on a ~mall PC board or card 20 which can be associated directly witb the controlled device such as the relay 114. Furtherm3re, the digi-tal IC ~0 and its as~ociated components can be of ex-trem~ly sm~ll size so that it can b~ ac'cually located in the hou3ing of - the device which it controls.
25 Thu~, if the device ~0 i~ employed to control a relay for a hot water heate~ or frcezer in a residence, it may be a9130Ciated directly with such relay and re~
ceivR message3 for controlling ~he relay over the hou~e s~iring of the re~idence. If the cont~olled de-30 vic~ doe~ not include a f ive volt source for pows~ringthe digital IC 80, the coupling ne~work 90 may pro~
vide ~uch power direc~ly fro~n the power line 7~, a~
will be d~cribed in more de~ail be~einafter.
In 30me 5ituz~ ,0n~ it i~3 desirat~l~ to pro-35 vid~ a varia~ly tim~a shed load fe~tur~ for part~cu-lar ~tand alone ~lave applic:~tion. For exampl~, if the dlgi'cal IC ~0 is employed ~o cont~ol a hot wat~r 7 ~

h~ater or freezer, it may be controlled from a cen-tral controller so tha~ the freezer or hot water heater may be turned off ~shed load .ins~ruction) dur-ing peak load period~ in accordance with predetermin-S ed time ~chedule~. Under these conditions it would be de~ira~l~ to provide a varia~ly ti.med facility for re^~toring power to the controlled freezer or hot water heater in the event that the central controller did not transmit a mes~age instructillg the digital IC
~0 to restore load. ~uch a variably tim~d ~hed load fe~ture may be provided in a sim~le manner by employing the arrangement shown in FIG. 11 wherein a variable timer 130 is as~ociated with the digital IC
80. The varia~le timer 130 may comprise a commercial type MC14536 device which is manufactured ~y Motorola Inc and others.
In the arrangement of FIG. 11 the COUT line of the digital IC 80 is connected to the re et pin of ~he variable timer 130 and is also connected to an internal NOR gate U625 o~ the device 80 whose output is inverted. The TOUT output line of the device 80 is oonnected to the cloc~ inhibit-pin of the timer 130 and the decode output pin of this timer is connected to the TIMR inpu~ pin of the device 80.
The device 80 in Fig. :Ll is also conencted in the stand alone Rlave mode of FIG. 10 in which mode the TOUT and TIMR lines are enabled. In the em~odiment o~ FIG. 11 the con~rolled relay 114 is connected to the TOUT line rather th~n ~o the COUT pi.n of the device 80. The timer 130 has an internal cloc~ whose fr~quency can be determined by the external resi~tors 132 and 134~ and the capacitor 136 a will ~e readily understood by those skilled in ~he art. In addl~ion, the timer 130 ha# a num~er of timer input ter~ninals A, 3, C and D to which shed time sel~ct ~wi~che3 138 may ~e ~electively connected to e~t~ h a de~ired varia~le timer interval.

~7~33 When power is applied to the digital IC 80 in FIG. 11 a powet on reset produces a lo~ic ~1" (re-store load 3tate) on the COUT pin. This signal is applied to the reset terminal of the timer 130 forc-ing the timer to reset and its decode output pin low.
This decode output pin is connected to the TIM:R line of the device 80 which is internally connected ~o the NOR gate U625. Since the TOUT pin i5 the log}c~l OR
of COUT and the decode output o~ the timer 130, upon power on reset TOUT is a logic 1 and the relay 114 is in a restore load state. When the COUT line is re-set, in response to a shed load instruction to the device 80, the timer 130 is allowed to ~tart count.Lng and ~he TOUT pin is a logic ~0~ caus$ng the load ~o ~e shed~ When the timer 130 counts up to a nu~er determaned by the shed time ~elect witches 138 its decode out pin goes high forcing TOUT high i.e. ~ack to the restore load s~ate and inhi~iting the timer clock. Accordingly, if the central controller for-gets to restore 102d to the relay 114 by means of a network message transmitted ~o the device 80, the timer 130 will restore load automxtically after a predetermined ~ime interval.
In FIG. 12 the main component parts o the digital IC 80 are shown in block diagram form when the device 80 is opera~ed in the stand alone slave mode and 1~ arranged to receive a message transmitted over the network 78 which includes a shed load in struction. The incoming message is amplified and limited in the coupling networ~ 90, as w111 ~e de-scribed in more detail hereinater, and i~ applied to the RX terminal ~pin 6) of th~ digital IC 80. It will be unde~tood that the incoming me~sage is a 33 bit me~sage ~ignal having the ~ormat d~scri~ed in de-tail heretofore in connection with ~ig. 2. Thi~ in-coming ~es~age is demodulat~d in a digital d~odu-lator 150 whicn also include~ the 3tart bit de~ection ~2~

and fr2ming logic nece sary to esta~lish the bit in~
t~rval~ of the incoming asynchronous message trans-mitted to the device 80 over the network 7~. The digltal demodulator and its accompanying framing logic will be deicri~ed in more detail hereinafter in connection with a de~cription of the detailed schema-tic diagram of the device 80 shown in FIG5. 18 to 33.
The output of the demodulator 150 i3 SUp-plied to a serial shit register indicated generally at 152. The serial ~hift regi~er 152 comprises a series of 26 serially connected ~ages the fir~t 24 of whictl are identif ied as a buff~r and store bit~ B3-B26 (Fig. 2) o~ the received mes~age. The next stage is the control ~it regi~ter U528 which store~ the control bit B2 (Fig. 2) of the received message. 'rhe f inal stage of the ser ial hif t re~ister 152 is a start bits register U641 which stores bits 30 and Bl (Fig. 2) oE the received message. In this connection it will ~e rec311ed that the two start bits B0 and Bl of each message both have a logic value of "ln and hence constitute a carrier signal which extend~ over two ~it interval~ so that both bits may be registered in the single regi~ter U641. In this connection it should be noted that all logic component~ having U
25 number~ refer to the corresponding logic element shown in det~il in the overall schematic of the digi-tal IC 80 ~hown in FIGS. 18 to 33~ The serial shift regi~er 152 i3 loaded from the le~t by the demodu-lated ou'cput of the demodulator 150 which is applied 30 to the data lnput of ~he register 152, ~hi data ~e-ing clocl~ed ints~ the register 150 by means o~ ~uf ~er ~hift clock pulses (BSHFCLK) dev~loped by ~che demodu-lator 150 at the end of each bit interval in a manner d~3cribed in more detail hereinaf ter . Accordingly, the inCv~ing message is ~hifted througn the Cegi$ter 152 until the start bits r~gi~ter U6~ t Dy the two s~art ~its ~0 and Bl to a logic nl~ value. In ~.2~4~

~hi~ connection it will De noted that the bits of the inc~ing me3sage are ~tored in the ~uffer portion o~
the regi~ter 152 in the manner shown in FIG. 2 with the lea~t 5ignificant b$t ~3 ~tored in the register next to the control ~it regi~ter U528,.
As the demodulated data bit~ are thu~ being loaded into ~erial hift registec 1!;2 th~y are also simultaneou~ly supplied to a BCH ~rroe code computer indicated generally at 154~ More particula~ly, the DEMOD output of the demodulator :L50 i~ ~upplied through a switch 156 to the input of ~he BC~ error code computer 154 and the output o~ this ~omputer i~
connected to a recirculating input through the swi~ch 158. The BCH error code computer 154 compri~e~ a serieR of 5 serially connected shift regi~te~ ~ages and when the switches 156 and 15~ are in the po~ition shown in FIG. 12 the computer 154 co~pute~ a 5 ~it ecror code based on the fi~st 27 me sage ~it~ which it receives from the demodulator 150 as the~ bit~
are ~@ing s~ored in ~h@ serial ghift regi3ter 152, The clock pulses on the 8SHFCLK line, which are u~ed to advance the serial shift reqister 152, are al~o supplied to a mes~age bit counter 160. The counter 160 i~ a six stage counter which develops an output on its end-of-word ~EOW) output line when it coun~ up ~o 32. In ~his connection it will ~e noted ~h~ by u~ing ~wo logic ~1" s~art ~it~ which aro counted as one, the total meqsage length may be counted by digital logic while providinq increased no~e lmmu~lty ~y virtue o~ the longer start ~it in-terval.
The message bit counter 160 also sets a la~ch at th~ end of the 26~h me~sag~ ~it and devel-opes an enabling ~ignal on it~ GT26 ~greater than 26) output line. The GT26 3ignal control~ the ~witches 156 ~nd 158 ~o that af~er ~he 26th me~age blt th~
DEMOD output of the demodulator 150 is supplied to a 7~

BC~ comparator 162 to which comparator the output o~
th~ BC~ ercor code computer 154 is al50 supplied. At the same time the ~witch 158 i5 opened by the GT 26 signal so that the BCH error code computed in the com-puter 154 remains fixed at a value corre~ponding tothe first 26 bi~s of the rec~ived m2s~sage. Since the demodulator 150 continue.~ to supply BSHFCLK pulses to the computer 154, the BC~ error code developed in the computer 154 is then shifted out and compared ~i~ by bit with the next 5 ~its of the received message i.e.
827-B31 ~Flg. 2) which constitute th~ BCH er~or code portion of the incoming rec~ived ~essage and are 3Up-plied ~o ~he other input of the BCH comparator 162.
Ie all five bits of the BC~ error code computed in the computer 154 correspond with the five bit~ of the BCH error code contained in ~its B27-~31 of the re-ceived message the comparator 162 develops an output on its BCHOK output line.
The digital IC 80 also includes an address decoder indicated generally at 164 which comprise~ a series of 12 exclu~ive OR gate~ and associated logic.
It will ~e recalled from the previous description of FIG. 2 that ~its Bll-B22 of a received me~sage con-tain an addre ~ corre~ponding ~o the particular stand alone slave with which the central controller wishe~
to co~unic2te. Also, it will be recalled from the prec~edin~ d~scription of FI&. 10 that the address ~eLect s~tche~ 120 are connected to the address pins A0-All of the digital IC 80 in accordance with the add~e~s a~Qigned to each particular s~and alone slave. ~he addre~s decoder 164 compares the set~ing of the ad~ress select switches 120 with the address stored in bit~ Bll-B22 of the buffer portlon of ~he ~erial shift regi~ter 152. If the two addre33e~ co~
incide the de~oder 164 dev@lopes an outpu~ on its ad-dre3s OR ~DDOK~ ou~put lin~.

~2~

The digital IC 80 also includes an instruc-tion decoder 156 which decodes the outputs of the buffer stages corresponding ~o bita a3-B6 (Fig. 2) which con~aln the ins~ruction which the addressed stand alone slave is to execute. Assuming that bits B3-B5 all have a logic value of "0", a sh~d load in-struction is decoded, as shown in FIG. 3, and the in-struction decoder 166 produces an output on its shed load line (SHEDN~.
A~ discussed generally hereto ore, the con trol ~it B2 of a message intended for 3 ~eand alone slave always has a logic value of nlW indicating that bits ~3-B26 of this message include address ~its and instruction bits which are to ~e compared and decoded in the decoders 164, 166 of the digital IC 80. Wben the control ~it register U528 in the serial shift register 152 is set an ena~ling signal is supplied over the CONTROL output line of the register U528 to the execute logic circuits 170~ The BCHOR output line of the comparator 162, the EOW output line of the message bit counter 160 and the ADDOR output line of the address decoder 164 are al~o supplied to the execute logic circuats 170. Accordingly, when the message ~it counter 160 indicates that the end of the message has been reached, the comparator 162 indi-cates that all bits of the received BCH error code agreed wlth the error code computed by the computer 154, the address decoder 164 indicates that the mes-~ag~ i~ in'cended for this particular stand alone ~lave, and the control l~it regi te~ U52~ i~ set, the logic circuits 170 develop an output signal on the EXECUTE line which is anded wi'ch the SHEDN output o the instruction decoder in the NAND gate U649 the output of which i~ employed to reget a shed load lat~h U651 and U6~2 .~o that the COUT output pin of tha ditigal IC 80 goes to a logic value of ~0" and power i~ removed ~rom the controlled device 82 (Fig.

~Z~

1). The stand alone slave thus executes the instruc-t1on c~ntained in the received message to shed the load of the controlled device 82. As discussed gen-erally heretofore when power is applied to thle digi-

5 tal IC 80 the shed load latch is ini~ially reset bythe ~ ignal appear ing on the PONN .1 ine so that the COUT line go~ss high when ~5v. power is appli~d to the dev i ce 8 0 .
When the message ~it B6 (~ig. 31 has a 10 logic value of "1" the 5tand alone 91ave not only executes a shed load instruction il the manner da--scribed in connection with FIG. 12 but al o is ar-ranged to transmit a reply mes~age baclc to the cen-tral controller as shown in FI~;. 4. In this reply, 15 message bits B25 and ~26 contain l:he two ~tatus in-puts STATl and STA~2 which appear on pins 26 and 25, respectively, of the digital IC ~0. Considered very generally, this reply message is developed by shift-ing out the data which has been stored in the serial 20 shift register 152 and employing this data to on-off ~ey a 115.2 k~z carrier which is then supplied to the TX output pin of the device 80. ~GweVer, in accord-ance with an important a pect of the di~closed system, the statu~ nals appearing on the STAT 1 25 and STAT 2 input pins of the device 80, which repre-sent the condition of the controlled relay, are not employed to ~et the status bit3 B25 and B26 of the r@ply m~3sage until after 15 bits have been read out of th~ serial shif t register 152. This gives consid-30 erabl~ t~me for the relay contacts to settle down be-fore their statu~ is added to the reply me~age being transmitted back to the central controller.
In Fig. 13 the operatlon of the stand alone lave in formatting and tran~mitting ~uch a reply 35 me~age back to the central controll~r i~ shown in block diagram form. Re~erring to thi~ figure, it is a~umed that a me~age has been received f rom the centr~l controll@r and ~as been stored in the serial hift r~gi~ter 152 in the manner descri~ed in detail heretofore in connection with Fig. 12. It is further as~u~ed th~t the control bit B2 of the received mes-sage has a logic value of "1~ and that the mes agebit B6 stored in the ~uffer portion of the cegi~ter 152 has a logic value ~1~ which lnstructR the stand a1One ~lave to transmit a reply mes~age ~ack to the central con~roller. When ~he B6 ~it has a Ul" value the in~truction decoder 166 produces an output ~ignal on it COM 3 output line. Also, at the end o~ the received message the execute logic circuit~ 170 (see Fig. 12) produce an EXECUT~ signal when the condi-tion descriDed in detail hereto~ore in connec~ion with Fig. 12 occur. When an EXECU~E signal is pro-duced a reply latch 1~2 provide an output which is employed to ~et a status la~ch 174. The ~tatu~ latch 174 provides a control signal to the status control logic 176. However, the condition of the status pins STAT 1 and STAT 2 is not employed to set correspond-ing ~ages of the ~uffer portion of the cerial hift regi~ter 152 until ~fter 15 ~its ~ave ~een shifted out of the register 152r At that time the me . ~age : bit counter 160 provide~ an output on its ~15~ output li~e which is employed in the ~tatus control logic 176 to 3et th~ corresponding stages of the buf fer portion of the regi3ter 152, these stages corre~pond-ing to t2 e location of bits B25 and B26 in th~ reply ~e3sage after 15 bit~ have been shifted out of ths 30 regi~t~r 152r Con~ider ing now the manner in which the re-ceived me~aqe which has ~een stored in the ~er ial ~hl~t regLster 152 is shifted sut to ~or~ a reply m~0s~ge, it will be recal}ed that a me3si~g~ which is 35 tr~nsmi~cted over the networ~c 78 requires two ~tart bit~ h~ving a logic value o ~'lU. ~Iowever, whon the messago was received it was ini~lally de~ect~d by de-tecting the presence of carrier on the network 7~ for a~dura~ion of 2 bits and, hence, the two start bits of th~ received me3~age are stored as a single ~it in the 3tart bits regic~ter US41. When a reply message is to be tran~mit~ed over the networlc it is neces~ary to provide a modulated carrier o~ two bits duration in respons~ to the ~ingle start ~it !3tored ln the re gi ter U641. To accomplish thiC, a trans~it ~trobe signal ~TXSTB) is derived from the reply latch 172 and is coupled through the N4R gate USOl to reset a one ~it delay fllp-flop 1~8 which ha~ its D input connected to the Five volt ~upply Vdd. As a re~ult the QN output of the flip-flop 178 i~ inverted to provide a transmit ~tro~e A (TXSTBA) signal which sets a transmit control la~ch 180. When the latch 180 i~ 3et it provides a transmit on (TXONN) signal whicb is employed to relea~e the framing counter~i in the demodulator lSO so that they ~egin to provide BSHFCLK pulse~ at one bit intecvals.
~or the first 26 ~i~5 of the reply message the output of the start bits regi~ter U641 is con-nected throuigh a switch 190 to a t-ransmit flip flop 182 which is al o set ~y the ~XSTBA ~ignal and is held in a se~ condition o that it does not respond to the fir ~ B5~FCLK pulse which is applied ~o its clock input. At the ~ame time the QN output of the on~ bit del2y fl~p-flop 178 i5 com~ined with the flr~t 3S~FCLR pu}se in the NAND gate U658 so as to provlde ~ ~ignal which ~ets a transmi~ enable latch lB4. ~h2n th~ transmit ena~le latch 184 is set it prov~des an enaDlin~ nal to the modulator 186 to which i$ also ~upplied a carrier signal having a fre-quency of 115.2 k~z. from the digital de~odulator lSO. When the tran~mit fllp-flop 1~2 i~ initlaLly ~et by the TXSTBA line going low, i~ provide~ a 1 on it~ Q output ~o the modulator 18~. Accordlngly~ when the tran3mit ena~le latch 18~ p~o~ide~ ~n ena~ling g3 signal to the modulatvr 186 a carrier o~tput is sup-plied to the TX output pin of the device 80 and is supplied ~o ~he networ~ 78. During this initial tr~n~mi~ion of carrier during the fir~t star~ bit interval the data in the se~ial shift regi~ter 152 is not shi~t~d out bscause BSHFCLR pulse~ to th~ cloc~
input of the register 152 are ~loc~ed by the NAND
gate U697. The NAND gate U697 has a-~ its second input a signal ~rom the G~26N output line of th~ me~age ~it counter 160 which i high until 26 ~its have been - shifted out of th~ register 152. Flowever, a third input to the NAND gate U697 iR the TXSTBA line wh~ch we~t low when the 1 bit delay flip-flop 178 was re-set. Accordingly, the first BSHFCLK pulse i~ not ap-lS plied ~o the cloc~ input of the regi ter 152 although this pulse does set the tran mit ENABLE la~ch 184 and enable carrier output to be supplied to the TX output pin for the first ~it interval. ~owever, a sbort in-terval a~ter the first BS~FC~K pulse, a delayed shif~
clock pulse (DSHFHCLK), which is also developed in ~he framing logic of the dem~dulator 150, is ~upplied to the cloc~ input of the 1 ~it deiay flip-flop 178 50 that the TXSTBA line goe~ high s~ortly a~ter the first BSH~ChK pul~e occurs. When the TXSTBA line goes high th~ BS~FCLX pulses pa~s through the NAND
gate U697 and shi~t data out of the register 152 and the serially connected tran~mit flip-flop 1~2 to the modulator 186 ~o that the ~ingle start bit 3tored in the ~egist~r U641 and the r~maining bits B2-B26 of th~ received message control the modulation of the carrier supplied to the TX ou~put pin~. In thi~
connection it will be notsd that ~he ~S~FCLX pulses are al~o supplied to the cloc~ inpu~ of the tran~mit ~lip-~lop 182 so as to permit the ~erial ~hift of data tO th~ TX output pin. Ho~ver, ~ di~cu3sed above, when the TXSTBA line Is low it hold~ th~ flip-flop 182 set so that it doe5 not re5pond to the first 3SHFCL~ pulse.
Considering now the man..er in which the STAT 1 and STAT 2 sta~us signals from the controlled device are added to the reply message, it will be re-called that the bu~fer stages are not set in accord-ance with the signals on the STAT 1 and STAT 2 pi~s until 15 ~its have ~een chifted out of the regi~ter 152 in order to allow time for the relay contactq of the controlled device to assume a final po~ition. It will also ~e recalled that the B S and 826 bit~ of the ceceived message are re~erved for 3tatu3 ~it~ to ~e added in a reply me~sag~ 50 that the la~t active bit in the received message is B24. When the B24 bit has been shifted 15 times it appears in the B9 stage of the buffer portion of the serial shift register 152. Accordingly, the conditions of the ~tatus pins STAT 1 and STAT 2 can be set into the B10 and Bll stages of the bu~fe after the l5th 3hift of data in the register 152. To this end, the mes~age bit coun~er 160 develops a ignal on the "lS" output line which is sent to the status con~rol-logic 176. This logic wa~ enabled when the status latch 174 was set in re~pon~e to a COM 3 ~ignal indicating that the reply wa3 requested. Accordingly, tne ~tatus control logic 'ch~n renponds to the "lS" signa~ by setting tbe B10 and Bll stages in accordance with the poten-tlal~ on the STAT 1 and S5~AT 2 pins. In thi-Q connec-tion lt wi}l be understood that the B10 and Bll ~tage~ of th~ bu~fer initially contained part of the add~e~s in the received me~age. However, after the received message has been shifted 15 bi~s during transmi3sion of the reply mes~age the stage~ 810 and Bll are ree to ~e set in accordanc~ with the ~tatu~
pins STAT 1 and STAT 2 and this statu~ will be trans-mlt~ed ou~ a~ a part of t~e reply me 3age in ~le B25 and B26 bit po~itions.

~s discussed generally heretofore, it is nece~ 4ry to compute a new BCH error code for the re-ply ~e3s~ge which is transmitted bac~ to the central con~roller due to the ~act that the status bits B25 and ~26 may now contain status in~ormation where they were no~ used ln the received message. As 900n as the trans~lt control latch 180 i~ se!t th~ TXONN 5i9-nal controls a switch U75~ so that the DEMOD output of the demodulator 50 i3 removed from the data input L0 of the BC~ error code computer 154 and the ouptut of the serial shift register 152 is connected to this input through the switch 156. ~owever, during the initial 1 ~it delay of the flip flop 178 BS~PCLR
pul es are blocked f rom the cloclt input of the co~-parator 154 by the NAND gate U672 the other input of whioh is the TXSTBA line which i~ low for tbe f irst start bit . After the f irst BSHFCL~ pulse tbe TXSTBA
line go~s high and succeeding BSHFCL~ pulses are sup-plied to the computer 154. The two start ~its of the transmitted mess2ge are thus treated as one bit by the computer 154 in the same manner as the two ~tar~
~ittivs of a received message are dec~ded as one bit for the register U641.
As the data stored in the register 152 i9 shifted out to ~he transmit flip-10p 182, this data is also 8Upp~ d to the data input of the BCH error cocle cc~puter 154 through ~che switch 156. Also, the recirculating input of the computer 154 1 connected through the switch 15~, as descri~ed h~retofore in connection with Fig. 12. Ac.~:ordingly, a~ the 26 bit~ ~tored in 'ch~ regi~sr 152 are shifted out of thi~ regi~ter, the caaputer 154 i3 computing a new BC~ error code which will take into account the status lnformation in ~its E~25 and B26 thereof.
Aft~r the 26th bit ha~ been qhi~ted out of the ~e9is-ter 152 a new f iv~ bit error cod~ i5 th~n pr~sent in the computer 154. When the message bit counter 160 ~L~27~

produce an outpu~e on 'che GT26 line the switches 156 and 1~ are opened while at the sam~ time the output 7 of the comput~r 154 i`Y connec"ed through th~ switch 190 to the input o the transmit elip-flop L82 in S place o4 the output ~rom the ~eria]L shift regicter 152. Since BSHCLR pul~eq are still applied to bo~h the BCH error code computer 154 and the transmit flip-flop 182 ~che ~iv~ ~it error code dev~loped in the computer 154 i9 succe3~ively cloc~ed through the transmit flip-flop 182 to the modulator 186 so aC to constltute the ~C~I error code portion of th~ trans-mi tted reply mes~age .
When the switch 156 i~ op~ned after the 26th ~it, a z~ro is appli~d to the data input of the BCH error co~e computer 154 o that as 'che f ive ~it error code is shlted out of the BCH error code coTaputer 154 the shi~t regi~ter ~tage~ ar~ ~ao~c filled with zeroe~. After the five error code bits have been shifted outg the next 8S~FCLK pul~e ~lo~ts a zero out of the computer 154 and through the t~an~mit ~lip-flop 182 to the modulator 186 to constitute the ~32 stop bit which has a logic va~ue 0~ n 0~ . Thi~;
compl~tes tran~mi~3ion of the 33 bit message onto the n~twor k 7 ~ .
W~en the message counter 160 has counted to 32 bits i~:8 }30W line iq upplied to a transmi~c of f fl~p-10p 192 ~o that a tr~nsmit of f signal (TXOFFN) d~lop~d by th~ f llp-f lop 192 . Th~ TXOFFN 9 ignal i~ ~ployed to r~et the ~tatus latch 174 and tne tr~n~nDit control latch 180. When ~che tran~mi~
control latch 180 i~ re~et i~c~ TXONN ouéput line re-sets the transtnit ENABLE latch 184. The reply latch 172 i3 re~et ~y timing pul~es STBAD d~veloped in ~he framlng logic of th~ demodula1:or 150, a~ will be de~cribed in more det~il hereinafSer.

9~3 ^ In Fig. 14 there is shown a block diagram of the dlgi~al ~C ao when operated in an expanded sla~ mo~e and showing the operation of the device 80 S in re~ponse to an ena~le interface instruction. It will be cecalled ~ro~ the pcevlous description that in the expanded mode, pin 24 (DATA) of the digital IC
is used as a bi-directlonal serial data line by means of which data stored in the serial shift regi~ter 152 may ~e read out ~y an associated microcompuger, 3uch as the m~crocomputer 84 (Fig. 1), or dat~ from the microcomputer can be loaded into the regi~ter 152.
Also, pin 26 of the device 80 act3 ~s a ~erial clock (SC~) input by means of which serial cloc~ pul~es supplied from the acsociatec microcomputer 84 ~ay ~e connected to the cloc~ input o~ the register 152 to control the shift of data fro~ thi~ register onto th~
data output pin 24 or the clocking o~ data pl~ced on the DATA pin into the r~gi~ter 152. Also, pin 25 of the device 80 (R~) is connected as a read-write con~rol line ~hich m~y ~e controlled by the a sociated microcomputer 84 to con~rol either the reading of data from the register 152 or the writing of data into thi~ register rom the microcomputes 84.
25 The RW line i~ also u~ed ~y the microcomputer 84 to force 'che digit~l IC B0 to transmit the data present in it~ r~gl~ter 152 onto the network 78 in the 33 ~i~
~e3~age for~ of thi~ network. Pin 9 of ~he devic~
80 functions a~ an interrupt line ~INT1 to the 30 mlcrocomputer 84 in ~he expanded mode and ~upplies an int~rrupt ign~l in re~ponse to an ena~le interface in~truotion which informs the micro 84 that a mes~age int~nd~d for it has been ~tor~d ~n the register 152.
An in~errupt signal is also prsduced on the INT line 35 afer 'che device 80 ha~ tran~m$tted da'ca loa~d into the regi~telr 152 onto the network. Pin 8 o~ th~ de-vice 80 ~upplie~ a ~u~y 3ign~1 (BUSYN) to the 1!~3~0-~7~3 ciated micro a4 whenever a message is being rec~ived by the.device ~0 or a me3sage i5 being transmitted by this device onto the ne~work 78.
It wi}l ~e under~tood that: the bloc~ dia-gr~m o~ Fig. 14 ~ncludes only the circuit components and logic gatec which are $nvolved .Ln set~ng up an interface with the a-q~oclat~d m~cro 84 and the bi-directional tran~mi3sion of data and control 3ignals between the micro 84 and the d~vice 80. In Fig. 14 it is assumed that a mes$age h~ been received from the central controller which contain~ an instruction to establish an interface with the ~Issoeia~ed micro-computer 84 in bitC B3-BS of the me~age and th~t th~
instruction decoder 166 has decoded this instruction by produclng an output on itC ena~le interface output line (EINTN). Also, when the device 80 i~ operating in an expanded slave mode pins l and 27 are grounded and the expanded mode line EMN i~ high.
In the expanded mode o~ operation of the digital device 80, a 3erial ~tatu~ regi ter 200 i~
employed which includ~s a BC~ error regl~er U642 and an RX/TX regi~er U644. The BC~ er~or register U642 i~ serially connected to the output of the control ~it register U528 in the serial snift regi~ter 152 over the CONTROL line. The RX/TX register U644 is ~erially connected to the output of the BC~ error re-gi~te~ U642 ~nd the output of the register 544 is ~upplied ~hrough an inverting tri-~tate outpu~ circuit U762 to tb~ bi-d~rectional ~erial DA~A pin 24.
~ 30 It will ~e recalled fro~ ~he previou3 di~-cus~ion of Fig. 1~ tha~ when th~ digital d~vloe 80 receive~ a me3sag~ ~ro~ the cen~ral con~roller which include3 an in~truction it will not execute that in-struction unle~ the ~CH co~parator 162 (Fig. 12) provide~ a BCHO~ output whioh indic~te~ that ~ach bit of the BC~ ~rro~ code in the rec~ved ~e~ag~ co~-pare~ equally wi~h the BC~ error cod~ co~puted ~n the devic@ 80. The ~Cil error re~ister U642 is et or re-set in . accordance with the BCHOK output from the BCH
compara~or 162. The BCH error regi~ter U642 is reset wh~n the initial me ~age is received req7ues'cing that 5 the interface be establi~hed ~ecause this in3truction would not have been execut:ed if it wa~ no~ error-free. E~owever, once thi3 interface has been ~et up the central controller may 3end addi tional mes~ages ~;o the microcomputer 84. During receipt of each of the~e additional tnessages the }3C~1 comlparator 162 com-pare the BCH error code contained in the received me~ age with the BC8 error code canpllted ~y the com~
puter 154 and will indicate an e~ror by holding the BCHOK line low if all ~its of the two codes are not 15 'che same. If the BCHOK line is low the BCi~ error register U642 i5 set. Howev~r, ~ince the interface has already ~een set up, this second mes~age stored in the regi~ter 152, which contains an error, may be read out by the micrc:cosnputer 84 by 3uccessively 20 clocking th~ SCK line and reading the DP.TA 1 ine. The presence of a loqic ~1~ in the ~CH error register po~ition (second ~it) of the data- read out by the microcomputer B4 indicate~ to the mic~vcomputer 84 'chat an ~rror in transmi~s~on has occur red and that 25 ~he microcomputer Ihay wiRh to ask the central con-troller ~o rep~at th~ me~sage.
~ he RX/TX register U644 is employed to }n-dl6:~te to the microcomputer 84 whe~her or not the ~r~a~ ~hift regi~ter 152 i~ loa~ed or empty when it 30 rec~v~ an interrup~ signal or~ ~che INr line, If the regi3ter 152 has been load~d with a received message ran ~be c~ntral controller the RX/TX register U644 is set. WhQn the micro read~ out the data ~tored in the register 152, the serial shift register 152 and ~y~35 the c~e~al -qtatus register 200 are back f il~l,ed with zeroes 90 that when the resdout i~ comple~e~ a zero will ~e s~ored in the RX/TX regi ~er U644. When data .~7~

i~ then loaded into the register 152 and transmit~ed out to the network thi zero remains stored in the RX/TX reglster since it is not used during transmis-. sion. According1y, when an interrupt is produced on the INT 1lne after the message i~ transmitted, the RX/TX register U644 remains at 2ero gO as Eo ~he in-dicate to the microcomputer tha~ the message has been sent and the regi~ter 152 is empty.
When the digital IC 80 i9 arranged to re-ceive a mess~ge from the netwvrk 78, the switches U759 and U760 have the p~ition qhown in Fiq~ 14 ~o th~t the output of the demodulator 150 $s ~upplied 'co the data input of the ~erial ~hift r~gi~t~r 152 and ~he received message may be cloc~ed into register 152 ~y means of the BSHFCLK pu1ses applied to the cloc~
input of the register 152. However, as soon a~ an enable interf ace command has been executed in tbe IC
80 control of the register 152 switches to the a~50-ciated microcomputer 84 by actuating the switches U759 and U760 to the opposite posi'cion. This insures that data which ha~ been ~tored in the register 152 during the received message is pres~rved for tran.~-mi~sion to the microcomputer 84. It is important to swi~ch contro1 of th~ regi~ter 152 to the microcompu-ter 84 immediately because the ~icro might not be a~le to re3pond immediately to its interrupt on the INT line and an incoming message might write over the data ~n the register 152 ~efore the micro reads out thl~ data.
- 30 While the interface is esta~lished to the microcomputer 84~ no more ne~work tr~nsmis~ion~ will ~e demodulated and placed in the qerial shift regis-ter 152 un~ he microcomputer 84 relinquishe3 con-trol. However, after control is ~hi~t~d to the micl:ocomputer 8q, the digital demodulator 150 conti-nue~ to demodulate ne'cworlt rne~age and when a net-wor~ mea~age is rece~ved produces a ~ign~1 on it~

~.,7~3 R~qDETN output lineO This 3ignal ls transmitted t~ough the NAND gate U671. Th~ output of the NAND
gate U671 i~ inverted to produce a BUSYN outpu~
signal to the a~sociated microcomputer 84. The microcomputer 84 is thus inormed that the device 80 ha~ detected activity on the networ~ 78. This activity ~ight be that the central controller is at-tempting to communicat~ with the microcomputer through the enabled slave mode digital IC 800 When the digital IC ~0 i~ transmitting a ~es~age back to the central controller over the network, as de~crib~d her@tofure, the TXONN signal developed by the tr~nR-mit control latch lB0 (Fig. 13) al~o supplies an ac-tive low sigrlal to the BUSYN output pin to ~nform the microcomputer 84 tnat a message i being transmitted by the digital IC 80 to the cen~ral contxoller over ~he network 7~.
Considering now in more detail the manner in whic~ control of ~he regicter 15~ is ~hited from 20 the network to the microco~puter 84, wben the ena~le interface com~nd is decoded by th~ instruction de-coder 166 it produce~ an EINTN out~ut which sets an ena~le interface }a'cch 202. Tbe low ou~put of the latch 202 i~ com~ined with the master slave signal 25 EMN, which i~ high in the expanded 31ave mode, in the NA~ ga~e U7~9 ~o a~ ~co provide as~ active higtl signal on the ENA~I.E outpu'c of ~:he NAND gate U749 which is on~ input of the NAN~ gate U686. Ass~ ing that the other input vf the NAND gate U686 is also a 1, the 3û outpult of U686 goes low which is inver~ed in ~he in-ver~er U736 ~o that the UPS~N line goe~ high. The UPSLN line i employed to control the -~witches U75~
and U760 and when it i-~ high ~witche~ th~ data input of t~le regi~ter }52 ~o ~he ~i-direc~ional 3erial DATA
35 line through inverter U547 and the cLoclc inpu~ of the register 152 to the ~er ial clock SC~ lin~ re pae-ticularly, the UPSLN line dlrectly controls switc~

~;~7~2~3 U760 ~o that the SCK serial cloc~ line is connected ~o the clock inpu~ of the register 152. Also, the UP5LN line through the inverter US47 is one input of the NOR g~te U597 the other input of which i~ the RW
S line which $s normally high due to an internal pull up resistor in the dlgital IC 80. Accordingly, a high on the UPSLN line causes the ~witch U75~ to dls-connect the demod outpu~ of 'che mo~ulator lS0 from the data input of the register 152 only when the RW
line is low.
When the microcomputer ~4 wi~he~ to read the data -~tored in th~ ~erial ~hift regi~ter 152 it does cO by providing serial cloc~ pul~e~ to the SCK
line. At the same time the RW line is high which controls the tri-state output circuit U762 to connect the outpu',: of the RX/TX regis~eer V644 to the bi-directional ~ATA line. Accordingly ~he DATA pin will contain the state of the RX/TX register U644 which can ~e read ~y ~he microcomputer 84. When the UPSLN
line i5 high and the RW lin~ i9 al~o high the output of the NAND gate U683 is low which is inverted by the inv~rter U~00 and applied as one input to the NAND
gate U801 the other input of which is the SCK line.
The output o~ tbe NAND gate U~0l is inver~ed ~y 25 inverter U~02 and is supplied to tne clock inputs of the 13C~I error regiqter U642 and the ~X/TX register U6 ~4 ~o th~t these registers are also shifted ~y pul~ produced by the ~icro on the SCX 1 ine .
Accordingly, when the micro clocks the SCX pin once 30 all of ~he da~a in ~che serial ~hift register 152 and 'che 3erially connected serial ~tatus regi~ter 200 is shifted to the right ~o that the ~tate of the BCH er-ror register U642 will be pre~ent at the DATA pin.
The mic:ro c~n then re~d the 3ATA pin again to o~tain 35 the ~tate of thi~ regis~cer. Thi3 clocking and read-ing proce~s continue~ until the ~icro h~.~ read out of the DATA pin all o~ the data in the serial shi~t 49 519~0 r~gi3t2r 152 and the serial status re9ister 200. In thi~ conn~ction it will be noted that the start bit regi~ter U641 is ~ypassed during the readout opera-tion since i~s information is u~ed only in transmit-ting a me~sage to the network. As indicated a~ove,the stage~ o~ the qerial status register 200 are in-cluded in the chain of data which m,~y be ~hifted out to the microcomputer 84 because these stages contain information which is us~ul to the microcomputer ~4.
It will also be noted th~t when an ena~le interface signal Ls produced and the UPSLN line is high, the RW line is also high which produces a zero on the output of U683. The ~act that both the VPSLN
line and the RW line are high forces switch U75~ to the DEMOD position. However, since the ou~put of U683 is low the da~a input to the serial ~hi~t regis-ter 152 will always be logic zeros. Accordingly, as data is ~eing read out of the register U644 on the DATA pin 24 the register 152 and the serial status register 200 are being back filled with zeros. Afeer the entire contents o thes~ register~ has ~een read out the RX/TX register U644 containa a zero ~o that a zero appear~ on the DATA pin therea~ter. A~ indicat-ed a~ove, when the micro receive~ a second interrupt on the INT line after a message has been transmitted the micro can read the DATA pin and verify that the ~essage h~ been sent.
- Co~3idering now the manner in which the ~t~ge~ of the ~erial 3tatu5 reglster 200 are ~et at the end of ei~her a received m~ssage or a trans~itted mesYage to provide the a~ove-de~cri~ed information to the micro, at th~ end of a received mes~age the mes-sage bit counter lS0 (Fig. 12) produce~ an EOW ~ig-nal whlch `1s com~ine~ with DSHFCLK pulseq fro~ the digital demodulator 150 in the NAND gate U647 (Pig.
14) to p~ovide a ~tatu~ strobe signal STSTB. The STSTB signal is com~ined with th~ BCHOg signal in the NAND gate U660 so that the 8C~1 error regis~er U642 is re~et if the received me~sage was error free. The BC~IOK signal is inverted in the inverter U555 whose output is also com~ined with the STSTB signal in the NAND gate U65~ 50 that the BCH error register U642 i~
set if there wa~ an error in ~he recelved message.
The STSTB signal is also com~ined with the E~ABLE
signal in the NAND ~ate U658 the ou~tput of which is supplied to one input of a ~AND gate U756 the other input of which is the TXONN line whlch i~ high when the device 80 is not transmitting a message. Accor-dingly, ~he RX/TX register U644 is set at the end of a received message.
When the device ao transmits a message to the network the TXONN line is low so that at ~he end of such ~ransmission the STSTB signal does not set the register U644. However, as indicated above, the register U644 is back filled with a zero as data is read out of the register 152. Accordingly, the micro can read the DATA pin, to which the output of the register U644 is connected, and determine that a me~-sage has been ~ransmitted to the network and the register 152 is empty. The register U644 is reset when power i5 applied to the device ~0 and when the interface is disa~led and the ENABLE signal disap-pear-~. This re~et is accomplished through the NAND
gate U657 and inverter U725 which ~:ogether act as an AND gate the inputs of which are the PONN signal and the ENABLE s ignal .
After the micro has read out the data stor-ed in the serial shift register 152 and the status register 200 it can either switch control ~ack to the network immediately or it can load data ir~to the ser-ial ~h~ft register 152 and then command tne device 80 to transmit the data loaded into the regi~ter }52 on-to the network in a 33 bit ~s3age having the aDove descri~ad network forma~ The ~icro switches control back to the network immediately ~y p~lling tne RW
line low and then high~ However, the low to high ~ran~ition on the RW line, which is performe~ ~y the microcomputer 84, occurs a~ynchronously with respect S to the framlng logic in the demodulator 150. Accor-dingly, lt i8 important ~o make sure! that the device 80 sees the ~ero to one transition which the micro-computer 84 places on the RW line. Thi~ transition i5 detect~d by a digital one shot 204 the two stages of which are clocked ~y the STBDD timing pulses from the framing logic in the demodulator 150. The stages of the one ~hot 204 are reset ~y the! RW line 30 tha~
during the period when the RW line i~ held l~w by the microcomputer 84 the output line RWR of the one ~ho~
204 remains high. However, upon the zero to one transition on the RW line the digital one sbot 204 is permitted to respond to the STBDD pul~es and produces an output pulse on the RWR line of guaranteed minimum pulse width due to the fact that it is derived from 20 the framing logic timing pulses in the demodulator 150. The RWR line thu~ goes low for a fixed interval of time in re~ponse to a zero to ~ne transition on the R~1 1 ine .
When the R~R line goes low it sets a buf fer 25 control latch 206 the output o which is connected to one input of the NAND gate U753. The other inpu'c o~
the NAND gate i5 the RW line. Accordingly, afte~ the zero o 1 transition on the RW line this line is high ~o that the output of the MAND gate ~753 is no longer 30 a "la and the UPSLN line goes from high to low. When thi~ occur~ the switche~ U759 and U760 are re~urned to the positions sbown in F1g . 14 so that ~uf fer con-trol i5 shifted from the micro ~ack ~o the network.
Con~idering now the ~ituation where the 35 micro wi~hes to load ~ata lnto the serial shift regis~er 152 and then command the device B0 to tran~-mit the data in the regi ter 152 onto the networ~, ~7a~9;~

the micro f irst pu115 the RW line low which ena~les dat~ to ~e transmitted from the DATA line through the NOR gate U5~8, the switch U75~, the NAND gal:e U~2 and l:he invert~r U730 to the data input of the regis-ter 152. As stated previously, a high on the UPSLNline has al~o cauRed the switch U760 to connect the SCK serial cloc~ line to the cloc~ inpu~ of the register 152. Data from the micro may now be placed on the DAT~ pin and clock~d into the register 152 by the positive clock edges of the SCX clock pulses.
The data entering the register 152 beglns with a control bit having a logic value of ~0~ followed by the least signif ieant bit of the ~uf~er bits B3--B26 and ends up with the most significant bi~ of the ~uffer bits. It should be noted that the micro does not load the start bits register U641.
After this data has ~een loaded into the register 152 the micro pulls the RW pin high. The low to high transition on the RW line after SCK
puls~s have been supplied to the SCR line is inter-preted ~y the device 80 as meaninq ~hat data has ~een loaded into the register 152 and- that this data should now be tra~smitted out to ~he network in the 33 ~it message format of the networ~. To detect this condition a transmit detect flip flop 20~ is employ-ed. ~ore particularly, the clock pulses developed on the SCX line ~y the microc~mputer 84, identified as BS~RCX pul e~, are applied to the cloc~ input of the flip-flop 208 and the RW line is connected to its D
input. When the RW line i5 low and a BSERCK pulse is tran~mitted o~er the SCK line from the microcomputer ~4 the Q output line of the flip-flop 208 goes low.
Thi~ output ls supplied to the NO~ gate U628 the oth~r input o~ which i~ the RWR line. Accordingly, wh~n the RW line is again pulled bigh ~t the end of transmis~ion of data into ~he regi~er 152 th~ R~R
line goes low so that the output of the NOR gate U628 ~.~7~f~

goe~ high~ Thi~ output is supplied as one input to a N~R gate U601 and passe~ through this gate so as to provide a low on the TXSTB line. A low on the TXST3 llne cau~es the device 80 to transmit the data stored 5 ln the serial shif~ register 152 onto the network in the 33 bit network format in exactly the same manner a de~cri~ed in detail here~ofore in connection with Fig. 13 wh~rein the device 80 tran,smitted a reply message back ~o the central controller. Howçver, 10 since the micro does not load data into 'che start bits register U641, it i~ nece~sary to set this register b~fore a message is transmitted.. This is accomplished by the TXSTBA line which goe~ low at the ~eginning of a transmitted message and sets the register stage U641 as shown in Fig. 13.
Accordingly, when the TXSTBA line goe~ high at the end of the 1 bit delay provided ~y the flip-flop 178, the start bits register U641 is set and its logic al~
can be shifted out to form the second half of tbe two Dit start signal of the transmitted message as described previou~ly.
~ hen the transmit ena~le.latch 1~4 ~Fig.
13) is ~et at the start of transmission of this mes-sage, the output of ~he NAND gate U66~ (Fig. 13~ is 25 employed to set the transmit detect flip flop 20~
through the NAND gate Ul;64 the other inputs of which are the power on ~ignal PONN and the ENABLE signal.
When an STSTB s:Lgnal is produced at the end of this tr~n~mitted me~sage in response to the delayed clock 30 pul~e~ DS~FI::LK the TXONN line is low so tha~ the out-put of a N~ND gate U687, to which these ~wo ~ignals are input'ced, remains high leaving the buf fer control latch 206 ~et. This ~ean3 that buf fer control, which wa3 switched to the networ~ at the ~eginning of trans-mission, rem~ins that w~y.
In order to signal the a~ociated micrvcom-puter û4 that an inter~ace i~ ~e$ng et up between 7 ~

the expanded slave mode device 80 and the micro 50 that two-way data transmission over the networ~ is po~ible, the device 80 produces a high on the INT
pin 9 as ~oon as an ena~le interface instruction is decoded ~y the decoder 166. More particularly, when the RX/TX register U644 i~ set at the end of a re-ceived mesqage containing the snab:Le interface in-struction, as descri~ed previously, tbe output of th~
NAND gate U756 is supplied as one input to the NAND
gate U1000 the other input of which is the TXONN
line. Since the TXONN line is high except during transmission a clock pulse is supplied to the inter-rupt flip-flop 210, also identified a3 U643. The D
l}ne of the flip-~lop 210 is connected to the 5 volt supply so that when this flip-flop receive~ a cloc~
pulse its QN output ~oes low, which i~ inverted and supplied to the INT pin 9 of the device 80. This signals the associated microcomputer that an inter-face has ~een established ~etween it and the expanded 2û slave device 80 so that the micro may read the data stored in 'che serial shift register 152 from the ~ATA
pin and load data into this regi~ter in the manner described i~ detail heretofore. As soon as the micro produces ~che f irst pulse on the SCK line, either in reading data from the register 152 or writing data into the register 152, this SCK pulse reset~ the interrupS flip f lop 210 and removes the interrupt sign~l from the INT line. More particularly, this SCE; pul~e is supplied to one input of a NOR gate U1002 the other input of which is the output of a NAND gate U65~. The output of th~ N~ND gate U657 is high when the interface is ena~led and power i9 on the device 8~ so the ~irst SCK pulse resets the in-terrupt flip flop 210.
If the micro loads ~he seridl 3hift regis-ter 152 and instruct3 the expanded ~lave devic~ ~0 to tran~mit this me5sage back to the networ~ the TXONN

line goes low during such transmission, as described in detail heretofore in connection with Fig. 13.
During such ~ransmission the NAND gates U75~ and Ul~00 are blocked 50 that the RX/TX register U644 is s not set at the end of the transmitted message. How-ever, when the TXONN line goes high again ater the message ha~ been tran~mitted the interrupt 1ip-flop 210 is again cloc~ed so that a signal is produced on the INT pin thuq signalling the micro that transmis-sion of a message back to the centrall con~roller ha~been completed. The fact that tran~mi~sion ha~ b~en completed can be verified by the micro by reading the DATA pin which is tied to th~ output of the RX~TX
. register U644 and would show a n 0~ stored in this re-gister. In this connection it will be noted that the micro can read the DATA pin any ~ime that the RW line is high to ena~le the tristate ou~put U762, even though control of the register 152 has ~een shifted baclc to the networ~. Cloc~ing of the interrupt flip-20 f lop 210 i~ timed to coincide witA the trailing edgeof the BUSYN signal on pin 9 so that the INT line goes high at the same time that the BUSYN line goes high.
While the microcomputer 84 may be program-med in any ~ui'cable ma!lnner to receive data from and 25 transmit data ~co the expanded mode slave digital IC
80, in FIG. 15 there is shown a general or high level flow chart fof the microcomputer ~4 ~y means of which it may respond to the interface and establish bi-directiollal commun~ca1:ion with and data transmission 30 to the networ~ 7~ through the digital IC 80. Refer-ring to this f igure, it is assumed that the associ-a~ed digital IC ~0 has received a message which in-clude~ an enable interaoe command ~ut has not yet produced an interrupt on the INT line. Vnder these 35 condition~ the RW line i9 high and the SCK line i5 low, as indicated by the main micro program bloc~
212. As soon as an interrupt occur-~ on the INT line 9~

the ~icro reads the DATA line, as indicated by the ~lock 213 in the flow chart o~ Fig. lS. As described generally heretofore, the ~X/TX register U644 is set at the end of a received m*ssage which include~ an S enable interface command so that the DATA line, under these conditlons is high. Accordingly, the output o~
the decision bloc~ 214 is YES and the micro then reads the contents of the regi~ter 1S2 in the digital IC ~0, as indicated by the process bl.oc~ 215. As de-scri~ed generally heretofore, the micro performs this read out by cloc~ing the SCK line 27 times and read-ing the DATA line on the leading edge of each SCR
pulse. Af~er the 27th SCK pul3e a zero wlll be stored in ~he RXfTX register U644, as described heretofore in connection with Fig. 14.
After it has read the contents of the re-gister 152 the micro has to decide whether it wi~he~
to reply ~ack to the centra} control}er or whether it wishes ~o switch control of the register 152 ~ack to the network without a reply, as indicated by the de-cision block 216 in Fig. lS. Assumlng first th~t the micro wishes to switch control b~c~ to the network withou~ a reply, as indicated ~y the proce~s bloc~
217, the micro aocomplishes this by holding the SCX
line low and pulling the R~ line low and then ~ack high. When oontrol i~ switched ~ac~ to the network, the progr~m returns ~o the main .~icro prog~am to a~ait the oc~urrence of another interrupt on tbe INT
line in response to a message from the central con-troller. In this connection it will be recalled that a~ ~oon a~ the micro sends one pul~e over the SC~
llne to read out the content~ of the register 152 the interrupt FF U643 is re~et and the INT pin goe~ low ag~in.
After reading the content~ of the register 152, th~ microcomp~er 84 mæy wi~h to reply to the central controller ~y loading d~ta into ~he r~gister ~74~3~

152 and commanding the digital IC 80 to transloit a 33 blt m~s~age ~ignal to the network including this data. Under such conditic3ns the c 1tpllt of th~ deci-~ion bloclc 216 i~ Y~S and the microcompu'cer 84 can 5load data into the regi~ter 152 as indicated by the proces~ bloc~ ~19. A~ de~cri~ed heretofore, the micro load~ data into ~he register 152 ~y pulling the RW line low and then serially placing data bits on the DATA line and cloc~ing each bit into ~he regi ter 10152 by the positive clock edges of SCX pulses it places on the SCK line. The d~ta entering the chip begin~ with the control ~it, followed by the l~a5t significant ~it of the buffer bits and ends up with the mos~ significant ~it of the ~uffer bits. The SC~
15line is thus cloc~ed 25 times to load the regi~ter 152.
After the register 152 is loaded the micro read the BUSYN line to de~ermine whe~her it is high or low, as indicated by the decisivn block 220. It 20will ~e recalled that the BUSYN line goe~ low if a me~age on th~ networ~ i~ demodulated by ~he digi~al demodulator portion of ~he digital ~C 80 even though control of the register 1;2 has ~een shifted to the micro computer 84. Also, a burst of noise may be in-25terpreted by the d~modulator 150 as an incoming si~nal. Under the~e conditions the microcomputer 84 hould not commænd the IC 80 to transmit a message on~o the networ~. If the BUSYN line is high the micro then gives a transmit command to the digital IC
3080, ~8 indicated by the process ~loc~ 221. As de-~cribed heretofoce, thi~ command is performed ~y pul-ling the RW line high af tsr it has been held low dur-ing the loading of data into the digital rc 80. Con-trol i~ th~n returned to the main micro program, as 35indlcated in Fig. 15.
After the dlgital IC 80 ha3 ~ran~mitted the data which has ~een loaded into tho regi~ter 15~ onto ~27~9~.~

the network 78 it produces an interrup~ hiqh on the INT line at the end of the transmitted message. In r~ pons2 to this interrupt the data line is again read by the micro a~ indicated by the block 213.
However, at the end of a trans~itted message the data line l5 no longer high since the RX/TX register U644 contains a zero at the end of a transmitted me~sage, as described heretofore. Accordingly, the output of the decision ~loc~ 214 is negative and the program pro-ceedR to the decision hlock 222 to cletermine whether~urther transmission is required from the mic~ocompu-ter 84 to tne centr~l controller. If such tran~mi~-sion is required, further data is loaded into th~ re gister 152, as indicated by the bloc~ 219. On the other hand, i ~o further transmission is required the INT line is reset as indicated ~y the process ~lock 222. As descri~ed generally heretofore, this is accomplished by holding the RW line high while 3p-plying one SCK pulse to the SCK line. This single SCK pulse reset~ the interrupt flip flop 210 (FIG.
14~ and removes the interrupt signal ~rom the INT
line.
It will thu~ be seen that the pre~ent com-munication ~y3te~ p~ovides an extremely flexible ar-rangement for ~idirectional communication between thecentral cDntroller and the microcomputer B4 through the digital IC ~0. After the interface is set up the micro re~dn the meqsage transmitted from the central oontroller to the IC ~0 and can either switch control 30 back to the central controller to receive another m~s~age or may transmi t a mes~age of its own to the central controller. Furthermore, the micro can send a ~erie~ o messages to the central controller by successively loading data into the regi3ter 152 and commanding the digital IC ~0 to tran~mit thi~ data bac~ to the central controller, a~ indicated by ~loc~s 219, 220 and 2~1 in Fig. 15. In thi~ connec-~.~7~

tion it will be understood that after the interfacei5 initially set up in the first messa~e transmitted by the central con~roller, subsequent messages from thi3 central controller to the micro u3e all 24 buf-fer bits a~ data bits and the control bit is a n o~ .
All other devices 80 on the ~ame networ~, whether in the stand alone slave mode or the exp,anded mode, will interpret such a message a~ not intended for them due to the fact that the control bit is re4et, even though the data ~ransmitt~d may have a pattern cor-responding to the addre3s of one of theRe other de-vices ~0. The transmi~sion of data bac~ and fort~
~etween the central controller and the microcompu~er 84 continues until the central con~roller di~a~:Les the interface.
The interface may ~e disa~}ed by a direct disable interface instruction to ~he device 80 a~o-ciated with the microcomputer, in which case the mes-sage trans~itted by the central controller will have a control bit set (~1") and will have address bits corresponding ~o the address of this device ao. . The device 80 ~ill respond to the disa~le interface in-struction by resetting the enable interface lat~h 202 (Fig. 14). In the alternative, the central control-ler can disable the in~erface implicitly by simplytransmitting a mes~a~e over ~e ne~work which is ad-dre~sed to a~other a.~ital IC ~0 in which the control bit i~ set. The in~erface~ digi~al IC 80 will also rec~iv~ thi~ message ~u~ will recognize the occur-rence of a control bit of ~lN together with anaddre~ which i~ not its own and will disa~le the in-ter~ace in re~ponse ts tn~ condition, as will be descri~ed in more de~ail hereinafter. aowever, in the exp~nded slave mode this implicit mode of disa~l-ing the interface will not ~e effective if a BCHerror L~ detected in the r~ceived me~age. Tbis is done becau~e the received me~gage might h~ve been in-tended for the interfaced microcomputer but a noiseimpulse cau~ed the control bit to be demodulated as a ~e ql~ in~tead of a 2ero~ Under these conditions, the ~C~OK l~ne will no~ go high a~ the end of the receiv-ed message and thi~ condltion is used to maintain theint~rface, a~ will be descri~ed in more detail here-inafter.

A~ discussed generally heretofore, the digital IC ~0 may also be pin conf.igured to operate in an expanded master mode as indicated at ~tation ~4 in FIG. 1. In the expanded master mode the devicle 80 is permanently interfaced with a microcomputer 86 so that the microcomputer ~6 can operate a~ an alternate controller and can send shea and restore load signals to any of the stand alone slaves 80 of the communication networ~ if the central controller 76 is inactive and does not place any messages on the network. This interfac~ is permanently established when the MODEl pin l of the device 80 at station ~4 is ungrounded, as shown in Fig. 1, so that the EMN
line in Fig. 14 is always low and ~ne ENABLE line is always held high through the NAND ga~e U749. The expanded mas~er device 80 a~ station #4 should have an addres~ which is different from the address of any of the other device~ 80 on the line 78 so as to permit the central controller to communicate with the micro~omputer 86.
The microcomputer 86 can also establish co~munication over the pow~r line 7~ ~ith the ~icroco~puter 84 through the expanded slave IC device at station ~3. To esta~lish such two way co~munication, the microcomputer 86 merely transmits data to the expanded mast2r device 80 over the bidirectional DATA line which data includes the addre~ of the expanded slave device 80 at station ~3 and an enable interface instruction. The expanded ~f2J7~

maqter 80 includes this data in a 33 bit message forma~ed in accord~nce with ~he protocol required by the communication networ~ and transmits this message over the power line 78 to the expanded slave 80 at s station #3. The expanded Alave B0 at this station re~ponds to the enable interface instruction by establishing the ~bove de~cri~d interface with the microcomputer 84 after which the bidirectional ex-change of data ~etween the microcomputers ~4 and 86 is made possible in the manner described in detail heretofore.
A diqital I~ 80 which is pin configured to operate in the expanded master mode is al50 used a~
an interface ~etween the central control computer 88, 15 which may comprise any microcomputer or main frame computer, which is employed to con~rol the remote stations connected to the central controller 76 over the power lines 78. The expanded ma~ter device 80 associated with the central controller 76 should also 20 have an address assigned to it which is different from the address assigned to any of the other digital IC's on the line 78, including the -~igital IC ~0 at station ~4 associated with the microcomputer 86.
This is true even th~ugh the interface to the central control compu~er 8~ is ~lways enabled as discussed previously in connection with the expanded master de-vice ~0 at ~tation ~4.
Since the expanded master digital IC's 80 a~soci ted with the cen~ral computer 88 and the micr~computer ~6 each produces a BUSYN 5 ignal when-ever it is receiving a message from the networ~, the presently decc~i~ed communicatiorls and control system permit~ the use of multiple ma~ers on the same net-woek line. If, ~or exa~pl~, the microcomputer 86 wi~he~ to send a m~ss~ge to any other point Ln the sy~tem, inclu~Lng the central controller 76, the microcomputer 86 can monitor i~ BUSYN line to see if ~7~

any message is on the networ~ at that time. In the ~ame manner, the central controller 76 can monitor lt~ ~USYN line be~ore ~ending a message to be sure the microcompu~er 86 i5 not sending or receiving a me~sage at that time.
5~o As will ~e recalled from the preceeding general discu~sion, the coupling ne~work 90 provides bidirectional coupling between the network 78 and the digital IC ~0 which iq tuned to the carrier frequency of 115.2kHz. The coupling network 90 also provides amplification of the received signal and limits this signal in both the positive and negative directions to five volts pea~ to pea~ ~@fore it is applied to lS the RX input terminal of the device ~0. The coup~ing network 90 also couples the transmi~ter output termi-nal TX to the power line and drives it with suffi-cient power to provide a signal of 1 volt runs ampli-tude on the power }ine 78 when the device 80 is transmitting a message onto the networ~.
In FIG. 16 a coupling network 90 is shown which is particularly sui~a~le for applications wherein the device 80 i5 ~0 be associated with a con-trolled unit, such as a hot water heater or freezer, in a residence~ In such applications a +SV supply for the device 80 15 not usually available and the coupling netwo~k 90 of FIG. 16 is arranged to func-tion fro~ She conventional ~ower line and dev~lop a - suit~ble power supply for the device 80. Referring to thi figu~e, the power lines 230 and 232, which mzy be a 2~0 volt AC line, supply power to a load 23~, which may comprise a hot water heater or ~reezer in a re~idence, through a power rel~y indicatea generally at 236 wnich has the normally closed power relay contact~ 23~ and 240. A pro~ective device 242 is connected ~etween the power line 23~ a~d neutral, thiR voltage normally be~ng 120 volts AC. A full wave rec~ifier 244 rectifies the AC voltage on the line 232 and the output of the rectifier 244 is connected through a diode 250, a resistor 248 and a filter capacitor 246 to ground so tha~: a DC volt.age o~
S approximately lS0 volts is developed across the capacitor 246~
In order to provide a suitable voltage level for energizing the device 80, the voltage ac-ross the capacitor 246 i~ connected through a resis-tor 252 to a Zener diode 254 across which a voltage of ~ 10 V. is developed, a capacitor 256 b~ing con-nected across the Zener dlode 254 to provid~ addi-tiona} filtering. A volta~e regulator, indicated generally at 258, is connected acro~s the Zener diod~
254 and is arranged to developed a regulated ~5 vol~s at its output which is connec~ed to the Vdd pin 28 of the device ao. The voltage regulator 25~ ~ay, for example, comprise a type LM309 regula~or manufactured by National Semiconductor Inc.
A trans~ormer 260 is employed to provide ~idirectional cs:~upling between ~che networ~ 78 and the device 80. The transformer 260 i~cludes a primary winding 262 and a econdary winding 264, the primary winding 262 being connected in ~eries with a capaci-tor 266 between the power line 232 and neutral. The two winding~ 262 and 264 of tbe transformer 260 are decoupled 30 ~S to permit the winding 262 to func-tion a~ a part of a tuned re~onant circuit which in-cludes the capacitor 266, this resonant circuit being tuned to the carrier frequency of 115.2 kHz. More particularly, as shown in FIG. 16A the core structure of the trans~ormer 260 is formed by two ~ets of op-po~ed E shaped ferrite core ~ec~ions 2S8 and 270 opposed E shaped ferrite co~e sections 268 and 270 the opposed leg~ of which are ~eparated ~y a small air gap. Preferasly, these core ~ections are m~de of type 814E250/~E2A ferrite material made by the Ferrox ~7~93 Cube Corp. The winding 262 is wound on the opposed upp~r ~eg portions 272 of the sections 268 and 270 and the windinq 264 is wound on the bottom leg sec tions 274. The winding~ 262 and 264 are thu~ de-coupled by the magnetic shunt ~ormecl by the opposed center legs of the core ~ections 26~ and 270 so as to provide su~stantial decoupling between these wind-ings. The winding 262 has an inductilnce of 0.2 mil-lihenries and consists of 100 turns of AWG~36 wire.
The winding 264 has an inductance of 7.2 millih~nries and consists of 600 turns of AWG~40 wire. The turns ratio ~etween the primary winaing 262 and the secon-dary 264 is thus 1:6. The air gaps ~etween the opposed legs of the core sections 26~, 270 are pre-fera~ly 63 mils.
The upper end of the winding 264 is con-nected to the 150 volt potential developed ~cros~ the capacitor 246 and the bottom end of this winding i~
connected to the collector of a high voltage NPN
transistor 2U0 the emitter of which is connected to ground through a small re~istor 2S2. Prefera~ly, the tran~istor 2~0 is a type MJE 13003 ~shich is manufac-tured by Motorola Inc. In ~he alternative, a high voltage FET type IR720 manu~actured ~y International Rectifier Co~ may be employed as the transistor 2~0.
The bottom end of th~ winding 264 is also connected through a cap~citor 284 and a pair of reversely con-nected diode~ 286, 288 to ground.
When a modulated carrier message is trans-~itted over the power line 232 to the remote locationof th~ device 80, the on-off Iceyed carrier signal may have an amplitude in the ~illivolt range if the mes-sage has been trancmitt~d a substantial distance ove~
the pow~r line. The winding 262 and capaci tor 266 of the coupling networ~ ~0 act as a ~irs~ resonant cir-cuit which i8 tuned to the car~ier frequency of llS.2 kHz and has a Q of approxi~ately 40. The winding 26~

~74~93 and the capacitor 2~4 al50 act as a re~onan~ circuit which is ~uned to the carrier frequency. Prefera~ly, ~he capacitor 266 is a polypropylene 400 V. capacitor having a capacitance of 0.01 micro~arads. The capa-S citor 284 preferably has a value of 270 pico~arads.
I the siqnal on the line 232 ha an amplitude of 10 millivolts, for example, approximately Q times the input voltage will be developed acros9 the winding 262 i.e. a signal of 400 millivolts amplitude. The signal developed acros-~ the winding 264 is increased by a factor of 6 due tv the turn~ ratio of the trans-former 260, and i5 coupled through the capaci~or 2~4 to a filter network which includ~s the serie~ resis-tors 2~0, 292, and 2~4. A shunt re~istor 296 is con-nected between the resis~ors 2~0 and 2~2 and groundand~ a small capacitor 2981 which prefera~ly has a value of 100 picofarads, is connected between the junction of the resistors 292 and 294 and ground.
The output of this filt~r circuit is sup-plied to one input of a comparator 300 the other in-put of which is connected to ground. The comparator 300 may, for example, comprise on~-section of a quad comparator commerci~l type LM239 manufactured by Na~ional Semiconductor, Inc. The ccmpara~or is 25 energized from the + 10 V. supply developed across the Zener diode ~54 and lts output i3 supplied to the RX pin 6 o the ~evice 8û. This output is also con-nected thsough the re~istor 302 to the five Yolt out-put of the ~egula~or 25~. A small amount of posi~ive feedback is provided for the comparator 300 by means of the re~istor 304 which i9 oonnected b~ween the out~ut of the comparator 300 and the plu5 input ter-minal thereo, the resistor 304 preferrably having a value of 10 megohms. The slight positive feed~ac~
provided by the ~e~istor 304 creates a small dead band at ~he input o the comparator 300 so that a signal of approximately 5 millivolt~ i~ required to ~4~9~

develop a signzl in the output and noise voltages ~low thi~ l~vel will not ~e reproduced in the output of th~ comparator 3Q0. However, when the incoming signal exceed~ a five millivolt level it is greatly S amplified, due to the extremely high gain of the com-parator 300 so that an amplified carrier signal of five volts amplitude is developed across the resistor 302 and is applied to the RX input termina} of the device 80.
Considering now the operation of th~ coupl-ing network 90 during the transmission o a message from the device 80 to the network, the modulated c,ar rier signal which is developed on the TX pin 10 of the device ao is coupled through a capacitor 306 to lS the ~ase of the transistor 280. This ~ase is also connected through a diode 308 to ground and through a resistor 310 to ground. The transis~or 280 is a high voltage NP~ transistor so that the collector of this transistor oan ~e connected through the transformer winding 264 to the 150 volt supply appearing across ~he capacitor 246. The capacLtor 306 is provided to couple the TX output of the device ~0 to the ~ase of the transistor 280 ~ecause when power is applied to the device 80 the TX output pin 10 assumes a five volt potential which would destroy the ~ransistor 280 if the capacitor 306 were not provided.
The tran~istor 280 is turned on and o~f ~y th~ ~odulated carrier signal which is coupled to the baQe of thi~ transistor through the capacitor 306 and hence develops a voltage of approximately 150 volts aero3 the winding ~64 during the carrier on portions of the tran~mitted message. When the transistor 280 is ~urned off there i~ a substantial current being draw~ th~ough the winding 264, which cannot change instantan20usly, so ~hat a large bac~ EMF pulse is also d~veloped across the winding 264. Th~ reversely connec~ed diod~s 2~6 and ~ protect the rec~iv~r in-put circuitry in ~oth polarities from the high vol-tage pulse~ which are deve}oped across the winding 264 during the transmit mode. Ho~ever, it will be understood that the diodes 286 and 288 do not conduct 5for small amplitude signals and hence the received carrier signal may be coupled through the capacitor 284 to ~he comparator 300 withou~ :interference ~rom the diodes 286 and 288.
The large carrier voltage developed across lOthe winding 264 i~ stepped down in the transformer 260 and drives the power line 232 so that the 33 bit message developed by the device 80 may be transmitted over a substantial distance to the central control-ler. At the carrier frequency the power line 232 15will have a very low impedance of approximately lO
ohm5 whereas the reactance of the capacitor 266 is about 300 ohms at the carrier frequency. According-ly, the power line is essentially driven in a current mode.
20Considering now the manner in which the de-vice 80 controls the relay 236 and i~cs associated load 234 in response to ~ shed loa~ ins~ruction, the relay 236 i provided with a high current coil 320 which controls th~ high current relay contacts 238, 25240, the coil 320 ~ing connected in series with the normally clo ed contacts 322 and an- SCR 3~4 to ground. The othe~ side o the relay coil 320 is con-nected 'co th~ unfiltered full wave rectified output of th~ rectif i2r 244 . A relatively low current hold-30ing coil 326 i~ also connected from this point to the drain ele~rode of an FET 328 the source of which is connected through the resistor 330 to ground. The COU~ pin 8 of the device 80 i3 connected to the gate el~ctrod~ of an FET 332 th~ drain el~ctrode of which 35is connected to the +5 V. supply 'chrough the re~istor 334 and the source is connected to ground. The drain ~L~7~3 of the FET source is connectea to the gate o~ the FET
328.
When power is applied to ~he device 80 the COUT pin goe~ high which causes the F~T 332 to con-duct and the voltage developed across the resistor 334 holds the FET 3~8 nonconductive. Accordingly, there is no current flow through the resistor 330 and the SCR 324 is held off. When a shed load instruc-tion i5 received by the device 80 the COUT line goes low which turns of the FET 332 and causes the FET
328 to conduct. The voltage produced across the re-sis~or 330 turn~ on the SCR 324 50 that the relay coil 320 is energized and opens the main relay con tacts 23~ and 240. At the same time, the normally closed contacts 322 in series with ~he coil 320 are opened. However, since the FET 328 i~ conducting the relay coil 326 is energized and holds the contacts 238, 2~0 and 322 open. However, the coil 326 has an impedance su~tantially greater than the coil 320 so that only a small current is required to hold the contact~ of the relay 236 open. When a r~store load instruction is received by the device 80, the COUT
line again goes high and the FET is rendered noncon-ductive so that tbe coil 326 is no longer energized and the normally clo ~d contacts of the relay 236 are again clo~ed. Since the relay 236 has no auxiliary contacts to provide status feed~ac~, ~he STAT1 and STAT~ pins 26 and 25 are connected bac~ to the COUT
pln 8 of tbe device 80.
If it i~ desired to have a varia~le time out feature, as discus~ed in detail heretofore in connection with Fig. 11, the~TOUT pin 9 and the TIMR
pin 24 of the device 80 in FigO 16 may b~ connected in the manner shown in Fig. 11 to provide a var iable time ou~ fea~ure in association with the relay 236.
It will be under~tood tbat the coupling network 5~0 can ~e of very small phy~ ical ~i ze due to 7~

the f~ct that the coupling transformer ~60 is rela-t~ively small. The coupling networ~ 90, the device 80 and the control devices 332 328 and 324 may all be loeated on a small circuit ~oard whic~h can be mounted within the hou~ing of the relay 236 ~o as to provide an addres~able relay in a simple and economical man-ner. Furthermore, existing relays can be converted into addressa~le relays ~y simply in~talling such a Doard and making appropriate connections to the power line.
It will ~e appreciated that in many in-stanees the controlled deviee associated with the digital IC 80 will have a low voltage ~.C. pawer ~up-ply which is provided for other logic circuits in the controlled device. In such instance, the coupling network of Fig. 16 can be modified a~ shown in Fig.
17 to operate directLy from a low vQltage D.C. power source. Referring to this figure, only the portions of the network of Fig. 16 are shown which are chang-ed from the arrangement of Fig. 16. Specifically, the upper end o~ the winding 264 is connected to a ~24 volt supply (assumed to be availa~le from the con~rolled device) and the bottom end of the winding 264 is connect~d through a resistor 340 to the drain electrode of an FET 342 the source of which is c~n-nected to ~round. Prefera~ly the FET is a power FET
commercial type 2N6660. The gate of the FET 342 is corlnected to ground through the diode 3G8 and through the capacitor 306 to the TX terminal of the device 80. The dra$rl of 'che FET 342 is also coupled through a dlod~ 344 and a resi~tor 346 to a light emitting diode 34~. In the circuit of Fig. 17 the voltage regula~or 258 and compara'tor 300 are of a suitable canmercial type to ~e energized ~irectly from the +24 V. ~upply. Since a lower D.C. voltage is availa~le in the circuit of Fig. 17 both of the windirlg~ ~62 and 264 of the transform~r 260 of Fi9~ 17 ha~e the 7~

same number of turns, i.e. 100 turns of AWG ~36 wire, and the capacitors 266 and 284 are both 0.01 u~d.
capacitors.
In operation, the circuit of Fig. 17 re-ceives an on~o~f modulated carrier signal ~rom the power line 78 wh~ch is coupled through the transform-er 260 without step up ~ecause both windings 262 and 264 have the same number of turns. The ~ignal deve-loped across the winding 264 is coupled through ~he capacitor 2~4 and the input filter and co~parator 300, as descri~ed in connection with Flq~ 16, to the RX terminal of the device 80~ In the transmit ~ode the modulated carrier signal on the TX terminal is supplied through the capacitor 306 to the gate of the FET 342 so as to turn this device on and off which produces a modulated carrier current in the transformer winding 264 which is tr~nsmitted to the power line 78. Since the windings 262 and 264 have the same num~er of turns in the embodiment of Fig. 17 there is no step down of the transmi~ted signal in passing through the transform~r and hence the level of ~he transmitted message in the power line 7~ is a~ou~ the same as the em~odiment of Fig. 17 even though the 24 V. supply is approximately one ~ixth of 25 the +lSO V. sup~ly in the em~odiment of Fig. 16.
The I,ED 348 will indicate the per iods dur ing whicn the device 80 is transmi~ting a messa~e to the netffor~ 78.

Figs. 18 to 33, inclusive, when arranged in the manner shown in Fig. 34, comprise a detailed ~chematic diag~am of th~ digital IC 80 de~cribed generally heretofore. Generally speaking, in this schematic diagram the logic signals which are deve-loped at the outputs of various portions of the schema~ic are given a letter a~breviation which ends with NN" whenever that particular ~ignal i~ an ac~ive 7 ~

low output~ Otherwise the ~ignal is active high.

Considering now in more detail the digitaL
receiver-demodula~or 150 and its associated start ~it detection and framing logic, it should first ~e pointed out ehat while this demodulator i5 particu-larly suitable for demodulating power line carrier information in high noi~e environments and lends it-self to implementation Ln digital large-scale inte-gration circuitry, such as the device 80, this de-modulator i5 of broad general application and can ~e used wherever it is required to demodulate ASK
modulated binary data. The demodulator may be used by itself since it is readily implemented in digital logic or may ~e used as a part of a larger 5ystem ~5 in the digital IC 80.
As discussed generally heretofore, the re-ceiver-demodulator 150 is arranged to demodulate data tra~smitted over a power line. Power line carrier signals are affecte~ ~y three types of noise:
Gaussian noise, coherent signals/ and impulsive noise. The carrier signal plus noi~e is fed into tne digi~al demodulator 150 through the coupling ne~wor~
~0 which includes an inpu~ f ilter which couples the 25 device 80 to the power line 7~, as descri~ed in de-tail heretofor~ in connection with Fig. 16. This in-put filter produces oscillations ~ringingJ in re-sponqe to the impulsive noise input On ehe one hand lt i~ desirable to reduce the noise power ~and-wldth of the input fil~er, i.e. high Q, while at thesame time there is a need for a relative low Q inpu~
filter to reduce the ring down time as~ociated with inpulsive noise. The filtering action of the digital de~odulator 150 attempts to reconcile the~e two con-flicting requirements.
A~ discussed generally heretofore, the car-rier modulation system employed in ehe digit~l IC 80 ~'7~

is on-off keying of a caerier fEequency of 115.2kHz a?c 300 baud. This modulation sy tem wa~ chosen in preference to phase shift modula~ion at the data rates required because of 'ch~ signif icant phase dis-S turbance~ as~ociated with the power line 78. Thecarrier ~requency of 115. 21~H2 i cho~en ~ased upon spectural analy~es of typical power .Lir3e systems and the 300 baud bit rate is chosen to provide maximum throughpu~ with acceptable error rates.
10The general approach in the digital demodu-lator 150 is to require phas~ coher~nce in the hor~
term i.e. over one and a half carrier cycles, :Eor frequency detectlon, and to ~ense continued phase coherence in the longer term i.e., l/6th of 8 bi~, or 1564 carrier cycles at 300 ~aud, to diRcriminate against impulsive noise. Impuls$ve noise al~o pro-duces frequency information that i9 coherent in the short term but is not perfectly coherent in the longer term. The reason that the longer term iS not 2~ extended to an entire bit or a longer fraction of a bit i~ ~hat the power line produce3 phase discontinu-ities thal: are signif icant over the ~ime interval in-volved. An example of a phase discontinuity ~ing produced on the power lin~ i5 a line impedance dis 25 turbance cau~ed by rectifiers ~aginning to conduct or ~nding conduction in assoc ation with a capacita~ive input f ~ltor . The~e phase di scontinui ties a~e de-tec'c~d and lead to bi~c errors. ~y choosing the in-tegration time of 1/6th of a ~it~ each phase distur-30 bance can lead only to a degradation of 1/6th of abit .
The digital demodulator 150 thus senses ~oth ~requency anà pha~e of an incoming ~ignal over a 1/6th-of a bit interval (approxim~tely 556 micro~
35 ~econds at 300 baud)~ If the input frequency i9 cor-rect and maintains pha~e coherenee for at le~t three foueths of the l/6th bit interval, a counter is ~27~93 inc~emented. After 5iX of these 1 6th ~it intervals are pr~ce~ed, the counter contents are examined. If the counter count~ up to four or more ~assuming that it ~tarted out at o)~ the demodu:Lator outputs a s demodula~ed logic 1. If the counter content are less than ~, the demodulator outputs a demodulated logic 0.
Referring first to the ~loc~ diagram of the digital demodulator 150 ~hown in ~IG. 35, an oscil-lator and timing cu~system 400 is employed to pro-vide all o the timinq ~ignal~ and stro~es for the other portions of the dçmodulator 150. A 3.6864 MHz _0.015% oscillator is employed to drive these ~iming circui~s. The carrier input ~ignal which is ampli-fied and limited in the coupling network ~0 and is applied to the RX input terminal of the device R0, is inputted to a pair of carrier confirmation circuits 402 and 404, these circuits wor~ing ~0 out of phase with respect to each other. Each of the carrier con-firmation circuits 402 and 404 examines the input signal and determines if it iR within an acceptable band of frequencies centered about tne carrier. This is done on a cycle ~y cycle basis. Each carrier con-firmation circuit has two outputs. One output pro-duces a pul~e if the signal is within the pass ~and and the ~ampled pha3e of the input signal is a logic 1. The other produceq a pulse if the signal is with~
in the pa~ band and the sampled phase of the input 3ignal is a logic 0. The four outputs of the carrier confirmatlon circuits 402 and 40~ are used as cloc~
input~ to a ~eries of four pha~e counters 406, 408, ~10, 412 which ar~ reset every 1-6th of a ~i~. At 300 baud each ~it contain~ 384 cyclec of the 115.2kHz carrier. Therefore, a sixth of a bit contains 64 carrier cycles. Should any one of the phase countets 406-412 count up ~o 48 or more, there~y indicating phase coherence over three fourths of the sixth ~it ~t~ 7~ ~

interval, a logic 1 is produced at the output of a four input OR gate U166, the four inputs of which are the outputs of the phase counter 406-412.
The output of the OR gate U166 i~ connected to the start bi~ detection an~ ~raming logic Lndicat-ed generally at 414. Considered generally, the first logic 1 input to the circuit 414 triqgers the tact ~it detector. The start ~it detector then releases the rese~ on a counter and increments it at intervals of one sixth of a ~i~. This coun~er then counts 11 more sixtb bit intervals. At the end of each six~ch Dit interval the outpu'c of the OR gate U166 i8 stro~ed and causes this same counter to increment if it is a logic 1. At the ~nd of the 12th interval, the counter is examined. If the counter contents are 8 or more, two valid start ~i~5 are a~sumed. The counter then resets and six one-sixth bit intervals are counted off. At the end of each interval again the ou~put of the OR ga~e U166 is strobed and incre-ments the counter if it is a logic 1. The counter isexamined at the end of each 5iX one-sixth bit inter-vals~ If the counter indicates 4 ~r more a demodu-lated logic 1 is provided on the demod output line.
If the counter indicates less than 4 a logic zero is demodulated. This process is repeated 30 more times to yield a complete word of 32 bits ~including the two start ~ts). If in the ~eginning the counter doe~ no~ coun~ up to ei~ht over a ~wo ~it interval, th~ ~tart bit logic 414 resets itself and looks for the next logic 1 ou~ of the OR gate U166.
Considering now in more detail the carrier confirmation circuits 402 and 404, each o~ these cir-cuit ,sa~ples the carrier input at twice the carrier frequency of 115.2kHz. The only difference between the two circuits is in the phase of the sampling, the circuit 402 sampling 90 out of ph~e with rea~ect to circuit 404. Referring to Fig. 36, the ~ 3tro~e ~,~7~ 3 ~ample~ of the carrier confirmation circuit 402 are indicated ~y the downwardly directed arrows relative .o the incoming carrier and the ~0 stro~e samples of ~he carrier confirmation circuit 402 are indicated ~y S the upwardly directed arrows. It can be seen from Fig. 36 that b~cause of the quadrature sampling of the clrcuits 402 and 404 the uncertainty of sampling the carrier input signal around its edges is elimi-nated ~ecause if one of ~he circuits 402 or 404 is lG sampling the carrier ~ïgnal in the area of transition from high to low the other circuit is ~ampling the carrier siqnal in the middle o~ the square wave car-rier input. Accordingly, ~y simultaneously counting the outputs of bo~h of the carrier confirmation cir-cuits 402 and 404 one can be sure that one of them is sampling the incoming carrier square wave signal away from its edges.
Each of the circuits 402 and 404 stores itsthree most recent sample~, each sample representing a half cycle strobe o~ the incoming carrier. After every other sample the circuit will produce a pulse on one o two outputs provided the ~hree storea sam-_ples form a one-zero-one or a zero-one-zero pa~tern.
The pul~e will appear at one output if the most re-cent sample is a logic 1 and will appear at the otherif the mo~t recent ~ample is a logi~ 0. It can thus ~e s~en th~t an outpu~ pulse will occur on one outpu~
on e~ch o~ th~ c~rcuits 402 or 404 every 8.68 micro-second~ should the alternating pattern of half cycle ~ampl~s continue. By requiring 3 consecutive samples of the input to be opposite in phase, the demodulator lS0 places a more strict criterion on acceptance of an input a~ the valid carrier signal than would a circuit which looks only at the two most recent half cycle ~ample~. Thi~ technique o~ requiring three consecut~ve salQples of the input to be oppo~ite in phase has been found to be very ef~ective in rejec~

d~ 3 ing noi~e in the intervals with no ~ignal present and the carrier confirmation cireui~s 402 and 404 are ef-fective in rejectinq all frequencies except the odd harmonic mult$ples of the carrier frequency.
Considering now the details of the carrier conflrmatlon circuits 402 and 404, and referrin~ to Figs. 18 and 19 wherein these circu$t~ are ~hown in the detailed schematic diagram of the d~vic~ 80, the 3.6864MHz oscillator signal which is developed by the crystal oscillator connected to pin's 3 and 4 of the device 80 is divide~ down ln the divider ~tage~ U102 and U103 so as ~o provide a 921.6kHz signal which is u~ed to clock a two st~ge Johnson counter comprising the stage~ U104 U105. The Q and QN output~ of the stage U105 comprise oppositely phased ~quare waves of a requeney twice the carrier requency of 115O2k~z.
These outputs are supplied through the inver~ers Ul~
and U40 to act as clock signals for the carrier con^
firmation circuits 402 and 404. However, the circuit 402 ;s clocked when U18 goes positive and U40 goes negative whereas the circuit 404 is clocked when U18 goes negative and U40 goes posltive so that the cir-cuits 4~2 and 404 strobe the incoming carrier 90 apart on the carrier wave.
In order to provide a circuit which stores the 3 most recent samples of the incoming carrier a two ~tage shift register iq clocked at twice carrier ~requency. Thus, considering the carrier confirma-tion circult 402, the shift register stages U113 and 3~ U114 are cloc~ed at twice the carrier fr~quency, as de~crlbed heretofore; the output of each ~tage being exclusi~ely ORd with i~ input ~y means of the ex-clu~iv~ OR ga~e~ U133 and U134, re~pectively. The exclu~ive-OR outputs of the gates 133 and 134 are anded in the NAND gate U137 the ou~put of whlch i s inv~rted ln the inverter U35 and applied to the D
input of a register stage U115. The incoming carrier ~'7~
~ 77 51930 on ehe RX pin 6 is applied through the inverter U25, ~he N~ND ga~e U133, and the inverters U16 and U39 to the D input of the first register stage U113. The other input of the NAND qate U139 i~ controlled by the TXONN ~ign~l so that no carrier input is supplied to the carrier confirmation circuit~ 402 and ~0 while the device ~0 iq transmitting.
Assuming that a one-zero-one pattern exists on the D input to shift register stage 113, the Q
output of this 3tage and the Q output of register stage V114, tnis mean~ that the past sample, which is 2ero, i~ stored in U113 and the ~ample before that, which is a one9 i5 stored in U114. However, the pre-sent sample on the b input of U113 has not yet been store~. Under these condit$ons, the outputs of the exclusive OR gates U133 and U134 will ~e one, the output of the NAND gate U137 will ~e a zero which is inverted an~ applied to the D input of the regi~ter staqe U115. On the next clock pulse the Q output of U115 will ~e a one. If, at the time of this cloc~
pul~e the D input to U113 remains a one, ~his one is clocked into U113 so that its Q output is a one which represent~ the stored present sample at the time of this clock pul~e. Th~ Q outpu~ ~f the stage U115 is suppl~ed a~ one input to the NAND gates U15~ and U159 ~ and the Q output of the stage U113 is supplied di~ectly a~ ~nother input to the NAND gate U15~ and through the inv~r~er U36 as another input of ~he NAND
ga~e UL5~.
A strobe ~ignal occurring a~ carrier fre-quency i~ applied a a ~hird lnpu~ to ~he NAND gates U158 and U159. More particularly, the stages of the Johnson counter U104 and UlOS are com~ined ln ~h~ NOR
gate~ V66 and U65 ~o prov1de twice carrier frequency slgn~l~ which are applied to a ripple counter com-pri~ing the stages U106-UllO. The input and output o~ the first scage D106 is com~ined ~n NOR gat~ U130 ~.~7~
7~ 51930 to provide a strobe at carrier frequency for the N~ND gate3 U158 and U15~. In this connection it will be noted that the Q output of the stage 115 is always a l irrespective of the 101 or 010 patterns set up at S the inputs and outpu~ of the stage~ Ul13 and Ull~.
However, the Q output o~ the stage rJil3 i~ ~upplied di~ectly to the NA~D gate U15~ and through the in verter 136 to the N~ND gate Ul59. Accordlngly, only one of these NAND gates will be enabled depending upon the condition of the Q output of the ~tage Ul13.
When this output i~ a O the NAND gate Ul59 will pro-duce a pulse on the ZEROA output l:Lne w-hereas when the Q output of the stage U1~3 is a one the NAND gate U158 will produce a pulse on the ONEA output line.
It will thus ~e seen that the pulse on either the ONEA out~ut or the ZEROA output of the carrier confirmation circuit 402 mean~ that over ehe relatively short term of one and a hal~ carrier cycles the input carrier is generally in phase with the timing signals esta~lished in the device 80 through the crystal oscillator 102. The term gener-ally i5 u~ed because a given pattern may contlnue to be produced even though ~he incoming carrier shifts in phase by a substantia~ amount, as shown by the dotted line in Fig. 36. If the same pattern con-tinues, thu~ indicating that the incoming signal con-tinue~ to b~ in pha~e with the timing circuits of the device 80, an output will continue ~o ~e produced on either th~ ONEA output or the 2EROA output of the ci~cu~ 402 e~ch carrier cycle.
The carrier confirmation circuit 404 oper-ates subgtan~ially identically to the circuit 402 ex-cept that it is cloc~ed opposite to 402 so that the incoming carrier signal is strobed at a 90 p~int relative to the carrier con~irm~tion ci~cuit 402.
Thu~, if the circuit 40~ tro~ing the incoming carriet near the edges o~ the carrier, ~nd hence may .~ 7 ~

not qiYe a relia~le 101 or 010 pattern, the carrier confirmation circuit 404 will ~e strobing the incom-ing carrier midway between i~s edge~ so that a reli-able pattern ls obtained by the circuiLt 404.
S A~ de~cri~ed generally heretofore, the phase counters 406~412 are e~ployeld ~ep~rately to count the number oE pulses developed on the four out-puts of the confirmation circuits 402 and 404 during a time interval equal to l/6tn of a bit. If any of these counters reaches a count o~ 48 during the 64 carrier cycles which occur during a l/6th blt inter val at 300 ~aud, or 12 out of 16 at 1200 baud, it is assumed that a valid carrier signal exi~ted for that 1/6th bit interval and an output is supplied to the lS OR gate U166. More particularly, referring to Figs.
19 and 20 wherein the counters 406 412 are shown in detail, and considerin~ the phase counter 406, the ONEA output of the carrier confirmation circuit 402 is supplied through the NAND gate U140 as the cloeK
and notclock input to a ripple counter comprising the stages U71-U76. At. 300 ~aud~ when the counter 406 reaches a count of 48 the Q outputs of the R16" stage U75 and the ~32" stage U76 are combined in the NAND
gate U141 th~ zero output of whioh is supplied to the NAND gate UL66 which OR8 the zeroes outputted by the count@r~ 406-412 and corresponds to th~ OR ~ate U166 of Fig. 26. When the ccsunter 406 reaches a count of 48 the output of the NAND gate U141 is suppli~d bac~
to the oth~r input o~ the NAND gate U140 to disa~le 'che input Of the counter 406 during the remainder of the l/6th ~i t in~erval . In a similar manner, the phase oollnter 4û~ Gounts ehe pul~ developed on the ZE~OA outpu~ of the carrier con~irmation circuit 402, the pha~e counter 410 counts ehe pulses on the ONEB
output o~ the carrier confirmation circuit 404 and the pha~e oounter 41~ count~ ~he pulYe~ on the Z~OB
output of the circuit 404.

'9~3 S193~
The digital demodulator 150 is thus capa~le of rece~vlng a transmitted message even though the received carrier Rignal drifts con~inuously by a sub~tantial amount ~hroughout a received message tran~mitted at 300 ~aud. This i~ achleved by providing the pha~e counting channel~ 406-,412 all of which only counts over an interval of' one ~ixth bit.
The received message may drift ~ufflcien~ly relative to one of these channels during one eLxth of a bit to alter the 101 or 010 pattern of one of the carr~er conf irmation circuits ~02 or 404 but the other will not have the pattern altered over thl~ in~erval.
Thus, referring to Fig. 36, if the received carr.ler dri~ts to the left ~y a substantial amount ~s indicated by the dotted line in Fig. 36, the 101 pattern of the 0 sa~ples will not change ~ut the 90 sample pattern changeQ ~rom 101 to 010 ~y virtue of this carrier driftO The 0 samples will thus glve a valid one sixth ~it count with ~his amount of carrier d~ift even ~hough the ~0 samples will not. By ORing the outputs of all of ~he phase connector 406-412 several one sixth bit lntervals may be successively counted t!lrough dif ferent phase counter~ and there~y accommoda~e su~stantial dri~t ~ in either direction ~etween the received carrier and the sampling stro~es ~` developed in ~he demodulator 150. As a result, the 33 bit received message may be demodulated without the use of a pha~e lock ioop or other ~ynchronizing ci~cuit ~nd even though the crystal oscillators at the central controller and the remote station are operating asynchronously and at slightly differen~
frequencies.
A~ di~cus~ed generally hereto~ore the phase counter~ 406-412 also count the pha3e coherences o~ the carrier confirmation circui~s 402 and 404 over only a 1/6th ~lt in~erval so as to avo~d any pha~e di~tur-~ances whlch may be produced on the power line used ~74~

as the network tranqmi5Qion medium. Accordingly, the pha~e counters 406-412 are reset after each 1/5th bit interval. More particularly, the output of tne ripple counter U106 110, the input of which is cloc~ed S at twice carrier frequency, is supp.lied through the switch U122, the 1nverter5 U873 and 874, the switch U128 and the inverters UB67 and U17 to a two stage Johnson counter comprising the stage~ Ulll and U112.
The output of this counter is a signal at l/64th car-rier frequency which is equal to a 1/'6th ~it interval at a 300 baud rate. Accordingly, th~ output of the inverter Ul5, which is connected to the Q output of the stage U112, is employed to reset the phase counters 406-412. More particularly, the output o~
lS the inverter Ul5 is supplied as a clock input to the flip flop Ul72 the D input of which is connected to the ~SV supply. The Q output of ~he stage Ul72 is coupled through the inverters U20 and U50 ~o the RSTPHAS line (reset phase countees) anG resets all of the phase counters 4()6-412. The stage U17~ is reset by the output of the NOR gate U65 which is delayed with respect to the output o~ the NOR gate U66 which controls the ripple counter U106-UllO.
Consider$ng now in more detail the start ~it detection and ~raming logic portion of ~he demod-ulator 150, the Johnson counter comprising tbe stages Ulll and Ul12 is employed to develop a num~er of tim-ing ~ignals which are employed in the start ~1t de-tection and framing ~ogic circuits. More particular-ly, the inputs and outputs of the stages Ulll and Ul12 are combined in a series of NOR gates U670U10, Ul32 and U200 to provide a num~er of stro~e signals.
The nomenclature and tlm$ng of these strobe signals is shown in Fi9. 37 wherein the waveform 37(a) is the output o the ~witch U128 whlch occurs at 24 times ~lt r~ at 300 ~aud. The output of the NOR gate U6?
is identified as STBAD and is shown in F~g. 37~b).

7 ~

The output of the NOR gate U132, identlfied as STBB, i 8hown ln ~ig. 37(c). The output of the NOR g~te U68, $dentified as.STBBD, is ~how~ in Fig. 37~d).
The output of the NOR gate U69, identi f ied as STBCD
is qhown in Fig. 37~e). The output o the NOR ga~e U200, identified as 5TBD, i5 ~hown i~ Fig. 37(f) and the output of the NOR gate U70, identified as STBDD, is ~hown in Fig. 37.~9).
Should one of the phase counters ~06-412 counts to 4~ durin~ a 1/6th bit Lnterval and the OR gate U166 produces an output, a ~lt framing counter 420 (Fig. 22) has its reset released and is in~remented by one. The ~it fræminy counter 420 is initially set to count 12 l/~th ~it interv~ls to pro-vide a framP of reference to determine whe~her the incoming signal co~npri~es two start bi~s ~oth having logic ~1" values. At the same time a demodulator counter 422 (Fig. 21) is employed to count the num~er of outputs produced ~y the OR gate U166 from any of the phase counters 406-412 during the two ~it inter-val esta~lished ~y . the bit framing counter 420. If the demoaulator counter 422 counts to 8 or more dur-ing thi~ two bit interval a valid ~tart ~it is assum-ed. On the other hand, if ~he counter 422 has a count o~ less than ~ when the counter 420 has counted to 12 the framing logic is reset and waits for the next logic 1 out of.the OR gate U166. More particu-l~rly, when the O~ gate U166 produces an output it is ~upplied through the swltch U12~ to the D îrput of the flip flop U95 (Fig. 22) which is clocked by the output of the Johnsç~n coun~er stage U112 near the end of each l/6th ~it interval. When the flip f}op U~S
goes high it clocks a flip flop Ull9 the D input of which i3 connected to the +SV Supply 90 that the QN
output of ~ goes low. This output, through the NAND gat~ ~162, the inverter U53, the NOR gate U176 and the invercer U54, controls the bit ~eset }ine .

~ ~ 4~ 1~3 (BITRST) so that the reset on both of the counters 420 an~ 422 is released~ Also, the ~it framing counter 420 i~ incremented ~y 1 ~y means of the ST~AD
pul~e ~Fig. 37(b)) which is supplied through the in s verter U~65 to cloc~ the first stage U98 of the coun-ter 420. Also, when U95 goes h$gh i.t i~ anded with the STBAD pulse in the NAND gate U]L55 which incre-ments the demodulator counter 422 by 1.
When the bit framing counter 420 has count-ed to 12, which occurs two bit intervals later, the "4" and "8" output stages U100 and U10} thereof are supplied to the NOR gate U131 the output of which se~s a frame latch comprising the NOR gateQ U169 and U170. This latch produces an output on the FRAME
line which is anded with the STBB pulses (Fig. 37tc~) in the NAND gate U153 the output of which 1~ inverted in the inverter U58 and supplied as an input to the NAND gate U152. The other input of the NAND gate U152 is the Q output of the last stage U121 of the demodulator counter 422. Accordingly, if during the fir~t two bi~ interval the demodulato~ counter 422 ha~ received 8 or more cloc~ pulses from the flip flop U95, which indicates that the phase counters 406-412 haVe collectlvely produced an output for ~ of the 12 1/6th bit intervals corresponding to the two start ~it~ of a received message, the Q output of the . last stage U121 will be high and the output of the NA~D gate U152 is employed to se~ a received word detect latch U151 and U165. When this latch is set the RXWDETN 11ne, which is the inve~ted output of thiq latch, goes low for the remainder o a received message. This RXWl:iETN signal pa~se~ through the NAND
gate U171 to one inpu~ of a three input NAND gate U163 the other two inputs of which are the frarne out-put of the latch U16s, U170 and the STBaD stro~e pulses ~Fig. 37(dJ). Accordingly, when the ~XWDETN
line goes low after the frame latch has baen s~t the ; 7~ r~'93 8~ 51930 NAND gate U163 produce~ an GUtpUt which is inverted in the.inverter U567 to produce shift register clock pul~es on the BS~FCLK line. The output of the demoa-ulator counter ~22 passes through tne NOR ga~e U29 and the inverter U63 to the D~MOD ou~put llne as soon as the counter 422 counts 8 1/5th ~it in~ervals.
However, the demodulated data is not; clocked into the serial shift register 152 until B';HFCLK pulses are produc~d at the end of the two start ~it framing in-terval when the output of the NAND gate U163 ~oeslow. After the BSHFC~K pulses are produced th~ STBDD
pulses are com~ined with the F~AME signal in the NAND
gate U164 so a~ .to produce delayQd ~hift regi~ter clock (DSHFCLK) pulses which occur after the BSHFCLK
pulses and are used at various points in the devlce 80, as descri~ed heretofore. The DEMOD output line of the demodulator 150 is supplied through the switch U758 (Fig. 31) to the input of the 8CH error code computer 154 so as to ena~le this computer to compute 20 a BC~ error code based on the f irst 27 bits of the received message. The DEMOD ou~pu~ is also supplied through the switch U75Y (Fig. 27) to the input of the serial ~hift register 152, as will ~e described in more detail hereinaf~cer. The DEMOD output is also supplied to the du~l function pin 22 of the device ~0 when thi~ device ls operated in a test mode, as will be descri~d in more.detail hereinafter.
Th~ RXWDETN line also controls resetting of the counters 420 and 422 since when this line goe~
low it indicateq tha~ a valid start ~it of two ~it lnt~rvals ~ength ha~ ~een received. More particular-ly~ the RXt~DE~N llne is supplied through the NAND
gate U16 2 and the inverter U53 to one input o~ a three input NO~ gate U176. The STBCD strobe pulses 35 are and~d with the frame signal in tne NAND gate U150 and invert~d in the inverter U55 to ~upply another input to the NOR gate U1~6. The third input of this NOR gate is the intern21 reset line INTRES which is normally low. Accordingly, an output is supplied from the NOR ga~e U176 in response to the low output produced by UlS0 whlch ls inver~ed in the inverter U54 and supplied to the bit reset 11ne BI~ST to reset the ~it framlng counter 420 and the demodulator counter 422.
After a .valid start bit has been received, which lasted for two bit intervals, it i~ neces~ary to adjust the ~it ~raming counter 420 so that it will count up to only 6 to ~et the frame latch U169, Ul?0.
Thi~ is accompli hed by combining the RX~DETN signal, which passes through th~ NAND gate U201 and the inv~r-ters U202 and U~61, with the STBAD pulses whlch are supplied as the other input to a NAND gate U~62 through the inverter U866.. As a result, the N~ND
gate U~62 supplies a clock signal through the NAND
gate ~864 to the second stage U99 of the ~it raming counter 420 while the output of the first stage U~
is bloc~ed ~y the NAND gate U860. Accordingly, the stages U100 and U101 of the counter 420 are com~ined in ~he NOR ga~e U131 to set the rame latcb U16Y, U170 at a cQunt of 6 for the remaining bits of the received m~ssage. ~ ~
With regard to the demodulator counter 422, it will be recalled ~hat if this counter counts to four during the next ~it interval, i.e. the phase counter~ 406-412 have collelctively produced an output for four l/6th bi~ in~ervals during the next full bit interval, le is assumed tha~ a logic 1 has b~en received. Accordingly, the Q output of the stage U120 is also connected through the NOR ga~e U29 to the DEMOD line. In ~his connection it will be understood ~hat while the stage U120 produces an output during the ~tart bit framing interval before a count of 8 iq reached.in ~he counter 422, this output appearing on the D~MOD line i~ not used tO load the ., . 86 51930 shift register 152 because no BS~FCLX pulses ~ave ~een produced at ~hat time. The STBDD stobe pulses ~Fig. 37~g~J, which occur at the end of a 1/6th ~it interval, are us~d to re~et the fr~me 12tch U169, U170 at the end o~ either the initlal two star~ ~it framing cycle or at the end of each succeeding ~it lntarval.
If the ~it framing counter 420 counts to 12 during the initial two ~tart ~its interv~l and the demodulator counter 422 dve not count up to 8 or more during this period it is a~sumed that two valid ~tart ~its have not ~een received and the flip flop Ull9 is xeset as well a~ the counters 420 and 422.
More particularly, if the counter 422 doe~ not count to 8 or more the RXWDETN line is high which appears as one input to the ~AND gate U149. The other input o~ this NAND gate is a one when the STBCD stro~e pulse is nanded wi~h FRAME so that the output of the NAND gate U164, identif ied as RSTWORD goes high ana 20 re~ets the f}ip flops U~5 and Ull~. When tnis occurs the ~ not output of Ull9 goes high and the output of NAND gate U162 goes low whlch passes throu~h the NOR g~te U176 and cause~ the BITRST line to go high which resets the counters 420 and 422.
At tne end of a 33 bit message the EOW
- line from the me~s~ge bit cour.-er 160 yoe~ high and sets the latch U167, UI6~ so that the OUtpl~t of this latch, whiCh is one input of the NAND gate U148 goes high~ Upe:~n the occurrence of the ST~D pul~e to the 30 other input of the NAND gate U14~ the RXWI~ETN latch UlSlt U165 i~ reset so that the RXWDETN line goes h~gh indicating ~he end of a messaqe. Also, a low on th~ output of the NAND gate U148 produces a higb on the output of the NANI) gate U164 wh~ch re~ets the 35 ~llp f lops UY5 and ~JllY .
From the a~ove detailed description of the digi~al demodulator 150, it will ~e ev$dent that this 3~7~J9~

demodulator is particlarly suita~le for receivinq and ~emodula~ing on off keyed carrier message~ transmit-ted over a power line which may have phase distur-bances which produce large ho].es in ~he received mes-~ag~. This is because the pnase counte~s 406-412 can detect a valld l/6th ~it when 16 Otlt of the 64 car-rier cycles are missing from the received signal.
Also, the demodulator counter 422 can indlcate a valid "logic 1" when 2 out o the six l/6tn ~it in-lG tervals are missing in the received mes=age. In Fig.
38 there is shown the test results of the dlgital de-modulator 150 wh~n used in different noi~e environ-ments. Referring to this figure, the abci~ a i~ a linear ~cale of signal to noise ratio in DB ana the ordinate is a linear scale of ~he bit error rate.
For example, a bit error rate of 10-3 is 1 bit ~rror in the detection of l,000 ~its. The curve 424 in FIG. 38 show5 the bi~ error rate of ~he digital de-modulator 150 when an input signal ampli~ude of 100 milivolts peak to peat~ i~ mixed with different ampli-tudes of white noise to provide different signal to noise ratioq. This lO0 milivol~ input ~ignal plus noise wa~ applied to ~he input of the coupling net-work 90 (in pl~ce of tne power line 232 (FIG. 16)) and the signal to noise ratio was measured at ~he - junctio~s of capacitor 284 and the diodec 286 and 2~8 in the coupling network of Fig. 16 with a spec~rum analyze~ having a b~ndwidth of 300 Hz. ~he curve 424 ~hows that at a signal to noise ratio of 17 DB a bit er~or rate of l in lO0,000 is achieved. At a qignal to noise ratio of 9 a bi~ error rate of l in l,000 is achieved. For comparison, the curve 426 ~hows the theoretical ~$t error rate curve for a diferentially coherent pha~e shift ~eyed -qi~nal wi~h whlte no~se.
Curve 42~ in Flg. 3~ ~hows the bit error r~te o~ tne d~modulator 150 wh~n u.~ed on a power line in~tead of ' with a white nolse generator. Slnca it wa~ not .
.

88 51g30 possible to vary the noise level of tne power line, dlfferent value~ of signal input were employed/ point A on the curve 428 being o~tained with a ~ignal input of 30 milivolts peak to peak and point: B on the curve S 428 being obtained with a signal in~ut of 60 mili-volts peak to pea~.
By oomparing CUrYeS 424 and 4~, it will ~e seen that the digital demodulator 150 provides suh-stantially Detter performance i.e. lower ~it error rates when used w$th the power line than when the input signal i5 mixed with white noise. ~his is ~ecause the power ~lne noise is pr imarily impulsive whereas the white noise signal is of uniform distrihution throughout all frequencies. The digital lS demodulator 150 is particularly designed to provide error free bit detection in the presence of impul3ive noi e, as discussed in detail heretofore.
The bandwidth of the digital demodulator 150 ha3 also ~een measured ~y applying a sweep generator to the RX input pin of ~he device 80 and sweeping through a ~and o frequencie~ ce~tered on the carrier frequency of 115.2 kHz. It was foun~ that the demodulator 150 totally rejects all frequencies yreater than 1.2 ~z away from tne carrier frequency (115.2 kHz) except for odd harmonies of the carrier the lowest of which is; 3 times the carrier frequency.
A~ discussed generally heretofore, the di-gital IC ao c~n be pin conf igured to opera~e at a 1200 ~aud rate when the device 80 is to ~e used in les noi~y environmen~s such as the dedicated twisted pair g2 ~hown in Fig. 8. In accordance with a fur-ther aspect of ~he disclosed system thi~ modification is accompllqned in the digital demodulator 150 by simply re~etting the pha~e coun~ers 406-412 every 16 cycles of carrier rather than every 64 cycles of car-rier. Al~o, the input to the Johnson counter Ulll, U112 is stepped up by a factor of 4 ~o that all of the strobe signals (Fig. 37) developed in the output of this counter, which repeat at a 1/6th bit rate, are increased by a factor of 4. More particularly, when the ~AUD0 pin 2 of the device flO ls grounded a low ~ignal is coupled through the inverters U24 and U4g to con~rol tha switch U122 so that ~he ou~put o~
the stage U10~ in the ripple count:er U106-UllO is supplied to the Johnson counter Ulll, U112 through the switch U12~. At the same time thi~ signal con-trols the switches U123, U124, U125 and U126 ~Fig.
19) to delete the first two stages o~ each o the phase counters ~06 412 from their recapective counting chains so that these counter~ now hav0 only t~ count up to 12 during a .16 ca~rier cycle ~it interval in order to indicate à valid 1/6th ~it pulse on the out-put line thereof. However, all of the digital circuitry, described in detail heretofore in connec-tion with the operation of tbe demodulator 150 at a 300 baud rate, continues to function in the same man-ner for input data received at a 1200 ~aud rate whenthe baud zero terminal i 5 g~ounded. Also, all of the other circuitry of the digital IC ~0, which has been descri~ed gen~erally heretofore, func~ions properly to receive me sages from t~e networ~ and transmit mes-sages to the networ~ at the increased ~aud rate of - 1200 baud by simply grounding the BAUD0 pin 2 of the device 80.
As discu~sed generally heretofore, tne - digltal IC ~0 may also be pin configured to accept unmodula~ed base band ~ata ~t the extremely high ~aud rate v 38.4K baud. To accomplish this the baud 1 pin 7 of the device ~0 is grounde~ so tha~ the output of the inverter U12 (Fig. 18), which i3 identifi~d as TEST in the detai}ed sch~matic, goes high. When this occur~ the switch U12~ is switched to lt3 A lnput so that th~ 921.6kHz -qignal from the John~on counter U102, U103 is applied directly to the input o~ ~he ,7 ~

Johnson coun~er Ulll, U112. This later Johnson coun-~er thus operates to produce the above described strobe pulses at a ~requency of 6 times the baud rate of 38.4kHz. At the same time the carrier conflrma-tion circuits 402, 404 and the phase counters 406-412 are ~ypassed ~y supplying the Baud 1 signal to the wltch U12~ so ~hat this switch i l:hrown to the B
position in which the RX input is supplied directly eo the D input of the flip flop U~.5. All of the start bit detection and framing logic deqcri~ed in detail bere~ofore in connection with tbe operation of the demodulator 150 at a 300 ~aud rate, will now ~unction at the ~8.4k baud rate.
When the device ~0 is operated at a 3~.4~
~aud rate the Baud 1 signal line is also used ~o con-trol the swltch U761 (Fig. 25~ so that the QN QUtpUt of the transmit.Elip flop U640 is supplled to the TX
output pin 10 of the device 80 through the inverters U733, U740 and U74S. Accordingly, all of the digital 2B circuitry in the device 80 is capa~le of receiving message~ from a low. noise environ~en~, such as a fi~er optic caDle, executing all of the instructions heretofore de3cribed including interfacing with an associated microcomputer, and transmitting messages ~acK to th2 networ~.all at the elevated baud rate of 38.4k baud, 5~,~.~
Considering now in more detail the s~rial shift register 152, this register comprise~ the seri-ally connected stages U536, U537, U535, U515-51~, U533, U534, U529 532, U5~1, U500, US01, US38, U~22, U523, U526, US24, U525, US27, US2~ and ~641 ~Figs.
26-29). As dlscu ~ed generally heretofore the stage U52B stores the con.trol bit of the received mes~age and tbe stage U641 stores a logic "1" for the two start b~ t3 of the r.eceived mes age. The demodulated data of ~ne received mes~age is tranamlt~ed th~OUgh . .

7 ~

the switch U75~, the NAND gate U6~2 and the inverter U~30 to the D input of the first stage U536 of the register 152, this input ~eing identified as BUFDATA.
The BS~FCLK pulses developed in thç demodulator 150 are quppli~d a~ one input ~o a ~AND gate U6~ ~Fig.
29). The other two inputs of the NAND ga~e U69~ are the TXS~BA llne and the GT26N line t~oth of which are high at the beginning of a received me~sage. Accor-dingly, the B~HFCLK pul~es are inverted in the inver-ter U727 and appear on the ENSHF line which is sup-plied through the switch U760 (Flg. 26J and the in-verter~ U540, U543, U544 and U545 to the 3UFCK cloc~
line of the register 152 and through the inver~er U546 to the BUFCKN line, these lines forming the snain cloc~ line~ of the register 152. The register 152 is reset from the internal reset line INTRES through the inverters ~34 and 575 (Fig. 27J. Th~ mann~r in which data may be read out of the regi~ter 152 ~y an a~so-ciated microcomputer or loaded into this regis~er by a mic~oCQmputer has been descri~ed heretofore ln con-nection with Fig. 14.
Address Decoder-l64 .
Referring now to the detailed circuitry of the addre~ decode~ 164, this decoder comprises the exclusive OR gate U57~-U5~Y (Figs. 27 and 2~) which compare the outputs of 12 stages of the register 152 with the 12 address pin~ A0-All, the A0 pin Deing co~pared w~th the output of the 16th stage U500 and the output of address pin All ~e~ng compared wi~h the output of the fith stage U516 of the register 152.
The exclusive OR gate outputs are combined in the NOR
gates U596, U5~3, U5~5 a~d U5~2. the output3 o~ which are further combined in the four input NAND gate U636 (Fig. 2~). If bits Bl1-322 o~ the received m~s8age, wh~ch are ~tored in the indlc3ted staqes o~ the re-gi~ter 15~ all compare equally with the ~ett$ng~ of the addre~s select switehes 120 IFig. 10) which are ~ d 9 3 51930 connected to the address pins A0-All, the output of th~ NAND gate U636 9Oes low, as indicated ~y the ADD~CN output line of this gate.
~5~
Considering now in more det:ail the instruc-tion decoder 166~ the Q ~nd QN outputs of the regis-ter stage.~ U527, U52S and U524 (Fig. 2~), are coupled through inverters tQ a series of NAND gates U691, U6~0, U6~, U6~8, U639, U63~ and U637 (~19. 30) the 10 outputs of which provide tne decoded Lnstructions de-scribed in detail heretofore in connection with Fig.
3.
The manner in which a shed load ln~truction is carried out ha been dascrlbed in d~tall hereto-15 fore in connection with Fig. 12. However, it is pointed out that the SHEDN output of the instruction decoder 166 is supplied as one input to a 3 input NAND gate U698. The other ~wo inputs of this NAND
ga~e are the SCRAMN instruction and ~he bloc~ ~hed 20 instruction BLSHEDN. Accordingly, when either of these other tWQ instructions are developed they are combined with ehe execut~ function in the NAND gate U649 and set the ~hed load latch U651 and U692.
As dlscu~sed generally heretofore, the 2S central controller can iqsue ~lock shed or ~loc~
- restore instructions in response to which a group of six~een s~an~ alone slaves will simul~aneously shed or re tore their loads. More particularly, when a ~lock sh~d instructi~n is decoded the BLSHEDN line goes low and when a block restore instruction is decoded the BLRESN lin~ goe~ low. T~ese lines are inputted to a NAND gate U752 whose output is high when either of the~e ln~uotlons is decoded. The output of U752 is supplled as on~ lnpu~ to the NOR gate U~34 the other input of wh~ch ls the output of U59~ co~respondlng to the four LSB'3 of the addre~5 decoder 164. The NOR
gate U634 thus produces a 2ero even though t~e four ~"~ ;3 ~3~

~S~'s of the decoded address do not correspond to the address ~ssigned ~o these stand alone lave~. The output of U634 is inverted in U566 and providas a one to U636 80 th~t ~he ADDOK goes high and a ~hed load or restore load operation is perorm,ed in all slxteen stand alone slaves. .
Wlth regard to the enable interf ace in-struction EINTN, thls signal is inv~erted in the in-ver~er U699 and com~ined with the execute function in the NAND gate U65~ so as to set the enaDle interface latch U654 and U6~3. A~ discu~s2d generally hereto-fore, when the device ao i5 in t~le expanded slave mode and an enable inter~ace in truction 18 receLved tbis devic~ es~a~lishes the above descri~ed interace with ~he microcomputer 84 which is maintained un~il a disable interface instruction i supplied from the master whlc~ resets the ena~le interface latch ~654, U693. More particularly, a disaDle interface in-struction DINTN is inverted in the inverter U700 (Fig. 2~) and supplied through the NAND gates U633 and U680 to re~et ~he ~atch 654, 693.
It is also po~si~le for the master to di~-able the inter~ace indirectly and without requiring the master to s~nd a disa~le i~terface instr wtion to 2S the device 80 which has already esta~lished an inter-face. More particularly, the ma~ter can accomplish ehe di~a~ling of the interface implic~tly ~y trans-miteing a ~e~sàqe on the network which is addressed to a digital IC at a di~ferent remote statlon, this ~es~age in~lud~ng a control ~it which is set. When ~hl~ occur~, ~3~h devices w$11 receive ~he ~essage transmltted ~y the master. However, the device ~0 which has already established an interface, will recoqnize ehat the ad~ress of the received message is no~ his own, ln which case the ADDOK line l~l9. 2~) will ~e low. This signal is inverted in the lnverter U564 so as to provlde a high on one inpu~ of the NAND

~,~ 7 ~ ~3 .

gate U681. When t~e execute stro~e si~nal EXSTB goes hgh the other input of the NAND gate U681 will be high so ~ha~ a low is supplied to the other input of the NAND qate U680 which resets the latch U6S4, U693 in the ame ~anner as would a disable inter~ace in-struction, When the ADDO~ line is low, the NAND gate U812 is not ena~led so that no EXECU~'E instruction is produced in response to the me3sage addressed to a differen~ digital IC ~0. The ena~le interface latch is also re~et when powe~ is applied to the device ~0 over the PON~ line.
Considering now ehe logic cireuitQ 170 (Fig. 12) employed ~o provide the EXECUTE ~ignal, wnen the ADDECN line goes low it passeQ through the lS NAND gate U~10 to one input of the NAND gate U~12.
It will ~e recalled from the previous general de-scription that lf the control ~it register 52~ is set, the BC~ compa~ator indicates no error in trans-mission by producing a high on the BCHOK line, and the end of a word is reached, all three lines EOW, CONTROL, and B~HOK are high. These three signals are inputted to a NAND gate U748 ~Fig. 32) and pass through the NOR ga~e U604 so as to provide a high on the execute strobe line EXSTB. This line is supplied ~hrough the inv~rter U1005`(Fig. 29) and the NOR gate - U1006 to thq other input o the NAND gate U812 the output of whi~h is inverted in the inver~er U735 to provide a h~gh on the EXECUTE line.
- A~ discussed generally heretofore, the expanded mode slave device 80 will no~ ~isa~le the i~terface to the as ociated microcomputer 84 in re~ponse to a received message with a d1fferent`
addre~, if a BCH error i~ indicated in the received m~age. Thls re~trlction is es~abli~hed ~ecause tne recelved message migh~ have ~een intend~d or t~e expanded mode slave but ~he control bit wa~ garbled in~o a "1" ~y a noise impulse. More particularly, if a .

BCH error is noted in the received message the BCHOK
line w~ll not ~o high and no high will be produced on the EXSTB line. Accordingly, even though the ADDOK
11ne i3 low the NAN~ gate U681 will not produce an output and ~he enable intecace latch U654 and U693 remainq se~ 80 tha~ the interface is no~ disa~led.

Considering now in more detail the mes~age bit counter 160, this counter comprises the s1x ripple counter stages U503 and U510-U514 ~ig. 31) which are cloc~ed by the BSHFCLK pulseq developed by the demodulator 15û. As described generally hereto-fore, the message bit counter 160 eont these pu1.ses from the demodulator 150 and when a count of 32 is reached provides an output on tne EOW line which is the Q output of the last stage U514. The counter 160 al50 provides a strobe pulse for the status latch at a count of 15 and provides both positive and negative GT26 and GT26N si~nals upon a count of 26.
Considering first the manner in which the "15" stro~e i~ produced, the Q outputs of the first and third st~ges 503 and 511 are com~ined in the NAND
gate U869 and the Q outputs of the second and fourth stages are combined in the NA~D gate U~70, the out-puts of these two gates ~eing ANDED in ~he NOR gate --- U871 to provide an. output on the FIFTEEN lina when the indicat~d ~tagqs of the counter 160 are all high.
C3n~dering how the GT26 signals are devel-oped, th~ Q outputs of the second stage U510, the ourth stage U512, and the fiftn stage U513 are com-b~ned in the NAND gate U6g6 so that on a count of 26 this gate produces an output which goes to the NOR
gate U747. The second input to ~he NOR gate U747 is a com~ination of ~he Q outputs of ~tages U503 and U5ll, wh~ch must ~oth be zero for a valld count of 26, in the NOR gate U630. Th~ third input to ~he ~OR
gate U7~2 i8 the ~SHFC~K pulse which, ater a count of 26 in the counter 66Q sets a latch comprising the NOR gates U631 and U6320 When thi5 latch is se~ the GT26 line goes high and the GT26N lines goes low.
It will be recalled from the previou~ g*n-eral de~cription ~hat the message blt counter 160 isemployed during both the reception o a me sage and the transmission o~ a message to count the ~it in~er-vals to determine the end of a word. ~lowever, when ~he device ~0 is neither receiving a message or transmitting a message this counter should be re~et.
Also, it will ~e recalled from the previou~ gen~ral escription that the BUSYN output pin 8 of the device 80 goes low when the device 80 is either receiving a message or transmitting a message to inform the in-terfaced microcomputer of this condition. Con ider-ing first the manner in which the BUSYN ou~put is produced, when tne device ~0 is receiving a word the RXWDETN line is low and when the device ~0 transmit-ting a message the TXONN line is low. These lines 20 are ORed in the NAND gate U671 the output of which is supplied oYer the BUSY~ line and through the B termL-nal of the switch U~53 (Fig. 32), and ~he inverters - U~O~, U741 and U746 (Fig. 33) to the BUSYN pin 8 of the device 80. Accordingly, a negative signal is prod~ced on pin 8 when the device 80 is ~ither re-ceiving or transm~tting a message.
Considering now the manner in which tAe me sage bit counter 16G is reset, it will ~e recalled frotn tne preYic~us general description c~f FIG. 13 ~hat durinq a transmit message a TXSTBA signal is produced by the one bit delay flip flop U646 so as to provide a two ~it i~tervai wide start pulse at the ~eginning of the me~saqe while providing only a count of 1 for ~oth qtart bits. . Accordinqly-, it i~ n~ce~sary to hold the mes~age b.it coun~er 160 reset during the time p~riod of the first start ~it. Thi~ i~ aCcom-plished ~y th~ TXSTBA signal which i5 suppliea ~s one 3 ~7~

input to a NAND gate U6~5 an~ is low auring tne first ~tart ~it. The other two inputs of the NAND gate U695 are the yower PONN signal which resets the mes-sage bit counter 160 when power i'3 applied to the devlce 80 but is oth~rwi~e normal.ly high, and the BUSYN line which.ls hlgh whenever a message i5 being either received or transmitted i.e. a period when the counter 160 ~hould count the bits of the message.
Accocdingly, after the fir~t transmitted start ~it the TXSTBA line goes high and the reset i5 released on the co~nter 160.
~LY_ Considering now the BCH computer 154 in mo~e detail, this computer is instructed ~ased on the polynomial x5+x2+1 ana hence comprises the five stage shif t register U505-U509 (Fig. 32), as will be readi-ly understood by those s~illed in the art. In this connection, reference may ~e had ~o the ~ook ~rror Correcting Codes by Peter~on and Weldon, MIT P~ess 2nd. Ed. 1~2, for a detailed description of the func-tioning and instruction of a BC~ error correcting code. The shift ~egister stages U505-U509 are cloc~-ed by the BSHFCI,E~ pulses developed by the demodulator 150 which are applied to one lnput o~ the NAND gate 25 U672 tne other input of which is the TXSTBA signal -- which is high except dur lng the f itst start ~it of a transmitted message. The output of ~he NAND gate U672 is inverted in the inverter U711 to provide clock pulses for the BCH shift register US~5 U50g~
30 ~he demo~ul~ted data of the received mes-~age is sup-plled through the switch U758 (Fiq. 31) and the NAND
gate U673 (~ig. 32) ana the inverter U712 to one in-put o~ an excl~sive OR gate U577 the output of which i5 cunnecte~ to tne. D input o 'che first stage US05.
35 ~he other input of the exclusive OR gate U577 is the output of a NOR gate U603 having the GT26 line as one input and the yN output of ~he last ~tage U50~ as the 98 ~ l930 other input. During the ~irst 26 message ~it the NOR
gate U~03 and exclusive OR gate U577 act as a recir-culating input from tne output to the input o~ the computer 154. Also the D input of the first stage 505 and the Q output of tne second ~tage ~506 provide inputs to an exclusive O~ gate U590 the output of which is connected to the D input of the third stage U507. Accordinglyr during the recept;ian o the first 26 message bits the computer 154 computes a ~lve ~it BCH error code which is stored in t:he stages U505-USO9. The stage U505-509 of the BC~ error code com-puter are reset concurrently with the message ~lt counter 160 by the output of the inverter U731.
~5~ .
It will be recalled from the previous gen-eral description that fallowinq reception of the 26 meqsage bits the BCH error code computed in computer 154 i compared with the error code appearing as the message bitS ~27-B31 of the received message in the BCH compar~tor 162. More particularly, the Q output of the laQt stage U509 is one input of an exclusive OR gate US~l (Fig. 32) the other input of which is the DEMOD data from the output of the switch U758.
As soon a~ the GT26 line goes hi~h at the end of 26 message bits the NOR ga~e`U60~ ~loc~s the recircula-.-- t~on connection from the QN output of stage 509 to the excluslve OR gate U5~7. The gate U603 thus func-tion~ a~ the swltch 158 in Fiq. 12. At the same time the GT26 line is lnverted in the inverter U713 and ~upplied as t~e second input to the NAND gate U673 50 as to remove DEMOD data from the input to the compu-ter 154. The gate U673 thus performs the function of the switch 155 in ~ig. 12. Accordingly, su~s*quent BSHFCLK pulses will act ~o shift the BCH error code store~ in the register U505-509 out o~ this register for a bit by ~it comparlson in the exclusive NOR gate U591. The output of.this NOR gate i~ supplied as one ~7~

input to a NAND gate U755 (Fi9. 33) the other input o~ which is the QN output of a BCHOK fliæ flop US20.
The flip flop U520 is held reset during transmission by the TXONN line which i5 one input to a NAND gate U750 the output of which is connectea to the reset terminal of U520. U520 is also reset through the other input of U~50 when the counters 160 and 154 are reset. The flip-flop U520 is cloc~ed ~y BSHFCLR
pulses through the NAND gate U676 ~Fig. 32) only after the GT26 line goes high at the end of ~he 26th message bit. When the flip flop U520 is reset its QN
output iQ a one which is supplied to the NAND g,ate U755. When the two inputs to the exclusive NOR gate U5Yl agree this gate produces a one so that the output of U75~ is a æero to the D inpu~ of U520 so that its QN output remains high. If all five ~its o~
the two BCH error codes agree the QN outpu~ of U520 remains high to provide a hLgh on t~e BCHOK llne.
I~ the two.inputs to US~l do not ag~ee~ say on a comparison of the secona ~it in each code, the o~tput of U591 will be a zero and the o~tput of U755 will ~e a one which is clocked into the flip flop U520 on the next BSCHFCI,K pulse . Thi s cau es the QN
output of U520 to go low which is fed back to U75S to cause U755 to produce a one at~its output regardless of the other input from the exclusive NOR gate U5~1.
Accotdlngly, even though the thi~d, ~ourth and fifth bits compare equally and the gate U591 produces a one for these comparisons, the flip flop U520 will remain with a one on its D inp~t so that the QN input of U520 will be low at the end of the five bit comparison and indicate an error in the receive~ message.
~t~t~ ~On~
Considering now ln more detail the manner in whiCh tne sta~us signals on pins 26 and 23 (STATl and STAT2) a~e added to a reply messag~ t~anQmitted Dac~ to the central con~roller as ~itq 25 and 26, it 10~ 3 51930 will be recalled from the prec2ding general descrip-tion that 8 period of time equal to ~iteen ~its is allowed ~or the controlled relay contacts t~ settle beore the status of these contacts is set into the register 1S2. More particularly, when ifteen bits of data have ~een sh$fted out of the regi~ter 152 during a transmitted reply message, the data pre-viously stored in stage U535 has ~een shifted beyond the stages U500 and U501 and hence these stages may ~e ~et in accordance with the signals on STATl and STAT2. The STATl signal is ~upplied to one lnpul: o a NAND gat~ U820 (Fig. 28) the output of which sets stage U500 and through the inverter U825 to one input of a NAND ga~e U~21 the output of which resets the s~age U500. Also, the STAT2 signal is applied to one input of a NAND gate U822 the output of which sets the stage U501 and through the inverter U~26 to one input of a NAND gate U823 the oueput of which resets the s t29e U 5 01 .
It will ~e recalled from the previous des-cription of 'che message bit counter 1 60 that after this counter has counted to 15 the output of th~ NOR
gate U871 goes high~ This signal is supplied as one input to a NAND gate U6~5 (Fig~ 23~ the other input of which is the DSHFCLK pulses so that ~he output of the NAND gate U685 goe~ low near the end of the bit in-terval afte~ a count of 15 is reached in the couneer 160. A3suming that the status latch U662 and U663 ha~ been set in response to a reply instruc~ion, as described previously in connection with FIG. 13, the two inputs to the NO~ gate U59g will be 2ero 30 that a 1 ls produced on tne output of thi~ gate wblch is supplied a3 one input to the NOR gate U678 ~Fig. 29) the othe~ input o~ whlch i5 the IN~RES llne. The ou~put o~ the NOR gate U~7~ is inverted in the lnver~
ter U570, which i~ supplied to the other lnput of all four of the NAND gates U820-U823. Accordlngly, in re~ponse to the FIFTEEN si9nal ~he stages U50~ and U~01 are set or reset in accordance with the signals on the STATl and S~AT2 lines.

A~ discussed generally heretofore, a digital IC 80 may ~e pin configured to operate in a test mode in which the outpu~s of th~ digi~al demodu-lator lS0 are ~rough~ out to dual purpose pins of the device 80 so that test equipment can be connected there~o. More particularly, the digital IC ~0 is pin configured to operate in a test mode by leaving both the mode 1 and mode 0 pins ungrounded so th~t they both have a "1" input due to the internal pull up re-sis~ors within the ~evice 80. The "1" on the mode 1 line is supplied as one input to the NAND gate U838 (Fig. 18) and the l on the mode 0 pin 27 is inverted in the inverters U~27 and U~2~ and applied a~ the other input of the NAND ga~e U83~ the output of which goes low and i5 inver~ed in tne inverter U~46 50 that ~0 the OIN line is high in the test mode. The OIN line controls a series of 3 tristate output circuits U~SS, U~56 and U~57 (Fig. 26) connected r~spectively to the address pins All, A10, and Ag. The l~XWDElN outpu~
line of the demodulator lS0 is spuplied througn tne inverter U831 to the input of the tristate output circuit U855. The DEMOD output of the demodulator 150 is supplie~ through the inverter 830 to the inpu~
of the tri3tate U856 and the ~S~FCLK pulse line from tbe demodulatoc 150 i9 supplied through the inverter U829 to the input of the tristate UH57. The OIN line also contr~ls the All, A10 and A9 addre~s lines ~o that these lines are -qet at "1" during the test oper-ation ~nd hence the ~ignals supplied to the dual pu~
pose address pins P21 22, and 23 during test will not in~erfere in the address decoder portion of the device 80.

The portion of the digital IC 80 beyond the demodulator 150 can be tested at the 38.4k baud rate by applying a tes~ message to the RX pin 6 at 38.4~
baud. This message may, for example, te~t the re-~ponse o~ the device ~0 to a message including a shed load command and the COUT output line can be chec~ed to see if ~he proper response occurs. This por~ion of the digital IC 80 m~y thu3 ~e ~ested in les3 than l millisecond due to the fact that ~he 38.4 k ~aud rate i5 utilized. In this connection it wlll be noted that the ~aud l pin 7 of the device 80 i~
grounded for the test mode so that the switch Ul2 (Fig. 20) bypasses the digital demodulator 150.
~lso, this TEST signal controls the switch U761 (Fig.
25~ so that the TX out pin lO i~ connected direstly to the QN output of the transmit flip flop U640, as in the 3~.4k ~aud rate transmit and receive mode.
The digital demodulator 150 of the device 80 may ~e tested ~y configusing the ~aud O and baud l pins for the desired ~aud rate of either 300 or 1200 and supplying a test message at that baud rate to the RX input pin 6 of the device 8~. The DEMOD, RXWD~TN
signal and the B5C~FCLK pulses which are prod wed ~y the demodulator 150 may ~e chec~ed by examining the dual function p~ns 21, 22 and 23 of the device 80.
9~L~ C~c~it As discussed generally heretofore, tne di-gital IC 80 i~ designed so ~hat whenever ~5V is ap-plied to the Vdd pin 2a of the device 80 the COUT
line i5 pulled high even thsugh no message i9 sen~ to the device to restore load~ Thi~ feature can ~e em-ployed to provide local override capa~ility as shown in FI~. 39. Referring to thi~ figure, a wall ~witch 440 is shown connec~ed in ~erie~ wi~h a lamp ~42 and a set of normally closed relay contact~ 444 ~cross the 115 AC line 446. A digital IC 80 which is opPr-ated in the ~and alone slave mode is arranged to control the relay contacts 444 in respon e to mes-~9~3 received over the power line 446 from a central controlle~. More particularly, the COUT line of the digital IC 80 i~ connected to the g,~te electro~e of an FET 448, the drain of whicn is connected to ground and the source of which i~ connected through a resis-tor 45U ~o the +5v. supply output of the coupling network 90. 1 The source of the FET 448 i~ also con-nected to the gate electrode of a second FET 452 the drain of which is connected to groun,d and the ~ource of which is connected to a relay coil 454 which control~ the relay contacts 444, the upper end of the relay winding 454 ~eing al~o connected to the ~5v.
supply.
The coupling network 90 ~hown in FIG. 39 is substantially identical to the coupling network chown in detail in FIGS. 16 except for the fact that AC power for the coupling n~twork 90, and specifically the rectifier 244 thereof, is con-nected to ehe bottom contact of the wall switch 440 so that when the wall ~witch 440 is open no AC power is supplied to tne coupling netwox)~ 90 and bence no plus five voltY i~ developed by the regulated five volt supply 258 (Fig. 16) in the coupling networ)~ ~n.
In this connection it will be understood tha~ the portion~ of the coupling networ~ ~0 not shown in Fig.
39 are identical to tne corresponding portion of this networ~ in Fig. 16.
In operation, the relay contacts 444 are normally closed when the relay coil 454 is not energ1zed and the wall switch 440 controls the lamp 442 in a conventional manner. During periods when the wall switch i5 closed and the lamp 442 i~
en~rgized AC power i5 supplied to the coupling net-work 90 RO that it is capa~le of receiving a message over ~he p~wer line 44~ and ~upplying tni~ me~sage to the RX input terminal of the digital IC 80. ~ccord-c 7~i~D ~

ingly, if the central controller wishes to turn off the lamp 442 in accordanc2 with a prede~ermined load scbedule, it transmits a shed loaa message over the power line 446 which is received ~y the digital IC ~0 S and tnis device responds to the shed loaa instruction by pulling the COUT line low. The FET 448 iq thu cut off so tha~ the gate electrode of the FET 452 goeq h~gh and ~he FET 452 ic rendered conductive so that the relay coil 454 is energized and the contacts 444 are opened in accordance with the shed load instruction. However, a local override function may ~e performed ~y a per on in the vicinity o~ the w~ll switch 440 ~y simply opening this wall switch and then closing it again. When the wall switch 440 is opened AC power is removed from ~he coupling networ~
and the +5v. power supply in this network ceases to provide 5 volt power to the digital IC 80.
Also, power is removed from ~he FET'S 4~8 and 452 so that the relay &01l 454 is deenergized so that the normally closed relay contacts 444 are closed~ When the wall 3witch 440 is again closed five volts is developed by the ~upply in the co~pling networ~ Y0 and supplied to pin 2~ of the digital IC 80 which responds ~y powering up with the COUT line high.
When this occurs the FET 44~ is rendered conductive and current through the resistor 450 holds the FET
452 of ~o th~t the relay 454 remains deenergized and the contact~ 444 remain closed. If the digital IC 80 powered up with the Ct)UT line low then the relay coi 1 30 454 would be energized on power up and would open the contac'cs 444, thus preventing the loc~1 override feature. I~ will thu~ be seen that when power ls re-moved from a particular area which lnclude3 the lamp 4q2, in accordance with a preprogrammed lighting 35 schedule, the shed load inst~uction from the central controller can ~e overriden by a per~on in the room in which the lamp 442 i3 located by ~imply opening ~7~3 the wall ~witch 440 and then closing it again. This local override function is accomplished substaQtially immediately and without re~uiring tne digital IC ~0 to tranamit a message back to the central contro}-S ler and having the central controller send ~ac~ amessage to ~he digi~al IC ~0 to re~5tore load. In prior ar~ sy~tems such as ~hown in the a~ove mention-ed prior artU~patents Nos. 4,367,414 ~nd 4,396,844, local override is accompli~h~d only by having the re-mote device send a request for load to the centralcontroller which reque~t i~ detected ~y poll~ng all o~ the remote devices, the central con~roller then sending back a me~sage to that p~rticular re~ote station ~o restore load. Such a process take3 many seconds during which time the personnel located in the room in which the lamp 442 has be~n t~rned off are in the dark.
The coupling network 90, the digital IC ~0, the FET' 8 448, 452 and the relay 454 may all be mounted on a s~all card which can ~e directly associ-ated with the wall switch 440 so as ~o provide an ex tremely simple and low co~t addressahle relay station with local o~erride capa~ility.

In Figs. 40 and 42 tnere is shown a serie~ of timing diagrams which illus~rate the ~ime required tc ascomplish various function within the digi~al IC 80. In the accompanying Figs. 41 and 43, th~ time required to accomplish these functions at each of the baud ra~es at which the digital IC 80 i9 arr~nged to operate are also given. All time interval~ given in Figs. 41 and 43 are maximum values unle~ o~herwise indicated. Raferring to Fig. 40, the timing diagram3 in this Fig. relate to the operation of the dlgital IC 80 when in a ~and alone ~lave mode. Thu~, F~g. 40(a) ~howg the length o~ a receiv~d network message (TMJ and al~o ~how~ the ~'7~

delay be~ween the end of the receiYed message and a ,~
change. in poten~ial on the COUT output line of the ~k digital IC 80 (Fig. 40b) . Fig. 40 (c) illustrates the additional delay TR which is explerienced between the time the COUT line i~ changed and the start of a transmitted message when a reply is ceques~ed by the central controller. This Fig. also ~hows the length o~ time ~ST from the start of the transmitted reply message to the ti~e at which the ignals on the STATl and STAT2 lines are stro~ed into the serial shift register o~ the digital IC 80. Figure 40~) shows ~he reset pulse which is eithe~r developed in-ternally within th~ device 80 ~y the Sch~idt trigyer Ul80 (Fig. 1~) or may be sent to the device 80 from lS an external controlling device, this pulse having a minimum width of 50 nanoseconds for all ~hree baud rates. A comparison of Figs. 40(~ and 40(d) also shows the time (TCR~ required to reset the COUT out-put line in response to the reset pulse shown in Fig.
40(d~.
Referring now to FIG. 42, this figure shows the various timing diagrams in connec~ion with the digital IC 80 when operated in an expanded moae in set~ing up the interface with an associatec~ microcom-25 puter and in reading data from 'che serial shif~ reg-i~'cer o~ the device 80 and loading data into this regis'cer. In ~IG. 42 (a) the time delay ~etween the ret:eipt of a lDeqsa9e from the central controller and th~ time the BUSYN line goe~ low ~Fig. 42 (~J ), which i~ identified as the delay TBD, is shown. The time from the end of a received mes~age to the time ~he BUSYN line i~ brought high again is shown by the in-terval TIBD, when compaeing Figs. 42 (a) and (~) .
Al~o, lthi~ same delay is produced in developing an interrupt pulse on the I~T line, as ~hown in FIG.
42~c~.

a~3 ~ comparison of FIGS. 42 (a) and ~2 (f ) shows the time TDM between the end of a received message and the ~ime data is available on the DATA pin of the digital IC 80. A comparison o~ Fig~;. 42 ~c) and ~e~
S show~ the time deLay TIRST between the leading edge of the f irst ser ial clock pulse producecl on 'ch~ SC}~
line ~y the microcomputer and the 'cime at which the device 80 causes the INT line to go low.
Figure 42 (e) shows the width TSCK of the serial clock pulses supplied to the SCK line by the microcomputer, these pul~es having a rninimum width of 100 nanoseconds ~or all ~aud ra~ces. A ~omparison o~
Fig 42 ~e) and 42 (f ) shows the maxiinum ti~e TSD
availa~le to the microcomputer ~co apply an SCR pulse to the SCK line in reading data out of the serial shift regi ter of the digital IC 80. A compari30n of these Figs. also shows the ~et up time TWSU required be~ween the time the microcomputer pu~s data on the DATA line and the time when the microcomputer can thereafter cloc~ the SCK line reliably. A~ 3hown in Fig. 43 this time is a minimum of 50 nanosecond~ for all three baud rates. A comparison of Figs. 42(d) and (g) show~ the time TT required after the RW line is pulled high after it has ~een low for the digital ?5 IC 80 to start tran~mitting a message oneo the net-work. A co~pari30~ of Figs. 42(b) and (d) 3how~ the tl~e TBT ~equired between the ti~e the R~ line i~
pulled high and the time the digital IC ~0 re~ponds by pull~ng th~ BUSYN li~e low.
Obviously, many ~odification~ and varia-tions of the present invention are possible in light of the above teachings. Thus i~ i~ to be under-qtood ~ha~, within ~he scope of the appended claims, the invention may be practiced otherwise than as speci-flcally de~cribed hereinabove.

Claims (4)

108 51,930 WE CLAIM:

1. A single hardware based digital integrated circuit device connected to a communication network line for receiving a massage from a central controller also connected to said network, the received message including a plurality of address bits and instruction bits followed by a set of error checking bits the logic value of which is determined by the preceding bits of the received message, a serial shift register in said device for storing the received message bits preceding said error checking bits, error code computing means included in said device, for computing a new set of error checking bits based on the logic values of the received message bits preceding said error checking bits as said message bits are stored in said serial shift register, means in said device for comparing said new set of error checking bits with a set of error checking bits of the received message on a bit by bit basis and developing an output signal if all bits of the two sets compare equally, means in said device for shifting out to said network line at least certain of the bits stored in said register to form a portion of a transmitted message, means in said device for supplying said certain bits to said error code computing means as they are shifted out of said register so that a set of transmission error checking bits is computed by said error code computing means based on the logic values of said certain bits, and means for supplying said set of transmission error checking bits to said network line as another portion of said transmitted message.

2. A device as set forth in claim 1, which includes means in said device for comparing the address bits of the received message with an address assigned to said device and upon coincidence thereof executing a 109 51,930 control function in accordance with a predetermined combination of said instruction bits.

3. A device as set forth in claim 1, wherein said device includes a control output terminal connected to a controlled element external to said communication device, a status terminal connected to said controlled element to indicate the condition thereof, means in said device for comparing the address bits of the received message with an address assigned to said device and upon coincidence thereof controlling the logic value of said output terminal in accordance with a first combination of said instruction bits, and means in said device responsive to a second combination of said instruction bits for transmitting a reply message to the network, said reply message including said received address and instruction bits and a status bit representing the condition of said status terminal.

4. A device as set forth in claim 3, wherein said status bit is supplied to said error code computing means so that said set of transmission error checking bits is computed taking into account the logic value of said status bit.

A device as set forth in claim 1, 2, 3 or 4 wherein said set of error checking bits comprise a five bit BCH error checking code.