CA1260535A - Voltage surge arrester circuits - Google Patents
Voltage surge arrester circuitsInfo
- Publication number
- CA1260535A CA1260535A CA000467460A CA467460A CA1260535A CA 1260535 A CA1260535 A CA 1260535A CA 000467460 A CA000467460 A CA 000467460A CA 467460 A CA467460 A CA 467460A CA 1260535 A CA1260535 A CA 1260535A
- Authority
- CA
- Canada
- Prior art keywords
- circuit arrangement
- series
- power mosfets
- electronic
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/18—Automatic or semi-automatic exchanges with means for reducing interference or noise; with means for reducing effects due to line faults with means for protecting lines
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/025—Current limitation using field effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Emergency Protection Circuit Devices (AREA)
- Interface Circuits In Exchanges (AREA)
- Structure Of Telephone Exchanges (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
- Indexing, Searching, Synchronizing, And The Amount Of Synchronization Travel Of Record Carriers (AREA)
- Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
Abstract
SUMMARY:
VOLTAGE SURGE ARRESTER CIRCUITS:
A circuit arrangement for the diversion of surge voltages, in particular for use in exchange systems, with a main distributor (HV) and a subscriber assembly (TB) having an electronic SLIC, in which there are arranged in the series arms of the a/b-wires prior to each electronic SLIC two power-type MOS-FETs connected in series and in mutual opposition and serve as current delimiters.
VOLTAGE SURGE ARRESTER CIRCUITS:
A circuit arrangement for the diversion of surge voltages, in particular for use in exchange systems, with a main distributor (HV) and a subscriber assembly (TB) having an electronic SLIC, in which there are arranged in the series arms of the a/b-wires prior to each electronic SLIC two power-type MOS-FETs connected in series and in mutual opposition and serve as current delimiters.
Description
~LZ~(1S35 20365-2~36 VQLTAGE SURG~A R~STER CI CUITS~
The invention relates to voltage surge arrester circuits particularly for use in exchanye systems having a main distributor and a subscriber assembly provided with an electronic SLIC
~Subscriber Line Interface Circuit).
The transition from conventional to electronic SLICs in inteyrated technology necessitates a new form of protection that is re~uired for IS -~eahnology. Previous proposals basically provided only for the diversion of ~he currents produced by the surge voltage. Relatlvely hlgh currents must still be diver~ed from the subscr.tber assembly, which leads to elaborate constructions incompatible with the construction of modern electronic circults.
One object of the present invention is to provlde a circult arrangement for t.he elimination of surge voltages which is arranyed between the main distributor and the subscriber assembly and which in the event of a surge voltage at the input permits only a maximum permissible current level which can still be tolerated by an electronic SLIC.
In accordance with the present invention there is provided a circuit arrangement for drainage of over-voltages in switching systems comprising a main dlstrlbutor and a subscriber module with an electronic SLIC (subscriber line interface circuit), in which a two-pole electronic current limiter is in each case arranged in series arms of a/b wires connecting the main distributor to the electronic SLIC, characterized in that two in series and oppositely connected power MOSFETs each are arranged a~
~9 ~26~3~ ~0365-2~36 current limiters and that optoelectronic couplers are used for generating a positive bias voltaye at gates of the power MOSFETs.
la ~6~)S3~i The invention will now be described with reference to the drawings, in which:-Figure 1 is a fundamental schematic circuit diagram of one exemplary embodiment;
S Ei'igure 2 shows details of a current limiter of mono-lithic construction;
Figure 3 is a graph showing the characteristic curve of the current limiter shown in Figure 2: and Fi~ure 4 is s simplified representation of a multiple 10 crosspoint having a support function.
The fundamental schematic circuit diagram shown in Figure 1, is of an overall protection circuit for an exchan~e system, which consists of a main distributor HV and a subscriber assembly TB. In the main distributor HV, the components not 15 particularly liable to damage are provided with thyristor diode protection, comprising two thyristors, Thl and Th2. This limits residual voltage peaks to a specific value (e.g. 250V). Guide values for the thyristor diodes Thl and Th2 are 100 A ( 10/100u s ) and 500 A (8/20,~s) respectively, for example. In highly endan-20 gered zones where additional protection is required, ~as discharge cells Ç1 and G2 are provided, with respective decoupling resistor, R1 and R2, interposed between each gas discharge device, G1 or G2, and the associated thyristor diode, Thl or Th2.
In this way all high discharge currents are restricted 25 to the main distributor HV, and only transient voltage peaks of up to 250V can occur across the subscriber assembly TB.
~l2~0S35i However, the electronic Sl,IC can withstand on]y a low blocking voltage in the subscriber assembly TB, and a residual peak voltage of 250 V is too high. Therefore, each of the two series arms, a to a' and b to b', has interposed a current limiter, 5 S1 and S2 respectively, which each consists of two mutually opposed power-type MOS-FET s connected in series . This ensures that ln the event of a surge voltage appearing across the input, only a maximum permissible current is allowed, which is low enough to ` be tolerated by the electronic SLIC. Thus in the event of a surge 10 voltage the current limiters Sl and S2 absorb the voltage peaks as series voltage drops. It goes without saying that the dielectric strength of these limiters S1 and S2 must exceed the maximurn occurring peak voltage (e.g. 300 V).
The transmission technology requirernents to which a 15 series element is subjected, such as low resistance and linearity in the operating range, are fulfilled by the power-type MOS-FETs.
Two power-type ~OS-FETs are required, connected in series in mutual opposition to one another, in order that the transmission and limitation functions can be fulfilled even in the event of 20 reversal of the current direction. It is advantageous to combine the two drains in terms of circuitry, which facilitates a monolithic integration of the current limiters S1 and S2.
The requirements imposed on the relative tolerance of the current limiters Sa and Sb, which serve as series resistors 25 Ra ~ Rb in the two wires , a to a ' and b to b ', are governed by the following logic-links:
)S35 Ra, Rb ~ 5 n for I ~ ~ 100 mA and ~ R = ¦Ra - Rb¦ ~ 1 n If the maximum current is limited, e.g. to a level of 150 mA at 300 V no overload can occur at the maximum occurring transient interferences of one ms duration, Although it is true that the peak currents which continue to pass through the current limiter can still produce voltages above the operating voltages across the SLIC inputs, a ' and b ', these are diverted by c] amping diodes Dl to D4 which ~"`! are normally integrated into every SLIC. These clamping diodes Dl to D4 are required for the relative protection of the electronic SLIC and therefore do not ~generate additional costs. Because the transient peak currents are limited to 1~;0 mA, these diodes Dl to D4 can remain relatively small in dimensions.
The distribution of the protective measures between the indivi dual protection locations results in the following advantages . Only low vol tages occur at the output terminals, a and b, of the main distributor HV and these require no special spatial clearance in subseq uent insulation . The ~- absorbtion and reflection of the interference energy associated 20 with the surge voltage is carried out for the major part in the main distributor HV which, in terms o~ its mechanical construction, is also the most suitable to perform this task . The combina tion of different protective principles, namely parallel diversion in the main distributor HV and series current limitation in the subscriber assembly TB, renders the protection for devices, systems and individuals both effective and cost-~avourable. No ~2~ i3S
high voltages nor high currents need to be discharged from the subscriber assembly TB. The diode protection in the electronic SLIC provides the necessary relative protection, i~e. it is operative when the surge vol tage exceeds the instantaneous 5 applied battery voltage. The distribution of the protection locations also facilitates a clearly defined delimitation of protection characteristics and protection level.
This method can also be used for the standardisation of the protection values, which is advantageous since the 10 protection func-tions occur in different areas of responsibility, such as individual operatin~g companies or system manufacturers, for example.
Figure 2 gives the fundamental circuit diagram of a monolithic current limiter S1 (S2) to be arranged in a series 15 wire from a to a ' or b to b ', between the main distributor and the subscriber assembly. The current lirr.iter 51 (S2) consists of two power-type MOS-FETs, T1 and T1 ', whose drains are ~` ~! combined in the circuit, and which are thus components connected . . .
in series and in opposition to one another with a common sub-20 strate drain. Series resistors R and R', and multiple diodes, M
and M ', serve to set the bias voltage for the current limitation in the case of transistors of the enhancemen~ type.
In place of the multiple diodes, M and M' represented in the drawing, the current limitation can also be effected with 25 the assistance of Zener diodes.
More advantageous are transistors of the depletion type which are conductive without the provision of any bias, (gate and source connected). However, in this case the current limitation value must be governed by the transistor parameters.
The graph shown in Figure 3 the charac-teristics curve of the current limiter element corresponding to the Figure
The invention relates to voltage surge arrester circuits particularly for use in exchanye systems having a main distributor and a subscriber assembly provided with an electronic SLIC
~Subscriber Line Interface Circuit).
The transition from conventional to electronic SLICs in inteyrated technology necessitates a new form of protection that is re~uired for IS -~eahnology. Previous proposals basically provided only for the diversion of ~he currents produced by the surge voltage. Relatlvely hlgh currents must still be diver~ed from the subscr.tber assembly, which leads to elaborate constructions incompatible with the construction of modern electronic circults.
One object of the present invention is to provlde a circult arrangement for t.he elimination of surge voltages which is arranyed between the main distributor and the subscriber assembly and which in the event of a surge voltage at the input permits only a maximum permissible current level which can still be tolerated by an electronic SLIC.
In accordance with the present invention there is provided a circuit arrangement for drainage of over-voltages in switching systems comprising a main dlstrlbutor and a subscriber module with an electronic SLIC (subscriber line interface circuit), in which a two-pole electronic current limiter is in each case arranged in series arms of a/b wires connecting the main distributor to the electronic SLIC, characterized in that two in series and oppositely connected power MOSFETs each are arranged a~
~9 ~26~3~ ~0365-2~36 current limiters and that optoelectronic couplers are used for generating a positive bias voltaye at gates of the power MOSFETs.
la ~6~)S3~i The invention will now be described with reference to the drawings, in which:-Figure 1 is a fundamental schematic circuit diagram of one exemplary embodiment;
S Ei'igure 2 shows details of a current limiter of mono-lithic construction;
Figure 3 is a graph showing the characteristic curve of the current limiter shown in Figure 2: and Fi~ure 4 is s simplified representation of a multiple 10 crosspoint having a support function.
The fundamental schematic circuit diagram shown in Figure 1, is of an overall protection circuit for an exchan~e system, which consists of a main distributor HV and a subscriber assembly TB. In the main distributor HV, the components not 15 particularly liable to damage are provided with thyristor diode protection, comprising two thyristors, Thl and Th2. This limits residual voltage peaks to a specific value (e.g. 250V). Guide values for the thyristor diodes Thl and Th2 are 100 A ( 10/100u s ) and 500 A (8/20,~s) respectively, for example. In highly endan-20 gered zones where additional protection is required, ~as discharge cells Ç1 and G2 are provided, with respective decoupling resistor, R1 and R2, interposed between each gas discharge device, G1 or G2, and the associated thyristor diode, Thl or Th2.
In this way all high discharge currents are restricted 25 to the main distributor HV, and only transient voltage peaks of up to 250V can occur across the subscriber assembly TB.
~l2~0S35i However, the electronic Sl,IC can withstand on]y a low blocking voltage in the subscriber assembly TB, and a residual peak voltage of 250 V is too high. Therefore, each of the two series arms, a to a' and b to b', has interposed a current limiter, 5 S1 and S2 respectively, which each consists of two mutually opposed power-type MOS-FET s connected in series . This ensures that ln the event of a surge voltage appearing across the input, only a maximum permissible current is allowed, which is low enough to ` be tolerated by the electronic SLIC. Thus in the event of a surge 10 voltage the current limiters Sl and S2 absorb the voltage peaks as series voltage drops. It goes without saying that the dielectric strength of these limiters S1 and S2 must exceed the maximurn occurring peak voltage (e.g. 300 V).
The transmission technology requirernents to which a 15 series element is subjected, such as low resistance and linearity in the operating range, are fulfilled by the power-type MOS-FETs.
Two power-type ~OS-FETs are required, connected in series in mutual opposition to one another, in order that the transmission and limitation functions can be fulfilled even in the event of 20 reversal of the current direction. It is advantageous to combine the two drains in terms of circuitry, which facilitates a monolithic integration of the current limiters S1 and S2.
The requirements imposed on the relative tolerance of the current limiters Sa and Sb, which serve as series resistors 25 Ra ~ Rb in the two wires , a to a ' and b to b ', are governed by the following logic-links:
)S35 Ra, Rb ~ 5 n for I ~ ~ 100 mA and ~ R = ¦Ra - Rb¦ ~ 1 n If the maximum current is limited, e.g. to a level of 150 mA at 300 V no overload can occur at the maximum occurring transient interferences of one ms duration, Although it is true that the peak currents which continue to pass through the current limiter can still produce voltages above the operating voltages across the SLIC inputs, a ' and b ', these are diverted by c] amping diodes Dl to D4 which ~"`! are normally integrated into every SLIC. These clamping diodes Dl to D4 are required for the relative protection of the electronic SLIC and therefore do not ~generate additional costs. Because the transient peak currents are limited to 1~;0 mA, these diodes Dl to D4 can remain relatively small in dimensions.
The distribution of the protective measures between the indivi dual protection locations results in the following advantages . Only low vol tages occur at the output terminals, a and b, of the main distributor HV and these require no special spatial clearance in subseq uent insulation . The ~- absorbtion and reflection of the interference energy associated 20 with the surge voltage is carried out for the major part in the main distributor HV which, in terms o~ its mechanical construction, is also the most suitable to perform this task . The combina tion of different protective principles, namely parallel diversion in the main distributor HV and series current limitation in the subscriber assembly TB, renders the protection for devices, systems and individuals both effective and cost-~avourable. No ~2~ i3S
high voltages nor high currents need to be discharged from the subscriber assembly TB. The diode protection in the electronic SLIC provides the necessary relative protection, i~e. it is operative when the surge vol tage exceeds the instantaneous 5 applied battery voltage. The distribution of the protection locations also facilitates a clearly defined delimitation of protection characteristics and protection level.
This method can also be used for the standardisation of the protection values, which is advantageous since the 10 protection func-tions occur in different areas of responsibility, such as individual operatin~g companies or system manufacturers, for example.
Figure 2 gives the fundamental circuit diagram of a monolithic current limiter S1 (S2) to be arranged in a series 15 wire from a to a ' or b to b ', between the main distributor and the subscriber assembly. The current lirr.iter 51 (S2) consists of two power-type MOS-FETs, T1 and T1 ', whose drains are ~` ~! combined in the circuit, and which are thus components connected . . .
in series and in opposition to one another with a common sub-20 strate drain. Series resistors R and R', and multiple diodes, M
and M ', serve to set the bias voltage for the current limitation in the case of transistors of the enhancemen~ type.
In place of the multiple diodes, M and M' represented in the drawing, the current limitation can also be effected with 25 the assistance of Zener diodes.
More advantageous are transistors of the depletion type which are conductive without the provision of any bias, (gate and source connected). However, in this case the current limitation value must be governed by the transistor parameters.
The graph shown in Figure 3 the charac-teristics curve of the current limiter element corresponding to the Figure
2 arrangement. As can be seen from the drawing, the curve exhibits an exact zero transition which is essential to the desired current limiter function.
In Figure 4 there is a representation of a multiple crosspoint having a protective function, with the assistance of which not only is a current limiter function carried out in the arm from a to a '; but which also can assume other functions in the BORSCHT-concept, where BORSCHT signifies Battery Feeding, Over Voltage Protection, Ringing, Signalling, _oding, Hybrid (~ wire - 2 wire conversion), Testing). This multiple cross-point includes four transistors Tl, Tl',Tl", T1"' whose drains are combined in the circuit. At the crosspoints a" and a"' the ringing voltage (R) can for example be input-coupled or test devices (T) can be connected. In the exemplary embodiment shown in Figure 4, respective opto-electronic couplers, 01, 01', 01" and 01"', serve to produce the necessary positive bias voltage to set a current limit value.
The module represented in Figure 4 can also be designed as a monolithic integrated modu~e, in which case further power-type MOS-FETs (Tl"". . . ) can be additionally integrated for the input-coupling of further of the above-described functions.
1%~)53~;
In addition to the above-described circuit arrangemen-t for an exchange system, the invention can also be used as an automatic series safety measure in general device technology.
In this case, to allow for the possibility of a long-term load, S it is desirable to insert a heat sensor which can effect a circuit separation if operated.
In Figure 4 there is a representation of a multiple crosspoint having a protective function, with the assistance of which not only is a current limiter function carried out in the arm from a to a '; but which also can assume other functions in the BORSCHT-concept, where BORSCHT signifies Battery Feeding, Over Voltage Protection, Ringing, Signalling, _oding, Hybrid (~ wire - 2 wire conversion), Testing). This multiple cross-point includes four transistors Tl, Tl',Tl", T1"' whose drains are combined in the circuit. At the crosspoints a" and a"' the ringing voltage (R) can for example be input-coupled or test devices (T) can be connected. In the exemplary embodiment shown in Figure 4, respective opto-electronic couplers, 01, 01', 01" and 01"', serve to produce the necessary positive bias voltage to set a current limit value.
The module represented in Figure 4 can also be designed as a monolithic integrated modu~e, in which case further power-type MOS-FETs (Tl"". . . ) can be additionally integrated for the input-coupling of further of the above-described functions.
1%~)53~;
In addition to the above-described circuit arrangemen-t for an exchange system, the invention can also be used as an automatic series safety measure in general device technology.
In this case, to allow for the possibility of a long-term load, S it is desirable to insert a heat sensor which can effect a circuit separation if operated.
Claims (5)
- THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
l. A circuit arrangement for drainage of over-voltages in switching systems comprising a main distributor and a subscriber module with an electronic SLIC (subscriber line interface circuit), in which a two-pole electronic current limiter is in each case arranged in series arms of a/b wires connecting the main distributor to the electronic SLIC, characterized in that two in series and oppositely connected power MOSFETs each are arranged as current limiters and that optoelectronic couplers are used for generating a positive bias voltage at gates of the power MOSFETs. - 2. A circuit arrangement according to Claim 1, characterized in that the power MOSFETs have drains which are connected together.
- 3. A circuit arrangement according to Claim 1 or 2, characterized in that additional power MOSFETs are arranged in the series arms of the a/b wires for coupling in further functions.
- 4. A circuit arrangement according to Claim l or 2, characterized in that the current limiter comprises a monolithically integrated chip.
- 5. A circuit arrangement according to Claim 1 or 2, characterized in that additional power MOSFETs are arranged in the series arms of the a/b wires for coupling in further functions, and in that the current limiter comprises a monolithically integrated chip.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP3340927.7 | 1983-11-11 | ||
| DE19833340927 DE3340927A1 (en) | 1983-11-11 | 1983-11-11 | CIRCUIT ARRANGEMENT FOR DERIVATING OVERVOLTAGE |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1260535A true CA1260535A (en) | 1989-09-26 |
Family
ID=6214136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000467460A Expired CA1260535A (en) | 1983-11-11 | 1984-11-09 | Voltage surge arrester circuits |
Country Status (8)
| Country | Link |
|---|---|
| EP (1) | EP0142128B1 (en) |
| JP (1) | JPS60118024A (en) |
| AT (1) | ATE40773T1 (en) |
| BR (1) | BR8405721A (en) |
| CA (1) | CA1260535A (en) |
| DE (2) | DE3340927A1 (en) |
| FI (1) | FI81469C (en) |
| ZA (1) | ZA848759B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3712572C1 (en) * | 1987-04-14 | 1988-08-04 | Telefonbau & Normalzeit Gmbh | Circuit arrangement for overvoltage protection and call current feed on a connection line for telecommunications, in particular telephone switching systems |
| CA1260171A (en) * | 1987-05-15 | 1989-09-26 | Reinhard W. Rosch | Protection arrangement for a telephone subscriber line interface circuit |
| DE3814661A1 (en) * | 1988-04-29 | 1989-11-09 | Nixdorf Computer Ag | DEVICE FOR SWITCHING THE CALL AC VOLTAGE ON SUBSCRIBER CONNECTION LINES |
| US5146384A (en) * | 1989-04-28 | 1992-09-08 | Northern Telecom Limited | Automatically resetting protection arrangement for a telephone subscriber line interface circuit |
| EP0529949B1 (en) * | 1991-08-27 | 1996-06-26 | AT&T Corp. | Common mode voltage surge protection circuitry |
| GB9223773D0 (en) * | 1992-11-12 | 1992-12-23 | Raychem Ltd | Switching arrangement |
| EP0684677B1 (en) * | 1993-02-10 | 2003-12-17 | Line Electronics Corporation | Overcurrent protective circuit and semiconductor device |
| DE4326596C2 (en) * | 1993-08-07 | 1997-07-17 | Sel Alcatel Ag | Protective circuit arrangement for electronic subscriber circuits |
| WO1995007570A1 (en) * | 1993-09-08 | 1995-03-16 | Siemens Aktiengesellschaft | Current limiting device |
| US6049447A (en) * | 1993-09-08 | 2000-04-11 | Siemens Ag | Current limiting device |
| DE4402461A1 (en) * | 1994-01-28 | 1995-08-03 | Sel Alcatel Ag | Protection circuit for a subscriber line circuit and subscriber line circuit with it |
| US6266223B1 (en) * | 1999-06-30 | 2001-07-24 | Tyco Electronics Corporation | Line protector for a communications circuit |
| DE102007036330A1 (en) | 2006-09-12 | 2008-04-03 | Tremco Illbruck Productie B.V. | Bonding method, useful e.g. in building applications, involves applying polyurethane foam of specific setting time to substrate and pressing on component to be bonded |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3631264A (en) * | 1970-02-11 | 1971-12-28 | Sybron Corp | Intrinsically safe electrical barrier system and improvements therein |
| DE2435606C3 (en) * | 1974-07-24 | 1979-03-01 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Series connection of field effect transistors for the realization of a high-ohmic linear resistance |
| US4170740A (en) * | 1978-02-24 | 1979-10-09 | International Telephone And Telegraph Corporation | High voltage switch and capacitive drive |
| US4200898A (en) * | 1978-06-19 | 1980-04-29 | The United States Of America As Represented By The Secretary Of The Navy | Current limiter |
| DE2834894A1 (en) * | 1978-08-09 | 1980-02-21 | Siemens Ag | Two terminal electronic overvoltage protector for telephone line - has diodes blocking currents of one polarity and electronic circuit blocking overcurrent of opposite polarity |
| JPS5638931A (en) * | 1979-09-06 | 1981-04-14 | Sony Corp | Overcurrent detector circuit |
| DE3215551A1 (en) * | 1982-04-26 | 1983-10-27 | Siemens AG, 1000 Berlin und 8000 München | CIRCUIT ARRANGEMENT FOR OVERVOLTAGE PROTECTION OF INTERFACE CIRCUITS |
-
1983
- 1983-11-11 DE DE19833340927 patent/DE3340927A1/en not_active Withdrawn
-
1984
- 1984-11-07 AT AT84113450T patent/ATE40773T1/en not_active IP Right Cessation
- 1984-11-07 EP EP84113450A patent/EP0142128B1/en not_active Expired
- 1984-11-07 DE DE8484113450T patent/DE3476727D1/en not_active Expired
- 1984-11-08 JP JP59235927A patent/JPS60118024A/en active Granted
- 1984-11-09 FI FI844416A patent/FI81469C/en not_active IP Right Cessation
- 1984-11-09 CA CA000467460A patent/CA1260535A/en not_active Expired
- 1984-11-09 ZA ZA848759A patent/ZA848759B/en unknown
- 1984-11-09 BR BR8405721A patent/BR8405721A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0142128A1 (en) | 1985-05-22 |
| JPS60118024A (en) | 1985-06-25 |
| JPH0586129B2 (en) | 1993-12-10 |
| FI844416L (en) | 1985-05-12 |
| FI844416A0 (en) | 1984-11-09 |
| DE3476727D1 (en) | 1989-03-16 |
| BR8405721A (en) | 1985-09-10 |
| ZA848759B (en) | 1985-07-31 |
| ATE40773T1 (en) | 1989-02-15 |
| FI81469C (en) | 1990-10-10 |
| EP0142128B1 (en) | 1989-02-08 |
| FI81469B (en) | 1990-06-29 |
| DE3340927A1 (en) | 1985-05-23 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |