CA1258520A - Digital signal transmitting system - Google Patents
Digital signal transmitting systemInfo
- Publication number
- CA1258520A CA1258520A CA000567713A CA567713A CA1258520A CA 1258520 A CA1258520 A CA 1258520A CA 000567713 A CA000567713 A CA 000567713A CA 567713 A CA567713 A CA 567713A CA 1258520 A CA1258520 A CA 1258520A
- Authority
- CA
- Canada
- Prior art keywords
- signals
- signal
- data
- digital
- mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/86—Arrangements characterised by the broadcast information itself
- H04H20/88—Stereophonic broadcast systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/28—Arrangements for simultaneous broadcast of plural pieces of information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
- H04H20/65—Arrangements characterised by transmission systems for broadcast
- H04H20/76—Wired systems
- H04H20/77—Wired systems using carrier waves
- H04H20/78—CATV [Community Antenna Television] systems
- H04H20/79—CATV [Community Antenna Television] systems using downlink of the CATV systems, e.g. audio broadcast via CATV network
Abstract
ABSTRACT OF THE DISCLOSURE
A digital signal transmitting system produces digital signals of up to four different modes for transmission over an unused television channel in an existing cable television transmission line and which requires no more bandwidth than that normally required by a single existing television channel, the various modes of digital signals all include synchronizing signals and service bit signals which are used to address any of the numerous terminals at the receiving side to control access to the various modes of digital signals transmitted over the single channel. By controlling the transmission of the modes to have constant time intervals, which can be selected based upon different sampling times, high quality audio signals may be transmitted or/and data channels or monaural audio signals, all of which may be transmitted over the single cable television transmission line.
A digital signal transmitting system produces digital signals of up to four different modes for transmission over an unused television channel in an existing cable television transmission line and which requires no more bandwidth than that normally required by a single existing television channel, the various modes of digital signals all include synchronizing signals and service bit signals which are used to address any of the numerous terminals at the receiving side to control access to the various modes of digital signals transmitted over the single channel. By controlling the transmission of the modes to have constant time intervals, which can be selected based upon different sampling times, high quality audio signals may be transmitted or/and data channels or monaural audio signals, all of which may be transmitted over the single cable television transmission line.
Description
12S85~20 BACKGROUND O~_THE INVENTION
Field of the Inventisn:
This invention relates generally to a digital signal transmitting and receiving system and, more ~pecifically, to a system for use in transmitting a digital signal such as might be derived by digitally converting an analog stereo cignal, announcement ignal, facsimile data signal, or a computer game program, on a cable television transmission line using a single, unused television channel having ~ ban~width of approximately 6MHz.
BRI~:E` DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic in block diagram form of a ~igital data tr~nEmitting ~y6tem using a cable television tran~mission line ~uitable ~or u e with the present invention;
~ ig. 2 i6 a digital signal receiviny 6ystem employing a cable television transmission line suitable for use with the present invention;
Figs. 3A and 3B represent digital signal formats used in a digital signal transmitting ~ystem according to the present invention;
Figs. 4~-4D schematically represent digital signal formats for use in an embodiment of a digital ~ignal transmitting system according to the present invention;
~ ig. 5 is a block diagram of a digital signal generator according to an embodiment of the present invention;
Fig. 6 i8 a block diagram of a digital signal generator ~ccording to another embodiment of the present invention;
~ ig. 7 is a block diagram of a digital cignal qenerator according to another embodiment of the present invention;
Fig. 8 is a block diagram of B digital signal generator according to another embodiment of the present invent~on;
Fig. 9 is a block diagram of a digital signal generator according to a an~ther embodiment of the present invention;
Fig. 10 i~ a ~lock diagram of a demodulator for u~e ~n the present invention;
Fig. 11 is a block diagram o~ a anoth~r embodiment of a demodulator for use in the present invention;
Figs 12A-12H are timing waveform diagrams 6howing the operation o~ the demodulators ~f Figs. 10 and 11; and Fig. 13 is a block diagram of an embodiment of zn nddressing circuit according to the present invention;
.. ..
Description of the Backqround:
In order to better understand the signal transmitting system of this invention an overall system ~uitable for employing the present invention is first described. The present invention is intended to employ a cable television (CATV) transmission line ~nd Fig. 1 shows a digital signal transmitting system for use with such transmission line. Input terminals 201-204 are arranged to 12S8SZo receive ~nalog signals, which might be analog 6tereo signals, and such input signal6 are fed to analog-to-digital convertors 207-210, respectively. The resultant digital signals from analoy-to-digital convertors 207-210 are then fed to a multiplexer 213 that produces at its ~utputs two ~erial data streams that represent the four input ~ignals having been time division multiplexed. ~i~e division n multiplexing being a ~nown approach to tra~smitting a number ~f 6ignals over a commmon path by using different time ~terv~16 f~r the tran~mission of the intelligence of each message signal. Then, the time division multiplexed digital signals from multiplexer 213 are fed to a filter 214, which is provided to suppress intersymbol interference that causes code error. Filter 214 may advantageously eomprise a binary ~F
transversal filter having tap coefficients adjusted so that the modulation signal satisfies Nyquits'~ fir~t criterion.
The output of filter 214 is fed to a four-level convertor 215 which may be thought of as operating as a digital-to-analog c~nver~or so that it converts the input digital signals to a four-level, base-band ~ignal. This four-level analog signal produced by four-level convertor 215 has four different amplitude values ranging from zero to three, which are respectively expressed as ~o" + ~on = no~l "0 + ~ 1" + ~0~ - ~2n, and ~1~ + ~ln ~ ~3n. This pseudo-analog output signal is fed to an amplitude-modulation (AM) modulator 216 wherein it ~M
modulates an intermediate frequency signal (IF) having a frequency of 3B.9MHz, for example, ~upplied by oscillator 217. The output of the AM modulatox 216 i8 fed through a vestigial side-band filter 218 to a mixer 219. This vestigial side-band modulation is the ~ame as in conventional television transmissions. Thus, the filtered signal is mixed in mixer 219 with an RF signal (fc ~ fif) ~upplied by a local oscillator 220. The output signal of mixer 219 repre~ents a modulated fiignal having a carrier frequency fc of 97.25M~z, for example, and such output signal i~ fed through a bandpass filter 221 to output terminal 222 as the modulated, system output signal, the ~ndwidth of which is limited to 6M~z. The output signal ~eveloped at output terminal 222 is then fed to a head end of a CATV system (not shown). Thus, the original input signals are placed in ~n unused television channel on a conve~tional cable television transmission line and require no more bandwidth (6NHz) t~en a typical ~ingle television channel.
Fig. 2 shows a eystem for ~receiving~ a signal as might be placed on the ~ATV transmission line by the ~ytem of Fig. 1, in which the modulated ~ignal transmitted through the-transmission line of the CATV 6ystem is supplied at input terminal 231 to a wide bandwidth receiver front end 232 where it is amplified and ~onverted to an intermediate frequency (IF) signal of 58.7 MHz, for example, and this intermediate frequency signal is supplied to a phase-locked loop (PLL) synchronous detector 233, which functions as an AM detector, so that the four-level, base-band qignal, as produced by the four-level convertor 215 of Fig. 1, is i2S8S20 demodulated. An automatic gain control (AGC) circuit 246 i5 provided with an input from PLL detector 233 and produces an output control signal fed to front end 232 to prevent ~verloading of the front en~ amplifier. The output ~ignal from the phase-locked loop detector 233 is fed to a level comparator 234, which operates an a kind of analog-tG-digital convertor, by demodulating the detected signal and pr~duces a series digital signal ha~ing four possible values, ~on, ~ 2~, and ~3n, on ~he basis of whether the output signal from the PLL detector 233 exceeds a reference level, as represented by a so-called eye pattern. ~he eye pattern is generally known in data tran~mission by an oscilliscope display of the detector ~oltaye waveform in a data modulator/demodulator. This pattern gives a convenient sepresentation of cross-over distorti~n and can be derived in the known fashion, based upon the overall frequency characteristics of the ~ystem and the relationship thereto hetween the Nyquist frequency and the transmission capacity of the system in bits per second.
The digital signal thus essentially demodulated by level comparator 234 is fed to a demultiplexer 235~ Also produced by the level comparator 234 is a bilevel synchronizing signal fed to a clock reproducing circuit 245 that produces a bit clock signal applied to demultiplexer 235 to control the output thereof in the appropriate time-division manner. Also produced by clock reproducing circuit 24S is a synchronizing ~ignal fed to both the automatic gain control circuit 246, as well as to l~S8SZO
demultiplexer 235. Demultiplexer 235 then produces a plurality of digital sig~als in a time-division manner that are supplied, respectively, to digital-to-analog (D/A) convertors ~39 - 242, so that analog signals corresponding to the original input signals as applied at inputs 201 -204, (Fig. 1) are respectively developed at output terminals 243 - 246.
Nevertheless, eve~ though the system is described hereinabove would appear to be a workable and feasible ~ystem in actuality such ~ystem is not avaiable for use in a effective and usable ~orm, principally ~ecause of the lack of an economical ~ethod of addressing the receiver terminals.
The problem being that in a ~ransmission 6y~tem, such as ca~le television, in which the ~ignal is transmitted through a cable, that is, hard wired, at the receiving ~ide at which-the ~ignal~ ~re being distributed there may be fewer than several hundred receivers, or there may be up to several tens of ~housands of receivers. In other words, there i5 a wide spread in the number of receiving units that may be connected to the cable television transmission line.
In the proposed systems, each of the receiver terminals usually has an individual ~ddress signal and the transmitter side then transmits a control signal corresponding to each address number, wherein the receiving state of each receiver terminal can be controlled.
In the systems proposed to use cable television tranmission lines as outlined above, the control signal that ~2S8SZO
corresponds to each address is formed as a bit ~eries, which can cover the maximum number of receiver terminals and in most cases this involves a bit series of approximately 20 bits. The control signal used to perform such addressing is then transmitted using a special address network line that is different from the data network line. Accordingly, if ~uch address network line is designed to permit it to accommodate a system having a large number of receiver terminals, for example, ranging from several tens of thousands to several hundred-thousands, then this address network line will be uneconomical and will be too sophisticated and expensive for ~ystems having a substantially fewer number of terminal receivers. On the other hand, if the addres network line is designed to ~ccommodate a sy6tem having, for example, less than ~everal hundred terminal~ then ~uch address network line is almost unusable when applied to a system having a subtantially greater number of receiver terminals and, thus, the address network lines must be increased correspondinsly.
Accordingly, as described above, while the concept of a system for transmitting digital sisnals on a cable television transmission line is feasible, the data addressing system is not available ~uch that the address network lines need not be chanqed in accordance with the scale of the EyStem~ in order to eliminate the redundancy and uneconomical provision o~ more address network lines than required for the smaller ~ize system. Purthermore, becal7se special ~ddreqs network lines must be provided, the l;~S~35ZO
data addressing system becomes complex in its circuit arrangement and is thereby expensive in view of the associated manufacturing costs.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the presen~
invention to provide an improved digital signal transmitting and receiving 6ystem that can overcome the a~ove-noted shortcomings inherent in the prior art.
It is another ~bjert o~ the present invention to provide a digi~al signal transmitting and receiving system for transmitting a digital audio signal or digital data ~ignal using the transmission line of a cable television network.
It is a further object of the present invention to provide a digital siynal transmitting and receiving ~ystem suitable for transmitting digital zudio signals or digi~al data eignals in which a large number of receiver terminals of a cable television y~tem can be addressed without requiring cpecial addressing network lines.
According to one aspect of the invention a digital signal transmitting sy~tem is proviaed including a circuit generating digital word signals in a first mode in which each of the signals consists of a word synchronizing 6ignal, and data signals having a first bit code and being sampled at a first sampling frequency and a circuit for generating digital word signals in a second mode, each of the word signals in the second mode con6i~ting of a word synchronizing signal ~nd data ~ignals having a second bit 12585'~0 code and being sampled at a sec~nd sampling frequency and a selective transmitter that selectively transmits the first mode of digital word si~nals and the second mode of digital word signals through a transmission line o~ a cable television system.
According to another aspect of the present invention a digital signal receiving system is provided that includes a circuit to receive digital signals in a first mode in which the firs~ mode digital signals consist of a word ynchronizing ~iqnal, a f irst ~ervice bit signal, and data signals having a first bit code and being sampled by 2 first ~ampling frequency and for recei~ing a second mode of digital word ~ignals, each consisting of a word synchronizing signal 7 a ~econd service bit ~ignal, and data 6i~nal6 including second bit codes and being sampled at a ~econd sampling frequency. A demodulator is connected to the signal input terminal of the receiver and latches the first-mode of the digital word signals and conver~s the digital word ~ignals to analog ~ignals. A second demodulator is provided that is connected to the signal input terminal of the rec~iver and la~ches the second mode of digital word signals and also converts such signals into analo~ signals. A control system is provided that c~ntrols the mode of the first and second demodulators in order to selectively enable one or the other in response to a mode control 6ignal.
In yet another embodiment of the invention the transmitter and receiver are com~ined into a complete system 12S~35~0 in which a single tra~smitter can provide digital data for a plurality of receivers and such plurality of receivers may be accessed or addressed using only the cable television transmission line over which the actual data signals are transmitted~
The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative e~bodimen ~ thereof to be read in conjunction with the nccompanying drawings.
DESCRIPTION OF ~HE PREFERRED EMBODIMENTS
-While Figs. 1 and 2 have been described hereinabove as being exemplary of digital data transmission and receiving systems the present invention as it relate~ to the addressing network is described in relation to Figs. 3 through 13 and, in particular, Figs. 3A and 3B represent a data format ~ccording to the present invention. In Fig. 3A, one frame is ~hown as being formed of 256 words, which at the preferred transmission rate corresponds to 5.81ms. Eacb frame begins with a frame synchronizlng signal FS formed of eight ~its and is followed by a ~ervice bit word of four bits and a first data word W0 of 156 bits. Thereafter, are the remaining 255 data words, W1 to ~255, each word being formed of 156 bits, each beginning with word ~ynchronizing signals WSl to WS255 and each being formed of eight bits, and service bit words SBl to SB255, each being formed of four bits, respectively. Note that the frame ~ynchronizing signal FS also serves as the word 12~35Zo eync~ronizing 6ignal (WSO) for the first data word WO.
Pig. 3B represents one of the 256 words of a frame and, as shown therein, the eight bits of the fiynchronizing signal SYNC are at the beginning of the word f~llowed by the - lOa -~XS8S20 four service bits and then the data word is made up of four data channels, CH1 - CH~, each data channel having a data length of 32 bits and a s~mpling frequency of 44.lKHz, and an error correction code ECC. An error correction code is added at each of the recpective data channels CHl - C~4 and may comprise a Bose-Chaudhuri-Hocquenghem (BCH) code or Extended Hamming Code, each having a length of se~en bits.
Figs. 4A - 4D illustrate data formats for a plurality of different operating modes of the present invention and, specifically, Fig. 4A represents a first mode (A) in which 32-bit data represents a stereo digital audio signal such that a left channel stereo signal L includes 16 bits and a right channel stereo signal R includes the similar 16 bits. This 16-bit data format is based upon a sampling freguency of 44.1RHz and is the same data format as the presently available ~ompact audio disc (CAD), which is fa~t becoming a very popular music source for high quality stereo music programs.
Fig. 4B represents a ~econd mode (B) in which the data format of 32 bits are divided into four sets of eight bits and can represent two channels of stereo signals La, Ra and Lb, Rb. This format provides data suitable for multichannel stereo music, not quite of the extreme high quality of mode A represented in Fig. 4A. The quality of sound according to mode ~ is the equivalent to, or better than, conventional FM broadcasting.
Another mode (C) is represented in Fig. 4C, in which an 8-bit data format is provided and in which the sampling frequency of 44.lKHz of Figs. 4A and 4B is halved to provide a s ?ling frequency of 22.05K' . This results in a data format that can provide eight monau-21 chann~ls a to h which a~e suitable for monaural voice service, sucl~ as news, weather forecasts, communications, an~ the like. Mode (D) is represer.ted in Fis. 4D and is a combination of mod~s (B) and (C) anc can be used to transr.it one high fidelit~-stereo program and four monaural audio programs. In such case, the 8-bit stereo channels employs a frequenc~ of 44.lK~:z resulting in two channels of eight bits, e~ch intermixed with four monaural mode chanr,els, havir.g a frequenc~ cf 22.05XHz. The mode represented in Fig. 4D
realizes a pl~rality of modes within a single data channe' and, thus, provides an elaborate service capability. Note that in Figs. 4~-4D no attempt is made tG show the e~zct time relatlonsh_p between the various modes, a"d the various modes in these Figs. are not drawn to scale.
There are twenty five different combinations of the above-~escribed mGdes, that is, twenty five different s~stems can be specified simply by altering the prosramming of both the transmitting and receiving sides, without modifying the hardware. Nevertheless, considering a data out~ut system according to combinatior.s of the these modes in which the s~mpling frequency is either 2.05KHz, or 44.lRHz, the data length is either eiqht bits or sixteen bits and the signal system is eithe- ~.onaural or stereo, then eight different mode combinations can be tabulated.
These are set forth in the following Table I. '12585ZO
TABLE I
__ . _ ~ . .. ._ s~gnal transmission~ 5 S ¦ S sl M ¦ M j Ml M
data length -¦ 16 16 ¦ 8 81 16 16 ¦ B¦ 8 . _ _ samplinq ~reguency ¦ 4 2 4 2 4 2 4 2 mode 5164¦5162iS84lS82 M164 M162 M84 M82 12S85Zo As seen in Table I, letters S and M designate stereo mode and manaural mode, respectively, reference numerals 4 and 2 designate campling frequencies of 44.1KHz and 22.05KHz, respectively, and the bottom row containing notations 5162, S84, S82, M164, M162, M84, M82 designate different modes that are formed by combining the signal system, the data length, and the sampling frequency. For example, S164, indicates a mode wherein the signal is a stereo signal, the data leng~h is sixteen bits, and the sampling frequency i6 44.lKHz, while M82 indicates a mode in which the signal is monaural, the data length is eight bits, and the sampling frequency is 22.05KHz. The indications representing the other modes are similarly deduced.
Encoders suitable for generating the various modes as described above in relation to Figs. 4A-4D and in Table I, are shown in Figs. ~ through 9 and, of the above different modes 6hown in Table I, the fundamental modes thereof are Sl64, S84, S82, and M82 and, accordingly, an example of an encoder corresponding to each of such fundamental modes is described hereinbelow.
Fig. 5 is a block diagram of an encoder for transmitting the Sl64 mode of Table I in which 32 bits of one data channel are divided into left and right channel stereo signals of sixteen bits each, with the sampling frequency of 44.lKHz. This is the mode represented in Fig.
4A hereinabove. In Fig. 5, a left channel audio analog signal L is applied at input terminal l and a right channel analog signal R is supplied to input terminal 2, and the thus supplied analog signals are fed to respective analog-to-digital convertors (A/D) 3, 4 in which they are converted to digital signals based upon a sampling frequency of 44.1KHz. The resultant digital signals are then the sixteen bit data words as shown in Pig. 4A. The respective digital signals from A~D convertors 3 and 4 are ~ed to a parallel-to-serial convertor (P/S) 5, wherein they are converted from two parallel signals to a serial signal, which is developed at ou~put terminal 6 as the data output signal. Subsequently, this erial data ~ignal at ~utput terminal 6 can be further processed in accordance with any specific or particular use requirement, for example, when this data output signal is intended to be further transmitted using the transmission line of the cable television sys~em the output data signal is amplitude modulated using the vestigial side-band system, as done in ~tandard television systems, and then transmitted to the appropriate receiving side at the customer location.
Fig. 6 is a block diagram illustrating another example of an encoder and, specifically, an encoder corresponding to the S84 mode, which as set forth hereinabove is a fundamental mode of this system, in which 32 bits of one data channel are divided into four segments of eight bits, representing two left and two right stereo channel signals having a sampling frequency of 44.lKHz. The input terminals for the left channel audio analog signals La and Lb are provided at ll and 12, while the right channel analog signals Ra and Rb are supplied, respectively, to input terminals 13 and 14. The analog signals thus applied are fed to respective A/D convertors 15-18 in which they are ~ 25~5~0 converted based upon a sampling signal having a frequency of 44~lRHz 2nd thereby produce digital signals each data length of which is eight bits, as shown for example in Fig. 4B.
These data signals in this "B" mode are then fed to a parallel-to-serial convertor 19 and are developed into a serial bit stream made available at output terminal 20.
Again, this serial digital output ~ignal can be modulated in accordance with the known television techniques and placed on a transmission line of a CATV system.
~ n encoder for producing the ~C" mode as represented in ~ig. 4C, is shown in Fig. 7 in block diagram form in whi~h the S82 mode is produced having 32 bits of one data channel divided into fvur ~ets of eight bits representing four channels of left and right ~tereo signals, with a ~ampling frequency of 22.05KHz over two data words.
Left channel analog ~ignals La, Lb, Lc, and Ld are supplied respectively to input terminals 21, 22, 23, and 24 and right channel analog sigrials Ra, Rb, Rc, and Rd, are supplied to input terminals 25, 26, 27, and 28, respectively. The analog signals applied to inp~t terminals 21-28 are supplied to respective A~D convertors 29-36 wherein they are converted to digital ~ignals based upon a sampling signal having a freguency of 22.05KHz. In this mode then the signals La, Lb, Lc, Ld, Ra, Rb, Rc, and Rd are sequentially provided within a period of 45.4 micro seconds, corresponding to $he reciprocal of the sampling frequency, to a parallel-to-serial convertor 37, in which they are converted from the parallel signals to the serial signal stream which is then made a~ailable at output terminal 38, l~S8SZO
and again which can be signal.processed according to any desired end use.
Fig. 8 is a block diagram of an example of an encoder corre~ponding to the MB2 mode, in which 32 bits of one data channel are respectively divided into four cets of eisht bits representing eight channels monaural signals and having a sampling fresuency of 22.OSKHz over two words. The eight channel monaural signals a ~o h are fed in at input terminals 41 - 48, respectively, and are supplied to respective ~/D convertors 49~56 wherein they are converted to digital signals on the basis of a sampling signal having a frequency of 22.05KHz. Such digital signals will each have a data length of eight bits, as shown in Fig. 4C, and accordingly, this encoder produces the ac" mode discussed hereinabove. The digital signals are then fed to parallel-to-serial convertor 57 in which they are converted from the parallel ~ignals to a serial bit ~tream which is then made available at output terminal 5B as the required data output ~ignal.
Fig. 9 is a combination or a hybrid encoder capable ~f producing mode "D~ as discussed above in which a plurality of different modes, for example, two modes such as the S84 mode, as shown in Fig. 6, and the M82 mode, as shown in Fig. 8 hereinabove. Thus, in Fig. 7, 3eft channel analog signal La is fed in at input terminal 61 and right channel analog signal Ra is fed in at input terminal 62. These analog signals are then applied to respective A/D convertors 67 and 68 wherein they are converted to digital signals ba~ed upon a sampling ~ignal having a frequency of 44.lKHz l~S~3520 and are then fed to parallel-to-serial convertor 73. Analog signals a to d of respective monaural channels are fed to input terminals 63-66 and are then applied to corresponding A/D convertors 69-72, respectively wherein they are converted to digital signals, all of which have a similar sampling frequency of 22.05RHz. The output of A/D
convertors 69 - 72 are fed to parallel-to-serial convertor 73. Accordingly, parallel-to-serial convertor 73 is supplied with stereo signals and monaural signals and then converts the parallel digital signals into ~erial digital data ~tream and produces at output terminal 74 a mixed output data ~ignal. More specifically, the encoder of Fig.
S produces one channel of stereo signals having a ~ampling frequency of 44.1~Hz and data length of eight bits, and four channels of monaural ~ignals having a sampling frequency of 22.05R~z and also having a data length of eight ~its.
Note that one frame is processed at a rate of 22.7 micro-seconds, which is derived as a reciprocal of the 44.1~Hz sampling frequency, and results in a transmission bit rate of approximately 7.4 mega ~its per 6econd (MBPS).
This rate corresponds to the general transmission capacity of a CATV system.
Upon transmitting, each of the above modes is selected in advance and its signal is then transmit~ed. The receiver at the customer location must employ the appropriate decoders, and such decoders are represented in Figs. 10 and 11. In the decoder of Fig. 10, a common conventional 8-bit digital-to-analog (D/A) convertor is employed as the convertor, whereas in the embodiment of Fig.
~ u ~ u ~ ~L
~2S8S~O
11 a conventional 16-bit D/A convertor is employed.
Therefore, of the four fundamental modes, the decoder shown in Fig. 10 can be used for the M82 mode, the S82 mode, and the S84 modes, while the decoder of Fig. 11 is employed for the S164 mode. As for the ~84 mode, this can be processed substantially the same as the S82 mode and in which case the decoder of Fig. 8 is employed.
Referring now specifically to Fig. 10, input terminal 83 receives a ~erial data signal having a data ~ormat according to any of the above-de~cribed format modes produced at the transmitting side, and the serial data at input terminal 81 is fed to a serial-to-parallel (S/P) convertor 82a, which forms a part of demodulating circuit 82. Demodulating circuit 82 may be advantageously formed as a single integrated circuit. S/P convertor 82A converts thP
serial data received at input terminal 81 to parallel signals based upon a clock signal produced by a timing circuit 82b. The output signals thus produced are latched into a latch circuit 82c on an 8-bit by 8-bit basis, as determined by a latch signal also produced by timing circuit 82b.
Therefore, latch circuit 82c produces the 8-bit data of a monaural signal, as might be represented in Pig.
12A, during a period of 45.4 micro-seconds in the M82 mode, whereas latch circuit ~2c would produce each 8-bit data of left and right channel stereo signals during a period of 45.4 micro seconds in the S82 mode, as represented in Fig.
12B. Similarly, in the M84 mode, as represented in ~ig.
12C, 8-bits of data of two monaural signals is produced 12S8S~
during a period of 22.7 micro-seconds and in the M162 mode, as represented in ~ig. 12D, the lowermost 8-bit data of the 16-bit monaural signal is produced during the first half period of 45.8 micro-seconds, while the upper 8-bits of data is produced in the latter half of the second half of the 45.4 micro-seconds period.
Fig. 12E represents the S84 mode, in which each 8-bits of data of the left and right channel stereo signal is produced dusing a period of 22.7 micro-seconds by latch circuit 82c. Fig. 12F represents the S162 mode in which lower 8-bits of data and upper 8-bits of data of a left channel ~tereo signal are produced during the first half of the 45.4 micro-seconds period, whereas the lower 8-bits of data and upper 8-bits of data of the right channel 6tere~
signal are produced during the latter half of this period.
In the M164 mode, as represented in Fig. lOG, the lower 8-bits of data of the 16 bit monaural signal are produced during the former half of the 22.7 micro-seconds period, while the upper 8-bits of data thereof is produced during the lat~er half of such period.
The selection of any of the above modes is of course made in advance ~y a mode selection signal, which can then be fed to timing circuit 82b, fed in at input terminal 83. The state of such mode selecting signal as required to set each of the fundamental modes S164, S84, S82, and M82 has a code indicated in Table II as set forth hereinbelow.
--lg--S~20~1 12S~O
TABLE II
Mode Ml M0 C2 Cl C0 ... _ _ ~
S1~4_ 0 0 x x x S ~--1 O 1 K ~
CB2_1 _ 0 ~ D 0 ~J~
Table II represents that each of the fundamental modes may be ~pecified by two bits (M1, ~0) and the channel of each mode may be specified ~y three bits (C2, Cl, C0).
Thus, in the decoder of Fig. 10, ~or example, because the S84 mode, the S82, and the M82 are able to be processed, the mode selection signal corresponding to each of the above modes, and formed of bit sequences as indicated in Table II, must be supplied at input terminal 83. The various ~tates in Table II in which the result is irrelevant, that is, ~don't care~ are represented by an x.
In all events, the output signal from a latch circuit 32c is fed to 8-bit D/A convertor 84 wherein the 12S8S~O
data are converted from digital parallel signals to a single analog signal fed to a selector input of switch 85.
Switching circuit 85 is operable to change the input ~ignal betwen two separate outputs in response to a left/right switching signal produced by timing circuit 82b, so that the output signal from D/A convertor 84 is fed to output terminals 86a and 86b, alternately. Thus, in the case of a stereo mode signal the left channel signal is delivered to one of the output terminals, 86a or 86b, and the right channel ~ignal is delivered to the other output terminal.
Conversely, in the case of the monaural mode, the monaural signal is delivered to both ~utput terminals 86a and 86b by a bridging action of switching circuit 85 (not shown).
The decoder of Fiq. 11 is required for the S164 mode and employs two latch circuits 87 and 88, which correspond to the lower 8-bits and upper 8-bits of the 16-bit signal, respectively, are arranged at the output stage of latch circuit 82c and a 16-bit D~A convertor 89 is connected at the outputs of la~ch circuits 87 and 88. A
timing circuit 90 is provided that receives inputs from timing circuit 82b and provides latch signals for latch circuits 87 and 88 and also provides the left/right switching signal fed to switching circuit 85. Timing circuit 90 provides the appropriate control cignals based upon the sampling signals having frequencies of 22.05KHz, 44.1K~z, and the left/right switching signal, as applied thereto from timing circuit 8Zb. In order to have timing circuit 82b proYide ~he appropriate timing signals to timing circuit 90, and because the ~elected mode is the S164 mode, SO~u~i 12585~0 the mode ~election signal formed in accordance with the bit series shown i~ the first row of Table II must be fed into terminal 83. As in the decoder of Fig. 10, the Eerial data is fed in at input terminal 81 and input to serial-to-parallel convertor 82a, in which it is converted in accordance with a control signal from timing circuit 82b and then latched into latch circuit 82c. Output of data from latch 82c is performed in accordance with latching circuit from timing circuit 82b such that the lower 8-bits of data o~ the 16-bit data i5 latched in~o latch circuit 87, while the upper 8-bits of data is latched into latch circuit 88. Accordingly, at the output of latch circuits 87 and 88 are the lower eight bits and the upper eight bits of the left channel ~tereo signal during the first half of the 22.7 micro-second period and the lower eight bits and the upper eight bits of the right channel stereo ~ignal during the second half thereof. Thi~ arrangement is repre~ented in Fig. 12~. The outputs of latch circuits 87 and 88 are fed to D/A convertor 89 wherein they are converted to analog signals and fed as inputs to swi~ching circuit 85.
Switching circuit 85 i5 changed in position in response to the left/right switching signal produced by timing circuit 90 and, accordinqly, the left channel signal is produced at either one of output terminals 86a or 86b and the right channel signal is produced at the other output terminal.
Although in ~he above-described embodiment of the pre6ent invention four data channels are all dividPd into a plurality of data word lengths this need not be the case and all that is required in that one data channel be divided 1258~20 into such data lengths. For example, an arbitrary combination of the various modifications in which only one data channel is divided could be provided with the remaining data channels being continuous data instead of being divided. Additionally, it should be understood that while the sampling frequency~ data length, and the like are set forth above relative to the different embodiments these parameters are merely examples and the present invention is not limited to these particular values but can be varied as required.
Referring back then to Figs. 3A and 3B it is noted that service bit signals SBl to 5B255 were ~dded to the word synchronizing signals ~Sl - WS255, respectively as being formed of four bits and 50 one ~ervice bit ignal is employed over two words. Eight bits of ~uch 6ervice bit signal can then be used as ~he above mode selection signal a~ might be fed in at terminal 83, for example, the most significant bit (~S~) is assigned to a parity check function, the ~econd significant bit t2SB) is assigned as emergency broadcasting, the third significant bit (3SB3 is assigned to facsimile broadcasting, the fourth significant bit (4SB) is assigned to communication broadcasting, the fifth significant bit ~5SB) is assigned to stereo broadcast in which the data length is 16-bits, as shown for example in Fig. 4A, the sixth significant bit ~6SB) is assigned to ~tereo broadcasting, in which the data length is B-bits, as represented in Fig. 4B, the seventh significant bit ~7SB) is assigned to monaural broadcasting, in which the data length is 8-bits, as represented in Fig. 4C, and the least ~ So2C21 ~25~5ZO
significant bit (LSB) is assigned to the transmission of computer software, such as computer games or the like. In the use of ~uch service bit signals employing 8-bits AS
described hereinabove, when any one bit is a a ~1 n then the terminal on the receiving side is controlled to carry out the operation corresponding thereto. The logical state of this sisnal may be chosen as required.
Because the frame synchronizing signal and the word synchronizing signal can be easily discriminated one from another at the receiving side, i~ is possible to readily identify 256 addresses for 256 words comprising one - frame, for example, as 6een in Fig. 3A. Thus, on the basis of the contents of the service bits added to each word synchronizing signal~ it is possible to carry out the various services corresponding thereto, as explained hereinabove. Nevertheless, when it is required to provide addresses that exceed 256 in number, ~ome further action must be taken. Therefore r the service bit SBf which is added to the frame synchronizing signal FS is provided ~ith and desired 4-bi pattern, which can represent, for example, a start pattern involving the beginning of addressing, a continuous pattern representing the continuity of addressing, and an end pattern which represents the end of addressing and so forth. These patterns can then be followed by the frame synchronizing signal FS of an arbitrary number in accordance with the ~cale of the system.
Accordingly, when the word synchronizing signals are sequentially counted from the frame synchronizing signals that are added with the service bits of the start pattern, a l~S85ZO
large number of addresses can be suitable assigned. Fig. 13 schematically lllustrates in block diagram form an embodiment of a practical circuit to accomplish this.
In Fig. 13, input terminal 100 receives information having the above-described signal format and such informati~n i5 fed to a service bit latch 102, to a word synchronization detector 103, to a frame synchronization detector 104, and ~o a service bit detector 105 for detecting the service bit that is added to the frame ~ynchronizing signal. Word ~ynchronization detector 103 ~equentially detects the word synchronizing signal arranged between respective frame synchronizing signals, as seen for example in ~igs. 3A and 3B, and supplies the detected word synchronizing signal as a clock signal to a counter 106, in which such clock signal~ are counted up. The frame synchronizing detector 104 operates to detect the frame ~ynchronizing signal added at the beginning of each frame, as represented in Fig. 3A, and produces an output signal fed to service detector 105 that operates as its drive signal.
Service bit detector 105, when receiving the sutput signal from frame synchronizing detector 104, detects the service bit added to the frame synchronizing signal and identifies the particular pattern, that is, the pattern of the start, continuous, and end patterns, to which such service bit belongs. In the event the service bit belongs to the start pattern, service bit detector 105 produces at its output a reset ~ignal, whereby the contents of counter 106 are cleared. Thus, in synchronism with the frame synchronising signal added with the service bits that represents the start 1258~20 pattern, counter 106 will sequentially count up the word synchronizing signal following the frame synchronizing signal. If the identified pattern represents the continuous pattern, then the count operation of counter 106 is continued and ultimately ended when the frame synchronizing signal is added with the ~ervice bit, which indicates that the end pattern is detected.
The output of counter 106 is fed to one input of coincidence circuit 107 and operates as the address data therefor. This input is compared with another address data signal fed into the other input of coincidence circuit 107 from an addressing circuit 108, in which self-addressing data, that is, the address n~mber, has been stored in advance. When the two address data signals fed into coincidence circuit 107 are in agreement, coincidence circuits 107 produces an output signal fed to service bit latch 102, which operates as the latching signal. Because service bit latch 102 is continuously 6upplied with the received data at input terminal 100, when the latching ~ignal from coincidence circuit 107 is received, service bit latch circuit 102 will latch the service bit added to the word synchronizing signal at that time as its self-service bit. ~he latched service bit is then supplied to a microcomputer 109, which produces system control signals at it output terminal 110 in accordance with the contents of the service bit. As a result, based upon the system control ~ignal, operation of the corresponding apparatus (not shown) is controlled by the microcomputer 109.
~ . SO2021 lZ58~ZO
As seen from the above, because the service hit is used to control the state of each receiving terminal, communications, emergency bro~dcasting, facsimile transmission or ~he like are possible only to the specified user and, moreover, in the situation where charges are made for the various services, such as pay audio, pay channel television, or pay computer games, the receiver at the *erminal side can be controlled (addressed) to allow only the appropriate 6ubscribers to enjoy the appropriate ser~ice.
Accordingly, with the present invention because at least one channel of digital siynals among a plurality of channels is divided into a series of shorter data lengths and each divided data length transmitted within a constant time interval, which interval can be ~elected, the signal can be transmitted in various ~odes such as high quality stereo musi~, multi-channel stereo music, audio services such as news, weather forecasts, communications broadcasting, and the like each requiring ~egmented multiple channels. For example, in a cable television transmission line where the bandwidth of a typical television channel of 6MHz is employed, a 16-bit signal having a sampling frequency of 44.lRHz will permit a music program of up to four stereo channels to be transmitted. When one such standard bandwidth television channel is provided with an 8-bit fiignal having a sampling frequency of 44.lR~z then up to eight stereo channels of music can be transmitted simultaneously. Thus, ~ubscription music ~ervice is quite possible.
. SO2021 l'~S~5'~0 Furthermore, in making ~acsimile transmissions, and employing the M82 mode, for example, eight channels of faesimile signals can be transmitted simultaneously though a single data channel. This permits use of extremely high speed ~acsimile receivers and, thus, even greater facsimile transmissions become possible. When transmitting computer software and assuming the M82 mode is being employed, for example, when one bit is assigned to one particular compu~er software routine 64 different oomputer software programs can be transmitted simultaneously through one data channel.
~ ccording to the present invention, because the service bit added to the frame synchronization signal as a auxiliary information is detected and the word synchronization signal is ~equentially counted thereby to identify the address ~$ate 7 addressing over ~ plurality of frames is possible. This means that when a system has a very large number of receiver terminals it is possible to easily control the receiving state at each of these terminals, because a very large number of addresses are afforded by ~preading the addressing over a plurality of frames.
Although illustrative embodiments of the present invention have been described in detail above with reference to the accompanying drawings, it is understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope or spirit of the invention, as defined by the appended claims.
Field of the Inventisn:
This invention relates generally to a digital signal transmitting and receiving system and, more ~pecifically, to a system for use in transmitting a digital signal such as might be derived by digitally converting an analog stereo cignal, announcement ignal, facsimile data signal, or a computer game program, on a cable television transmission line using a single, unused television channel having ~ ban~width of approximately 6MHz.
BRI~:E` DESCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic in block diagram form of a ~igital data tr~nEmitting ~y6tem using a cable television tran~mission line ~uitable ~or u e with the present invention;
~ ig. 2 i6 a digital signal receiviny 6ystem employing a cable television transmission line suitable for use with the present invention;
Figs. 3A and 3B represent digital signal formats used in a digital signal transmitting ~ystem according to the present invention;
Figs. 4~-4D schematically represent digital signal formats for use in an embodiment of a digital ~ignal transmitting system according to the present invention;
~ ig. 5 is a block diagram of a digital signal generator according to an embodiment of the present invention;
Fig. 6 i8 a block diagram of a digital signal generator ~ccording to another embodiment of the present invention;
~ ig. 7 is a block diagram of a digital cignal qenerator according to another embodiment of the present invention;
Fig. 8 is a block diagram of B digital signal generator according to another embodiment of the present invent~on;
Fig. 9 is a block diagram of a digital signal generator according to a an~ther embodiment of the present invention;
Fig. 10 i~ a ~lock diagram of a demodulator for u~e ~n the present invention;
Fig. 11 is a block diagram o~ a anoth~r embodiment of a demodulator for use in the present invention;
Figs 12A-12H are timing waveform diagrams 6howing the operation o~ the demodulators ~f Figs. 10 and 11; and Fig. 13 is a block diagram of an embodiment of zn nddressing circuit according to the present invention;
.. ..
Description of the Backqround:
In order to better understand the signal transmitting system of this invention an overall system ~uitable for employing the present invention is first described. The present invention is intended to employ a cable television (CATV) transmission line ~nd Fig. 1 shows a digital signal transmitting system for use with such transmission line. Input terminals 201-204 are arranged to 12S8SZo receive ~nalog signals, which might be analog 6tereo signals, and such input signal6 are fed to analog-to-digital convertors 207-210, respectively. The resultant digital signals from analoy-to-digital convertors 207-210 are then fed to a multiplexer 213 that produces at its ~utputs two ~erial data streams that represent the four input ~ignals having been time division multiplexed. ~i~e division n multiplexing being a ~nown approach to tra~smitting a number ~f 6ignals over a commmon path by using different time ~terv~16 f~r the tran~mission of the intelligence of each message signal. Then, the time division multiplexed digital signals from multiplexer 213 are fed to a filter 214, which is provided to suppress intersymbol interference that causes code error. Filter 214 may advantageously eomprise a binary ~F
transversal filter having tap coefficients adjusted so that the modulation signal satisfies Nyquits'~ fir~t criterion.
The output of filter 214 is fed to a four-level convertor 215 which may be thought of as operating as a digital-to-analog c~nver~or so that it converts the input digital signals to a four-level, base-band ~ignal. This four-level analog signal produced by four-level convertor 215 has four different amplitude values ranging from zero to three, which are respectively expressed as ~o" + ~on = no~l "0 + ~ 1" + ~0~ - ~2n, and ~1~ + ~ln ~ ~3n. This pseudo-analog output signal is fed to an amplitude-modulation (AM) modulator 216 wherein it ~M
modulates an intermediate frequency signal (IF) having a frequency of 3B.9MHz, for example, ~upplied by oscillator 217. The output of the AM modulatox 216 i8 fed through a vestigial side-band filter 218 to a mixer 219. This vestigial side-band modulation is the ~ame as in conventional television transmissions. Thus, the filtered signal is mixed in mixer 219 with an RF signal (fc ~ fif) ~upplied by a local oscillator 220. The output signal of mixer 219 repre~ents a modulated fiignal having a carrier frequency fc of 97.25M~z, for example, and such output signal i~ fed through a bandpass filter 221 to output terminal 222 as the modulated, system output signal, the ~ndwidth of which is limited to 6M~z. The output signal ~eveloped at output terminal 222 is then fed to a head end of a CATV system (not shown). Thus, the original input signals are placed in ~n unused television channel on a conve~tional cable television transmission line and require no more bandwidth (6NHz) t~en a typical ~ingle television channel.
Fig. 2 shows a eystem for ~receiving~ a signal as might be placed on the ~ATV transmission line by the ~ytem of Fig. 1, in which the modulated ~ignal transmitted through the-transmission line of the CATV 6ystem is supplied at input terminal 231 to a wide bandwidth receiver front end 232 where it is amplified and ~onverted to an intermediate frequency (IF) signal of 58.7 MHz, for example, and this intermediate frequency signal is supplied to a phase-locked loop (PLL) synchronous detector 233, which functions as an AM detector, so that the four-level, base-band qignal, as produced by the four-level convertor 215 of Fig. 1, is i2S8S20 demodulated. An automatic gain control (AGC) circuit 246 i5 provided with an input from PLL detector 233 and produces an output control signal fed to front end 232 to prevent ~verloading of the front en~ amplifier. The output ~ignal from the phase-locked loop detector 233 is fed to a level comparator 234, which operates an a kind of analog-tG-digital convertor, by demodulating the detected signal and pr~duces a series digital signal ha~ing four possible values, ~on, ~ 2~, and ~3n, on ~he basis of whether the output signal from the PLL detector 233 exceeds a reference level, as represented by a so-called eye pattern. ~he eye pattern is generally known in data tran~mission by an oscilliscope display of the detector ~oltaye waveform in a data modulator/demodulator. This pattern gives a convenient sepresentation of cross-over distorti~n and can be derived in the known fashion, based upon the overall frequency characteristics of the ~ystem and the relationship thereto hetween the Nyquist frequency and the transmission capacity of the system in bits per second.
The digital signal thus essentially demodulated by level comparator 234 is fed to a demultiplexer 235~ Also produced by the level comparator 234 is a bilevel synchronizing signal fed to a clock reproducing circuit 245 that produces a bit clock signal applied to demultiplexer 235 to control the output thereof in the appropriate time-division manner. Also produced by clock reproducing circuit 24S is a synchronizing ~ignal fed to both the automatic gain control circuit 246, as well as to l~S8SZO
demultiplexer 235. Demultiplexer 235 then produces a plurality of digital sig~als in a time-division manner that are supplied, respectively, to digital-to-analog (D/A) convertors ~39 - 242, so that analog signals corresponding to the original input signals as applied at inputs 201 -204, (Fig. 1) are respectively developed at output terminals 243 - 246.
Nevertheless, eve~ though the system is described hereinabove would appear to be a workable and feasible ~ystem in actuality such ~ystem is not avaiable for use in a effective and usable ~orm, principally ~ecause of the lack of an economical ~ethod of addressing the receiver terminals.
The problem being that in a ~ransmission 6y~tem, such as ca~le television, in which the ~ignal is transmitted through a cable, that is, hard wired, at the receiving ~ide at which-the ~ignal~ ~re being distributed there may be fewer than several hundred receivers, or there may be up to several tens of ~housands of receivers. In other words, there i5 a wide spread in the number of receiving units that may be connected to the cable television transmission line.
In the proposed systems, each of the receiver terminals usually has an individual ~ddress signal and the transmitter side then transmits a control signal corresponding to each address number, wherein the receiving state of each receiver terminal can be controlled.
In the systems proposed to use cable television tranmission lines as outlined above, the control signal that ~2S8SZO
corresponds to each address is formed as a bit ~eries, which can cover the maximum number of receiver terminals and in most cases this involves a bit series of approximately 20 bits. The control signal used to perform such addressing is then transmitted using a special address network line that is different from the data network line. Accordingly, if ~uch address network line is designed to permit it to accommodate a system having a large number of receiver terminals, for example, ranging from several tens of thousands to several hundred-thousands, then this address network line will be uneconomical and will be too sophisticated and expensive for ~ystems having a substantially fewer number of terminal receivers. On the other hand, if the addres network line is designed to ~ccommodate a sy6tem having, for example, less than ~everal hundred terminal~ then ~uch address network line is almost unusable when applied to a system having a subtantially greater number of receiver terminals and, thus, the address network lines must be increased correspondinsly.
Accordingly, as described above, while the concept of a system for transmitting digital sisnals on a cable television transmission line is feasible, the data addressing system is not available ~uch that the address network lines need not be chanqed in accordance with the scale of the EyStem~ in order to eliminate the redundancy and uneconomical provision o~ more address network lines than required for the smaller ~ize system. Purthermore, becal7se special ~ddreqs network lines must be provided, the l;~S~35ZO
data addressing system becomes complex in its circuit arrangement and is thereby expensive in view of the associated manufacturing costs.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the presen~
invention to provide an improved digital signal transmitting and receiving 6ystem that can overcome the a~ove-noted shortcomings inherent in the prior art.
It is another ~bjert o~ the present invention to provide a digi~al signal transmitting and receiving system for transmitting a digital audio signal or digital data ~ignal using the transmission line of a cable television network.
It is a further object of the present invention to provide a digital siynal transmitting and receiving ~ystem suitable for transmitting digital zudio signals or digi~al data eignals in which a large number of receiver terminals of a cable television y~tem can be addressed without requiring cpecial addressing network lines.
According to one aspect of the invention a digital signal transmitting sy~tem is proviaed including a circuit generating digital word signals in a first mode in which each of the signals consists of a word synchronizing 6ignal, and data signals having a first bit code and being sampled at a first sampling frequency and a circuit for generating digital word signals in a second mode, each of the word signals in the second mode con6i~ting of a word synchronizing signal ~nd data ~ignals having a second bit 12585'~0 code and being sampled at a sec~nd sampling frequency and a selective transmitter that selectively transmits the first mode of digital word si~nals and the second mode of digital word signals through a transmission line o~ a cable television system.
According to another aspect of the present invention a digital signal receiving system is provided that includes a circuit to receive digital signals in a first mode in which the firs~ mode digital signals consist of a word ynchronizing ~iqnal, a f irst ~ervice bit signal, and data signals having a first bit code and being sampled by 2 first ~ampling frequency and for recei~ing a second mode of digital word ~ignals, each consisting of a word synchronizing signal 7 a ~econd service bit ~ignal, and data 6i~nal6 including second bit codes and being sampled at a ~econd sampling frequency. A demodulator is connected to the signal input terminal of the receiver and latches the first-mode of the digital word signals and conver~s the digital word ~ignals to analog ~ignals. A second demodulator is provided that is connected to the signal input terminal of the rec~iver and la~ches the second mode of digital word signals and also converts such signals into analo~ signals. A control system is provided that c~ntrols the mode of the first and second demodulators in order to selectively enable one or the other in response to a mode control 6ignal.
In yet another embodiment of the invention the transmitter and receiver are com~ined into a complete system 12S~35~0 in which a single tra~smitter can provide digital data for a plurality of receivers and such plurality of receivers may be accessed or addressed using only the cable television transmission line over which the actual data signals are transmitted~
The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description of illustrative e~bodimen ~ thereof to be read in conjunction with the nccompanying drawings.
DESCRIPTION OF ~HE PREFERRED EMBODIMENTS
-While Figs. 1 and 2 have been described hereinabove as being exemplary of digital data transmission and receiving systems the present invention as it relate~ to the addressing network is described in relation to Figs. 3 through 13 and, in particular, Figs. 3A and 3B represent a data format ~ccording to the present invention. In Fig. 3A, one frame is ~hown as being formed of 256 words, which at the preferred transmission rate corresponds to 5.81ms. Eacb frame begins with a frame synchronizlng signal FS formed of eight ~its and is followed by a ~ervice bit word of four bits and a first data word W0 of 156 bits. Thereafter, are the remaining 255 data words, W1 to ~255, each word being formed of 156 bits, each beginning with word ~ynchronizing signals WSl to WS255 and each being formed of eight bits, and service bit words SBl to SB255, each being formed of four bits, respectively. Note that the frame ~ynchronizing signal FS also serves as the word 12~35Zo eync~ronizing 6ignal (WSO) for the first data word WO.
Pig. 3B represents one of the 256 words of a frame and, as shown therein, the eight bits of the fiynchronizing signal SYNC are at the beginning of the word f~llowed by the - lOa -~XS8S20 four service bits and then the data word is made up of four data channels, CH1 - CH~, each data channel having a data length of 32 bits and a s~mpling frequency of 44.lKHz, and an error correction code ECC. An error correction code is added at each of the recpective data channels CHl - C~4 and may comprise a Bose-Chaudhuri-Hocquenghem (BCH) code or Extended Hamming Code, each having a length of se~en bits.
Figs. 4A - 4D illustrate data formats for a plurality of different operating modes of the present invention and, specifically, Fig. 4A represents a first mode (A) in which 32-bit data represents a stereo digital audio signal such that a left channel stereo signal L includes 16 bits and a right channel stereo signal R includes the similar 16 bits. This 16-bit data format is based upon a sampling freguency of 44.1RHz and is the same data format as the presently available ~ompact audio disc (CAD), which is fa~t becoming a very popular music source for high quality stereo music programs.
Fig. 4B represents a ~econd mode (B) in which the data format of 32 bits are divided into four sets of eight bits and can represent two channels of stereo signals La, Ra and Lb, Rb. This format provides data suitable for multichannel stereo music, not quite of the extreme high quality of mode A represented in Fig. 4A. The quality of sound according to mode ~ is the equivalent to, or better than, conventional FM broadcasting.
Another mode (C) is represented in Fig. 4C, in which an 8-bit data format is provided and in which the sampling frequency of 44.lKHz of Figs. 4A and 4B is halved to provide a s ?ling frequency of 22.05K' . This results in a data format that can provide eight monau-21 chann~ls a to h which a~e suitable for monaural voice service, sucl~ as news, weather forecasts, communications, an~ the like. Mode (D) is represer.ted in Fis. 4D and is a combination of mod~s (B) and (C) anc can be used to transr.it one high fidelit~-stereo program and four monaural audio programs. In such case, the 8-bit stereo channels employs a frequenc~ of 44.lK~:z resulting in two channels of eight bits, e~ch intermixed with four monaural mode chanr,els, havir.g a frequenc~ cf 22.05XHz. The mode represented in Fig. 4D
realizes a pl~rality of modes within a single data channe' and, thus, provides an elaborate service capability. Note that in Figs. 4~-4D no attempt is made tG show the e~zct time relatlonsh_p between the various modes, a"d the various modes in these Figs. are not drawn to scale.
There are twenty five different combinations of the above-~escribed mGdes, that is, twenty five different s~stems can be specified simply by altering the prosramming of both the transmitting and receiving sides, without modifying the hardware. Nevertheless, considering a data out~ut system according to combinatior.s of the these modes in which the s~mpling frequency is either 2.05KHz, or 44.lRHz, the data length is either eiqht bits or sixteen bits and the signal system is eithe- ~.onaural or stereo, then eight different mode combinations can be tabulated.
These are set forth in the following Table I. '12585ZO
TABLE I
__ . _ ~ . .. ._ s~gnal transmission~ 5 S ¦ S sl M ¦ M j Ml M
data length -¦ 16 16 ¦ 8 81 16 16 ¦ B¦ 8 . _ _ samplinq ~reguency ¦ 4 2 4 2 4 2 4 2 mode 5164¦5162iS84lS82 M164 M162 M84 M82 12S85Zo As seen in Table I, letters S and M designate stereo mode and manaural mode, respectively, reference numerals 4 and 2 designate campling frequencies of 44.1KHz and 22.05KHz, respectively, and the bottom row containing notations 5162, S84, S82, M164, M162, M84, M82 designate different modes that are formed by combining the signal system, the data length, and the sampling frequency. For example, S164, indicates a mode wherein the signal is a stereo signal, the data leng~h is sixteen bits, and the sampling frequency i6 44.lKHz, while M82 indicates a mode in which the signal is monaural, the data length is eight bits, and the sampling frequency is 22.05KHz. The indications representing the other modes are similarly deduced.
Encoders suitable for generating the various modes as described above in relation to Figs. 4A-4D and in Table I, are shown in Figs. ~ through 9 and, of the above different modes 6hown in Table I, the fundamental modes thereof are Sl64, S84, S82, and M82 and, accordingly, an example of an encoder corresponding to each of such fundamental modes is described hereinbelow.
Fig. 5 is a block diagram of an encoder for transmitting the Sl64 mode of Table I in which 32 bits of one data channel are divided into left and right channel stereo signals of sixteen bits each, with the sampling frequency of 44.lKHz. This is the mode represented in Fig.
4A hereinabove. In Fig. 5, a left channel audio analog signal L is applied at input terminal l and a right channel analog signal R is supplied to input terminal 2, and the thus supplied analog signals are fed to respective analog-to-digital convertors (A/D) 3, 4 in which they are converted to digital signals based upon a sampling frequency of 44.1KHz. The resultant digital signals are then the sixteen bit data words as shown in Pig. 4A. The respective digital signals from A~D convertors 3 and 4 are ~ed to a parallel-to-serial convertor (P/S) 5, wherein they are converted from two parallel signals to a serial signal, which is developed at ou~put terminal 6 as the data output signal. Subsequently, this erial data ~ignal at ~utput terminal 6 can be further processed in accordance with any specific or particular use requirement, for example, when this data output signal is intended to be further transmitted using the transmission line of the cable television sys~em the output data signal is amplitude modulated using the vestigial side-band system, as done in ~tandard television systems, and then transmitted to the appropriate receiving side at the customer location.
Fig. 6 is a block diagram illustrating another example of an encoder and, specifically, an encoder corresponding to the S84 mode, which as set forth hereinabove is a fundamental mode of this system, in which 32 bits of one data channel are divided into four segments of eight bits, representing two left and two right stereo channel signals having a sampling frequency of 44.lKHz. The input terminals for the left channel audio analog signals La and Lb are provided at ll and 12, while the right channel analog signals Ra and Rb are supplied, respectively, to input terminals 13 and 14. The analog signals thus applied are fed to respective A/D convertors 15-18 in which they are ~ 25~5~0 converted based upon a sampling signal having a frequency of 44~lRHz 2nd thereby produce digital signals each data length of which is eight bits, as shown for example in Fig. 4B.
These data signals in this "B" mode are then fed to a parallel-to-serial convertor 19 and are developed into a serial bit stream made available at output terminal 20.
Again, this serial digital output ~ignal can be modulated in accordance with the known television techniques and placed on a transmission line of a CATV system.
~ n encoder for producing the ~C" mode as represented in ~ig. 4C, is shown in Fig. 7 in block diagram form in whi~h the S82 mode is produced having 32 bits of one data channel divided into fvur ~ets of eight bits representing four channels of left and right ~tereo signals, with a ~ampling frequency of 22.05KHz over two data words.
Left channel analog ~ignals La, Lb, Lc, and Ld are supplied respectively to input terminals 21, 22, 23, and 24 and right channel analog sigrials Ra, Rb, Rc, and Rd, are supplied to input terminals 25, 26, 27, and 28, respectively. The analog signals applied to inp~t terminals 21-28 are supplied to respective A~D convertors 29-36 wherein they are converted to digital ~ignals based upon a sampling signal having a freguency of 22.05KHz. In this mode then the signals La, Lb, Lc, Ld, Ra, Rb, Rc, and Rd are sequentially provided within a period of 45.4 micro seconds, corresponding to $he reciprocal of the sampling frequency, to a parallel-to-serial convertor 37, in which they are converted from the parallel signals to the serial signal stream which is then made a~ailable at output terminal 38, l~S8SZO
and again which can be signal.processed according to any desired end use.
Fig. 8 is a block diagram of an example of an encoder corre~ponding to the MB2 mode, in which 32 bits of one data channel are respectively divided into four cets of eisht bits representing eight channels monaural signals and having a sampling fresuency of 22.OSKHz over two words. The eight channel monaural signals a ~o h are fed in at input terminals 41 - 48, respectively, and are supplied to respective ~/D convertors 49~56 wherein they are converted to digital signals on the basis of a sampling signal having a frequency of 22.05KHz. Such digital signals will each have a data length of eight bits, as shown in Fig. 4C, and accordingly, this encoder produces the ac" mode discussed hereinabove. The digital signals are then fed to parallel-to-serial convertor 57 in which they are converted from the parallel ~ignals to a serial bit ~tream which is then made available at output terminal 5B as the required data output ~ignal.
Fig. 9 is a combination or a hybrid encoder capable ~f producing mode "D~ as discussed above in which a plurality of different modes, for example, two modes such as the S84 mode, as shown in Fig. 6, and the M82 mode, as shown in Fig. 8 hereinabove. Thus, in Fig. 7, 3eft channel analog signal La is fed in at input terminal 61 and right channel analog signal Ra is fed in at input terminal 62. These analog signals are then applied to respective A/D convertors 67 and 68 wherein they are converted to digital signals ba~ed upon a sampling ~ignal having a frequency of 44.lKHz l~S~3520 and are then fed to parallel-to-serial convertor 73. Analog signals a to d of respective monaural channels are fed to input terminals 63-66 and are then applied to corresponding A/D convertors 69-72, respectively wherein they are converted to digital signals, all of which have a similar sampling frequency of 22.05RHz. The output of A/D
convertors 69 - 72 are fed to parallel-to-serial convertor 73. Accordingly, parallel-to-serial convertor 73 is supplied with stereo signals and monaural signals and then converts the parallel digital signals into ~erial digital data ~tream and produces at output terminal 74 a mixed output data ~ignal. More specifically, the encoder of Fig.
S produces one channel of stereo signals having a ~ampling frequency of 44.1~Hz and data length of eight bits, and four channels of monaural ~ignals having a sampling frequency of 22.05R~z and also having a data length of eight ~its.
Note that one frame is processed at a rate of 22.7 micro-seconds, which is derived as a reciprocal of the 44.1~Hz sampling frequency, and results in a transmission bit rate of approximately 7.4 mega ~its per 6econd (MBPS).
This rate corresponds to the general transmission capacity of a CATV system.
Upon transmitting, each of the above modes is selected in advance and its signal is then transmit~ed. The receiver at the customer location must employ the appropriate decoders, and such decoders are represented in Figs. 10 and 11. In the decoder of Fig. 10, a common conventional 8-bit digital-to-analog (D/A) convertor is employed as the convertor, whereas in the embodiment of Fig.
~ u ~ u ~ ~L
~2S8S~O
11 a conventional 16-bit D/A convertor is employed.
Therefore, of the four fundamental modes, the decoder shown in Fig. 10 can be used for the M82 mode, the S82 mode, and the S84 modes, while the decoder of Fig. 11 is employed for the S164 mode. As for the ~84 mode, this can be processed substantially the same as the S82 mode and in which case the decoder of Fig. 8 is employed.
Referring now specifically to Fig. 10, input terminal 83 receives a ~erial data signal having a data ~ormat according to any of the above-de~cribed format modes produced at the transmitting side, and the serial data at input terminal 81 is fed to a serial-to-parallel (S/P) convertor 82a, which forms a part of demodulating circuit 82. Demodulating circuit 82 may be advantageously formed as a single integrated circuit. S/P convertor 82A converts thP
serial data received at input terminal 81 to parallel signals based upon a clock signal produced by a timing circuit 82b. The output signals thus produced are latched into a latch circuit 82c on an 8-bit by 8-bit basis, as determined by a latch signal also produced by timing circuit 82b.
Therefore, latch circuit 82c produces the 8-bit data of a monaural signal, as might be represented in Pig.
12A, during a period of 45.4 micro-seconds in the M82 mode, whereas latch circuit ~2c would produce each 8-bit data of left and right channel stereo signals during a period of 45.4 micro seconds in the S82 mode, as represented in Fig.
12B. Similarly, in the M84 mode, as represented in ~ig.
12C, 8-bits of data of two monaural signals is produced 12S8S~
during a period of 22.7 micro-seconds and in the M162 mode, as represented in ~ig. 12D, the lowermost 8-bit data of the 16-bit monaural signal is produced during the first half period of 45.8 micro-seconds, while the upper 8-bits of data is produced in the latter half of the second half of the 45.4 micro-seconds period.
Fig. 12E represents the S84 mode, in which each 8-bits of data of the left and right channel stereo signal is produced dusing a period of 22.7 micro-seconds by latch circuit 82c. Fig. 12F represents the S162 mode in which lower 8-bits of data and upper 8-bits of data of a left channel ~tereo signal are produced during the first half of the 45.4 micro-seconds period, whereas the lower 8-bits of data and upper 8-bits of data of the right channel 6tere~
signal are produced during the latter half of this period.
In the M164 mode, as represented in Fig. lOG, the lower 8-bits of data of the 16 bit monaural signal are produced during the former half of the 22.7 micro-seconds period, while the upper 8-bits of data thereof is produced during the lat~er half of such period.
The selection of any of the above modes is of course made in advance ~y a mode selection signal, which can then be fed to timing circuit 82b, fed in at input terminal 83. The state of such mode selecting signal as required to set each of the fundamental modes S164, S84, S82, and M82 has a code indicated in Table II as set forth hereinbelow.
--lg--S~20~1 12S~O
TABLE II
Mode Ml M0 C2 Cl C0 ... _ _ ~
S1~4_ 0 0 x x x S ~--1 O 1 K ~
CB2_1 _ 0 ~ D 0 ~J~
Table II represents that each of the fundamental modes may be ~pecified by two bits (M1, ~0) and the channel of each mode may be specified ~y three bits (C2, Cl, C0).
Thus, in the decoder of Fig. 10, ~or example, because the S84 mode, the S82, and the M82 are able to be processed, the mode selection signal corresponding to each of the above modes, and formed of bit sequences as indicated in Table II, must be supplied at input terminal 83. The various ~tates in Table II in which the result is irrelevant, that is, ~don't care~ are represented by an x.
In all events, the output signal from a latch circuit 32c is fed to 8-bit D/A convertor 84 wherein the 12S8S~O
data are converted from digital parallel signals to a single analog signal fed to a selector input of switch 85.
Switching circuit 85 is operable to change the input ~ignal betwen two separate outputs in response to a left/right switching signal produced by timing circuit 82b, so that the output signal from D/A convertor 84 is fed to output terminals 86a and 86b, alternately. Thus, in the case of a stereo mode signal the left channel signal is delivered to one of the output terminals, 86a or 86b, and the right channel ~ignal is delivered to the other output terminal.
Conversely, in the case of the monaural mode, the monaural signal is delivered to both ~utput terminals 86a and 86b by a bridging action of switching circuit 85 (not shown).
The decoder of Fiq. 11 is required for the S164 mode and employs two latch circuits 87 and 88, which correspond to the lower 8-bits and upper 8-bits of the 16-bit signal, respectively, are arranged at the output stage of latch circuit 82c and a 16-bit D~A convertor 89 is connected at the outputs of la~ch circuits 87 and 88. A
timing circuit 90 is provided that receives inputs from timing circuit 82b and provides latch signals for latch circuits 87 and 88 and also provides the left/right switching signal fed to switching circuit 85. Timing circuit 90 provides the appropriate control cignals based upon the sampling signals having frequencies of 22.05KHz, 44.1K~z, and the left/right switching signal, as applied thereto from timing circuit 8Zb. In order to have timing circuit 82b proYide ~he appropriate timing signals to timing circuit 90, and because the ~elected mode is the S164 mode, SO~u~i 12585~0 the mode ~election signal formed in accordance with the bit series shown i~ the first row of Table II must be fed into terminal 83. As in the decoder of Fig. 10, the Eerial data is fed in at input terminal 81 and input to serial-to-parallel convertor 82a, in which it is converted in accordance with a control signal from timing circuit 82b and then latched into latch circuit 82c. Output of data from latch 82c is performed in accordance with latching circuit from timing circuit 82b such that the lower 8-bits of data o~ the 16-bit data i5 latched in~o latch circuit 87, while the upper 8-bits of data is latched into latch circuit 88. Accordingly, at the output of latch circuits 87 and 88 are the lower eight bits and the upper eight bits of the left channel ~tereo signal during the first half of the 22.7 micro-second period and the lower eight bits and the upper eight bits of the right channel stereo ~ignal during the second half thereof. Thi~ arrangement is repre~ented in Fig. 12~. The outputs of latch circuits 87 and 88 are fed to D/A convertor 89 wherein they are converted to analog signals and fed as inputs to swi~ching circuit 85.
Switching circuit 85 i5 changed in position in response to the left/right switching signal produced by timing circuit 90 and, accordinqly, the left channel signal is produced at either one of output terminals 86a or 86b and the right channel signal is produced at the other output terminal.
Although in ~he above-described embodiment of the pre6ent invention four data channels are all dividPd into a plurality of data word lengths this need not be the case and all that is required in that one data channel be divided 1258~20 into such data lengths. For example, an arbitrary combination of the various modifications in which only one data channel is divided could be provided with the remaining data channels being continuous data instead of being divided. Additionally, it should be understood that while the sampling frequency~ data length, and the like are set forth above relative to the different embodiments these parameters are merely examples and the present invention is not limited to these particular values but can be varied as required.
Referring back then to Figs. 3A and 3B it is noted that service bit signals SBl to 5B255 were ~dded to the word synchronizing signals ~Sl - WS255, respectively as being formed of four bits and 50 one ~ervice bit ignal is employed over two words. Eight bits of ~uch 6ervice bit signal can then be used as ~he above mode selection signal a~ might be fed in at terminal 83, for example, the most significant bit (~S~) is assigned to a parity check function, the ~econd significant bit t2SB) is assigned as emergency broadcasting, the third significant bit (3SB3 is assigned to facsimile broadcasting, the fourth significant bit (4SB) is assigned to communication broadcasting, the fifth significant bit ~5SB) is assigned to stereo broadcast in which the data length is 16-bits, as shown for example in Fig. 4A, the sixth significant bit ~6SB) is assigned to ~tereo broadcasting, in which the data length is B-bits, as represented in Fig. 4B, the seventh significant bit ~7SB) is assigned to monaural broadcasting, in which the data length is 8-bits, as represented in Fig. 4C, and the least ~ So2C21 ~25~5ZO
significant bit (LSB) is assigned to the transmission of computer software, such as computer games or the like. In the use of ~uch service bit signals employing 8-bits AS
described hereinabove, when any one bit is a a ~1 n then the terminal on the receiving side is controlled to carry out the operation corresponding thereto. The logical state of this sisnal may be chosen as required.
Because the frame synchronizing signal and the word synchronizing signal can be easily discriminated one from another at the receiving side, i~ is possible to readily identify 256 addresses for 256 words comprising one - frame, for example, as 6een in Fig. 3A. Thus, on the basis of the contents of the service bits added to each word synchronizing signal~ it is possible to carry out the various services corresponding thereto, as explained hereinabove. Nevertheless, when it is required to provide addresses that exceed 256 in number, ~ome further action must be taken. Therefore r the service bit SBf which is added to the frame synchronizing signal FS is provided ~ith and desired 4-bi pattern, which can represent, for example, a start pattern involving the beginning of addressing, a continuous pattern representing the continuity of addressing, and an end pattern which represents the end of addressing and so forth. These patterns can then be followed by the frame synchronizing signal FS of an arbitrary number in accordance with the ~cale of the system.
Accordingly, when the word synchronizing signals are sequentially counted from the frame synchronizing signals that are added with the service bits of the start pattern, a l~S85ZO
large number of addresses can be suitable assigned. Fig. 13 schematically lllustrates in block diagram form an embodiment of a practical circuit to accomplish this.
In Fig. 13, input terminal 100 receives information having the above-described signal format and such informati~n i5 fed to a service bit latch 102, to a word synchronization detector 103, to a frame synchronization detector 104, and ~o a service bit detector 105 for detecting the service bit that is added to the frame ~ynchronizing signal. Word ~ynchronization detector 103 ~equentially detects the word synchronizing signal arranged between respective frame synchronizing signals, as seen for example in ~igs. 3A and 3B, and supplies the detected word synchronizing signal as a clock signal to a counter 106, in which such clock signal~ are counted up. The frame synchronizing detector 104 operates to detect the frame ~ynchronizing signal added at the beginning of each frame, as represented in Fig. 3A, and produces an output signal fed to service detector 105 that operates as its drive signal.
Service bit detector 105, when receiving the sutput signal from frame synchronizing detector 104, detects the service bit added to the frame synchronizing signal and identifies the particular pattern, that is, the pattern of the start, continuous, and end patterns, to which such service bit belongs. In the event the service bit belongs to the start pattern, service bit detector 105 produces at its output a reset ~ignal, whereby the contents of counter 106 are cleared. Thus, in synchronism with the frame synchronising signal added with the service bits that represents the start 1258~20 pattern, counter 106 will sequentially count up the word synchronizing signal following the frame synchronizing signal. If the identified pattern represents the continuous pattern, then the count operation of counter 106 is continued and ultimately ended when the frame synchronizing signal is added with the ~ervice bit, which indicates that the end pattern is detected.
The output of counter 106 is fed to one input of coincidence circuit 107 and operates as the address data therefor. This input is compared with another address data signal fed into the other input of coincidence circuit 107 from an addressing circuit 108, in which self-addressing data, that is, the address n~mber, has been stored in advance. When the two address data signals fed into coincidence circuit 107 are in agreement, coincidence circuits 107 produces an output signal fed to service bit latch 102, which operates as the latching signal. Because service bit latch 102 is continuously 6upplied with the received data at input terminal 100, when the latching ~ignal from coincidence circuit 107 is received, service bit latch circuit 102 will latch the service bit added to the word synchronizing signal at that time as its self-service bit. ~he latched service bit is then supplied to a microcomputer 109, which produces system control signals at it output terminal 110 in accordance with the contents of the service bit. As a result, based upon the system control ~ignal, operation of the corresponding apparatus (not shown) is controlled by the microcomputer 109.
~ . SO2021 lZ58~ZO
As seen from the above, because the service hit is used to control the state of each receiving terminal, communications, emergency bro~dcasting, facsimile transmission or ~he like are possible only to the specified user and, moreover, in the situation where charges are made for the various services, such as pay audio, pay channel television, or pay computer games, the receiver at the *erminal side can be controlled (addressed) to allow only the appropriate 6ubscribers to enjoy the appropriate ser~ice.
Accordingly, with the present invention because at least one channel of digital siynals among a plurality of channels is divided into a series of shorter data lengths and each divided data length transmitted within a constant time interval, which interval can be ~elected, the signal can be transmitted in various ~odes such as high quality stereo musi~, multi-channel stereo music, audio services such as news, weather forecasts, communications broadcasting, and the like each requiring ~egmented multiple channels. For example, in a cable television transmission line where the bandwidth of a typical television channel of 6MHz is employed, a 16-bit signal having a sampling frequency of 44.lRHz will permit a music program of up to four stereo channels to be transmitted. When one such standard bandwidth television channel is provided with an 8-bit fiignal having a sampling frequency of 44.lR~z then up to eight stereo channels of music can be transmitted simultaneously. Thus, ~ubscription music ~ervice is quite possible.
. SO2021 l'~S~5'~0 Furthermore, in making ~acsimile transmissions, and employing the M82 mode, for example, eight channels of faesimile signals can be transmitted simultaneously though a single data channel. This permits use of extremely high speed ~acsimile receivers and, thus, even greater facsimile transmissions become possible. When transmitting computer software and assuming the M82 mode is being employed, for example, when one bit is assigned to one particular compu~er software routine 64 different oomputer software programs can be transmitted simultaneously through one data channel.
~ ccording to the present invention, because the service bit added to the frame synchronization signal as a auxiliary information is detected and the word synchronization signal is ~equentially counted thereby to identify the address ~$ate 7 addressing over ~ plurality of frames is possible. This means that when a system has a very large number of receiver terminals it is possible to easily control the receiving state at each of these terminals, because a very large number of addresses are afforded by ~preading the addressing over a plurality of frames.
Although illustrative embodiments of the present invention have been described in detail above with reference to the accompanying drawings, it is understood that the invention is not limited to those precise embodiments, and that various changes and modifications can be effected therein by one skilled in the art without departing from the scope or spirit of the invention, as defined by the appended claims.
Claims (5)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A digital signal transmitting system comprising:
means for generating a first mode of digital word signals, each digital word signal consisting of a word synchronizing signal and data signals having a first plurality of data channels of data sampled at a first sampling frequency;
means for generating a second mode of digital word signals, each digital word signal consisting of a word synchronizing signal and data signals having a second plurality of data channels of data sampled at a second sampling frequency; and means for selectively transmitting said first mode of digital word signals and said second mode of digital word signals through a transmission line.
means for generating a first mode of digital word signals, each digital word signal consisting of a word synchronizing signal and data signals having a first plurality of data channels of data sampled at a first sampling frequency;
means for generating a second mode of digital word signals, each digital word signal consisting of a word synchronizing signal and data signals having a second plurality of data channels of data sampled at a second sampling frequency; and means for selectively transmitting said first mode of digital word signals and said second mode of digital word signals through a transmission line.
2. A digital signal transmitting system according to claim 1, in which said transmission line comprises a cable television transmission line and in which one of said first and second modes of digital word signals is amplitude modulated on a carrier frequency and transmitted on said cable television transmission line.
3. A digital signal transmitting system according to claim 2, in which said first mode of digital word signals includes left channel and right channel stereo signals, said first sampling frequency is 44.1 KHz, and said first plurality of data channels includes code words having 16 bits.
4. A digital signal transmitting system according to claim 2, in which said second mode of digital word signals includes a monaural signal, said second sampling frequency is 22.05 KHz, and said second plurality of data channels includes code words having 8 bits.
5. A digital signal transmitting system according to claim 2, in which each of said first and second modes of digital word signals further includes service bit signals for identifying said first and second modes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000567713A CA1258520A (en) | 1983-11-09 | 1988-05-25 | Digital signal transmitting system |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58210353A JPS60103748A (en) | 1983-11-09 | 1983-11-09 | Digital signal transmission system |
| JP210353/83 | 1983-11-09 | ||
| CA000467176A CA1248624A (en) | 1983-11-09 | 1984-11-06 | Digital signal transmitting system |
| CA000567713A CA1258520A (en) | 1983-11-09 | 1988-05-25 | Digital signal transmitting system |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000467176A Division CA1248624A (en) | 1983-11-09 | 1984-11-06 | Digital signal transmitting system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA1258520A true CA1258520A (en) | 1989-08-15 |
| CA1258520C CA1258520C (en) | 1989-08-15 |
Family
ID=25670522
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000567713A Expired CA1258520A (en) | 1983-11-09 | 1988-05-25 | Digital signal transmitting system |
| CA000567714A Expired CA1258521A (en) | 1983-11-09 | 1988-05-25 | Digital signal transmitting system |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000567714A Expired CA1258521A (en) | 1983-11-09 | 1988-05-25 | Digital signal transmitting system |
Country Status (1)
| Country | Link |
|---|---|
| CA (2) | CA1258520A (en) |
-
1988
- 1988-05-25 CA CA000567713A patent/CA1258520A/en not_active Expired
- 1988-05-25 CA CA000567714A patent/CA1258521A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CA1258521A (en) | 1989-08-15 |
| CA1258520C (en) | 1989-08-15 |
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