CA1240031A - Electrical circuits for timing signals - Google Patents

Abstract

ABSTRACT

"Improvements relating to electrical circuits for timing signals"

A counter 47 is provided to count an expected 32 pulses in a pulse train comprising a signal received at A and passing through an AND gate 60 when enabled. However if the pulses in the leading and trailing edges are of low amplitude they may be below a threshold level and thus be missed so that the counter 47 will not reach the required count of 32.
However when the sequence of pulses terminates a counter 62 is then able to reach a full count of three upon receipt of pulses from an oscillator 64 transmitted at twice the frequency of the pulses in the signal. This releases a latch 58 so that the oscillator pulses can pass through the AND gate 65 to the counter 47 so that the count is completed. Since the losses of pulses at the beginning and end of the signal are expected to be symmetrical addition of pulses at twice the frequency in the counter 47 to those already received from a signal will compensate for the pulses lost at the beginning and end of the signal and will ensure that the output from the counter 47 occurs approximately at the same instant when the end of the trailing edge of the signal is reached.
Hence the output from the counter 47 is a true reflection of the timing of receipt of the signal.
Figure 4

Description

"Improvements relating to electrical circuits fQr timing signals"

This invention relates to various electrical circuits particularly, but not exclusively, those which are useful in an automatic distance measuring apparatus.
Distance measuring apparatus is known wherein a sonic or ultrasonic pulse is transmitted and the time taken between the transmission and the return echo is measured to determine the total distance travelled by the pulse, and hence the distance of the object reflect-ing the pulse.
Existing distance m~asuring apparatus of the above kind have several major drawbacks and it is the object of this invention to alleviate these.
From a first aspect this invention provides a missing pulse detector for determining the true termination time of a sequence of pulses in a signal of an assumed predetermined length haviny a rising edge and a trailing edge which may include pulses which do not reach a predetermined threshold, the detector including a counter connected to count pulses exceeding said chreshold, up to a predetermined number, an oscillator for producing pulses at twice the frequency of the pulses in the signal and an enabling circuit for allowing pulses from the oscillator to pass to the counter only after the MJ/MIO

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termination of a sequence, of threshold-exceeding pulses from the signal.
Assuming that the sequence of pulses in the signal is generally symmetrica~ an equal number of pulses will be lost from the beginning of the signal as from the end, should any pulses fail to reach the predetermined threshold. Hence adding on twice the number of pulses at double the frequency to the end of the count of pulses ~ which have exceeded the threshold will result in a total count (up to the predetermined number) terminating approximately at the instant of receipt of the end of the trailing edge of the signal. Thus the true termination time of the signal is correctly determined.
In the preferred arrangement the connection of the oscillator to the counter for the supply of double frequency pulses is through a latch-controlled unit which is connected to receive the sequence of threshold-exceeding pulses from the signal. This latch-controlled unit ideally will include a counter. When the normal 2Q pulses are passing through,the counter will be re-set by each of these pulses after only two pulses have been received from the oscillator, but when the s~quence of normal pulses terminates the third pulse from the oscillatox will be registered by the counter of the latch-controlled unit so that the latch will be set.
It is also of advantage to include a latch connected to be set by a first threshold-exceeding pulse received in said signal to initiate operation of the oscillator.
The invention also extends to a reflected signal measuring circuit including a missing pulse detector as hereinbefore defined and a circuit for transmitting a sequence of pulses and receiving any reflection of that sequence for supply to the missing pulse detector.
Such a signal measuring circuit will advantageously include combined resetting inputs to the counter and ~. any latches in the circuit which will receive a resetting signal upon initiation of ransmission of said sequence. The output from the counter may itself be connected to the combined resetting inputs through a delayed re-set circuit.
The signal measuring circuit will preferably include a calculation and display unit for determining the time between the transmission of the sequence of pulses and the provision of an output from said counter upon receipt of said predetermined number of pulses and converting the time to an indication of distance travelled by the ~0 reflected sequence of pulses for display on the display unit~
According to a further aspect of the invention, there is provided a reflected signal measuring circuit provided with an amplifier circuit having a variable gain which i5 highly linear with respect to an input gain control signal~

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When used in the receiver circuit of a distance measuring apparatus the variable gain linear amplifier circuit is preferably connected in series with a pair of fixed gain band pass amplifier circuits. The two band pass amplifiers provide a highly selective amplifica~ion of the frequency of the sonic or ultra-sonic signal used in the apparatus~ Finally, the receiver circuit includes a comparator which compares ~ the output of the band pass amplifiers with a predetermined threshold level.
When the above circuits are used together as part of a distance measuring apparatus, it is preferred that they are formed in a single integrated circuit chip, designated the Denver chip. This has the ad~antage that all the transistors and other components of the amplifiers and comparator will "drift" at the same rate, largely compensating each other. However, the components which determine the band pass characteristics and the gain are pr~ferably outside the chip proper - 20 so that these can be adjusted as desired.

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The invention may be performed in various ways and a preferred embodiment thereof will now be described with reference to the accompanying dxawings, in which:-Figure l is a block schematic diagram of a distance measuring apparatus in which the circuits according tothe invention have utility;
Figure 2 is a block circuit diagram of a receiver circuit including a variable gain linear amplifier, together with a pair of fixed gain band pass amplifier circuits and a comparator;
Figure 3 is a block schematic diagram of the complete circuit for a distance measuring apparatus incorporating a missing pulse detector;
Figure 4 is a block schematic diagram of the missin~ pulse detector of Figure 3; and Figure 5 is an illustration of wave forms for pulses and signals within the missing pulse detector circuit of Figure 4.
The apparatus shown in Figure 1 includes a transmitter circuit 10 which is arranged to supply timed bursts via line 11 to a directional electro-acoustic transducer 12. Each reflection by an ob~ect in the path of the signal is detected by the sa~e transducer 12 for reconversion to electrical form.
The detected bursts (echoes) are passed via a line 13 to a receiver circuit 14 for amplification and MJ/MIO ~5~
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detection.
The receiver circuit 14 discriminates large amplitude echoes reflected from a wall or other large surface, whose distance it is required to measure~ from 5 noise or echoes of lesser magnitude reflected from relatively small objects such as a chair (when measuring inside a building) or a post (when measuring outside).
Thus the~receiver circuit 14 is tuned to reject unwanted ~ frequencies and includes means for comparing the amplified echo signals with a reference threshold level set sufficiently high to reject small echoes yet provide an output on line 15 for large amplitude echoes.
It is necessary to compensate for the attenuation of sound in air which is substantially linear at 6db per 1% metres of distance travelled at 25C . For this purpose the receivercircuit 14 includes a variable gain amplifier which is fed with a linear ramp control signal derived from a ramp generator 16. The ramp control signal..is at a maximum when the ultrasonic burst is 2a transmitted, and thereafter decreases linearly with time to compensate for the attenuation of the sonic signals in air. Thus the magnitude of the processed echo signal from the amplifier output presented for comparison with a fixed threshold is substantially constant irrespective of the distance between the transducer and a large area object, subject to the s ~ 2~ 3~

maximum gain of the amplifier. Naturally, the receiver circuit also includes means for rendering such circuit unresponsive to the initial transmission burst.
The time between each transmitted burst and the detected echo burst after reflection is a measure of the distance of the object from the txansducer. This time interval is dPtermined by a counter 17 which counts ~clock pulses provided by an oscillator 18. The counter is re-set to ~ero by a pulse on line 35 each time a burst is transmitted, and stopped at its current count by a pulse on line 15 each time a reflected burst is detected which is of sufficient amplitude to trigger the comparison means in the receiver circuit 14. The current count may be displayed at 19 directly in desired units of length corresponding to the distanc~ between the transducer 12 and the object, by providing an appropriate choice of the frequency of th~ oscillator 18 or bv the use of suitable division circuits.
Referring to Figure 2, the receiver circuit comprises an input capacitor 20 via which a reflected echo signal from the transducer 12 (Figure 1) is supplied to a highly linear variable gain amplifier 21. The maximum value of the input siynal, after pre-amplification and some filtering (not shown) corresponds to the reflection from a large area wall close to the transducer 12.

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However, the gain of the amplifier 21 is controlled by a ramp s~gnal 22 supplied at 23 in such manner that the output 24 is a substantially constant peak to peak irrespective of the distance of the wall from the transducer, as her~inbefore described.
The output 24 of the amplifier 21 is passed to a fi~st amplifier circuit comprising a fixed gain operational amplifier 25 having a high pass filter ~ comprising a resistor 26 and a capacitor 27 and a low pass filter comprising a resistor 28 and a capacitor 29. The output signal at 30 is applied, to a second fixed gain band pass amplifier circuit similar to the first. The signal at the input 33 to the second amplifier circuit is reduced by the action of the potential divider 31, 32. The second fixed gain amplifier circuit comprises a fixea gain operational amplifier 34 similar to the first amplifier 25, together with a hiqh pass filter comprising the resistor 31 and a capacitor 36 and a low pass filter comprising a

2~ resistor 37 and a capacitor 38.
It is to be noted that the use of two fixed gain band pass amplifier circuits in series as described above provides a highly selective frequency response, .
certainly more selective than a single such amplifier circuit.
When the output signal at 39 exceeds the threshold, MJ/MIO ~8-g ~ 3~.

as will certainly b~ the case for large area walls and most large area objects in the field of. view of the transducer 12, a logic "1" signal is supplied on the comparator output 41 which corresponds to the output line 15 in Figure 1. The use of a suitable threshold voltage ensu.res that neither noise nor small objects such as a chair or post will trigger the comparator, yet allows reasonably large objects to be detected which ..however do not provide an echo signal of the maximum amplitude such as would be provided by a large area wall. The threshold lQvel may be manually adjusted.
The overall circuit illustrated in Figure 3 incorporates the transducer 12 connected via a buffer 42 to an integrated circuit chip 43 carrying the gain controlled bypass amplifiers 44 as illustrated in Figure 2 and a missing pulse detector circuit 45.
A separate control circuit 46 is connected into th.e portion of the chip 43 carrying the amplifiers 44 to initiate the transmission of a pulse from the trans-ducer 12 and is also connected to a counter 47 so as tosupply a re-set signal. Any echo signals received by the circuit pass through the amplifiers 44 and the miss-ing pulse detector 45 and the output is fed to the counter 47. When a predetermined count has been reached by the couhter 47 the time between inikiation of the transmission pulse from the transducer 12 and MJ/MIO -9~

the instant when -th~ counter reaches its predetermined level is converted into an indication of the distance travelled by the reflected signal which is then displayed by a display device 48.
The details of operation of the missing pulse detector can be seen from thecirCuit diagram of Figure 4 and the wave forms illustrated in Figure 5. Referring firstly to Figure 5 the first wave form X indicates an ~ideal reflected signal which passes through the amplifier 44. This has a sharp rising edge 50 and trailing edge 51 and all the pulses of the train are approximately of a similar height 52. In reality, hwoever, the signal is more likely to be that represented by the wave form Y having a s].oping leading edge 53 for the signal rise time and a downwardly sloping edge S4 for the trailing edge due to ringing of the signalO Generally however the signal will ~e sym~etrical about a centre line P3, the total signal length being from Pl to P5. In operation the detection level 55 will be set resulting in an output from the comparator ~0 (Figure 2) of the form as illustrated by wave form Z. This will provide a train of pulses which are in.fact chopped off at the leading and trailing edges and thus the counter 47 may not receive the total number of pulses required to provide an output and if the counter was set at a lower level ;

th~n thR ~xpected number of pulses to be rec~ived the timing of the.output from the counter w~uld not truly reflect the instant at which the actual trailing edge of the signal was received. The circuit of Figure 4 aims to overcome this difficulty.
Referring to Figure 4, when a transmission pulse sequence from the transducer 12 (Figure 3) is initiated the re-set signal from the control circuit 46 is fed ~.on a line 56 via an OR gate 57 to the re-set inputs 10 of latches 58 and 59 and the counter 47. Any echo passing through the comparator 40 (,Figure 2) is fed from the point A to an AND gate 60 which is gated with a

3.5 ms pulse from point B to disable the circuit whilst the transmission of pulses occurs. The pulse train as illustrated by wave ~oxm Z is thus fed into the counter 47 through an OR gate 61 and also operates to set latch 59 and provide a re-setting pulse to a " ~ 3" counter 62. If a strong signal is received as an echo then all the pulses in the train will pass ,.
through to the counter 47. In this example it is assumed that the circuit is designed to emit pulse trains incorporating 32 pulses which will be registered by a 5 bit counter 47 which will therefore go high and produce an output on line 63 after 32 pulses have been registered. However, if less than 32 pulses are received, the.,last pulse registered will be applied to MJ/MIo -12~

the re-set input of.the counter 62, but since no iurther pulses will ~e received to re-set this counter, the counter 62 will, upon receiving three clock pulses from an oscillator 64 go high to provide a setting pulse to the latch 58. The oscillator 64 supplies pulses at twice the frequency of those in the pulse train received at point A. For example the pulse train may have a frequency of 40 kHz whilst the oscillator 64 ~operates at a frequency of 80kHz. The oscillator 64 will of course have been enabled by the latch 59 which is set by th~ pulses passing through the AND gate 60.
Once the latch 58 has been set.by the output of the counter 62 it will enable one input of an AND gate 65 whose other input is fed from the oscillator 64.
Thus, after three pulses have been supplied to the counter 62 from the oscillator 64 after the last re-setting pulse for the counter has passed through the AND gate 60, a stream of pulses will be fed through the AND gate 65 and the OR gate 61 to the counter 47. ..
Because, as can be seen from the wave forms Y and Z
in Figura 5, the missing pulses are symmetrical at either end of the pulse train, adding on a number of 80 kHz pulses to the.end of the truncated 40 kHz pulse train will result in a total pulse count of 32 being achieved at approximately the correct instant as for a complete pulse train.o~ 32 40 kHz pulses. This can be MJ/MIO -12~

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seen from the further wave forms G, H and J illustrated in Fi~ure 5. G indicates the output state of the counter and shows that it goes high v~ry shortly (1~
normal pulses) after the end of the detected pulse train of wave form Z. Wave form H shows the output from the AND gate 65 as the 80 kHz pulses pass through it and arP applied to the counter 47. Finally wave form J
shows the instant at which the counter 47 goes high upon receipt of the truncated normal pulse train together with a number o missing pulses supplied at twice the frequency. This instant of output ~rom the counter 47 corresponds approximately to the end of the distorted pulse train as indicated by pulse train Y. The output ~rom the counter 47 is ~ed through a delayed re-set circuit 66 so that, after a predetermined time, the counter 47 and the two latches 58 and 59 are re-set (as indicated by the termination of the signals of wave forms J and H). The circuits described above are preferably formed in a single integrated chip, designated the Denver chip.

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Claims (10)

1. A missing pulse detector for determining the true termination time of a sequence of pulses in a signal of an assumed predetermined length having a rising edge and a trailing edge, which sequence may include pulses which do not reach a predetermined threshold, the detector including a counter connected to count pulses exceeding said threshold, up to a predetermined number, an oscillator for producing pulses at twice the frequency of the pulses in the signal and an enabling circuit for allowing pulses from the oscillator to pass to the counter only after the termination of a sequence of threshold exceeding pulses from the signal.

2. A missing pulse detector according to claim 1, including a latch-controlled unit which is connected to receive the sequence of threshold-exceeding pulses from the signal, and wherein the connection of the oscillator to the counter for the supply of double frequency pulses is through the latch-controlled unit.

3. A missing pulse detector according to claim 2, wherein the latch-controlled unit includes a counter which will produce an output to set the latch only after receipt of three pulses from the oscillator.

4. A missing pulse detector according to claim 1, including a latch connected to be set by the first threshold-exceeding pulse received in said signal to initiate operation of the oscillator.

5. A reflected signal measuring circuit including a missing pulse detector for determining the true termination time of a sequence of pulses in a signal of an assumed predetermined length having a rising edge and a trailing edge, which sequence may include pulses which do not reach a predetermined threshold, the detector including a counter connected to count pulses exceeding said threshold, up to a predetermined number, an oscillator for producing pulses at twice the frequency of the pulses in the signal and an enabling circuit for allowing pulses from the oscillator to pass to the counter only after the termination of a sequence of threshold exceeding pulses from the signal, the measuring circuit also incorporating a circuit for transmitting a sequence of pulses and receiving any reflection of that sequence for supply to the missing pulse detector.

6. A reflected signal measuring circuit according to claim 5, including combined resetting inputs to the counter and to any latches in the circuit which will receive a resetting signal upon initiation of trans-mission of said sequence.

7. A reflected signal measuring circuit according to claim 6, including a delayed re-set circuit wherein the output from the counter is connected to the combined re-setting inputs through the delayed re-set circuit.

8. A reflected signal measuring circuit according to claim 5, including a calculation and display unit for determining the time between the transmission of the sequence of pulses and the provision of an output from said counter upon receipt of said predetermined number of pulses and converting the time to an indication of distance travelled by the reflected sequence of pulses for display on the display unit.

9. A reflected signal measuring circuit according to claim 5 and provided with at least one circuit selected from an amplifier circuit having a variable gain which is highly linear with respect to an input gain control signal, the variable gain linear amplifier circuit preferably being connected in series with a pair of fixed gain band pass amplifier circuits, and a comparator circuit which compares the output of the band pass amplifiers with a predetermined threshold level.

10. A reflected signal measuring circuit according to claim 5, wherein the majority of the circuit components are carried by a single integrated circuit chip.