CA1237337A - Thermal print head - Google Patents
Thermal print headInfo
- Publication number
- CA1237337A CA1237337A CA000496198A CA496198A CA1237337A CA 1237337 A CA1237337 A CA 1237337A CA 000496198 A CA000496198 A CA 000496198A CA 496198 A CA496198 A CA 496198A CA 1237337 A CA1237337 A CA 1237337A
- Authority
- CA
- Canada
- Prior art keywords
- elements
- buses
- voltage level
- marking
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims 2
- 229910052729 chemical element Inorganic materials 0.000 claims 1
- 230000000875 corresponding effect Effects 0.000 claims 1
- 238000007639 printing Methods 0.000 description 25
- 230000003071 parasitic effect Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000007651 thermal printing Methods 0.000 description 2
- 102000004726 Connectin Human genes 0.000 description 1
- 108010002947 Connectin Proteins 0.000 description 1
- 102000002356 Nectin Human genes 0.000 description 1
- 108060005251 Nectin Proteins 0.000 description 1
- 102100033740 Tenomodulin Human genes 0.000 description 1
- 101710114852 Tenomodulin Proteins 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
- B41J2/315—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material
- B41J2/32—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads
- B41J2/345—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads characterised by the arrangement of resistors or conductors
Landscapes
- Electronic Switches (AREA)
- Facsimile Heads (AREA)
Abstract
Abstract of the Disclosure A thermal print head includes electrical heating elements for marking a heat sensitive medium, and buses for delivering power to the elements (each bus being connected in common to a number of the elements); a power source applies to one of the buses a first voltage level which is at least sufficient, when applied to one of the elements, to cause marking, and the power source holds a second bus at a fixed second voltage level insufficient for causing marking. In other aspects, each element in the row is connected between a conductor for supplying power to and a conductor for sinking power from the element, and some of the sink conductors extend on one side of the row while other sink conductors extend on the other side of the row (for making electrical connection to a power sink); there are a number (N) of parallel rows of elements, and there are 2N buses, each bus being connected in common to a plurality of elements, and there is control logic for routing power via each one of the buses in turn;
and at least one of the buses is on one side of the rows of elements, and at least another one of the buses is on the opposite side of the rows.
and at least one of the buses is on one side of the rows of elements, and at least another one of the buses is on the opposite side of the rows.
Description
~23~33~
_~IERMAL PRINT ~I~AD
Ba~round of the Invention This invention relates to thermal print heads.
In typical heads, a row of electrically resistive heating elements are defined along the length of a resistive stripe by a series of conductive fingers which cross the stripe at regular intervals. Each heating element is thus spaced apart from the next element by the width of the finger which se~a~ates them and each element is bordered by and connected to the two associated fingers ~hich define the element. In order to print a dot on a sheet of heat-sensitive paper, an individual elemen-t is heated by driving current through it. A voltage is applied to one of the element's two associated fingers to supply power, and the other finger is grounded to withdraw (sink) power from the element. By printing a set of selected dots in one row, then moving the paper a shcrt distance (in a direction perpendicular to the resistive stripe) to a new position at which another set of selected dots is printed, and then repeating these steps, patterns of dots corresponding to alphanumeric characters or graphic symbols are formed.
Typically, every other finger along the stripe extends in one direction away from the stripe to connect to integrated circuitry which is arranged to permit grounding of various ones of the fingers a-t different times. The intervening fingers (to which the voltage is to be applied~ are not connected to the grounding intecJrated circuitry J but instead extend away from the stripe in the opposite direction from the grounding ingers. Every other one of these voltage fingers is ro~ted to a first bus which runs parallel to the stripe, while the remaining ,~'~
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voltage finyers are routed to a second bus, wnich also runs parallel to the stripe.
The printing of dots along a row is done in two phases: first, a voltage is applied to the first bus, and appropriate grounding fingers are grounded to cause heating of the elements corresponding to the desired dot positions; second, the voltage is applied to the second bus, and other appropriate grounding fingers are grounded.
Diodes are connected betweell each voltage finger and the bus to which it i5 routed to prevent so-called parasitic voltages from appearing on the b~ls to which the voltage is not being applied. ~uch parasitic voltages may erroneously cause printing by elements which have not been selected for heating.
Summary of the Invention In general, the invention features, in one aspect, applying to one of several buses a first voltage level which is at least sufficient, when applied to one of the elements, to cause marking, while holding a second bus at a fixed second voltage level insufficient for causing marking.
In preferred embodiments, che heating elements are arranged in rows, ~e.g. two parallel rows), and there are a series o conductors for sinking power from the elements, with every other one of these conductors extending on one side of the rows, and the intervening conductors extending on the other side, with each conductor serving two elements on each row, and each element being served by one of the conductors; and there are four buses (double the number of rows), with two of the buses being arranged on one side o the rows so as to ~3~733~
be adjacent to and to serve one of the rows, and with the other two buses being arrangecl on the other side of the rows so as to be adjacent to and to serve the other one of the rows.
Also in preferred embodiments, the elements are regularly spaced along the rows, with spaces between successive elements (each elemetlt having, e.g., a length equal to the length of one of the spaces), and one of the rows is offset from the other row (e.g. by an amount equal to the space length) such that in a pro~ection of one row onto the otl-er row, the eleme~nts o~ the one row woulcl cover at least a portion of the spaces alony the other row.
Also in preferred embodiments, the power sinking conduc~ors selectively connect the elements to a predetermined third voltage level, such that the voltage diEference between the first and third voltage levels is sufficient to cause marking, but the voltage diference between the second and third voltage levels, and the voltage difference between the first and second voltage levels, are each insufficient to cause marking; the second voltage level is lower than the first voltage level and is selected to have a value, relative to the first voltage level, which minimizes the aggregate power loss in the heating elements, e.g., a value equal to the third voltage level plus 3~7 of the difference between the first voltage level and third voltage level; control logic is provided ~or connecting the first voltage level Erom the power source to a selected one of the buses while connectin~ the second voltage level ~rom the power source to the o~her buses; and the control logic connects selected ones oE the elements to a power sin~c while the bus connected to the selected elements is connected to the Eirst voltage level, to cause markin~ by the selected elements.
3733~
In another aspect, the invention features a thermal print head in which each element in the row is connected between a conductor or supplying power to and a conductor for sinking power from the element, and some of the sink conductors extend on one side of the row while other sink conductors extend on the other side of the row for making electrical connection to a power sink.
In another aspect, the invention features a thermal print head having a number (N) of parallel rows oE
electrical heating elemellts for marking a heat sensitive medium, conductors for sinking power from the elements, 2N
electrical buses for routin~ power to the elements, each bus being connected in common to a plurality of elements, and control logic ~or routing power via each one of the buses in turn.
In another aspect, the invention Eeatures a thermal print head having a row of electrical heating elements Eor marking a heat sensitive medium, buses parallel to the row of elements for routing power to the elements, at least one of the buses being on one side of the row, and at least another one of the buses being on the opposite side of the row.
By holding the non-printing buses to a fi~ed second voltage level insufficient to cause marking, no diodes are required to counteract the parasitic voltages which could otherwise appear on the non-printing buses. Eliminating the diodes reduces the design and manufacturing costs and improves ~he reliability of the head, by making more space available on the head substrate. The availability of space also permits the use of four buses, two on each side o~ the elements. Four buses enable the use of two rows of printing elements, each served by two of the buses. By connecting each sink conductor to both rows, each sink 3~33~
conductor can serve four elements. Having alternate sink conductors lead out to different sides of the element rows red~ces the density of the required switching circuitry on the substrate which reduces design and manufacturing complexity and cost, and improves reliability. Using four buses permits four-stage printing which reduces the peak power load. Offsetting the two rows of elements with respect to each other assures that every location on a page can be printed.
Other advantages and features of the invention will become apparent Erom the ollowing description o the preferred embodiment, and from the claims.
Description of the Preferred Embodlment We first briefly describe the drawings.
Drawings Fig. 1 is a schematic view of a thermal printing system.
Fig. 2 is a view of a representative segment along the length of the thermal print head of Fig. 1, inc~iuding integrated circuitry shown schematically.
Fig. 3 is a schematic view of the power supply and control logic of Fig. 1.
Fig. 4 is an equivalent circuit diagram for the head of Fig. 2 reflecting one possible operating condition.
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_tructure Referriny to Fig. 1, in thermal printing system 10 a sheet of temperature-sensitive paper (or plain paper in conjunction with an ink-bearing temperature-sensitive ribbon) 12 is held against a thic~-film thermal print head 14. Paper driver 16 is arranged to move paper 12 to a succession of Eixed positions with respect to head 14.
Paper driver 1~ is connected via control signal line l7 and power line 19 to a power supply and control logic 18 (for providin-~ power and control signals to cause paper driver 16 to move paper 12 to the successive positions).
Power supply and control logic 18 is also connected via control signal lines 21 and bus power lines 23 to head 1~
(for providin~ power and control signals for causing head 14 to print a desired set of dots with respect to each successive position of paper 12). Power supply and control logic 18 is also connected via control signal line 25 and data line 27 to a microprocessor (not shown) for receiving streams of bits representative of information to be printed, and for receiving and sending related control signals.
Referring to Fig. 2, in head 14, a pair of parallel resistive stripes (each .0833 mm wide) of palladium-silver or palladium-gold 30, 32, are crossed by a series of conductive fingers 34 (each 0.0833 mm wide) also of palladium-silver or palladium-gold. The rows are separated by a 0.~5 mm space and the conductive fingers are spaced at regular intervals to define two parallel rows of printing elements 36, 38 (each 0~0833 mm square).
Elements 36 are offset from elements 38 along an imaginary axis 40 by a distance of 0.0833 mm such that, if elements 38 were moved along an a~is 42 to the location of row 30, each element 38 would fill the space between a pair of adjacent elements 36. There are a total of 2,59~ elements ~L23~7~3~7 along the 8 1/2" print head length ~only a few are shown in Fig. 2) with 1,236 elements in each row.
The fingers 34 which cross row 30 are arranged in four groups. One group of fingers 44 is connected to a conductive bus 46 oriented parallel to row 30. A second group of fingers ~8 (only two are shown in Fig. 2) passes under and is insulated from bus 46 and connects to a second bus 50 also oriented parallel to row 30. ~ third group of fingers 52 passes under and is insulated ~rom both buses 46 and 50 and connects to integrated circuit 5~1 (for cor)nectin~ selected fingers 5~ to ground). Fingers 52 also extend to and cross row 32 and have jogs 56 to accommodate the offset between elements 36, 38. A fourth group of fingers 57 extend to and beyond stripe 3~.
Likewise, the fingers 34 which cross stripe 32 are arranged in four groups, including fingers 52 in one group, fingers 58 which connect to a bus 60 (on the other side of stripes 30, 32 from buses 46, 50) in a second group, fingers 62 which connect to a bus 64 in a third group, and fingers 57 which connect to integrated circuitry 66 in a fourth group.
Each finger 52, by virtue of crossing both stripes 30, 3~, is connected to four elements, which are served individually by one of the four buses 46, 50, 60, 64. For example, a finger 52 connects to elements 70, 72, 74, 76, which in turn are connected respectively to buses 46, 50, 60, 64. Likewise, each finger 57 is connected to four elements also served respectively by one of the four buses 46, 50, 60, 64.
Each pair of adjacent ~ingers 57 has four elements 38 positioned between them, and each pair of adjacent fingers 52 likewise has four elements 36 positioned between them.
373~
Buses 46, 50, 60, 6~ and integrated circuits 5~, 66 are each connected independently via lines 4], 43, 45, 47, 49, 51 to power supply and control logic 18.
Integrated circuitry 66 represents one of six identical circuits arranged along the length of head 14 on one side of rows 30, 32; integrated circuit 5~ is identical to integratecl circuit 66 and likewise represents one of six identical circuits Oll the other side of LOWS
30, 32. Fach integrated circuit has fifty-four c~lls to serve fifty-our Eillc3ers 52, 57~ Thus ~he twelve circuits are able to serve all 6~ of ~ingers 52, 57.
Integrated circuitry 66 includes a shift register 110 having a set oE cells 112. Each cell 112 includes a transistor 114 whose emitter is grounded, whose collector is connected to a particular one of the fingers 57, and whose base is controlled by the value of a bit stored in the cell. ~en the bit has one value, transistor 11~ is driven to satuLation so that the corresponding finger 57 is effectively grounded (actually the finger is drawn down to the saturation voltage, Vsat, of transistor 119, e.g., 0.3 volts).
When the bit has the opposite value, transistor 11~ is off and the potential on the corLesponding finger 57 is permitted to float.
Referring to Fig. 3, power supply and contLol logic 18 includes a bus power supply 1~0 capable of producing highly regulated voltages at two levels: a higher level for causing printing at a selected element ~the higher level is selected so that the voltage drop across a given element will drive current sufficient to cause the element to heat to a temperature which causes mar~ing) and a lower level for driving the non-printing buses ~the lower level is selected so that the voltage drop across a given ~3~7337 element will not be sufficient to cause printing). ~us power su~ply 120 is connected via h.igh and low voltage lines 122, 124 to power-to-buses switching logic 126.
Logic 126 has outputs connected to bus connection lines 41, 43, 45, ~l7 for delivering the supply voltages, and has its input connected via control signal line 128 to control logic 130 for receiving signals which control the switc~ling of the supply voltages to bus lines at any given time.
Control loyic 130 is also connected via control and data lines 132, 134 to bit strealll swi~ching loglc 13~ ~or delivering, respectively, streams oE bits corresponding to dots to be printed, and related timing control signals which synchronize the operation of the integrated circuits 54, 66 with the powering of buses 46, 50, 60, 64. Logic 136 is connected via lines 49, 51 to circuits 54, 66 for carrying the bit streams and the timing control signals.
Control logic 130 is also connected via control signal line 17 to paper driver 16 and via control signal line 138 to paper drive power supply 140 to trigger the repositioning of the paper to each successive position at the proper time. The output of supply 140 is connected via power line 19 to paper driver 16.
Finally, control logic 130 is connected via control line ~5 and data line 27 to the microprocessor (not shown) to receive the bit streams and commands directing it when to print.
Reerring to Fig. 4, in one typical situation, during printing, bus 4~ is driven to the higher first voltage level (VA) and buses 50, 60, 64 are driven to the lower second voltage level (V~). Each resistance labelled RM represents a printing element wh.ich is intended to be 733~7 heated to print. RMM represents heating elements which are not intended to be heated to print but which are connected to the ~ame grounding finger as an RM
element. RNN represents a heating element which is not intended to be heated to print but is connected to the bus which is being driven to voltage VA. RN represents heating elements connected between the same grounding finger as an ~]N element, and one of the buses driven to voltage VB. With transistors 71, 73 turned on, Eingers 75, 77 are at a third voltage level Vsat.
Thus, V~ must be high eno-lgh so that each R~l heats sufficiently to cause printin~ ~rom a voltage drop oE VA
- Vs t across these resistors. VB must be low enough so that each RMM does not heat sufficiently to print with a voltage drop of VB - Vsat across it, and so that each RNN and RN does not print ~rom a voltage drop of VB - VA across each network consisting or RNN in series with three parallel RN elements.
Subject to those constraints, it is desirable to set VB at a level which minimizes the total power dissipated in the RMM 7 RNN and RN elements.
The voltages across the various resistors are as follows:
VRM = VA - Vsat VRNN = 3/~l (VA - V~) VRN = 1/~1 (VA - Vg) VRMM = VB ~ Vsat -3~3~
The minimum power dissipation ~ill occur when VRMM =
VRNN, i.e., when VB - Vsat = 3/4 (VA ~ VB) or V~ = 3/7 VA -~ 4/7 Vsat a 3/7 (V~ - V~at) -~ Vsat Thus, V~ should be set at 3/7 of the voltage across the printiny reslstors (i.e., 3/7 o V~ - Vsat) plus the saturation voltage (Vsat), so that VRM = VA - Vsat VRNN = 3/7 (VA - Vsat) VRN = 1/7 (VA - Vsat) VRMM = 3/7 (VA - Vsat) With that value of V~ the power dissipated in each of the non-printing elements is 3/7 x 3/7 = 9/49 = 18.2% of the power dissipated in each of the printing elements.
Operation To print a desired pattern of dots, paper 12 is moved to a successsion of fixed positions relative to stripes 30, 32. At each position, power is applied to those elements 36, 38 which need to be heated in order to mark desired dots at corresponding locations on the paper.
Power is applied in four stages. In each stage~ VA is applied to a particular one of the buses 46, 50, 60, 54, while V~ is applied to the remaining three buses. For example, VA is applied to bus 46 and VB is applied to buses 50, 60, 64. Under these circumstances, only half of the elements 36 on stripe 30, (i.e~, those which are connected to bus 46) can be selected to heat to print corresponding dots. A particular one of those elements ~L;Z3733~
heats to print by having integrated circuits 54, 66 connect to ground the finger 52, 57 which leads from the element to be heated, thus establishing VA - Vsat across the element. For example, in Fig. 2, element 70 can be heated to print a corresponding dot by grounding finger 100 to establish a current path (indicated by arrow 102). Appropriate bits are loaded into integrated circuits 54, 66 to cause, while VA i5 being applied to bus 46, the desired elements to be grounded and the others to remain floating.
Many unwanted parasitic electrical paths e~ist along the length of head 14 tendin~ to drive buses 50, 60, 64 to VA, for example the path ~arrow 104) from bus 46 via two elements to bus 50. Were bus 50 actually driven to VA, then element 72, being connected between VA and Vs t~
would erroneously print a dot. However, because VB
applied to bus 50 is regulated to be constant tnotwithstanding parasitic paths such as 10~), bus 50 cannot be driven to VA. Because VB is insufficient to cause printing by element 72, no erroneous printing occurs.
In the second stage of printing, the paper remains in the same position, VA is applied to bus 50, VB is applied to buses 46, 60, 64 and appropriate ones of fingers 52 and 57 are grounded to cause printing by desired ones of that half of the elements on row 30, which are connected to bus 50.
A similar procedure is followed in the third and fourth stages with the VA being applied first to bus 60, then to bus 64. Thus~ in the course of the four stages, any of the elements on rows 30, 32 can be caused to print.
Next the paper is moved along a~is 42 by a distance equal to the width of row 30 to a new position, at which ~ 237337 the four printing stages are again repeated, this time with an updated set of fingers 52, 57 being grounded in order to print desired dots at the new paper position.
The paper is then moved to a succession of new fixed positions, at each of which the four printing stages are repeated. Because the elements on rows 30, 32 are staggered with respect to each other, dots can be printed at all desired places on the page. The loading of bits into the shift registers, the switching of voltages onto buses ~6, 5~, 60, 64, and the advance of the paper to successive positions, are all synchroni~ed by control signals delivered from power supply and control logic 130. The microprocessor to which the power supply and control logic 1~ are connected is programmed to provide the needed bit patterns for integrated circuits 54, 66 based on the characters or graphic symbols to be printed.
By holding the non-printing buses to a fi~ed second voltage level insufficient for causing marking, no diodes are required to counteract the parasitic voltages which could otherwise appear on the non-printing buses.
Eliminating the diodes reduces the design and manufacturing costs and improves the reliability of the head, by making more space available on the head substrate. The availability of space also permits using four buses, two on each side of the elements. Four buses enables using two rows of printing elements, each served by two of the buses. By having each sink conductor connect to both rows, each sink conductor can serve four elements. ~aving alternate ones of the sink conductors lead out to different sides of the element rows reduces the density of the required switching circuitry on the substrate, thus reducing design and manufacturing complexity and cost, and improving reliability. Using four buses permits four-stage printing which reduces the peak power load. Offsettin~ the two rows of elements with respect to each other assures that every location on a pa~e can be printed.
Other embodiments are within the following claims.
For example, more than two rows of elements could be used, with the number of buses being double the number o rows.
~, '
_~IERMAL PRINT ~I~AD
Ba~round of the Invention This invention relates to thermal print heads.
In typical heads, a row of electrically resistive heating elements are defined along the length of a resistive stripe by a series of conductive fingers which cross the stripe at regular intervals. Each heating element is thus spaced apart from the next element by the width of the finger which se~a~ates them and each element is bordered by and connected to the two associated fingers ~hich define the element. In order to print a dot on a sheet of heat-sensitive paper, an individual elemen-t is heated by driving current through it. A voltage is applied to one of the element's two associated fingers to supply power, and the other finger is grounded to withdraw (sink) power from the element. By printing a set of selected dots in one row, then moving the paper a shcrt distance (in a direction perpendicular to the resistive stripe) to a new position at which another set of selected dots is printed, and then repeating these steps, patterns of dots corresponding to alphanumeric characters or graphic symbols are formed.
Typically, every other finger along the stripe extends in one direction away from the stripe to connect to integrated circuitry which is arranged to permit grounding of various ones of the fingers a-t different times. The intervening fingers (to which the voltage is to be applied~ are not connected to the grounding intecJrated circuitry J but instead extend away from the stripe in the opposite direction from the grounding ingers. Every other one of these voltage fingers is ro~ted to a first bus which runs parallel to the stripe, while the remaining ,~'~
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~;~37:33~
voltage finyers are routed to a second bus, wnich also runs parallel to the stripe.
The printing of dots along a row is done in two phases: first, a voltage is applied to the first bus, and appropriate grounding fingers are grounded to cause heating of the elements corresponding to the desired dot positions; second, the voltage is applied to the second bus, and other appropriate grounding fingers are grounded.
Diodes are connected betweell each voltage finger and the bus to which it i5 routed to prevent so-called parasitic voltages from appearing on the b~ls to which the voltage is not being applied. ~uch parasitic voltages may erroneously cause printing by elements which have not been selected for heating.
Summary of the Invention In general, the invention features, in one aspect, applying to one of several buses a first voltage level which is at least sufficient, when applied to one of the elements, to cause marking, while holding a second bus at a fixed second voltage level insufficient for causing marking.
In preferred embodiments, che heating elements are arranged in rows, ~e.g. two parallel rows), and there are a series o conductors for sinking power from the elements, with every other one of these conductors extending on one side of the rows, and the intervening conductors extending on the other side, with each conductor serving two elements on each row, and each element being served by one of the conductors; and there are four buses (double the number of rows), with two of the buses being arranged on one side o the rows so as to ~3~733~
be adjacent to and to serve one of the rows, and with the other two buses being arrangecl on the other side of the rows so as to be adjacent to and to serve the other one of the rows.
Also in preferred embodiments, the elements are regularly spaced along the rows, with spaces between successive elements (each elemetlt having, e.g., a length equal to the length of one of the spaces), and one of the rows is offset from the other row (e.g. by an amount equal to the space length) such that in a pro~ection of one row onto the otl-er row, the eleme~nts o~ the one row woulcl cover at least a portion of the spaces alony the other row.
Also in preferred embodiments, the power sinking conduc~ors selectively connect the elements to a predetermined third voltage level, such that the voltage diEference between the first and third voltage levels is sufficient to cause marking, but the voltage diference between the second and third voltage levels, and the voltage difference between the first and second voltage levels, are each insufficient to cause marking; the second voltage level is lower than the first voltage level and is selected to have a value, relative to the first voltage level, which minimizes the aggregate power loss in the heating elements, e.g., a value equal to the third voltage level plus 3~7 of the difference between the first voltage level and third voltage level; control logic is provided ~or connecting the first voltage level Erom the power source to a selected one of the buses while connectin~ the second voltage level ~rom the power source to the o~her buses; and the control logic connects selected ones oE the elements to a power sin~c while the bus connected to the selected elements is connected to the Eirst voltage level, to cause markin~ by the selected elements.
3733~
In another aspect, the invention features a thermal print head in which each element in the row is connected between a conductor or supplying power to and a conductor for sinking power from the element, and some of the sink conductors extend on one side of the row while other sink conductors extend on the other side of the row for making electrical connection to a power sink.
In another aspect, the invention features a thermal print head having a number (N) of parallel rows oE
electrical heating elemellts for marking a heat sensitive medium, conductors for sinking power from the elements, 2N
electrical buses for routin~ power to the elements, each bus being connected in common to a plurality of elements, and control logic ~or routing power via each one of the buses in turn.
In another aspect, the invention Eeatures a thermal print head having a row of electrical heating elements Eor marking a heat sensitive medium, buses parallel to the row of elements for routing power to the elements, at least one of the buses being on one side of the row, and at least another one of the buses being on the opposite side of the row.
By holding the non-printing buses to a fi~ed second voltage level insufficient to cause marking, no diodes are required to counteract the parasitic voltages which could otherwise appear on the non-printing buses. Eliminating the diodes reduces the design and manufacturing costs and improves ~he reliability of the head, by making more space available on the head substrate. The availability of space also permits the use of four buses, two on each side o~ the elements. Four buses enable the use of two rows of printing elements, each served by two of the buses. By connecting each sink conductor to both rows, each sink 3~33~
conductor can serve four elements. Having alternate sink conductors lead out to different sides of the element rows red~ces the density of the required switching circuitry on the substrate which reduces design and manufacturing complexity and cost, and improves reliability. Using four buses permits four-stage printing which reduces the peak power load. Offsetting the two rows of elements with respect to each other assures that every location on a page can be printed.
Other advantages and features of the invention will become apparent Erom the ollowing description o the preferred embodiment, and from the claims.
Description of the Preferred Embodlment We first briefly describe the drawings.
Drawings Fig. 1 is a schematic view of a thermal printing system.
Fig. 2 is a view of a representative segment along the length of the thermal print head of Fig. 1, inc~iuding integrated circuitry shown schematically.
Fig. 3 is a schematic view of the power supply and control logic of Fig. 1.
Fig. 4 is an equivalent circuit diagram for the head of Fig. 2 reflecting one possible operating condition.
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_tructure Referriny to Fig. 1, in thermal printing system 10 a sheet of temperature-sensitive paper (or plain paper in conjunction with an ink-bearing temperature-sensitive ribbon) 12 is held against a thic~-film thermal print head 14. Paper driver 16 is arranged to move paper 12 to a succession of Eixed positions with respect to head 14.
Paper driver 1~ is connected via control signal line l7 and power line 19 to a power supply and control logic 18 (for providin-~ power and control signals to cause paper driver 16 to move paper 12 to the successive positions).
Power supply and control logic 18 is also connected via control signal lines 21 and bus power lines 23 to head 1~
(for providin~ power and control signals for causing head 14 to print a desired set of dots with respect to each successive position of paper 12). Power supply and control logic 18 is also connected via control signal line 25 and data line 27 to a microprocessor (not shown) for receiving streams of bits representative of information to be printed, and for receiving and sending related control signals.
Referring to Fig. 2, in head 14, a pair of parallel resistive stripes (each .0833 mm wide) of palladium-silver or palladium-gold 30, 32, are crossed by a series of conductive fingers 34 (each 0.0833 mm wide) also of palladium-silver or palladium-gold. The rows are separated by a 0.~5 mm space and the conductive fingers are spaced at regular intervals to define two parallel rows of printing elements 36, 38 (each 0~0833 mm square).
Elements 36 are offset from elements 38 along an imaginary axis 40 by a distance of 0.0833 mm such that, if elements 38 were moved along an a~is 42 to the location of row 30, each element 38 would fill the space between a pair of adjacent elements 36. There are a total of 2,59~ elements ~L23~7~3~7 along the 8 1/2" print head length ~only a few are shown in Fig. 2) with 1,236 elements in each row.
The fingers 34 which cross row 30 are arranged in four groups. One group of fingers 44 is connected to a conductive bus 46 oriented parallel to row 30. A second group of fingers ~8 (only two are shown in Fig. 2) passes under and is insulated from bus 46 and connects to a second bus 50 also oriented parallel to row 30. ~ third group of fingers 52 passes under and is insulated ~rom both buses 46 and 50 and connects to integrated circuit 5~1 (for cor)nectin~ selected fingers 5~ to ground). Fingers 52 also extend to and cross row 32 and have jogs 56 to accommodate the offset between elements 36, 38. A fourth group of fingers 57 extend to and beyond stripe 3~.
Likewise, the fingers 34 which cross stripe 32 are arranged in four groups, including fingers 52 in one group, fingers 58 which connect to a bus 60 (on the other side of stripes 30, 32 from buses 46, 50) in a second group, fingers 62 which connect to a bus 64 in a third group, and fingers 57 which connect to integrated circuitry 66 in a fourth group.
Each finger 52, by virtue of crossing both stripes 30, 3~, is connected to four elements, which are served individually by one of the four buses 46, 50, 60, 64. For example, a finger 52 connects to elements 70, 72, 74, 76, which in turn are connected respectively to buses 46, 50, 60, 64. Likewise, each finger 57 is connected to four elements also served respectively by one of the four buses 46, 50, 60, 64.
Each pair of adjacent ~ingers 57 has four elements 38 positioned between them, and each pair of adjacent fingers 52 likewise has four elements 36 positioned between them.
373~
Buses 46, 50, 60, 6~ and integrated circuits 5~, 66 are each connected independently via lines 4], 43, 45, 47, 49, 51 to power supply and control logic 18.
Integrated circuitry 66 represents one of six identical circuits arranged along the length of head 14 on one side of rows 30, 32; integrated circuit 5~ is identical to integratecl circuit 66 and likewise represents one of six identical circuits Oll the other side of LOWS
30, 32. Fach integrated circuit has fifty-four c~lls to serve fifty-our Eillc3ers 52, 57~ Thus ~he twelve circuits are able to serve all 6~ of ~ingers 52, 57.
Integrated circuitry 66 includes a shift register 110 having a set oE cells 112. Each cell 112 includes a transistor 114 whose emitter is grounded, whose collector is connected to a particular one of the fingers 57, and whose base is controlled by the value of a bit stored in the cell. ~en the bit has one value, transistor 11~ is driven to satuLation so that the corresponding finger 57 is effectively grounded (actually the finger is drawn down to the saturation voltage, Vsat, of transistor 119, e.g., 0.3 volts).
When the bit has the opposite value, transistor 11~ is off and the potential on the corLesponding finger 57 is permitted to float.
Referring to Fig. 3, power supply and contLol logic 18 includes a bus power supply 1~0 capable of producing highly regulated voltages at two levels: a higher level for causing printing at a selected element ~the higher level is selected so that the voltage drop across a given element will drive current sufficient to cause the element to heat to a temperature which causes mar~ing) and a lower level for driving the non-printing buses ~the lower level is selected so that the voltage drop across a given ~3~7337 element will not be sufficient to cause printing). ~us power su~ply 120 is connected via h.igh and low voltage lines 122, 124 to power-to-buses switching logic 126.
Logic 126 has outputs connected to bus connection lines 41, 43, 45, ~l7 for delivering the supply voltages, and has its input connected via control signal line 128 to control logic 130 for receiving signals which control the switc~ling of the supply voltages to bus lines at any given time.
Control loyic 130 is also connected via control and data lines 132, 134 to bit strealll swi~ching loglc 13~ ~or delivering, respectively, streams oE bits corresponding to dots to be printed, and related timing control signals which synchronize the operation of the integrated circuits 54, 66 with the powering of buses 46, 50, 60, 64. Logic 136 is connected via lines 49, 51 to circuits 54, 66 for carrying the bit streams and the timing control signals.
Control logic 130 is also connected via control signal line 17 to paper driver 16 and via control signal line 138 to paper drive power supply 140 to trigger the repositioning of the paper to each successive position at the proper time. The output of supply 140 is connected via power line 19 to paper driver 16.
Finally, control logic 130 is connected via control line ~5 and data line 27 to the microprocessor (not shown) to receive the bit streams and commands directing it when to print.
Reerring to Fig. 4, in one typical situation, during printing, bus 4~ is driven to the higher first voltage level (VA) and buses 50, 60, 64 are driven to the lower second voltage level (V~). Each resistance labelled RM represents a printing element wh.ich is intended to be 733~7 heated to print. RMM represents heating elements which are not intended to be heated to print but which are connected to the ~ame grounding finger as an RM
element. RNN represents a heating element which is not intended to be heated to print but is connected to the bus which is being driven to voltage VA. RN represents heating elements connected between the same grounding finger as an ~]N element, and one of the buses driven to voltage VB. With transistors 71, 73 turned on, Eingers 75, 77 are at a third voltage level Vsat.
Thus, V~ must be high eno-lgh so that each R~l heats sufficiently to cause printin~ ~rom a voltage drop oE VA
- Vs t across these resistors. VB must be low enough so that each RMM does not heat sufficiently to print with a voltage drop of VB - Vsat across it, and so that each RNN and RN does not print ~rom a voltage drop of VB - VA across each network consisting or RNN in series with three parallel RN elements.
Subject to those constraints, it is desirable to set VB at a level which minimizes the total power dissipated in the RMM 7 RNN and RN elements.
The voltages across the various resistors are as follows:
VRM = VA - Vsat VRNN = 3/~l (VA - V~) VRN = 1/~1 (VA - Vg) VRMM = VB ~ Vsat -3~3~
The minimum power dissipation ~ill occur when VRMM =
VRNN, i.e., when VB - Vsat = 3/4 (VA ~ VB) or V~ = 3/7 VA -~ 4/7 Vsat a 3/7 (V~ - V~at) -~ Vsat Thus, V~ should be set at 3/7 of the voltage across the printiny reslstors (i.e., 3/7 o V~ - Vsat) plus the saturation voltage (Vsat), so that VRM = VA - Vsat VRNN = 3/7 (VA - Vsat) VRN = 1/7 (VA - Vsat) VRMM = 3/7 (VA - Vsat) With that value of V~ the power dissipated in each of the non-printing elements is 3/7 x 3/7 = 9/49 = 18.2% of the power dissipated in each of the printing elements.
Operation To print a desired pattern of dots, paper 12 is moved to a successsion of fixed positions relative to stripes 30, 32. At each position, power is applied to those elements 36, 38 which need to be heated in order to mark desired dots at corresponding locations on the paper.
Power is applied in four stages. In each stage~ VA is applied to a particular one of the buses 46, 50, 60, 54, while V~ is applied to the remaining three buses. For example, VA is applied to bus 46 and VB is applied to buses 50, 60, 64. Under these circumstances, only half of the elements 36 on stripe 30, (i.e~, those which are connected to bus 46) can be selected to heat to print corresponding dots. A particular one of those elements ~L;Z3733~
heats to print by having integrated circuits 54, 66 connect to ground the finger 52, 57 which leads from the element to be heated, thus establishing VA - Vsat across the element. For example, in Fig. 2, element 70 can be heated to print a corresponding dot by grounding finger 100 to establish a current path (indicated by arrow 102). Appropriate bits are loaded into integrated circuits 54, 66 to cause, while VA i5 being applied to bus 46, the desired elements to be grounded and the others to remain floating.
Many unwanted parasitic electrical paths e~ist along the length of head 14 tendin~ to drive buses 50, 60, 64 to VA, for example the path ~arrow 104) from bus 46 via two elements to bus 50. Were bus 50 actually driven to VA, then element 72, being connected between VA and Vs t~
would erroneously print a dot. However, because VB
applied to bus 50 is regulated to be constant tnotwithstanding parasitic paths such as 10~), bus 50 cannot be driven to VA. Because VB is insufficient to cause printing by element 72, no erroneous printing occurs.
In the second stage of printing, the paper remains in the same position, VA is applied to bus 50, VB is applied to buses 46, 60, 64 and appropriate ones of fingers 52 and 57 are grounded to cause printing by desired ones of that half of the elements on row 30, which are connected to bus 50.
A similar procedure is followed in the third and fourth stages with the VA being applied first to bus 60, then to bus 64. Thus~ in the course of the four stages, any of the elements on rows 30, 32 can be caused to print.
Next the paper is moved along a~is 42 by a distance equal to the width of row 30 to a new position, at which ~ 237337 the four printing stages are again repeated, this time with an updated set of fingers 52, 57 being grounded in order to print desired dots at the new paper position.
The paper is then moved to a succession of new fixed positions, at each of which the four printing stages are repeated. Because the elements on rows 30, 32 are staggered with respect to each other, dots can be printed at all desired places on the page. The loading of bits into the shift registers, the switching of voltages onto buses ~6, 5~, 60, 64, and the advance of the paper to successive positions, are all synchroni~ed by control signals delivered from power supply and control logic 130. The microprocessor to which the power supply and control logic 1~ are connected is programmed to provide the needed bit patterns for integrated circuits 54, 66 based on the characters or graphic symbols to be printed.
By holding the non-printing buses to a fi~ed second voltage level insufficient for causing marking, no diodes are required to counteract the parasitic voltages which could otherwise appear on the non-printing buses.
Eliminating the diodes reduces the design and manufacturing costs and improves the reliability of the head, by making more space available on the head substrate. The availability of space also permits using four buses, two on each side of the elements. Four buses enables using two rows of printing elements, each served by two of the buses. By having each sink conductor connect to both rows, each sink conductor can serve four elements. ~aving alternate ones of the sink conductors lead out to different sides of the element rows reduces the density of the required switching circuitry on the substrate, thus reducing design and manufacturing complexity and cost, and improving reliability. Using four buses permits four-stage printing which reduces the peak power load. Offsettin~ the two rows of elements with respect to each other assures that every location on a pa~e can be printed.
Other embodiments are within the following claims.
For example, more than two rows of elements could be used, with the number of buses being double the number o rows.
~, '
Claims (7)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A thermal print head comprising a first continuous stripe of material along which is defined a first row of elec-trical heating elements, circuitry connected to said elements for heating selected said elements to cause marking in correspon-ding regions of a surface to be printed on, said first row of elements being configured such that, when two adjacent said elements are heated, a non-marked gap appears between the result-ing two marked regions on said surface, and a second continuous stripe of material along which is defined a second row of elec-trical heating elements connected to said circuitry and configured such that, when said surface to be printed on is relocated (in a direction perpendicular to said rows) to a position where said marked regions lie adjacent said second row of heating elements, an element of said second row can be heated to cause marking in said gap.
2. A thermal print head of claim 1 wherein said circuitry comprises leads that overlap said continuous stripes to define overlap areas, said elements being defined between the locations where successive said leads overlap said stripes, and said ele-ments and said spaces having the same lengths in the direction of the length of said rows.
3. The thermal print head of claim 2 further comprising buses for delivering power to said elements, each said bus being connected in common to a plurality of said elements, a power source for applying to one of said buses a first voltage level sufficient, when applied to one said element to which said bus is connected, to cause marking of a surface to be printed on, the connections between said buses and said elements being arranged to define both an electrical path from said one bus to said one element to cause said marking, and unwanted electrical paths from said one bus via said elements to other said buses, said power source being arranged to hold said other buses at a fixed second voltage level insufficient for causing said marking.
4. A thermal print head comprising at least two parallel rows of electrical heating elements, buses for delivering power to said elements, each said bus being connected in common to a plurality of said elements, a power source for applying to one of said buses a first voltage level sufficient, when applied to one said element to which said bus is connected, to cause marking of a surface to be printed on, the connections between said buses and said elements being arranged to define both an electrical path from said one bus to said one element to cause said marking, and unwanted electrical paths from said one bus via said elements to other said buses, said power source being arranged to hold said other buses at a fixed second voltage level insufficient for causing said marking.
5. The thermal print head of claim 4 further comprising conductors for selectively connecting each said element to a predetermined third voltage level, the voltage difference between said first and third voltage levels being sufficient to cause said marking, the voltage difference between said second and third voltage levels being insufficient to cause said marking, and the voltage difference between said first and second voltage levels being insufficient to cause said marking.
6. The thermal print head of claim 5 wherein said second voltage level is lower than said first voltage level and is selected to have a value, relative to said first voltage level, which minimizes the aggregate power loss in said heating elements.
7. The thermal print head of claim 6 wherein said second voltage level is held at a value equal to said third voltage level plus 3/7 of the difference between said first voltage level and said third voltage level.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US687,069 | 1976-05-17 | ||
| US68706984A | 1984-12-28 | 1984-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1237337A true CA1237337A (en) | 1988-05-31 |
Family
ID=24758919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000496198A Expired CA1237337A (en) | 1984-12-28 | 1985-11-26 | Thermal print head |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0186059B1 (en) |
| JP (1) | JPH0657457B2 (en) |
| AU (1) | AU584915B2 (en) |
| CA (1) | CA1237337A (en) |
| DE (1) | DE3578406D1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB8804467D0 (en) * | 1988-02-25 | 1988-03-23 | Alcatel Business Systems | Thermal printing apparatus |
| US5144336A (en) * | 1990-01-23 | 1992-09-01 | Hewlett-Packard Company | Method and apparatus for controlling the temperature of thermal ink jet and thermal printheads that have a heating matrix system |
| US5235346A (en) * | 1990-01-23 | 1993-08-10 | Hewlett-Packard Company | Method and apparatus for controlling the temperature of thermal ink jet and thermal printheads that have a heating matrix system |
| US5134425A (en) * | 1990-01-23 | 1992-07-28 | Hewlett-Packard Company | Ohmic heating matrix |
| US5702188A (en) * | 1995-07-18 | 1997-12-30 | Graphtec Corporation | Thermal head and head drive circuit therefor |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1080297A (en) * | 1977-04-13 | 1980-06-24 | Frederick C. Livermore | Thermal printing device |
| JPS5796874A (en) * | 1980-12-08 | 1982-06-16 | Oki Electric Ind Co Ltd | Heat sensitive head for facsimile |
| JPS5816868A (en) * | 1981-07-24 | 1983-01-31 | Fuji Xerox Co Ltd | Printing head for thermal recording |
| JPS58134765A (en) * | 1982-02-06 | 1983-08-11 | Fuji Xerox Co Ltd | Heat-sensitive recording head |
| US4450342A (en) * | 1982-12-27 | 1984-05-22 | International Business Machines Corporation | Thermal print head |
| US4459462A (en) * | 1982-12-27 | 1984-07-10 | International Business Machines Corporation | Drive system for energizing elements of a fixed bar printer |
-
1985
- 1985-08-20 AU AU46449/85A patent/AU584915B2/en not_active Ceased
- 1985-09-30 JP JP21777285A patent/JPH0657457B2/en not_active Expired - Lifetime
- 1985-11-26 CA CA000496198A patent/CA1237337A/en not_active Expired
- 1985-12-12 DE DE8585115850T patent/DE3578406D1/en not_active Expired - Fee Related
- 1985-12-12 EP EP19850115850 patent/EP0186059B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0657457B2 (en) | 1994-08-03 |
| JPS61154955A (en) | 1986-07-14 |
| AU584915B2 (en) | 1989-06-08 |
| EP0186059B1 (en) | 1990-06-27 |
| EP0186059A3 (en) | 1987-03-04 |
| EP0186059A2 (en) | 1986-07-02 |
| AU4644985A (en) | 1986-07-03 |
| DE3578406D1 (en) | 1990-08-02 |
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| Date | Code | Title | Description |
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| MKEX | Expiry |