CA1215470A - Associative array - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A cellular array processor, comprising: an array of processor cells, each processor cell including a single bit processor having input/
output means connected to neighboring cells, external control registers, internal register means, for data storage, processing means, control means, means to access the external memory, and configuration control means, said array of processor cells responding simultaneously to an external command to process the data in said internal register means, each said processor cell containing configuration bits within its internal register means, whose contents may be processed by the processing means and which when set into a true condition perform a controlling, or mask, function which causes the control means for that cellular processor to modify or condition its response to the external control commands.

Description

S. Morton ~,/5/6-11 ASSOCIATIVE ~RRAY

~ack~round o the Invention .
1. Field of the Invention The present inventlon relates generally to associative processing and more specifically to an associative processing array structure having a variable word length controlled by configuration bits contained within the individual associative cells. The configuration bits may designate, for instance, the most significant and least significant bits in a word. Configuration bits may designate other functions for the associative cell such as disable or skip.
Additional, any of the associative cells in the array may be excluded from a word. The array also includes an extensive instruction set comprising boolean multiple, divide, and all combinations of single or double precision, shift or rotate, left or right operations. The associative processing array of the present invention is particularly advantageously utilized in an LSI (large scale integrated circuit) or VLSI ~very large scale integrated circuit~ configuration, in that increased flexibility may be obtained without an increase in the amount of circuitry and pin connections.
Associative processors having the aforementioned variable word length capability under control of configuration bits the ability to exclude bits and arithmatic and shit capability are useful not only in associative processing computers, but also are useful generally in systems requiring a fault tolerant, fast and flexible computation capability. Such systems include, by way of example, engineering workstations, data base management systems, topological analysis, graphics display, speech recognition, image enhancement, radar applications such as phased arrays, synthetic apertures, echo and wake analysis and tracking, text management syste~s and telecommunications, including digital filtering applications.

P ,~ . ,10~ ton Descriptlon of the Prior Art Associative processorS may be considered as arrays of single bit processors wherein each single cell only accesses its neighbor cells.
Associative processors may be accessed by mutual parallel data streams, the memory thereof is addressable by content and the data structure is based on tags.
While a conventional processor operates on one data item at a time sequentially, an associative processor operates on many data objects simultaneously. For this to be useful, the data objects must be of the same type for any individual instrUCtiOn so that it is meaning~ul to apply the same sequential instruction stream to operate simultaneously on these data objects. This class of processor is known as a Single Instruction Multiple Data processor ~SIMD).
The associative processor may consist of a rectangular array of single bit computers implemented in LSI, each capable, for example, of having rom 2R to 64R bits of memory. These cellular computers obey the same instruction simultaneously, each operating on its own data. The cells can communicate in all four directions with their neighbors and also with external data input and output registers.
The cells in a row of the associative processor array can be dynamically (from one instruction to the next) configured into an arbitrary number of fields of arbitrary defined length (within the constraints of the width of the array). Each field can then operate independently as if it were a separate computer of the given word length, able to perform arithmetic and logical operation. These fields can all obey the same instruction simultaneously, or they may be selectively disabled under program control.
The net effect is that of a set of computers of arbitrarily defined word length, which when they are enabled, obey the same arithmetic or logic operation simultaneously on different data items. This set of computers can be applied to problems requiring matrix arithmetic, algebra, vector calculations, image (pixal) processing, searching and pattern recognition problems, and speech recognition. They can perform both fixed point and floating point arithmetic to any required accuracy. The throughput of this set of processors is dependent on the size of the array, the length and number of fields and the proportion of the array which is enabled for a particular operation. For example, a 128 X 128 cell array 4'7q3 operating on 2048 eight bit numbers simultaneously using a 10 MHz clock is estimated to achieve on the order o~ 4,0~0 million additions or logical operations per second and on the order of 1,000 million multiplications per second.
Associative memories, sometimes referred to as Content Addressable ~emories, are well known generally, and are organized to function in an associative processor, wherein arithmetic operation may be performed on one or more digital words stored in -the memory simultaneously. Such associative processors are described in Unites States Patent No.
4,068,3~5. As illustrated by Unites States Patent No.
4,296,475, such con-ten-t- addressable memories are word-organized, and efforts have been made to reduce the number of connection pins required for employing the memory. Associ-ation between certain bits of an instruction word and previously assigned flags (from status flip-flops, for example) is known such that a da-ta processor executes instructions conditionally by providing masking bits in the instruction word to override one or more association bits. The foregoing is described by United States Patent ~o. 4,~10,452. Unites States Patent No. 4,044,338 describes an associative memory having separately associable zones. Selective coupling of circuit elements to adata bus wherein each circuit element has an associative address is described by Unites States Patent No. 4,188,670. United States Patent No. 4,159,538 is illus-trative of an LSI associative memory wherein the number of pin connections is reduced by sharing certain package pins by input data, output data and mask information. A serially accessed associative memory is described by Uni-tes S-tates Patent No. 4,153,943. An Associative Storage Apparatus for Comparing ~3a--Between Specified Limits is described by Unites States Patent 3,845,465. An Array Processor with processing elements arranged in a rectangular array is described by Unites States Patent 3,979,728. United States Patent 3~654~3941 Field Effect Transistor Switch, Particularly for Multiplex;ng, described multiplexing analog signals.
Summar~ of the Invention An associative processor is described wherein an array of associative processing cells is configured according to a format defined by configuration bits which perform functions previously performed by external masks. This provides increased flexibility in the use of an associative array in that word length can be arbitrarily extended, desired functions may be arbitrarily performed within the array, such as for instance skip or disable functions, and, the associative processor is no longer subject tc the requirement that the external mask designate which cells are to perform in a given manner.
The array of associative processing cells is intervened by five paths between adjacent horizontal cells. This provides the minimum number of interconnections and thus the minimum number of pins and the minimum amount of hardware, that is necessary to accomplish multiple divide and double precision rotate left and rotatè right operations.
~ four part multiplexer is described which allows an arbitrary number of these devices to be connected to series. Each of these multiplexers forms a part of a processing cell and allows a variety of communications between adjacent processing cells.
The multiplexer may be implemented in MOS (metal oxide semiconductor) or CMOS (complementary MOS) intergrated circuits, and may be dynamically configured to exclude faulty or unwanted processing cells from an operation, and to construct the minimum propagation delay path across a collection of processing cells.
This provides increased reliability, flexibility and speed a processing array, in the word length can be arbitrarily extended, the computation rate can be maximized and spare processing cells can be provided to compensate for cells that fail during the fabrication or life of the array.
It is an object of the present invention to provide enhanced flexibility in the use of Associative processors.
It is another object of the present invention to allow masking functions to be performed in accordance with information stored in internal cell memory hence avoiding limitations inherent in the use of external masks.
It is still another object of the present invention to allow arbitrarily long word lengths without regard to the number of processing cells contained on a chip.
It is yet another object of the present invention to allow for assignment of mask functions which are dependent upon the content of the cells input.

It is another object of the present invention to minimize the number of interconnections between processor cells in an associative processor.
Thus, in accordance with a broad aspect of the inven-tion, there is provided in an associative processor array inclu-ding M rows and N columns of identical processing cells, with each cell connected horizontally to its left and right to a neighboring cell and connected vertically to its up and down to a neighboring cell, with a vertical bus connecting all cells in a column and a horizontal bus connecting all cells in a row;
each cell including a memory for storing control and data information, with the output of said memory coupled to an arithmetic logic unit (ALU) and with the output of said A~U
coupled to registor means associated with each cell, with said cells as forming said array capable of performing arithmetic operations on words each consisting of a plurality of bits and each including a given number ofslices to enable an arithmetic function to be implemented by each cell, the improvement therewith of apparatus for providing data paths between cells in a given row in said array, comprising:
a first path coupled to each of said cells in said given row and operative to move a first bit from left to right or from right to left in said row with said path coupled to each of said memory means in said cells, a second path coupled to each of said ALUS in said cells in said given row and operative to propagate the arith-metic carry from said ALU of any of said cells to any right or left cell in said row, a third path coupled to each of said cells in said row and operative to move a second bit from one cell to the next in a given selected direction as from right to left or ~ J

- 5a -or from left to right, and means associated with each cell and responsive to said second bit to store said bit in said cell, a fourth path coupled to each of said cells in said row and operative to move a third bit from said ALU output of each cell from one cell the the next with said means associated with each cell responsive to said third bit for storing said bit in any of said cells, a fifth path coupled to each of said cells in said row and operative to move a fourth bit from one cell to the next in said row from left to right or from right to left, and storage register means associated with each cell for storing said fourth bit in each storage register means in said cell to enable said cell to determine which of said stored bits as said first to fourth are associated with a given slice of said word to enable each cell to perform said arithmetic function according to said bits as stored within said cell.
Brief Descriptlon of the Drawings Figure 1 is a Block Diagram of an associative processor.
Figure 2 is an illustration of an associative pro~
cessor chip showing the interconnection of processing cells.
Figure 3 is an illustration showing the primary horizontal interconnections between adjacent processing cells.
Figure 4 is an illustration showing the vertical interconnections between adjacent processing cells.
Figure 5 is an illustration showing the overall interconnections of a processing cell.
Figure 6 shows single word shift structures.
Figure 7 shows double word shift structures.
Figure 8 shows slice usage.

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- 5b -Figure 9 is a diagram of the common logic instruc-tion pipeline in an associative processor chip.
Figure 10 is a diagram of the cell logic - arithmetic instruction programmable logic array.
Figure 11 is a diagram of the arithmetic core in a processing cell.
Figure 12 shows a linear array bf Transversal Hori~ontal Multiplexers.
Figure 13 shows data flows in a Transversal Horizontal Multiplexers.
Figure 14 shows a detailed view of a Transversal Horizontal Multiplexer.
Figure 15 shows a control signal simplification circuit.
Figure 16A shows transmission gate representations.
Figure 16B shows a lumped equivalent circuit of the schematic circuit of Figure 16A when conducting.
Figure 17 shows a simplified equivalent circuit for a series of transmission gates.
Figure 18 illustrates signal path usage in an asso-ciative processor performing an Add instruction.
Figure 19 illustrates signal path usage in an asso-ciative processor performing an arithmetic/logical shift right instruction.
Figure 20 illustrates signal path usage in an asso-ciative processor performing a skip over field in an inter-mediate portion of a word operation.

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Fig. 21 illustrates signal path usage in an associative processor performing a sign extension operation.
Fig. 2Z shows path usage in an associative processor performing a rotate left instruction.
Fig. 23 illustrates signal path usage in an associative processor performing a double rotate left instruction.
Fig. 24 illustrates signal path usage in an associative processor performing a fixed multiply intermediate instruction.
Fig. 25 illustrates signal path usage in an associative processor performing a fixed divide intermediate instruction.

Detailed Description of the Invention 1. Introduction .. ..
Data processing on an associative processor as shown in FigO 1 is performed on an N x M array. The size of the array is not important for purpose of the invention although larger arrays will provide higher throughputs. The N X M array, by nature of the dynamic repartionability of an associative processor can equally well operate on N M-bit numbers, 2N M/2-bit numbers, 4N M/4-bit numbers, or other combination having the same number of total bits.
Additionally, the array may operate with a lesser number of total bit requirements although less than all cells in the array will be utilized during such operation.
The associative processor array described herein is implemented as M rows by N columns of identical cells. Each cell is a single-bit processor and is connected horizontally to its left and right, and vertically to its up and down, neighbors, and at right angles to the plane of cells, to bulk off-chip memory. ~n addition, there is a Vertical Bus connecting all cells in a column, and a Horizontal Bus connecting all cells in a row. A multiplicity of cells are preferably implemented on a single integrated circuit. A portion of this associative processor is shown in Fig. 2.
In order to process information in an associative processor, it is necessary to define the number of bits which comprise one number.
This is referred to as the word size. within the associative processor words are formed from groups of one-bit cells working together. Any cell within the associative processor can have any bit position in a word, although the bit-significance of the cells in a word must be unchanged or increase monotonically across a row.
Also, carry in an arlthmetic operation must flow from right to left, i.e., from a lesser numbered column to a greater numbered column.

~L~ 7~
~ orton 4/~/6-11 Minimum word sizes are 1 bit for logic operations and 2 bits for fixed point arithmetic operations.
Words may be formed from cells that are in multiple chips, and there is no fundamental upper limit on word size. A cell operates in a given manner regardless of whether it is on a chip boundary, hence a given cell works in exactly the same way regardless of whether its neighboring cell is in the same or a different chip.
It is furthermore irrelevant whether that other chip is in the same or a different row. The interconnection between adjacent cells along the horizontal rows in the processor is shown in Fig. 3 and includes five arithmetic connections, the carry path, the ALU path, the MQ path, the loop path and the status path.
An array of chips may be configured in two waysi either by placing chips side by side, to increase the width of the array, or one above another, to increase the height of the array. In either case the down signals for the bottom-most row are typically connected to the Vp signals from the top-most row. The connections of the five arithmetic processor signals will be described later. For ease of explanation, reference will be made to the arrangement wherein the array has 16 rows and 16 columns.
The operation of each cell in this array is determined by two things. (1) There are control bits that are sent to all cells and it will be assumed that there are 32 control bits. These bits are supplied from outside the chip and are partitioned into 24 data path control, 5 status control, 2 memory data register control, and 1 enable bit. The data path control bits include 6 instruction bits that choose the arithmetic, logic, shift, or configuration operation that is to be performed on a word. (2) There are configuration bits that are stored in a multiport RAM in each cell, and 3 of these bits are decoded to identify, among other things, the LSS, ISS's, and MSS
in a word. In all there are 7 configuration bits contained in each cell, 3 ALUP (Arithmetic Logic Unit Processor) Horizontal Masks, 3 AL~P Vertical Masks, and an Impedance Restoration Mask.
As shown in Fig. 11, each cell has 64 random access storage locations, each location comprising a single bit. This storage is a multiport RAM, which, in the view of the arithmetic and logic unit, has two outputs, A and 8. The 6-bit Read Address (R ADDR) selects one location, while the 6-bit Read/Write Address (R/W ADDR) selects another location. If a result is written to memory, the Read/Write Address specifies both one of the sources and also the destination of the data.

The multiport Ram is conceptually divided into upper and lower halves. The lower 32 locations are considered user memory and have no special properties. The upper 32 locations are considered sy~tem memory and have many special properties.
There are numerous direct inputs to, and direct outputs from, the system memory to provide control and data paths that operate in parallel with the arithmetic and logic unit. Access to off chip memory, the Up and Down Paths, and the Vertical and Horizontal busses is all provided through the system memory. The configuration bits, the multiplier/quotient register, and the status bits are also in upper memory.
The global view of connections to the chip and between cells is shown in Figure 2. The details of horizontal connections between two cells are shown in Figure 3, and of vertical connections between two cells in Figure 4. These connections apply regardless of whether or not the cells are in the same or different chips. All connections to a single cell are shown in Figure 5.
The five arithmetic path signals are connected between chips to enable words to span multiple chips. The ALU Left, Carry Left, MQ
Left, Loop Left, and Status Left signals from the left-most column of a chip are typically connected to the right of the right-most column oE a chip that is to the left in the same row, or, if the chip is in the left-most column of the array, to the right of the right-most chip in the array in the row above. The ALU Left, Carry Left, MQ Left, Loop Left, and Status Left signals of the top row, left-most chip in the array, are typically connected to the right of the right-most chip in the array in the bottom row.

2. Slice Types Cells are organized into words by the 3 ALUP Horizontal Masks.
The Configure instruction is intended to facilitate the loading of these masks independent of their state. These masks must be loaded before the instruction set, other than the Configure instructions, is executed.
The way a particular cell performs an instruction is dependent on the type of slice to which it has been set. The partitioning of a word into slices is shown in Figure 8, and the use of the five implemented slices, as chosen by the 3 ALUP Horizontal Mask bits, is:

7~
~. Morton 4/~/6-ll 9 _ Inactive causes a cell to have its storage frozen and to be horizontally invisible.

Horizontal Skip - causes a cell to be horizontally invisible, but allows its storage to be updated. The Horizontal Skip slice is useful when one wants to replicate a bit in a number of slices, such as for sign extension.

Fixed point arithmetic, which may also include characters, has three logical types of processor slices.

LSS: - least significant slice. End-of-word condition may be specified: Carry in, for an arithmetic instruction, or the serial input, for a shift left, is selected by Serial input select.
MSS: - most significant slice End-of-word conditions may be specified: The serial input, for a shift right, is selected by Serial Input Select.

ISS: - intermediate significance slice. All connections are specified by the instruction e.g., carry In comes fror~
the slice to the right, and carry out goes to the slice on the left.

Single-bit, logical values, may be slice type LSS. Arithmetic and rotation instructions require words with at least 2 bits, an LSS and an MSS, and may have any number of ~SS's.

3. Major Hardware Blocks 3.1 Instruction Pipellne The instruction pipeline consists of the common logic -instruction pipeline, shown in Figure 9, and the cell logic -instruction PLA, shown in Figure 10. The 29 ALUP Control signals must be stable immediately before the falling edge of the AL~P
Clock. Most of the first clock period is thus available for the settling of these signals.
During the second clock period, the 29 ALUP Control signals are transmitted from the common logic to the cells and are fed to the cell instruction PLA inputs and multiport RAM address decoders.

~~ 3 s. Morton 4/5/6-11 The instruction is executed during the third clock period.
Status, from a preceding cycle, modifies the output of the instruction PLA output register. Status can change every cycle and cannot be applied to the PLA inputs which are one cycle ahead of execution.
The three ALUP Horizontal Mas~ bits shown in Fig. 11 drive the PLA, thus care must be taken in the changing of the masks because a mas~ change affects instruction execution and the result is delayed by one clock cycle. The chip may either be fed a no-op using the Status Control signals, or the Configuration instruction, which is mask-independent, may follow a mask change.

3.2 Multiport RAM

The 64-word multiport RAM shown in Fig. 11 is conceptually divided into two halves. The lower, or user, half contains general purpose storage with no special inputs or outputs. The upper, or system, half contains many special inputs and outputs and provides many special functions. An example of address assignment is shown in Table 1. All of the bits have both read and write access within the cell.
The RAM has three ports. Two output ports, RAM A and RAM 8, are addressed by the Read Address and the Read/Write Address respectively. RAM A goes to the ALU "A" input, and RAM B goes to the ALU "B" input. The RAM input port BIN is also addressed by the Read/~rite Address.
An operation of the form:

A OPERATION B ~ B

read "A operation B goes to B", can be performed in a single cycle.
The contents of A, selected by the Read Address, is operated on by B, selected by the Read/Write address, and the result is conditionally stored in B. Whether or not B is loaded is determine,d by ALUP Enable, Storage Enable, and Status Storage Enable, as described later.
The operations include an exhaustive set of arithmetic, logic, shift and rotate instructions. Single word shift structures are shown in Figure 6, and double word shift structures are shown in Figure 7. The instruction set is summarized in Tables 3~6.

~a~
V ~ . ~ ~ ~ ~ I ~ Y / J / IJ --The system half of the multiport RAM provides access to various input/output paths, plus status and configuration control bits.
These bits are used as follows:

3.2.1 MQ

The MQ, multiplier/quotient, bit is used during multiply, divide, and double word shift and rotate instructions. This bit may be accessed independently of the Read and Read/Write Addresses through the MQ path.

3.2.2 MDR

The MDR, memory data register, connects the cell to external memory. The register may be accessed independently of the Read and Read/Write Addresses through the external memory path, and is controlled by the 2 MDR control signals, direction and strobe.

3.2.3 Status Register The Carry, Negative, Zero, and Overflow bits comprise the Status Register. The inputs to each bit are the ALU D Bus, for use when the bit is selected by the ~ead/Write Address, and other sources as selected by the instruction PLA. The writing into these locations is controlled separately from the writing into the location selected by the Read/Write AddressO This independent control is provided through the storage enable lines.
The inputs to the status register bits for the Arithmetic and Logic Instructions are: Carry bit - ALU carry out, Negative bit -ALU D BUS, Zero bit - Status Left/Right Multiplexer, Overflow bit -ALU Overflow. The Zero bit, actually the Not Zero bit, also called the Status Flipflop, is also used by all data-dependent instructions, such as multiply and divide, hence its meaning varies from instruction to instruction. The Zero Flipflop is inverted for the Arithmetic and Logic instructions being true when the result is NOT ZERO.

3.2.4 Sticky Overflow The Sticky Overflow bit is controlled separately from the Status Register. It provides the logical OR of itself and the ALU overflow, 7~

and may be used to provide a running check of whether or not an error condition occured. It is typically loaded when the MSB of a word becomes valid, such as the las-t cycle of a multiply sequence.
3.2.5 Bus and Path Four Registers, the Horizontal Bus, Vertical Bus, Down Path, and Up Path Registers provide inpu-t and output to the cell. Each register may be directly loaded from the bus or path that bears its name, and inversely, each bus or path may be driven directly from the register that bears the name or the bus or path. In addition, the regis-ters provide three-address operations, i.e., A PLUS B -> C, where C is one of the registers. Any one of these bits may be loaded from the ALU D BUS~ independently of the Read/Write Address. The registers may also be bypassed so that a bus or path may be directly connected to an input of the ALU, leaving the register contents unchanged. This direct input, along with a direct output from the ALU, provides results that accumulate from one row to -the next, so called "broadside operations", as will be explained later. The registers are controlled by the Input/Output Func-tion and the Input/Output Select signals, which are part of the Data Path Control signals.
3.2.6 Impedance Restoration Mask The Impedance Restoration Mask is used by the five arithmetic paths to minimize signal propagation across a chip.
It is expected to reduce the delay across -the chip by 5~% and has no special inputs.
3.2.7 ALUP Horizontal Masks The 3 ALUP Horizontal Masks organize cells into t -13-~

words. See "Slice Types".
3.2.8 ALUP Vertical Masks The 3 ALIJP Vertical Masks control the flow of information on the Up and Down paths. Masks ~ and 1 are decoded to con-trol the information fed into a row, and Mask 2 selects the data that is sent out of a row. See Table 2.
Setting ALUP Vertical Mask 2 true allows the output of the -ALU to be the output of a row, and the use of -the Direct Input instruction allows that output to be the input ~o the ALU of the next row. These are multiple row, or "broadside", operations. Multiple rows may thus operate on data that accumulates across the rows. The sum of data from all the rows may thus be computed in a single cycle. In addition, data may flow up or down, as chosen by the Input/Outpu-t Select signals.
3.3 Arithmetic and Logic Unit The Arithmetic and Logic Unit (ALU) provides seven arithmetic, seven logic, and two constant functions. These are identified in Table 3 and the first seven instructions in Table 4. These functions are executed explicitly by the logic instructions and by some of the Arithmetic instructions, and are executed implicitly by the other instructions.
3.4 Horizontal Data Paths There are five primary horizontal data paths between adjacent cells. These five, the ALU, Carry, MQ, Loop, and Status, Paths support arithmetic operations. The paths are fundamental to the operation of the chip, and provide the ability to have arbitrary word sizes, spanning the range of multiple words per chip, to multiple chips per word. These paths are brought out of the chip from each row from the left ct~

-13a-of the left-most column and the right of the righ-t-most column. The operation of four, ALU, MQ, Loop, and Status, of these paths is bidirectional and depends upon Transversal Horizontal Multiplexers. The carry path is unidirectional.
A basic problem in providing arbitrary word sizes is how to connect the opposite ends or words together. In a conventional, fixed word size computer, a single wire connects the MSS to the LSS. This connection is used for single word operations, such as rotate, and double word operations, such as multiply and divide. A single 16-bit AP chip would need hundredS cfwires if every possible MSS were directly tied to every possible LSS. Not only is the word size arbitrary, but the position of that word can be arbitrarily located in a sequence of cells. Further compounding the problem is the requirement of being able to connect an arbitrary number of AP chips toge-ther to form arrays of various sizes, so the number of possible interconnections is large.

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3.4.1 Transversal Horizontal Multiplexer A Transversal Horixontal Multiplexer moves a bit from a cell to its left or right neighbor, or moves a bit from the left or risht neighbor to the other neighbor, bypassing the cell. A series of cells may thus be arbitrarily divided into words by selecting some multiplexers to connect groups of bits forming the body of a word, and multiplexers in other cells to form boundary bits, i.e., at the LSS and the MSS, separating words. The instruction PLA uses the ALUP Horizontal Masks, which identify slice types, and the instruction code, to properly control the various horizontal multiplexers.
The primary implementation of the Transversal Horizontal Multiplexer is in MOS (metal oxide semiconductor) or CMOS
(complementary MOS) integrated circuits. The invention is intended for use in an array of like devices, or cells and facilitates the communication between three adjacent devices. See Figure 12.
Note that the Left signal from the center Transversal Horizontal Multiplexer, cell M, goes to the Right signal of cell M+l, and that the Right signal from cell M goes to the Left signal oE cell M-l.
Figure 13 shows the data flows that are possible with a Transversal Horizontal Multiplexer. Each multiplexer has four signal nodes, each providing a single-bit path, and control inputs.
There is an unidirectional input, Data In, and a unidirectional output, Data Out. The Left signal path to the Right signal of the left neighbor, and the Right signal path, to the Left signal of the right neighbor, are bidirectional. Five data flows are possible, as chosen by the control input:

1. From cell M to cell M+l: path lA connects Data In to Left, and path 2B connects Right to Data Out 2. From cell M to cell M+l: path 2A connects Data In to Risht, and path 28 connects Left to Data Out 3. From cell M-l to cell M~l: path 3 provides a unidirectional connection from Right to Left, and path lB provides a connection from Right to Data Out

4. From cell M~l to cell M-l: path 4 provides a unidirectional connection from Left to Right, and path 2B provides a connection from Left to Data Out.

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5. Between cell M~l and cell M-l: path 5 provides a bidirectional connection between Left and Right The power of the Transversal Horizontal MultipleXer is that it allows regular structures to be built that provide arbitrary word sizes while requiring data connections only between adjacent cells.
In addition, data in a cell can be left out of an operation, and furthermore, the number of connections between cells is minimized, without resorting to time division multiplexing of connections.
The Transversal Horizontal Multiplexer is composed of three two-input multiplexers, two tri-state buffers, and a bidirectional transmission gate. Multiplexer M3 is called the "Left/Right Multiplexer" because it selects between the Left and Right signals.
Only a single connection to each of the left and right neighbors is required. See Figure 14.
There are five control signals, Bypass, Left/Right Select, Output Select, Flow Left and Flow Right. The logic in Figure 15 allow the use of only three control signals, with Flow Left, Flow Right and Output Select being generated from Direction. Use of this logic has been assumed in the preceding discussion, and results in Data In flowing to either Left or Right, but not both simultaneously, and Data Out coming from incoming data on Left or Right rather than coming from outgoing data.
In the following discussions, the following definitions are used:

1. Transmission gate - input and output are interchangeable, with high impedance between input and output when the control line is false; and relatively low impedance between input and output when the control line is true.

2. Buffer - output follows input, with a low impedance to power or ground when control line is true; high impedance output when control line is false.

3. Two-input multiplexer - output, Y, follows input "0"
when Select line is false; output follows input "1" when Select line is true.

The detailed operation of the Transversal Horizontal Multiplexer is as follows:

S. Morton 4/5/6-11 1. Data flow from Data In to Left: Bypass at Tl is set false. Left/Right Select is set false to select Data In, Plow Left is set true so that the Left pin receives the selected data from M1, and Flow Right is set false so that data may come from the Right. Output Select is set true so that data at Right is sent to Data out at M3~

2. Data flow from Data In to Right: This is the same as case 1, except that Flow Right is true, Flow Left is false, and Output Select is false.

3. Data flow from Right to Left: Bypass is set false and Data In is irrelevant. Left/Right Select is set true so that data at Left flows to the M2 output~ Flow Right is set true so that the M2 output flows through B2 to Right. Flow Left is set false, and Output Select is set false so that the driving input flows through M3 to Data Out.

4. Data flow from Left to Right: This is the same as case 3, except Flow Left is true, Flow Right is false, and Output Select is true.

5. Data flow between Left Cell and Right Cell: Input Select, Output Select, and Receive Select are irrelevant. Flow Left and Flow Right are set false.
Bypass is set true so that a bidirectional, relatively low impedance connection is established between Left and Right. This is the state that is used when a cell is faulty since the minimum amount of logic must work in order for data to flow across a cell.

Another feature of the invention is that it allows the dynamic construction of minimum propagation delay paths. One notes that a signal must flow through a collection of Transversal Horizontal Multiplexers in order to get from one end of a word to the other, such as in a state left or state right instruction. There are two ways for a signal to cross a cell, through the multiplexer and buffer (Ml and Bl or M2 and 82 in Figure 14) or through the transmission gate (Tl in Figure 14).

A difficulty is the relatively high impedance of the transmission gate even in the active state. As the number of multiplexers through which data is propagated increases, the distributed capacitance, along with the increasing impedance of the string of transmission gates, slows down circuit operation.
Figure 16A shows a schematic representation of a CMOS
transmission gate. The transmission gate is built from two series pass transistors, one p-channel and one n-channel. When the Control line is high, either one of the transistors may conduct, depending upon the state of the Input signal, presenting a relatively low impedance path from input to output, and the gate is considered active. When the Control line is low, both transistors are off, and the Input is disconnected from the Output.
Figure 16B shows a lumped circuit model of a transmission gate.
For an active CMOS gate with minimum geometry, 4u design rules, with the circuit operating at 5 volts, CO + CI = 0.5pF and R = lR ohm, approximately.
Figure 17 shows a collection of these lumped circuit models in series, as in the case of a long, end-to-end chain. The resistive impedance to charge C at Node 1 is R plus S, where S is the source impedance. Likewise, the resistive impedance to charge C at Node 4 is 4R plus S, and so on. Thus the circuit speed decreases as the number of transmission gates in series increases.
If each transmission gate is replaced by a buffer, there is a constant impedance to drive each node, but the propagation delay through a buffer is much longer than through an isolated transmission gate. Some combination of transmission gates and buffers must thus be found to provide the optimum performance.
Propagation delay times for a minimum geometry, 4u design rule, CMOS process, with the circuit operating at 5 volt.s with minimal loading is approximately as follows:
1. Multiplexer and buffer - 10ns 2. Transmission gate - (3 + N)ns, for small values of N, where N is the index of the gate in a string of gates.

Thus, four Transversal Horizontal Multiplexers in series would have a propagation delay of 40ns for four buffers in series, or only 22ns for three transmission gates and one buffer in series. The circuit may thus run nearly twice as fast using a combination of L C ~ L L

transmission gates and buffers as using only buffers. One thus chooses the path through the buffer, in order to provide a low impedance signal, whenever parasitic delays outweigh the benefit of the transmission gate connection.
In general, a set of values for the Bypass, Flow Left, and Flow Right signals is chosen to minimize the propagation time. The choice depends upon the circuit fabrication technique, interface considerations between cells (which may be on different chips), and upon the word sizeO It is assumed in the previous example that only every fourth buffer may need to be activated, leaving the three intervening transmission gates potentially active.
The Impedance Restoration Mask is set true by the programmer in those cells where the use of a buffer, rather than a transmission gate, is desired. If the instruction PLA specifies that a connection from Left to Right, or Right to Left, is required, and the Impedance Restoration Mask is false, then the Bypass signal is set true, and the Flow Left and Flow Right signals are set false. The transmission gate is thus usedA Similarly, if the Impedance Restoration Mask is true, then Bypass is set false and the buffer that is enabled by Flow Left or Flow Right is used.
Likewise, if data in a cell is to be left out of an operation, 3ypass can be set true and Flow Left and Flow Right are set false.

3.4.2 Path Usage The implementation of dynamic word size configuration recognizes that only five horizontal paths between adjacent cells are required to support an extensive instruction set. The paths are used as follows:
Carry - propagate the arithmetic carry from the ALU Carry Output to the left, or move the carry from the right to the left.

ALU - move a bit from one cell to the next. The movement ma,y be to the left, to the right, from the right to the left, or from the left to the right. The typical input to this path is the ALU C Bus, i.e., the ALU output, and the typical destination is the multiport RAM.

MQ - multiplier/quotient - move a bit from one cell to the next. The movement may be to the left, to the right, from the right to the left, or from the left to the right. The typical input to this path is the MQ
flipflop, and the typical destination is the MQ
flipflop.

Loop - move a bit from one cell to the next. The typical input to this path is the ALU C Bus, i.e., the ALU
output, and the typical destination is the ~Q
flipflop. This path usually provides end-to-end coupling in double word operations.

Status - move a bit from one cell to the next. The movement may be to the left, to the right, from the right to the left, or from the left to the right. In addition, horizontal OR and XOR operations may be performed, using logic outside of the transversal horizontal multiplexer, so that one may perform a zero check or a parity computation on an entire word in a single operation. The typical input to the path is the ALU D
Bus, and the typical destination is the Status Register. Unlike the other paths where a single flipflop is the usual destination, the Status Path is widely used, as in the Multiply and Divide instructions, to transmit a single status bit to all Status flipflops in the word so that the slices may perform in a coordinated manner.
The usage of the paths in key instructions is shown in Figures 18-25.
The terminoiogy used in these figures is as follows:

A/S - determined by Serial Input Select lines - output of ALU Left/Right Multiplexer D - ALU D Bus L - output of Loop Left/Right Multiplexer M - output of MQ Left/Right Multiplexer S - output of Status Left/Right Multiplexer MPR - multiport RAM
MUX - multiplexer THMUX - transversal horizontal multiplexer MUL MSB - multiplier most significant bit 4 ~

Figure la shows the path usage in the ADD instruction. The Carry path moves the ALU carry output of each slice except the MSS
to the next slice to the left. The Status path with OR gates external to the Transversal Horizontal Multiplexers, provides a running OR of each bit of the sum, from right to left, so that the Zero/Status flipflop in the MSS is false only if all bits of the sum are false. The carry into the LSS is selected by the Serial Input Select lines, which choose among zero, one, and others.
Figure l9 shows the path usage in the ARITHMETIC/LOGIC SHIFT
RIGHT instruction. The ALU path carries the ALU C Bus of each slice except the LSS one bit to the right where it is stored in the multiport RAM. The Status path carries the bit shifted out of the LSS to all Status flipflops for use in multiple word shifts. The input to the MSS is chosen by the Serial Input Select lines, which select among 0 and the ALU C Bus, the latter for replicating the sign bit in arithmetic shifts.
Figure 20 shows the path usage in an example of a Skip Over Field operation. An ARITHMETIC/LOGIC RIGHT SHIFT instruction is executed, but cells in the middle of the word are set to the Inactive state.
Data from the third cell to the left flows on the ALU path past three Inactive cells and is stored in the third cell from the right. The number of cells in the Inactive state, the slice type of source and sink cell, and the direction of data flow, are all arbitrary.
Figure 21 shows the path usage in an example of an operation using Horizontal Skip. When all cells except the MSS and LSS are set to the Horizontal Skip state and an ARITHMETIC/LOGIC RIGHT SHIFT
instruction is executed, the bit from the MSS flows via the ALU path to, and is stored in, all other cells in the word.
Figure 22 shows the path usage in the ROTATE LEFT instruction.
The Read Address selects a location in the Multiport RAM. The contents of the location, in the LSS and all ISS's, is shifted one bit to the left via the ALU path. The contents of the location in -the MSS is entered into the loop path which carries it to the LSS.
The shifted data is written into the multiport RAM at the location selected by the Read/Write Address.
Figure 23 shows the path usage in the DOUBLE ROTATE LEFT
instruction. The operation is similar to ROTATE LEFT, except that a pair of words is shifted. The word in the location in the multiport RAM selected by the Read Address is shifted one bit left via the ALU
path where the bit shifted out of the MSS is entered into the LSS of a special location in the multiport RAM, the MQ register, via the Status path. The MQ register is shifted one bit to the left via the MQ path, and the bit shifted out of the MSS is entered into the LSS
of the location selected by the Read Address via the Loop path.
Figure 2~ shows the path usage in the MULTIPLY INTERMEDIATE
instruction. The algorithm used is to add the multiplicand to the partial product if the current LSB of the multiplier is true. The partial product is then shifted one bit to the right, along with the multiplier. The Status flipflop determines whether or not to add the multiplicand to the partial product. The Carry path moves the ALU carry output of each slice except the MSS to the next slice to the left. The ALU path moves each bit of the partial product sum one bit to the right, except for the MSS which gets the multiplier MSB, the sign bit which has been corrected for overflow. The shifted sum is loaded into the multiport RAM. The MQ path moves each bit of the multiplier, in the MQ flipflop, one bit to the right, except for the MSS. The shifted result i5 loaded into the MQ
flipflop. The Loop path moves the partial product sum in the LSS, past the other slices, to the MSS of the MQ flipflop. The Status flipflop in the LSS receives the multiplier bit being shifted from the MQ flipflop second LSS. The Status path carries that same bit, from the MQ flipflop second LSS, to the left to all Status flipflops other than in the LSS. This status bit is used in the following cycle. The instruction is executed for each bit of the multiplier except the last bit when the data is in 2's complement notation.
Figure 25 shows the path usage for the DIVIDE INTERMEDIATE
Instruction. The algorithm used is non-restoring division. The ALU
operation depends upon the status flipflop which stores the outcome of the previous cycle. The ALU path shifts the partial remainder, initially the most significant half of the numerator, one bit to the left, while the MQ path shifts the least significant half of the numerator, and eventually the quotient, one bit to the left. The halves of the numerator are tied together by the Loop path. The Status path conveys the sign comparison from the MSS to all slices of storage in the Status Register and use in the following cycle.
Sign comparison determines whether the denominator should be added or subtracted from the partial remainder.

3 5 Horizontal Busses The Hori~ontal Bus and the ORed Bus are connected in parallel to all cells in a row and are brought off the chip.

~a~ 7~
S . MOr tOn ~/5/6-11 .
The Horizontal Bus is bidirectional and may be loaded directly into the Horizontal Bus Flipflop in each cell, or may be used directly as an input to the ALU. The Horizontal Bus may be driven by the Horizontal Bus ~lipflop in a selected cell. One cell per row is selected by asserting the Vertical Bus line connected to that cell. The Input/Output Function and Input/Output Select lines control the operation of the Horizontal Bus.
The ORed Bus, which produces an inverted output, is unidirectional. The output is intended to be ORed with the like outputs of other chips in the row, where the OR is performed by a gate, not a wired OR. The driver is always enabled. One or more cells drive the bus, which is internally open collector, when one or more Vertical Bus lines are asserted. The source of data for the bus is the Horizontal Bus Flipflop.

3.6 Vertical Connections There are three vertical connections between cells, the Up path, the Down path and the Vertical Bus. Within an AP chip, the Vertical Bus is connected in parallel to all cells in a column, and the Up and DOWD paths connect all cells in serial in a column.
The operation of these paths is controlled by the Input/Output Function and the Input/Output Select pins. Each path may be driven by a specific bit in the multiport RAM, and each path may be directly loaded into that bit or may be directly connected into the input of the ALU, under control of the Read Address and the Read/Write Address. In addition, the loading of the multiport RAM
bits that drive the paths is controlled separately from the Read/Write Address by the Input/Output function lines, and provides a three-address mechanism, making possible operations of the form:

A OPERATIO~ B -~ C

where C is one of the Vertical Bus Register, the Up Register, or the Down Register.
Separate registers, i.e., multiport RAM bits, have been provided for the Up and Down paths to speed the alternate movement of data both up and down.
Each row of the chip has a small amount of logic that is used in common. Bidirectional buffers are provided for the Horizontal Bus.
The Horizontal Bus output buffer is enabled when the Input/output 7r~
~ / J / ~J -- L L

Select and Input/Output Function lines are in the Horizontal Bus Output Enable state, and when any Vertical Bus line is asserted.
Only one cell may drive the input to the buffer at one time. The Horizontal 8us input buffer is enabled when the Input/OutpUt Select and Input/Output Function lines are not in the Horizontal Bus Output Enable state.
Each column of the chip has a common bidirectional buffer. The output buffer is enabled when the Input/Output Select and Input/Output Function lines are in the Vertical Bus Output Enable state, and when any ~orizontal Bus is asserted. The input buffer is enabled when the Input/Output Select and Input/Output Function lines are not in the Vertical Bus Output Enable state.

3 7 Instructlon Pro~rammable Logic_Arrav Each cell is individually configured by its own set of masks, hence each cell must have its own instruction decoder. This decoder is a prograrrmable logic array (PLA), which is a regular structure that facilitates the redefinition, or correction, of functions.
There is a small number of inputs, ten, but a relatively large number of outputs, 40, only a few of which are usually active at one time. The instruction opcodes, slice enumerations, and internal multiplexer select codes have all been chosen to minimize the size of the PLA. The more an input to a multiplexer is used, the fewer are the number of ones in its select code.
The Status Flipflop modifies some of the PLA outputs so that instructions can be data dependent. The architecture is relatively simple in that only the choice of ALU operation is data dependent;
the path operation is not affected. The instructions which implernent multiplication and division make use of this data dependent feature and have an implementation that is specially tailored for fast operation.
The ALU OP multiplexer in Figure 10 chooses one of the two sets of four ALU OP bits depending upon the state of the Status Flipflop. If status is not relevent to a particular instruction, then both sets of ALU OP bits are the same.

4. Arithmetic Processor Signals Within the Arithmetic Logic Unit Processor the Data Path Control is through the instruction pipeline registors. The following Chip Signals are summarized in Table 7.

4.1 Data Path Control The following are all inputs:

1. Instruction Code S-0 - these signals deter~ine the instruction to be performed. Tables 3, 4, and 5 list the instructions.

2. Serial Input Select 1,0 - these signals select one of four inputs to the LSS ALU Carry circuit in the arithmetic instructions. The inputs are:

Carry right;
Logic 0;
Logic 1;
I Carry flipflop.

These signals also select one of four inputs to the shifter LSS
or MSS in the Shift and Rotate Instructions. The inputs are:

Logic 0;
ALU Right or ALU Left into the ALU path, or MQ Right or MQ
Left into the MQ path;
Carry flipflop;
ALU C Bus.

3. Read Address 5-0 - these signals choose one of 64 inputs to the ALU "A" input as shown on Table 1.

4. Read/Write Address 5-0 - these signals choose one of 64 inputs to the ALU "B" input as shown on Table 1. If a write is performed into the multiport RAM, these inputs also choose the location that is written into.
S. Input/Output Select 1,0 - an input or output in the Arithmetic Processor is chosen from:

Vertical Bus;
Horizontal Bus;
Down Path;
Up Path.

v ~ ~ ~ " -s / J / ~/ ~ L 1.

6. Input/Output Functions 1,0 - the operations of the bus, path, or associated RAM location as chosen by Input/Output Select is:

Output enable (drive the selected bus or path from associated RAM location);

Direct input (enable external bus or path to be used as ALU input)i Load from external (load associated RAM location from selected external bus or path);

Load from internal (load associated RAM location from ALU D 8us).

Selection of the Verti~al 8us with the output enable function produces an output from the row selected by a true signal on its the Horizontal Bus. Selection of the Horizontal Bus with the output enable function produces an output from the column selected by a true signal on its Vertical Bus. Selection of the Up Path or Down Path enables the output regardless of the Input/Output Function.

4.2 Status Control _.
These inputs control loading of the multiport RAM, the status register, and the Sticky Overflow Flipflop. All operations are performed on a cell by cell basis. Storage loading depends upon:
(1) ALUP Enable, (2) the Instruction, (3) Storage Enable, and (4) the ALUP Horizontal Masks. Note that the Zero Flipflop has multiple uses, and is also called the "Zero/Status Flipflop" and the "Status Flipflop".

lo Storage Enable 1,0 - loading of the status flipflops, the sticky overflow flipflop, and the multiport RAM are allowed in the following combinations:

Only the multiport RAM may be loaded;
Only the Status register and the multiport RAM may be loaded;
Only the Status register may be loaded;
All may be loaded.

3L5~ 3 2. Status Dependent Enable 2,1,0 - storage can be conditionally loaded only if the selected cor1dition is satisfied:

Horizontal Bus must be true;
Carry Flipflop must be true;
The Negative Flipflop must be true;
The Zero/Status Flipflop must be true;
Loading occurs;
The Carry Flipflop must be false;
The Negative Flipflop must be false;
The Zero/Status Flipflop must be false.

4.3 Per Cell Signals -l. External Memory - input or tristate output. The pin is an output if Direction is true, otherwise it is an input.

4.4 Per Row Si~nals Outputs are tristate unless noted.

l. ORed Bus Not - inverted two-state output. The signal is the logical NOR of (Data (N) AND Vertical Bus (N)) for all columns.

2. Horizontal Bus - input or output. The signal is the logical OR of (Horizontal Bus Flipflop (N) AND Vertical Bus (N)) for all columns. No more than one Vertical Bus line in an entire row of chips may be asserted at one time~ The Bus is driven only if it is selected by Input/Output Select, the Input/Output function is output enable, and any Vertical Bus line in the chip is true. Data is provided by the Horizontal Bus Register.

3. ALU Left, ALU Right - input and output, or output and input, respectively. The signals are used for shifting operations.

4. MQ Left, MQ Right - input and output, or output and input, respectively. The signals are used for operations that simultaneously shift two words.

~6 C~ 7~

~3 ~

5. Carry Left; Carry Right - output and input, respectively Data flows from right to left to propagate carry through the ALU.

6. Status Left, Status Right - input and output, or output and input, respectively. The signals are used for zero detection by the logic and some of the arithmetic instructions, and are used for special functions, double word shifts, and the Status Broadcast instructions.

7. Loop Left, Loop Right - input and output, or output and input, respectively. The signals are used in many operations to connect the most significant slice to the least significant slice.

4.5__Per Column Signals Summar~

1. Vertical Bus - input or output. The Vertical 3us output is active if it is selected by Input/Output Select, the Input/Output Function is output enable, and the Horizontal Bus is asserted. Data is provided by the Vertical Bus Register.

2&3. Up, Down - may be input and output or output and input, as determined by the ALUP Vertical Mask 0 and 1, the Input/Output Select and the Input/Output Function. The sourc~ of data is chosen by ALUP Vertical Mask 2.

MULTIPORT RAM MEMORY MAP

ADDRESS (hex) R ADDR and R/W ADDR
_____________ ___________________ 0-lF USER GENERAL PURPOSE
MULTIPLIER/QUOTIENT (MQ) 21 MEMORY DATA REGISTER(2 ZERO/STATUS

28 HORIZ BUS DIRECT ACCESS/HORIZONTAL BUS REGISTER (3,4) 29 VERTICAL BUS DIRECT ACCESS/VERTICAL BUS REGISTER (3,5) 2A DOWN PATH DIRECT ACCESS/DOWN BUS REGISTER (3,' 2B UP PATH DIRECT ACCESS/UP BUS REGISTER (3,5) 2F . - UNUSED -TABLE 1, CONT.

MULTIPORT RAM MEMORY MAP
___________________ ____ .
ADDRESS (hex) R ADDR and R/W ADDR
_____________ _____~_____________ ALUP HORIZONTAL MASX

NOTES:
1. BITS 20-21 AND 23-2B HAVE INPUTS IN ADDITION TO THE ALU D BUS.

2. FOR INPUT AND OUTPUT FROM/TO EXTERNAL MEMOR~; MAY BE USED AS A
GENERAL PURPOSE REGISTER.

3. CHOICE OF REGISTER OR DIRECT ACCESS IS MADE BY I/O FUNCTION.

4. THE REGISTER PROVIDES SOURCE OF OUTPUT TO BOTH HORIZONTAL BUS
AND ORed BUS.

5. THE REGISTER PROVIDES SOURCE OF OUTPUT.

'7~
, ALUP VERTICAL MASK FUNCTIONS
__._________________________ MASK CELL INPUT(l~ CELL OUTPUT(1) NOTES

0 0 UP or DOWN pin DOWN or U2 pin Fully Active (3) 0 1 logic 0 DOWN or UP pin Ignore input 1 0 UP or DOWN pin DOWN or UP pin Skip row (2) 1 1 UP or DOWN pin DOWN or UP pin Fully Active (3) FURTHER NOTES:

1. The Interrow Path, consisting of the UP and DOWN pins, is active only if the UP or DOWN bus is selected by I/O
Select. If the I/O Select is UP, then data flows from an UP pin in one row to a DOWN pin in the next row, and the source of data may be the UP Register. If the I/O
Select is DOWN, then data flows from a DOWN pin to an UP pin, and the source of data may be the DOWN Register.

2. UP pin receives DOWN pin signal (UP driver is enabled), or DOWN pin receives UP pin signal (DOWN driver is enabled).

3. Selection of the source to output is made by the Vertical Mask 2: 0 - UP or DOWN flipflop, 1 - ALU D
Bus.

3~

'7~

LOGIC INSTRUCTIONS
___~________________ , MNEMONIC ALU D BUS FUNCTION
ONE ONE
A_XOR_B - A XOR B
ZERO ZERO
A_AND_B A AND B
A_OR_B A OR B
A_XNOR_ B A XNOR B
A_NOR B A NOR 3 A NAND B A NAND B

NOTE: 1. ALU CARRY OUT = 0 FOR THE LOGIC INSTRUCTIONS.

3~

7~

FIXED POINT ARITHMETIC INSTRUCTIONS
_____________________________ _____ .
MNEMONIC FUNCTION
SIMPLE GROUP
~_MINUS_A B MINUS A MINUS 1 PLUS CIN
A_PLUS_CIN A PLUS CIN
A_PLUS_B A PLUS B PLUS CIN
B PLUS_CIN B PLUS CIN
A_MINUS_B A MINUS B MINUS 1 PLUS CIN
A_MINUS 1 A MINUS 1 PLUS CIN
NOT A_PLUS CIN A PLUS CIN
SPECIAL GROUP
MF MULTIPLY FIRST

MI MULTIPLY INTERMEDIATE
.

ML MULTIPLY LAST
DF DIVIDE FIRST
DI DIVIDE INTERMEDIATE
DL DIVIDE LAST

3~

~a 1~5 ~

SHIFT AND STATUS INSTRUCTIONS
_____________ _______________ MNEMONIC FUNCTION
ALSL ARITHMATIC AND LOGICAL
SHIFT LEFT(l) ALSR ARITHMATIC AND LOGICAL
SHIFT RIGHT(2) RL ROTATE LEFT
RR ROTATE RIGHT
DALSL DOUBLE ARITHMATIC AND
LOGICAL
SHIPT LEFT
DALSR DOUBLE ARITHMATIC AND
LOGICAL
SHIFT RIGHT
DRL DOUBLE ROTATE LEFT
DRR DOUBLE ROTATE RIGHT
PL PARITY LEFT
LOR l.OGICAL OR RIGHT
PSWAP PARALLEL SWAP
SSWAP SERIAL SWAP
SBL STATUS BROADCAST LEFT
SBR . STATUS BROADCAST RIGHT
QSL QUADRUPLE SHIFT LEFT
'; QSR QUADRUPLE SHIFT RIGHT

NOTE:
1. LEFT: DATA FLOWS FROM LSS TOWARD MSS, LSS COLUMN < MSS COLUMN
2. RIGHT: DATA FLOWS FROM MSS TOWARD LSS

t- ~r /
. TABLE 6 CONFIGURATION INSTRUCTIONS
_______________ _________.

MNEMONIC FUNCTION

CONFIGURE LOAD MULTIPORT RAM
INDEPENDENT OF
ALUP HORIZONTAL MASKS

7~

CHIP SIGNALS

1. COMMON CONTROL

1. GND, VCC, VDD 3 2. ALUP Clock 30 ALUP Enable 2. MEMORY DATA REGISTER CONTROL

1. Direction 2. Strobe _ _ _ 3. ARITHMETIC PROCESSOR

A. DATA PATH CONTROL

1. Instruction Code 0 - 5 6 7~
TABLE 7, CONT.

2. Serial Input Select 0,1 2 3. Read Address 0 - S 6 4. Read/Write Address 0 5 6 5. Input/Output Select 0,1 2 6. Input/Output Function 0,1 2 B. STATUS CONTROL

1. Storage Enable 0,l 2 2. Status Storage Enable 0,1,2 3 C. PER CELL

Note: For row M, M=0 to R-l, and column N, N=0 to C-l:

1. External Memory M, N 1 .

7~

TABLE 7, CONT.

D. PER ROW

Note: For row M, M=0 to R-l:

1. Not ORed Bus M
2. Horizontal Bus M
3. ALU Left M, ALU Right M 2 4 . MQ Lef t M, MQ Right M 2 5. Carry Left M, Carry Right 2 6. Status Left M, Status Right M 2 7. Loop Left M, Loop Right M 2 CH I P S IGNALS

E. PER COL~MN

Note: For column N, N=0 to C-l:

1. Vertical Bus N
2. t~p N, Down N 2 3~

e-~q~.r~
~ J

TABLE 7, CONT.

SUMMARY:

PINS = COMMON + PER CELL *(ROWS * COLUMNS) + PER ROW *(ROWS) + PER COLUMN *(COLUMNS) = 36 + (R* C) + (12*R) + (3* C) VARIOUS CASES:

R C COMMON CELLS TOTAL

~5,

Claims (16)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In an associative processor array including M rows and N columns of identical processing cells, with each cell connected horizontally to its left and right to a neighboring cell and connected vertically to its up and down to a neigh-boring cell, with a vertical bus connecting all cells in a column and a horizontal bus connecting all cells in a row; each cell including a memory for storing control and data information, with the output of said memory coupled to an arithmetic logic unit (ALU) and with the output of said ALU coupled to register means associated with each cell, with said cells as forming said array capable of performing arithmetic operations on words each consisting of a plurality of bits and each including a given number of slices to enable an arithmetic function to be implemented by each cell, the improvement therewith of apparatus for providing data paths between cells in a given row in said array, comprising:
a first path coupled to each of said cells in said given row and operative to move a first bit from left to right or from right to left in said row with said path coupled to each of said memory means in said cells, a second path coupled to each of said ALUS in said cells in said given row and operative to propagate the arith-metic carry from said ALU of any of said cells to any right or left cell in said row, a third path coupled to each of said cells in said row and operative to move a second bit from one cell to the next in a given selected direction as from right to left or from left to right, and means associated with each cell and responsive to said second bit to store said bit in said cell, a fourth path coupled to each of said cells in said row and operative to move a third bit from said ALU output of each cell from one cell to the next with said means associated with each cell responsive to said third bit for storing said bit in any of said cells, a fifth path coupled to each of said cells in said row and operative to move a fourth bit from one cell to the next in said row from left to right or from right to left, and storage register means associated with each cell for storing said fourth bit in each storage register means in said cell to enable said cell to determine which of said stored bits as said first to fourth are associated with a given slice of said word to enable each cell to perform said arithmetic function according to said bits as stored within said cell.

2. The associative processor array according to claim 1, wherein said first path is designated as the ALU path.

3. The associative processor array according to claim 1, wherein said second path is designated as the Carry path.

4. The associative processor array according to claim 1, wherein said third path is designated as the MQ path (multi-plier/quotient).

5. The associative processor array according to claim 1, wherein said fourth path is designated as the Loop path for providing end-to-end coupling in double word operations.

6. The associative processor according to claim 1, wherein said fifth path is designated as the Status path.

7. The associative processor according to claim 1, wherein said means associated with each cell is a flip-flop having an output coupled to said third bus and an input coupled to said fourth bus.

8. The associative processor according to claim 1, wherein said storage register means is a Status register for receiving and storing said fourth bit for each of said cells used in a word.

9. The associative processor according to claim 1, wherein said given number of slices includes a least significant slice, a most significant slice and an intermediate significant slice.

10. The associative array according to claim 1, wherein said first, third, fourth and fifth paths are coupled to transversal multiplexers associated with each cell in said given row and operative to selectively multiplex data on said paths.

11. The associative array according to claim 1, wherein said memory is a multiport RAM having two outputs A and B, with one output (A) connected to a first input of said ALU and a second output (B) connected to a second input of said ALU.

12. The associative array according to claim 1, wherein said paths as coupled to the left most cell in the top row are connected to the respective right path inputs of the right most cell in the bottom row.

13. The associative array according to claim 10, wherein said multiplexers include means for bypassing said data paths from any selected ones of said cells in said given row.

14. The associative processor according to claim 1, wherein said first, second, third, fourth, and fifth paths are coupled to each cell so that the right side on one cell is coupled via said paths to the left side of a right neighboring cell with the left side of said cell coupled to the right side of a left neighboring cell and so on.

15. The associative processor according to claim 14, wherein the last cell on the right of a row is coupled to the first cell on the left of said row via said paths.

16. The associative processor according to claim 14, wherein the last cell on the right of a row is connected to the first cell on the left of an adjacent row via said paths.