CA1215144A - Circuit pour minimiser les variations de frequence de l'horloge locale lors de l'etablissement d'un asservissement de phase a un circuit d'horloge de reference - Google Patents

Circuit pour minimiser les variations de frequence de l'horloge locale lors de l'etablissement d'un asservissement de phase a un circuit d'horloge de reference

Info

Publication number
CA1215144A
CA1215144A CA000455942A CA455942A CA1215144A CA 1215144 A CA1215144 A CA 1215144A CA 000455942 A CA000455942 A CA 000455942A CA 455942 A CA455942 A CA 455942A CA 1215144 A CA1215144 A CA 1215144A
Authority
CA
Canada
Prior art keywords
signal
circuit
response
signals
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000455942A
Other languages
English (en)
Inventor
Max S. Macrander
Robert C. Mclaughlin
Ivan L. Edwards
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GTE Communication Systems Corp
Original Assignee
GTE Communication Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GTE Communication Systems Corp filed Critical GTE Communication Systems Corp
Application granted granted Critical
Publication of CA1215144A publication Critical patent/CA1215144A/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
CA000455942A 1983-06-23 1984-06-05 Circuit pour minimiser les variations de frequence de l'horloge locale lors de l'etablissement d'un asservissement de phase a un circuit d'horloge de reference Expired CA1215144A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/507,436 US4510462A (en) 1983-06-23 1983-06-23 Circuit to minimize local clock frequency disturbances when phase locking to a reference clock circuit
US507,436 1983-06-23

Publications (1)

Publication Number Publication Date
CA1215144A true CA1215144A (fr) 1986-12-09

Family

ID=24018642

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000455942A Expired CA1215144A (fr) 1983-06-23 1984-06-05 Circuit pour minimiser les variations de frequence de l'horloge locale lors de l'etablissement d'un asservissement de phase a un circuit d'horloge de reference

Country Status (4)

Country Link
US (1) US4510462A (fr)
BE (1) BE899990A (fr)
CA (1) CA1215144A (fr)
IT (1) IT1175525B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4628461A (en) * 1984-04-30 1986-12-09 Advanced Micro Devices, Inc. Phase detector
US5581699A (en) 1995-05-15 1996-12-03 International Business Machines Corporation System and method for testing a clock signal
US6154508A (en) * 1998-03-23 2000-11-28 Vlsi Technology, Inc. Method and system for rapidly achieving synchronization between digital communications systems

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151485A (en) * 1977-11-21 1979-04-24 Rockwell International Corporation Digital clock recovery circuit
US4305045A (en) * 1979-11-14 1981-12-08 Bell Telephone Laboratories, Incorporated Phase locked loop clock synchronizing circuit with programmable controller
DE3025358A1 (de) * 1980-07-04 1982-01-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Regelsystem zum einstellen einer physikalischen groesse

Also Published As

Publication number Publication date
US4510462A (en) 1985-04-09
BE899990A (fr) 1984-10-15
IT1175525B (it) 1987-07-01
IT8421506A0 (it) 1984-06-20

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Legal Events

Date Code Title Description
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