CA1214282A - Low leakage cmos d/a converter - Google Patents
Low leakage cmos d/a converterInfo
- Publication number
- CA1214282A CA1214282A CA000434742A CA434742A CA1214282A CA 1214282 A CA1214282 A CA 1214282A CA 000434742 A CA000434742 A CA 000434742A CA 434742 A CA434742 A CA 434742A CA 1214282 A CA1214282 A CA 1214282A
- Authority
- CA
- Canada
- Prior art keywords
- converter
- well
- output lines
- negative
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A CMOS DAC with means to avoid leakage current. In one embodiment, the back gates of the CMOS switches are held at -200mV with respect to the output lines, and the logic low level to the off switch also is set at -200mV relative to the output lines. In another embodiment, the CMOS switches are ion-implanted. In a still further embodiment, the output lines are held at a potential 200mV more positive than the P- well of the CMOS switches.
A CMOS DAC with means to avoid leakage current. In one embodiment, the back gates of the CMOS switches are held at -200mV with respect to the output lines, and the logic low level to the off switch also is set at -200mV relative to the output lines. In another embodiment, the CMOS switches are ion-implanted. In a still further embodiment, the output lines are held at a potential 200mV more positive than the P- well of the CMOS switches.
Description
~Z~4'~8Z
BACKGROUND OF THE INVENTION
( ..
Field of the Invent lion This invention relates to digital-to-analog converters of the CMOS typo More particularly, this invention relates to minimizing leakage current in such converters.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURES 1-4 are circuit diagrams showing conventional CMOS DAY circuit configurations;
FIGURE 5 illustrates schematically the arrangement of . CMOS switches in a diffused integrated circuit chip;
FIGURE 6 is a circuit diagram illustrating one pro-furred embodiment of the present invention;
,.
FIGURE 7 is a circuit diagram showing one arrangement for developing a bias voltage for the embodiment of Figure 6;
FIGURE 8 is an equivalent circuit corresponding to Figure 7;
FIGURE 3 is a schematic illustration of an integrated circuit implementation of the Figure 7 bias voltage circuit and FIGURE 10 is a block diagram showing another implement station providing features of the invention.
Description of the Prior Art CMOS D/A converters have been available commercially for quite some time, and provide important advantageous features.
Referring now to Figure 1, conventional converters of the CMOS
type include a thin-film R-2R ladder network 10 the shunt nests-ions of which are connected to N- channel CMOS switch-pairs AHAB; AHAB; etc. The individual switches of each pair are come elementarily driven so that one switch is off while the other is on, and vice versa. The switches typically have a voltage across them of 10 my for a 10V reference voltage and a 10kJL- 20kQ ladder network, There are three commonly-used configurations of convent tonal CMOS D/A converters. In order to explain leakage current, each one of these configurations will be examined separately.
Referring first to Figure 2, the converter shown there comprises three separate lines for It'll r Iota ( ground). The ladder termination resistor 16 is tied to AND.
When an all zero's code is applied to the converter, all of tune current in the R-2R ladder 10 (except for the one bit of current flowing through the ladder termination resistor to AND) is steered to the Iota terminal. Ideally no current should under these conditions flow to the It'll terminal. However, in pray-lice a finite current does flow in the It'll terminal and is Nina as the leakage current.
When an all ones code is applied to the converter of Figure 2, all of the current in the R-2R ladder (except, again, ill for the one bit of current through the ladder termination resistor to AND) is steered to the It'll terminal. Any current flowing in the Iota terminal is defined as leakage current Referring now to Figure 3, again there are three sepal Out' Iota and AND. The ladder termination resistor 16 now is tied to Iota. When an all zero's code is applied to the D/A converter all of the current in the R-2R
ladder is steered to the Iota terminal, and any current flowing in the It'll terminal is defined as leakage current.
When an all one's code is applied to the converter of Figure 3, all of the current in the OR ladder (except for the one bit of current flowing through the ladler termination resistor to Iota) is steered to the It'll terminal. Because of this one bit of current flowing along the Iota line, it is not possible to measure leakage current. Hence, leakage current is only defined (- 25 along the It'll line for an input code of all zeros.
- ~z~z~æ
Referring now to Figure 4, there is an Tout line end ( an AND line, where AND incorporates AND and Iota of Figures
BACKGROUND OF THE INVENTION
( ..
Field of the Invent lion This invention relates to digital-to-analog converters of the CMOS typo More particularly, this invention relates to minimizing leakage current in such converters.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGURES 1-4 are circuit diagrams showing conventional CMOS DAY circuit configurations;
FIGURE 5 illustrates schematically the arrangement of . CMOS switches in a diffused integrated circuit chip;
FIGURE 6 is a circuit diagram illustrating one pro-furred embodiment of the present invention;
,.
FIGURE 7 is a circuit diagram showing one arrangement for developing a bias voltage for the embodiment of Figure 6;
FIGURE 8 is an equivalent circuit corresponding to Figure 7;
FIGURE 3 is a schematic illustration of an integrated circuit implementation of the Figure 7 bias voltage circuit and FIGURE 10 is a block diagram showing another implement station providing features of the invention.
Description of the Prior Art CMOS D/A converters have been available commercially for quite some time, and provide important advantageous features.
Referring now to Figure 1, conventional converters of the CMOS
type include a thin-film R-2R ladder network 10 the shunt nests-ions of which are connected to N- channel CMOS switch-pairs AHAB; AHAB; etc. The individual switches of each pair are come elementarily driven so that one switch is off while the other is on, and vice versa. The switches typically have a voltage across them of 10 my for a 10V reference voltage and a 10kJL- 20kQ ladder network, There are three commonly-used configurations of convent tonal CMOS D/A converters. In order to explain leakage current, each one of these configurations will be examined separately.
Referring first to Figure 2, the converter shown there comprises three separate lines for It'll r Iota ( ground). The ladder termination resistor 16 is tied to AND.
When an all zero's code is applied to the converter, all of tune current in the R-2R ladder 10 (except for the one bit of current flowing through the ladder termination resistor to AND) is steered to the Iota terminal. Ideally no current should under these conditions flow to the It'll terminal. However, in pray-lice a finite current does flow in the It'll terminal and is Nina as the leakage current.
When an all ones code is applied to the converter of Figure 2, all of the current in the R-2R ladder (except, again, ill for the one bit of current through the ladder termination resistor to AND) is steered to the It'll terminal. Any current flowing in the Iota terminal is defined as leakage current Referring now to Figure 3, again there are three sepal Out' Iota and AND. The ladder termination resistor 16 now is tied to Iota. When an all zero's code is applied to the D/A converter all of the current in the R-2R
ladder is steered to the Iota terminal, and any current flowing in the It'll terminal is defined as leakage current.
When an all one's code is applied to the converter of Figure 3, all of the current in the OR ladder (except for the one bit of current flowing through the ladler termination resistor to Iota) is steered to the It'll terminal. Because of this one bit of current flowing along the Iota line, it is not possible to measure leakage current. Hence, leakage current is only defined (- 25 along the It'll line for an input code of all zeros.
- ~z~z~æ
Referring now to Figure 4, there is an Tout line end ( an AND line, where AND incorporates AND and Iota of Figures
2 and 3. The ladder termination resistor 16 is tied to AND.
When an all zeros code is applied to the D/A converter, all true current in the R`2R ladder is steered to the AND terminal. Any current flowing in the Tout line is defined as leakage current.
Leakage current, as defined above for the circuit configurations of Figures 2 through 4, causes errors in the D/A
transfer characteristic, particularly at temperatures greater than 100C where the effect is most pronounced. Thus it is desired to reduce such errors.
.
The leakage currents described above actually comprise two separate components which arise for different reasons. To explain this reference is made to Figure 5 which shows somewhat schematically the IT structural arrangement of the switches AHAB
, for a conventional CMOS DAY. The N- substrate 20 normally is at the most positive supply voltage (TV to vow The P- well 22 is at zero potential (ground). leakage current in such a structure comprises the following two components:
(a) Sub threshold leakage current from the R-2R
ladder across the "off" switch to It'll or Ire, depending on along which line the leakage current is being measured. This is shown as If I
(b) Collector-emitter leakage current of the substrate NUN bipolar transistor with grounded base. Tune transistor is formed by a reverse-biased diode from the N-substrate collector) to the P- well (base), and a diode from the P- well (base) to tune No source diffusion (emitter). The N+ source diffusion (emitter) referred to is either to It'll or Iota, depending on along which line the leakage current is being measured. This is shown as It.
This invention is directed to means and techniques for eliminating or significantly minimizing the leakage currents de-scribed above.
SUMMARY OF THE INVENTION
It has been found that if, in the Figure S arrangement, the P- well 22 is biased negative (e.g. to about 200mV) with respect to the It'll and Iota terminals, the bipolar transistor leakage currents (It) flowing into the Tout lines are virtually eliminated. The sub threshold leakage current (If) also is - simultaneously reduced slightly because the negative bias on the P- well effectively increases the threshold voltage of the N-channel switches.
It further has been found that sub threshold leakage current (If) is eliminated if the logic low drive to the switches f AHAB is biased negative, e.g. by reducing the "off" gate voltage from OX to -200mV.
I
DISCUSSION OF PREFERRED EMBODIi~MTS
Referring now to Figure 6, showing one preferrer eye-immunity of the invention, the N- channel switches AYE and one switch drivers 30, 32 are placed in a common P- well generally indicated at 34 (e.g. corresponding to P- well 22 in Figure 5).
This common P- well is maintained at a negative potential of -200mV, as by means of a bias voltage source 36 connected to the well terminal 38, and forming part of the same IT chip.
An exemplary circuit for the bias voltage source 36 is shown in Figure 7. A negative supply voltage Us is applied across a resistor R3 in series with a regulating diode Do, pro-during a regulated voltage ED ox about -700 my. This voltage is divided by resistors Al and R2 to provide the -200mV bias vow t g ( TUB) lo The actual bias voltage selected will represent a come promise between too high a voltage which will increase the N+
source diffusion to P- well leakage and on-switch resistance (producing a gain error, and too low a voltage which will be insufficient both to stop the leakage current crossing the N+ -P- boundary and to turn off the sub threshold leakage current from source to drain. Present indications are that the lower limit of the bias voltage is about -150mV. Theupperlimit is not so definite, but preferably is in the range of about -300mV to -500mV.
The value of resistors Al and R2 should be selected so as to avoid any problems caused by transient currents (ITRANS) through the switch drivers. To illustrate the relationships involved, the following somewhat simplified analysis is presented:
~2~28Z
TRAYS I 1 = TUB
1 = TUB
1 2/Rl ED
2 = D - 1 Al TUB
ED = 0.7V V = 0.2V
R2 = 2.5Rl Let Al = RX R2 2.5RX
The equivalent circuit seen looking from the well into the r Figure 7 circuit is shown in Figure 8. In order that the tub potential not rise above OX at the time of switching, the voltage drop across the equivalent internal resistor 0.71g RX must be less than, or equal to, 0.2V.
i.e. ITRA~S x 0.714RX ova-X I- x 0.714 Assuming that the transient current is loam -0.2 -2 0.714 x 1 Rex 28 n ( . .. Al = 28n R2 = 70n The value o, R3 is chosen to assure that there is always a forward biasing current through the diode Do.
, . .
A more analytical approach to calculating component values would take into account variation of diode voltage With temperature, plus resistor variations with temperature (whether thin-film or diffused).
Figure 9 shows a suggested integrated circuit implement station of the circuit of Figure 7. The P- well 40 which normally contains the digital logic (not the well for the switch drivers 30, 32 and switches AHAB) is enlarged to provide a ground tub extent soon 42 to allow room for the P- - N+ diode Do plus a diffused N+ resistor 44u The series combination of Al and R2, 93 inn all, is divided in two, with 50~ in the digital ground tub 42, and Cowan a separate P- well 46. The reason for splitting the resistors between separate tubs is to avoid any more than 0.35V
forward bias across P- - N+ junctions, thereby ensuring all , parasitic diodes are turned off.
As the circuit is shown, R3 is external to the package.
It could also be included on-chip in the form of a thin-film resistor, its value depending on the voltage to be put on the CONTROL P
It will be noted that in the Figures 6 and 9 embodiment, both forms of leakage (If and It) are eliminated simultaneously, but the effect of transient currents in the switch drivers must be taken into account. To avoid such transient current effect, the N- channel switches AHAB, etc., may alternatively have their thresholds increased by ion-implantation, with only the back-gates of the switches being biased negative (as by -200mV). The P- well containing the N- channel switches would in such a modified arrange-mint be separated from that containing the switch drivers 30, 32 which can be placed in the grounded P- well 42 used by the digital logic. The bipolar transistor leakage current is as before elm-inated by the -200mV bias of the back gates. The sub threshold leakage current is eliminated by the ion-implanting of the N-channel switches.
The circuit of Figure 7 can be used for generating the -200mV bias for the P well containing the N- channel switches.
In this case, the equivalent resistance seen looking from the P- well is not critical since there will be no current flowing from the well. The biasing circuit can easily be integrated onto the D/A converter. Resistors Al, R2 and R3 could be thin-film and, as before, an external control voltage is required 'to bias this circuit into operation.
Still another embodiment of the invention is shown in Figure 10. This arrangement includes a conventional CMOS
Out and Iota both offset in a positive direct lion with respect to DGND and AND (zero volts). Illustratively, such offset is produced by connecting a positive bias voltage source 52 (e.g. 200mV) to the positive terminal of the output op-amp 54. The output of the ox amp is connected to the feed-back resistor RF/B terminal which, in conventional DAY con fig-unctions, leads to an on-board feedback resistor in the DAY
structure (as in Figure 6).
'J, 'I, I f, The Figure 10 configuration eliminates bipolartransis'Lor ; leakage current, and somewhat reduces sub threshold leakage current as a result of the effective increase in N- channel threshold voltage. The ladder termination resistor (not shown in Figure 10) must be connected to Iota Connecting the ladder termination resistor to AND would cause D/A con-venter non-linearity.
Although several preferred embodiments of the invent lion have been disclosed herein in detail, it is to be under-stood that this is for the purpose of illustrating the invention, and should not be construed as necessarily limiting the scope of the invention, since it is apparent that many changes can be made by those skilled in the art while still practicing the invention claimed herein.
When an all zeros code is applied to the D/A converter, all true current in the R`2R ladder is steered to the AND terminal. Any current flowing in the Tout line is defined as leakage current.
Leakage current, as defined above for the circuit configurations of Figures 2 through 4, causes errors in the D/A
transfer characteristic, particularly at temperatures greater than 100C where the effect is most pronounced. Thus it is desired to reduce such errors.
.
The leakage currents described above actually comprise two separate components which arise for different reasons. To explain this reference is made to Figure 5 which shows somewhat schematically the IT structural arrangement of the switches AHAB
, for a conventional CMOS DAY. The N- substrate 20 normally is at the most positive supply voltage (TV to vow The P- well 22 is at zero potential (ground). leakage current in such a structure comprises the following two components:
(a) Sub threshold leakage current from the R-2R
ladder across the "off" switch to It'll or Ire, depending on along which line the leakage current is being measured. This is shown as If I
(b) Collector-emitter leakage current of the substrate NUN bipolar transistor with grounded base. Tune transistor is formed by a reverse-biased diode from the N-substrate collector) to the P- well (base), and a diode from the P- well (base) to tune No source diffusion (emitter). The N+ source diffusion (emitter) referred to is either to It'll or Iota, depending on along which line the leakage current is being measured. This is shown as It.
This invention is directed to means and techniques for eliminating or significantly minimizing the leakage currents de-scribed above.
SUMMARY OF THE INVENTION
It has been found that if, in the Figure S arrangement, the P- well 22 is biased negative (e.g. to about 200mV) with respect to the It'll and Iota terminals, the bipolar transistor leakage currents (It) flowing into the Tout lines are virtually eliminated. The sub threshold leakage current (If) also is - simultaneously reduced slightly because the negative bias on the P- well effectively increases the threshold voltage of the N-channel switches.
It further has been found that sub threshold leakage current (If) is eliminated if the logic low drive to the switches f AHAB is biased negative, e.g. by reducing the "off" gate voltage from OX to -200mV.
I
DISCUSSION OF PREFERRED EMBODIi~MTS
Referring now to Figure 6, showing one preferrer eye-immunity of the invention, the N- channel switches AYE and one switch drivers 30, 32 are placed in a common P- well generally indicated at 34 (e.g. corresponding to P- well 22 in Figure 5).
This common P- well is maintained at a negative potential of -200mV, as by means of a bias voltage source 36 connected to the well terminal 38, and forming part of the same IT chip.
An exemplary circuit for the bias voltage source 36 is shown in Figure 7. A negative supply voltage Us is applied across a resistor R3 in series with a regulating diode Do, pro-during a regulated voltage ED ox about -700 my. This voltage is divided by resistors Al and R2 to provide the -200mV bias vow t g ( TUB) lo The actual bias voltage selected will represent a come promise between too high a voltage which will increase the N+
source diffusion to P- well leakage and on-switch resistance (producing a gain error, and too low a voltage which will be insufficient both to stop the leakage current crossing the N+ -P- boundary and to turn off the sub threshold leakage current from source to drain. Present indications are that the lower limit of the bias voltage is about -150mV. Theupperlimit is not so definite, but preferably is in the range of about -300mV to -500mV.
The value of resistors Al and R2 should be selected so as to avoid any problems caused by transient currents (ITRANS) through the switch drivers. To illustrate the relationships involved, the following somewhat simplified analysis is presented:
~2~28Z
TRAYS I 1 = TUB
1 = TUB
1 2/Rl ED
2 = D - 1 Al TUB
ED = 0.7V V = 0.2V
R2 = 2.5Rl Let Al = RX R2 2.5RX
The equivalent circuit seen looking from the well into the r Figure 7 circuit is shown in Figure 8. In order that the tub potential not rise above OX at the time of switching, the voltage drop across the equivalent internal resistor 0.71g RX must be less than, or equal to, 0.2V.
i.e. ITRA~S x 0.714RX ova-X I- x 0.714 Assuming that the transient current is loam -0.2 -2 0.714 x 1 Rex 28 n ( . .. Al = 28n R2 = 70n The value o, R3 is chosen to assure that there is always a forward biasing current through the diode Do.
, . .
A more analytical approach to calculating component values would take into account variation of diode voltage With temperature, plus resistor variations with temperature (whether thin-film or diffused).
Figure 9 shows a suggested integrated circuit implement station of the circuit of Figure 7. The P- well 40 which normally contains the digital logic (not the well for the switch drivers 30, 32 and switches AHAB) is enlarged to provide a ground tub extent soon 42 to allow room for the P- - N+ diode Do plus a diffused N+ resistor 44u The series combination of Al and R2, 93 inn all, is divided in two, with 50~ in the digital ground tub 42, and Cowan a separate P- well 46. The reason for splitting the resistors between separate tubs is to avoid any more than 0.35V
forward bias across P- - N+ junctions, thereby ensuring all , parasitic diodes are turned off.
As the circuit is shown, R3 is external to the package.
It could also be included on-chip in the form of a thin-film resistor, its value depending on the voltage to be put on the CONTROL P
It will be noted that in the Figures 6 and 9 embodiment, both forms of leakage (If and It) are eliminated simultaneously, but the effect of transient currents in the switch drivers must be taken into account. To avoid such transient current effect, the N- channel switches AHAB, etc., may alternatively have their thresholds increased by ion-implantation, with only the back-gates of the switches being biased negative (as by -200mV). The P- well containing the N- channel switches would in such a modified arrange-mint be separated from that containing the switch drivers 30, 32 which can be placed in the grounded P- well 42 used by the digital logic. The bipolar transistor leakage current is as before elm-inated by the -200mV bias of the back gates. The sub threshold leakage current is eliminated by the ion-implanting of the N-channel switches.
The circuit of Figure 7 can be used for generating the -200mV bias for the P well containing the N- channel switches.
In this case, the equivalent resistance seen looking from the P- well is not critical since there will be no current flowing from the well. The biasing circuit can easily be integrated onto the D/A converter. Resistors Al, R2 and R3 could be thin-film and, as before, an external control voltage is required 'to bias this circuit into operation.
Still another embodiment of the invention is shown in Figure 10. This arrangement includes a conventional CMOS
Out and Iota both offset in a positive direct lion with respect to DGND and AND (zero volts). Illustratively, such offset is produced by connecting a positive bias voltage source 52 (e.g. 200mV) to the positive terminal of the output op-amp 54. The output of the ox amp is connected to the feed-back resistor RF/B terminal which, in conventional DAY con fig-unctions, leads to an on-board feedback resistor in the DAY
structure (as in Figure 6).
'J, 'I, I f, The Figure 10 configuration eliminates bipolartransis'Lor ; leakage current, and somewhat reduces sub threshold leakage current as a result of the effective increase in N- channel threshold voltage. The ladder termination resistor (not shown in Figure 10) must be connected to Iota Connecting the ladder termination resistor to AND would cause D/A con-venter non-linearity.
Although several preferred embodiments of the invent lion have been disclosed herein in detail, it is to be under-stood that this is for the purpose of illustrating the invention, and should not be construed as necessarily limiting the scope of the invention, since it is apparent that many changes can be made by those skilled in the art while still practicing the invention claimed herein.
Claims (15)
1. In a CMOS digital-to-analog converter comprising at least one switch-pair in a common well, the individual switches of such pair being complementarily driven to "on"
and "off" condition respectively to switch a corresponding resistance network terminal to one or the other of a pair-of output lines in accordance with the state of an input bit, each switch having a driving gate and a back gate;
that improvement in such a converter for reducing leakage current comprising:
bias means to develop a predetermined potential difference between said output lines and said well with said well being more negative than said output lines, thereby to avoid bipolar leakage current.
and "off" condition respectively to switch a corresponding resistance network terminal to one or the other of a pair-of output lines in accordance with the state of an input bit, each switch having a driving gate and a back gate;
that improvement in such a converter for reducing leakage current comprising:
bias means to develop a predetermined potential difference between said output lines and said well with said well being more negative than said output lines, thereby to avoid bipolar leakage current.
2. A converter as claimed in Claim 1, wherein said bias means is operable to bias said well negative with respect to ground, thereby to bias the switch back gates correspondingly.
3. A converter as claimed in Claim 1, wherein said potential difference is in the range of about 150mV to 500mV.
4. A converter as claimed in Claim 3, wherein said potential difference is about 200mV.
5. A converter as claimed in Claim 2, including means to drive the off gate voltage negative with respect to said output lines.
6. A converter as claimed in Claim 5, where the off gate voltage is in the range of about 150mV to 500mV negative with respect to said output lines.
7. A converter as claimed in Claim 6, where said off gate voltage is about 200mV negative with respect to said output lines.
8. A converter as claimed in Claim 2, wherein said negatively-biased well includes the 'witch drivers for said switches.
9. A converter as claimed in Claim 8, including a second well forming a diode for developing the bias voltage.
10. A converter as claimed in Claim 9, including either diffused resistors on said second well or thin-film resistors for scaling down the diode voltage to the proper level.
11. A converter as claimed in Claim 2, wherein said switches are ion-implanted to avoid subthreshold leakage current.
12. A converter as claimed in Claim 1, including output op amp means connected to said output lines respectively; and a positive bias voltage source connected to said op-amp means to produce said potential difference.
13. A converter as claimed in Claim 12, wherein said op-amp means comprises an op amp with its input terminals connected to said output lines respectively;
a negative feedback resistor connected between the op-amp output and its negative input terminal;
said positive bias voltage source being connected to the positive input of said op amp.
a negative feedback resistor connected between the op-amp output and its negative input terminal;
said positive bias voltage source being connected to the positive input of said op amp.
14. A converter as claimed in Claim 13, wherein the bias voltage is in the range of about 150mV to 500mV.
15. A converter as claimed in Claim 1, wherein said common well is P-type in an N-type substrate;
said output lines being connected to an N-type region within said common well.
said output lines being connected to an N-type region within said common well.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US41431782A | 1982-09-02 | 1982-09-02 | |
| US414,317 | 1982-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1214282A true CA1214282A (en) | 1986-11-18 |
Family
ID=23640939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000434742A Expired CA1214282A (en) | 1982-09-02 | 1983-08-17 | Low leakage cmos d/a converter |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS5964919A (en) |
| CA (1) | CA1214282A (en) |
| DE (1) | DE3331180A1 (en) |
| FR (1) | FR2532800B1 (en) |
| GB (1) | GB2126814B (en) |
| NL (1) | NL8303052A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018045298A1 (en) * | 2016-09-01 | 2018-03-08 | Analog Devices, Inc. | Low capacitance switch for pga or pgia |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3665460A (en) * | 1968-09-26 | 1972-05-23 | Tokyo Shibaura Electric Co | Decoding system |
| US3932863A (en) * | 1971-12-13 | 1976-01-13 | Analog Devices, Inc. | Digital-to-analog converters |
| US4092639A (en) * | 1976-01-06 | 1978-05-30 | Precision Monolithics, Inc. | Digital to analog converter with complementary true current outputs |
| JPS55163914A (en) * | 1979-06-07 | 1980-12-20 | Nec Corp | Digital-analog converter |
-
1983
- 1983-08-17 CA CA000434742A patent/CA1214282A/en not_active Expired
- 1983-08-30 DE DE3331180A patent/DE3331180A1/en active Granted
- 1983-09-01 NL NL8303052A patent/NL8303052A/en not_active Application Discontinuation
- 1983-09-02 JP JP58160571A patent/JPS5964919A/en active Pending
- 1983-09-02 FR FR8314118A patent/FR2532800B1/en not_active Expired
- 1983-09-02 GB GB08323622A patent/GB2126814B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3331180C2 (en) | 1991-10-31 |
| FR2532800A1 (en) | 1984-03-09 |
| NL8303052A (en) | 1984-04-02 |
| GB2126814B (en) | 1986-03-19 |
| GB8323622D0 (en) | 1983-10-05 |
| JPS5964919A (en) | 1984-04-13 |
| DE3331180A1 (en) | 1984-03-08 |
| FR2532800B1 (en) | 1988-12-02 |
| GB2126814A (en) | 1984-03-28 |
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