CA1213072A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- CA1213072A CA1213072A CA000439317A CA439317A CA1213072A CA 1213072 A CA1213072 A CA 1213072A CA 000439317 A CA000439317 A CA 000439317A CA 439317 A CA439317 A CA 439317A CA 1213072 A CA1213072 A CA 1213072A
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- glass
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Abstract
ABSTRACT OF THE DISCLOSURE
A composite 24 is characterized by metal or alloy component 26 having a thin interface layer 28 on a surface 30 thereof. Another metal or alloy component 32 has a thin interface layer 34 on its surface 36. A glass 38, having a closely matched coefficient of thermal expansion to the metal or alloy components 26 and 32, bonds the thin inter-face layers 28 and 34 and electrically insulates the first component from the second component whereby thermal stress between the metal or alloy compon-ents and the glass is substantially eliminated.
A composite 24 is characterized by metal or alloy component 26 having a thin interface layer 28 on a surface 30 thereof. Another metal or alloy component 32 has a thin interface layer 34 on its surface 36. A glass 38, having a closely matched coefficient of thermal expansion to the metal or alloy components 26 and 32, bonds the thin inter-face layers 28 and 34 and electrically insulates the first component from the second component whereby thermal stress between the metal or alloy compon-ents and the glass is substantially eliminated.
Description
~. ~
IMPROVED _RINTED CIRCUIT_BOARD
WhIle the inventlon is sub~ect to a wide range of appllcations, it is especlal~y suited for use in pr~nted circuit board appllcatlons and wlll be part~c~larly described in that connectlon.
The pr~nted circuit industry produces most prin~ed circuits by adher~ng one or more layers of copper fo~l to organlc materials such as glass fiber re~n~orced epoxy, phenolic laminated paper, polyester 1~ fi~ms, polylmide ~ilms, etc. Although widely used, t~ese ~tructures haYe certain de~icienci es . F ! rstly, tne~r ma~imum operating tem~erature is restr~cted by the ma~imum temperature tolerance of the organic substrate used. Secondly, a substan~al mismatch 15 usually e~ists between the coefflcient of the~al e~pansion o~ the organic substrate and that of the copper foil, that o~ the solder compositions normall~
used to attach components to the circui~ry and that of the components themselves. The coefficient of therm21 20 .expan~ion of the org~nic materials is normally sub-starlt~ally greater than tha.t of the copper ~oi~ 9 the solder or the components being attached to the circuit.
This mismatch results in substantial '7thermal stresses"
whenever the finished product is thermally cycled.
These stresses create a Yariety of failure modes, such as ~enslle failure of the copper foi', failure cf the solder attachment of components to the circuit and tensile failure of the ~omponents themselves.
To alleviate some of the problems associated with 3a thermzl stress, the industry uses two distlnct ty~es of metal core ~oards. One is an epoxy or other organic insulat~on over the metal core (either steel or aluminum~, and the other is porcelain enamel ed s~e~l.
The mo~t popular is the metal core-orgznic ~.ype.
35 Typlcally, the metal core, such as . 050" ' h~ck a'~Lmin~, is drill ed with oYersi zed holes. As ~he core is coated ~2~
IMPROVED _RINTED CIRCUIT_BOARD
WhIle the inventlon is sub~ect to a wide range of appllcations, it is especlal~y suited for use in pr~nted circuit board appllcatlons and wlll be part~c~larly described in that connectlon.
The pr~nted circuit industry produces most prin~ed circuits by adher~ng one or more layers of copper fo~l to organlc materials such as glass fiber re~n~orced epoxy, phenolic laminated paper, polyester 1~ fi~ms, polylmide ~ilms, etc. Although widely used, t~ese ~tructures haYe certain de~icienci es . F ! rstly, tne~r ma~imum operating tem~erature is restr~cted by the ma~imum temperature tolerance of the organic substrate used. Secondly, a substan~al mismatch 15 usually e~ists between the coefflcient of the~al e~pansion o~ the organic substrate and that of the copper foil, that o~ the solder compositions normall~
used to attach components to the circui~ry and that of the components themselves. The coefficient of therm21 20 .expan~ion of the org~nic materials is normally sub-starlt~ally greater than tha.t of the copper ~oi~ 9 the solder or the components being attached to the circuit.
This mismatch results in substantial '7thermal stresses"
whenever the finished product is thermally cycled.
These stresses create a Yariety of failure modes, such as ~enslle failure of the copper foi', failure cf the solder attachment of components to the circuit and tensile failure of the ~omponents themselves.
To alleviate some of the problems associated with 3a thermzl stress, the industry uses two distlnct ty~es of metal core ~oards. One is an epoxy or other organic insulat~on over the metal core (either steel or aluminum~, and the other is porcelain enamel ed s~e~l.
The mo~t popular is the metal core-orgznic ~.ype.
35 Typlcally, the metal core, such as . 050" ' h~ck a'~Lmin~, is drill ed with oYersi zed holes. As ~he core is coated ~2~
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w~th epoxy, the holes are ~illed with the epoxy. Copper foil is then bonded to one or both surfaces o~ the core.
The holes are redr~lled to a desired slze and a liner of t'le epo~ (or other organic~ ls left in each hole. The ~inished metal core board compares to and may be processed as a standard plastic board. This may include electroless depos-ftion of copper ~n the holes to provlde current paths from top to bottom3 et~. Better heat disslpat~on is provided by the metal core board as compared to the glass fiber reinforced epo~y type boards wi~h rather poor thermal conductlYity.
The second type o~ board, porcelain en~meled steel, is considered either a metal core board or a metal clad board depending on the term~nology. Flrst, porcelaln enamel ~essentially a glas~y material) is ap~lied to a sheet o-f steel. A circult pat~ern is screen printed on the surface o~ the porcelain en2mel with one of the thic~ lllm "conducti~e inks" and the board is refired to crea~e a ~ontlnuous pattern of metall~c conductiYe elements. Through-holes cannot be used due to problems with short c~rcuiting and, therefore, multi-layer boards are not manufactured fn this manner. The porcelain (glass) ls rather thick and its thermal conductivity is relatlYely poor; in fact, it is even ?5 poorer than the therma~ conductiYlty o~ plastics used in plastic boards o, as a coating in met~l core boards described abo~e. It follows that the heat dissipation characteristics of the porcelai~ board are poor.
Conducti~e in~ technology usually requires ~ultiple applications of the conductive ink to DUi ld a conductor p~ttern which is thick enough to carry a desired electr~c current. The multiple sc-eenln~ and firing operat~ons u~ed ln applying th~ conductiYe ink tend to be reia~lvely complicated and ex?ensive.
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w~th epoxy, the holes are ~illed with the epoxy. Copper foil is then bonded to one or both surfaces o~ the core.
The holes are redr~lled to a desired slze and a liner of t'le epo~ (or other organic~ ls left in each hole. The ~inished metal core board compares to and may be processed as a standard plastic board. This may include electroless depos-ftion of copper ~n the holes to provlde current paths from top to bottom3 et~. Better heat disslpat~on is provided by the metal core board as compared to the glass fiber reinforced epo~y type boards wi~h rather poor thermal conductlYity.
The second type o~ board, porcelain en~meled steel, is considered either a metal core board or a metal clad board depending on the term~nology. Flrst, porcelaln enamel ~essentially a glas~y material) is ap~lied to a sheet o-f steel. A circult pat~ern is screen printed on the surface o~ the porcelain en2mel with one of the thic~ lllm "conducti~e inks" and the board is refired to crea~e a ~ontlnuous pattern of metall~c conductiYe elements. Through-holes cannot be used due to problems with short c~rcuiting and, therefore, multi-layer boards are not manufactured fn this manner. The porcelain (glass) ls rather thick and its thermal conductivity is relatlYely poor; in fact, it is even ?5 poorer than the therma~ conductiYlty o~ plastics used in plastic boards o, as a coating in met~l core boards described abo~e. It follows that the heat dissipation characteristics of the porcelai~ board are poor.
Conducti~e in~ technology usually requires ~ultiple applications of the conductive ink to DUi ld a conductor p~ttern which is thick enough to carry a desired electr~c current. The multiple sc-eenln~ and firing operat~ons u~ed ln applying th~ conductiYe ink tend to be reia~lvely complicated and ex?ensive.
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Pr~sently, ther is an ~ncrease ln the clrcuit dens~t~ Or printed c$rcu~t boards. This creates a need for narrower and mor~ closely spaced ~7wires~
or llnes on the printed clrcuit board. The minimum line wldth generated by the state o~ the art conductive lnk technology is l~mlted by the printing process ~or applylng the conductiYe in~. Also, the final conductiYe ~k CgenerallY elther copper- or sil~er-) porcelain-steel product ~requently has problems rela~ing to the metalllzed pattern. The pattern may ha~e a substantially dlfferent Chigher) coeff~cient oP therm~l expansion than the steel sub~trate . Th~ s causes a substant~al shear ~orce at ~e circu~t-porc~lain interface and substantial risk of ia~lure d~L~ing thermal cycl~ng.
Many of the a~ove-mentioned consldera~io~s regarding clad metal are described in a paper entitled ~Clad Metal Circuit Board Substrates for Direct Mounting o~ Ceramic Chip Carriers'~ by Dance and Wallace and presented at the First Annual Conference of the I~terna~ional Electronics Packaging Society, Cle~e~and, Ohio, 1981. Also, an article entitled "Use of Metal Core Sub trates ~r Leadless Chip Carrler Inter~
~onnection" by Lassen in Electron~c Packaging and 25 Production, March 1981, pages 98-104, dlscusses the latest technology ~n metal core substrates.
Presently, copper ~oll i5 adhered to an organic printed circuit substrate by elecl;rodeposition of ~'coral copper:' to the foil sur~ace. The result is a rough sur~ace ~ith re~entrance cavities to recei~e the surface layer of the organic substr~te and/or the orgarlic adhesi~re to form a "locked'l mechanical bond.
Slnce khe surface layer is a conductiYe metal structure (copper~ embedded in the organic makerial~ 35 considerable care must be exerc~sed to remo~e any resldual cor21 coooer treatment from the s~aces ~3~
Pr~sently, ther is an ~ncrease ln the clrcuit dens~t~ Or printed c$rcu~t boards. This creates a need for narrower and mor~ closely spaced ~7wires~
or llnes on the printed clrcuit board. The minimum line wldth generated by the state o~ the art conductive lnk technology is l~mlted by the printing process ~or applylng the conductiYe in~. Also, the final conductiYe ~k CgenerallY elther copper- or sil~er-) porcelain-steel product ~requently has problems rela~ing to the metalllzed pattern. The pattern may ha~e a substantially dlfferent Chigher) coeff~cient oP therm~l expansion than the steel sub~trate . Th~ s causes a substant~al shear ~orce at ~e circu~t-porc~lain interface and substantial risk of ia~lure d~L~ing thermal cycl~ng.
Many of the a~ove-mentioned consldera~io~s regarding clad metal are described in a paper entitled ~Clad Metal Circuit Board Substrates for Direct Mounting o~ Ceramic Chip Carriers'~ by Dance and Wallace and presented at the First Annual Conference of the I~terna~ional Electronics Packaging Society, Cle~e~and, Ohio, 1981. Also, an article entitled "Use of Metal Core Sub trates ~r Leadless Chip Carrler Inter~
~onnection" by Lassen in Electron~c Packaging and 25 Production, March 1981, pages 98-104, dlscusses the latest technology ~n metal core substrates.
Presently, copper ~oll i5 adhered to an organic printed circuit substrate by elecl;rodeposition of ~'coral copper:' to the foil sur~ace. The result is a rough sur~ace ~ith re~entrance cavities to recei~e the surface layer of the organic substr~te and/or the orgarlic adhesi~re to form a "locked'l mechanical bond.
Slnce khe surface layer is a conductiYe metal structure (copper~ embedded in the organic makerial~ 35 considerable care must be exerc~sed to remo~e any resldual cor21 coooer treatment from the s~aces ~3~
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betwPen the flnal pr~nted circuit lines. This avoids unwanted current passing between llnes, brldging o~
solde~ across the spaces bekween llnes, etc. Xn pr~ncipal, remo~al o~ residual coral copper treatmenk ~rom are~s requires addltional etching beyond that required to remo~e the base foll itself. This e~cessl~e etching leads to add~tional undercut~ing and partial de~truction of the circuit pattern~ Thus, the ~an~acturer of conventlonal copper ~oil-organlc circuit boards must strike a balance between enough etching to reliably remoYe the coral copper treatment while ~lnlmizing excessive etching to preYent under-cutting o~ the circult pattern.
The increased complexity o~ circuitry for inter-connecting various deYices mounted upon a printedcircult board often requires that both surfaces of the board contain conducti~e patterns. Some of the inter-connec~ions are provided by the clrcult pattern on the o~erse face o~ the board Cthe sur~ace to wh~ch the components zre mounted~ while other interconnections are provided upon the re~erse side of the board. The interconnection between the obverse and re~erse sides o~ the board may be provided by solder ~illed through-holes. ConYentional two sided copper ~oil-organic boards o~ th~s general configura~ion ~re widely used.
~owe~e~, in state of the art porcelain enameled steel substrate boards, two sided boards are not pract cal since the ~olid ~nd continuous steel substrate creates a continuous pa~h for elec~rical conduc~ion fr~m one throuh hole to another.
In certaln applications, the circuit require~ents include a double sided or multi-layered ~oard- ln which thermal exposure or other factors pre~ent the use of a copper ~oil organic board. An alternatiYe is a meta~
35 circuit pat ~ern on both sides of a suit~ble cer2:~ic, non-condllctiJe substrate with in~,erconnection bet,ween ~ 37~ 12086-MB
the two c~rcu~t~ h~ conductiYe through-hole~. Thls techn~ue ls used o~ speclalized printed circult boards and upon substra~es ~or h~rid package~.
As 1ntegra~ed clrcults ~ec~e larger ~more indi~dual functions on a single sillcon chip), and there ~s a corresponding increase ln the number of leads rOr lnterconnec~ion, the princlpal means o~
integrated clrcult interconnection~ the dual-in-llne CP~P~ package becomes ~mpractical. A DIP lncludes a lQ lead irame ~ith the leads emerglng ~rom the package and ~ormed ~nto "pinSn. As its n~me indlcates, the DIP
package has two rows of pins, one on either side o~ the package. The pins ~re inserted and soldered into holes in a printed c~r~uit board. Characteristically, the L~ p~ns are spaced apart on .100" centersO A relati~ely s~ple de~i¢e requiring a 20 lead package, 10 on side, w~ll b~ approximatel~ 1" long. A 40 lead DIP
pac~age ls abou~ 2Ir long and a 64 lead DTP package, about the largest now made, is appro~i~nately 3. 2" long.
For reasons relating to geometry, as the pac~ages become longer with more plns, they become wid2r.
Typically, the width o~ the completed package is approximately one-third lts length. For both mechan-ical and electronic re~sons, DIP packages with more than 64 lead~ are considered impractical to manufac~ure.
X~ever, large-scale integrated clrcuits orten require ~ore lnterconnections than proYided by DIP package~.
E~en with smaller integrated circuits, 'Ghe elrcllits are spaced together on the printed circu~t board ~ closely 30 as possi.ble~ Ob~iously, th~ package size limi-.s the closeness of ~he s~acing. Therefore, the semiconductor in~ustry has a growing interest in "chip carriersi'.
Chip carriers deal with the problems of large-scale circuits reauiring more interconnection~ khan 35 pro~ided ~y 2 DIP package 2S well as reduction of , ~
- ~L~3~72 package size for ~ntermedlate slzed integrated circults to tncrease component densit~ on the print~d clrcuit ~oard. The term chlp carrier, in lts broadest sense~
relates to packages, both ceramic and plas~ic. The con~iguratio~ o~ a chip carrier may be essentially square and leads emerge from withln the package on all ~our sides. Fur~hermore, typical center~to-center spac~ng of lead~ on a chip carrier is .050". Thusg a 64 lead de~rice ha~ing a 'Y~ootprintn of roughly 3 . 257' x 10 1,1" in a DIP package has a 1'~ootprint" of ap~ro~imately 0. 8" 3: 0 . 8" ln a chip carrler package . More impor-tarl~ly, the area coYered by the chlp carrier would be approximately 18% o~ that co~ered by the DIP package.
At thls time g ch~p carrier pac~ages with 128 and more 15 1 eads are be~ng produced.
The principal constraint in establishi~g .100'l as the normal spacing between le~ds on the DIP package is the lnsertion o~ the lead pins into holes on the prlnted circuit board. Allowing ~or the hole, a pad area around the hole ~or ~older adhesion and spacing between the holes to e7ectrlc211y isolate them from each otherJ it becomes dlf~icult to crowd them much closPr together.
Typically, the coe~flcient of thermal expansion o~
2S ~he DIP package is di~erent from that of the printed circuit board. The exten~ to which board and package d~mensions change with ~arying temperature can be accom~odated by deflection of the leads, i.e. between the printed circuit board and the package. E~fect-i~ely, the leads become spri~g members whichaccommodate the differences in coe~ficient of expansion.
State of the art chip carriers haYing .050" leads are not normally mounted by insertion of the leads into 35 holes in the printed circuit boarcs. Inst~ad, ;nost cnip carriers use a surface ..ount ing ~',ecnnlcue in which 3~
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the lead forms a pad mounted flush to the printed clrcu1 t l~oard and is soldered in place . The metallized pads on the e~terl or sur~ace of the chip packa~e are inte~ral with the package and expand and contract wikh the package~ There is no accommodatlo~ for de~leckion of leads due to changes in board and package dimensions, as in the case of DIP packages~ durin~
thermal cycling. As a result, the solder bond between the pad and the board is sub~ected to sub~tantial stresse~. The stresses increase as the total package size becomes larger and/or the board~s operation ls in an e2panded temperature range. Repeated stressing of the solder bond leads to ~atigue failureO
As ~ith 9IP packages, chip carr~er packages may use a plastic package or may require her~etic package. Wlth the DIP package, essentially the same external con~i~uration is employed ~or a hermetic (Ceramic Dual-In~Line ~ackage~ or a plastic package.
In both con~lgurations, the ~le~ible leads accommQdate for di~erential thermal expansion.
The "sta~dard" glass cloth reinforced epoxy board material ha~ a coefficient of therm21 expans~on o~ 15.8 x 10~fC. Cer~mic chip carriers usually made ~rom an aluminum o~ide ceramic have a coeff~cient of ~hermal e~pansion of 6.4 x 10-6/C. If thermal conducti~ity is particularly important, they made be made ~rom ber-yllium ox~d~e also ha~ng a coefficient ol thermal e~pansio~ o~ 6.4 ~ 10-6~C. In either event~ there is a substantial mismatch ln co~ffic1ent of thermal expansion be~ween the board and the ch~p carrier.
Therefore, substantlal stresses ~re imposed on the solder bond when su~j ected to signif~cant ~hermal c~c lin~ O
One solution h2s been to sur~ace mount t~.e cn~p carrier to a metallized pattern on 2n aluminum oxide cer~mic substrat e . The substrate has the same . "
coe~îcient of ther~al e~cpanslorl as the ehlp carrler.
P~ns ~a~ ~e ~raæed to the alumlna substrate and plugged into holes in the prlnted circu t board. Although this sork o~ con~lgurat~ on a~oids problems assoclated wlth ~isma.~ch ~ coe~lclent of thermal e~pa.nsion, lt also has ~e e~fect o~ sacri~icing much o~ ~he space saving adsrantage of the chlp carr{ erq A descri~tion o~ the latest technology with respect to chip carriers ~s pre~ented ln an artlcle entltled "Chip-Carriers, Pin-Grid Arrays Change the PC-Board Landscape" by Jerry Lyman, Elec_ronics, Decem~er 2~, 1981, pages 65 75. AnothQr ar~i~le entitled 1'Chip Carriers: ~oming Force in Packaging" by-Er~cksong ~n Electronic Packa in~and Produ tion, March 1981, pages 64-80 discusses ~he construction and other deta1 15 concerning chlp carriers.
U.SO Patent No. 3,546,363 to Pryor et al. dls-closes a composite metal product for use as a seal to glas es and ceramics which has properties o~ a low coef~icient of e~panslon, appro~imating that of the appropriate glasses and ceramics, good thermal conducti~rit~, and ~lne graln siæe in the annealed condlt ion .
~.S~ Patent Nos. 3,546,363; 3,618,203; 3,676,292;
3,726,g87; 3,826,627; 3,826,6~9; 3,837,895; 3,852,148;
and 4,149,910 disclose glass or ceramic to metal composites or seals wherein the glass or ceramic is bonded ta a base alloy ha~ring a thln ~ilm of re~ractory 02ide on i~s sur~ace . - _ j .
, ~3~97~2 It is a problem underlying the present inven-tion to provide a printed circuit board ~Jhich can accommodate substantial thermal cycling.
It is an advantage of the present invention to provide a composite and a process which obviate one or more of the limitations and disadvantages of the described prior arrangements~
It is a further advantage of the present invention to provide a composite and a process to form a printed circuit board which substantially reduce the formation of stresses between the circuit and the substrate due to thermal cycling.
It is a still further advan~age of the present invention to provide a composite and a pro~
cess to make printed circuit boards which are rela-tively inexpensive to manufacture.
It is a further advantage of the present invention to provide a composite and a process hav-ing improved heat dissipationO
In accordance with a particular embodiment of the invention, there is provided a composite adapted to be a printed circuit board system com-prising, a first metal or alloy component and a second metal or alloy-component. A glass or ceramic 2S component is disposed between the first component and the second component for bondin~ the first and second components to each other. The glass or ceramic component further has a coefficient o~ thermal expan-sion close to the coefficient of thermal expansion of the first and second components whereby thermal stress ~etween the first, second and glass or ceramic components may be substantially eliminated.
In accordance with a further embodiment of the invention there is provided a composite adapted to be a printed circuit board system comprising, a first metal or alloy component and a second metal or alloy 3~7Z
- ~a -component. Means are disposed between the first and second components for bonding the components to each other and for electrically insulating the components from each other. Grid means are embedded in the bonding and insulating means for stiffening the composite.
From a different aspect, and in accordance with the invention there is provided a process of forming a composite adapted to be a printed circuit board system. The process includes the steps of providing a first metal or alloy component and providing a secona metal or alloy component. A
glass or ceramic component is disposed between the first and second components, the glass or ceramic component having a coefficient of thermal expansion close to the coefficient of thermal expansion of the first and second components whereby thermal stress between the first, second and glass or ceramic com-ponents may be substantially eliminated. Then, bonding the first, second and glass or ceramic components together.
In accordance wit~ a further embodiment, there is provided a process of forming a composite adapted to be a circuit board system. The process includes the steps of providing a first metal or alloy component and providing a second metal or alloy component. A bonding and insulating component is disposed between the first and second components, and the first and second bonding components are bonded together. A grid component is embedded in the bonding and insulating component for stiffening the circuit board system.
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between each o~ the thin refractory oxide layers of two metal base alloy components to provide rlgidity to the mult i-layer c ompo s lt e ..
The lnventlon and ~urther deYelopments o~ the invention are now el~1cidated by means Or preferred ~mbodiments shown in ~he drawings:
Figure 1 is a cross section of a prior art printed clrcuit board;
~ gure 2 is a cross section o~ a metal core prior art pr~nted cirruit board;
Figure 3 is a cross section of a printPd circuit board haYing a glass c~mponent bonded between the coating of two copper alloys in accordarlce with the present invention;
Figure 4 is a printed circuit board haYing high thermal conducti~ity su~strates bonded to copper alloy com~onents;
Figure 5 is a cross-sec~ional view of a printed circuit board with a ~used interfaced layer between two substrates, Flgure 6 is a prin~ed circuit board ha~ing clrcuits on opposite surfaces and lnterconnections there~etween;
~ igure 7 1~ a cross-sectional view o~ a printed circu~t board hav~ng circuits on o~oosite surfaces and a metal grid therebetween;
Figure 8 is a top view of a metal grid used ~or.
reinforcement o~ a printed circuit board;
Figure 9 i5 a view through 9-9 of F1gure 8;
30 Figure 10 is a side ~e~ o~ ~ mult~-12yer printed circu~t board in accord~nce with the present inventlon;
~igure 11 1~ a slde Yiew of a leadless chip carrier in accordance with ~he present in~ention;
~igure 12 i5 a ~lew through ~1-ll o~ ~igure 10;
and .
. .
3~2 12~6-~B
~ igure 13 ls a side ~iew of a leadless chlp ca~rier mounted upon a printed clrcuit board ln accordance with the present invention~
As shown ~n ~gure 1, pr~or art printe~ c~rcults 10 are produced by adhering one or more layers o~ copper foil 12 to organlc material 14 such as glass flber re~nforced epo~y, phenolic laminated paper, etc. These structures have se~eral deficiencies ~ncluding ~estricted maximum operating temperature due to the or~anic su~strate and substantial mlsmatc~ between the coefficient o~ thermal expanslon of the organic sub~
strate and that o~ the copper foil, the solder composltions to attach components to the circuitry and the components themselves~ Substantlal thermal stresses, resulting ~rom the mismatch, create failure modes such as tensile ~ailure of the copper foil, ~ailure o~ the solder attachment of components to the clrcuit and tensile ~ailure o~ the components them-~elves.
There is some use o~ metal core boards 16 fo~ld in F~gure 2. Typically, these include a metal core 18, a copper foll 22 and an epox~ insulating layer 20 bonded to both layer 20 and foil 22. Thls type o~ board pro~ides better heat dlssipatlon than the normal glass ~iber r~in~orced epoxy boards but still has the restricted ma~imum operating temperature related to the organic substra~e. Also, substantial mlsmatch between t~e coef~icient o~ ~hermal e~pans~on o~ the organic substrate and the copper ~oil causes the types of problems associated wi~h conventional printed circults as shown ln Flgure 1~
The present invention overcomes these problems by providing a composite or printed circuit board 24 as shown in Figure 3. The composite may include a first metal or metal base alloy component 26 having a thin interface layer 28 on at least a ~irst , .
~ 3~
surface 30 ther~of and a second thin interface layer 34 on at least surface 36 of a metal or metal base alloy component 32. A glass component 38 is bonded to the ~irst and second thin interface layers 28 and 34 to insulate the component 26 from the second component 32.
The preferred alloy for use in the embodi-ments of the present invention is a copper base alloy containing from 2 to 12% aluminum and the balance copper. Preferably, the alloy contains from 2 to 10%
aluminum, 0.001 to 3% silicon, and if desired, a grain refining element selected from the group con-sistiny of iron up to 4.5%, chromium up to 1%, zirconium up to 0.5%, cobalt up to 1% and mixtures o~ these grain refining elements and ~he balance copper. In particular, CDA alloy C6381 containing 2.5 to 3.1% aluminum, 1.5 to 2.1% silicon, and the balance copper is useful as a substrate for this invention. Impurities may be present which do not prevent bonding in a desired environment.
The 3110ys useful with this invention and, especially alloy C6381 are described in U. S.
Patent Nos. 3,341,369 and 3,475,227 to Caule et al.
which disclose copper base alloys and processes for 2~ preparing them.
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The present invention is not restricted to applications of alloy C6381 but includes the broad field of metal or alloys which have the ability to form continuous interface layers on their surface.
Several examples of other metal alloys such as nickel base and iron base alloys are dlsclosed in U. S. Patent Nos. 3,698,964, 3,730,779 and 3,810,754.
The present invention uses any suitable glass or ceramic component 38, such as cited in the patents above, preferably with a coefficient of thermal ex-pansion which closely matches the metal components.
The glass is bonded to the thin inter~ace layers 28 and 34 and functions to adhere the metal com-ponents together and electrically insulate them from each other. Since the glass and the copper alloy substrates preferably have the same or closely matched coefficients of thermal expansion, thermal stresses in the system may be essentiàlly eliminated and the problems associated with thermal stress in the finished product alleviated.
Table I lists ~arious exemplary glasses and ceramics which are adapted for US2 in accor~ance with this invention.
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TABLE I
Coeff~clen~ Or Thermal Gla~s or ~eramlc Type E
Ferro Corp~l No. RN 3066-H 167 x 10-7 Ferro Corp.l No. RN-3066-S 160 ~ 10-7 lPropr~etary composit~on manufactured by Ferro Corpora-tion, CleYeland, Ohio.
Re~erring again to the embodiment as lllustrated in ~g~re 3, a ~oll layer 32 is bonded to a th~cker suppor~ive layer Z6 by means of glass 38. The foll 32 may be subsequentlally treated with a l'resist" pattern and etched to produce a prlnted circuit. The result ~s a wrought copper al~oy circuit attern bonded to and insulated from a wrought copper alloy supportive substrate 26 by a layer o~ glass 38 which serves as both an adhesiYe and an insulating materlal. This configuration has a number of advantages o~er the prior technique Or printing circuitry upon the sur~ace of porcelaln with conductiYe ink. Firstly, in the prior 20 conducti~e ~nk technology, multiple lay~rs of the conductlYe ~n~ are applled to provide an adeauate conductive pattern for the required electric current.
Xowe~er, the circuit foil 32 may be of any desired thickness and rPplaces the multiple screening and ~5 ~ring operations by a single firing operation and a single etch~ng operation. Secondly~ recent increases in circuit density of prlnted circ~lit ~oards create a need ~or narrower and more closely spaced printed "wires" or lines. The prior conducti~e in~ technology ~s limited to the minimum line width ~enerated ~y the printing process. The present invention, howeYer, e~ches copper foil and provides narrow lines and spaces 25` in conYentional etched copper ~o~ 1, org~nic sub strate circuits. Thirdly, the .~etalli~ed ~attern 35 formed on the conductiYe ~ nk-po-cel2~ n-steel ci~cult _}5_ 12o86~
board has a substantiall~ hi~her coef~tcient of thermal e~pans~on than the steel substrate. Thermal cycling de~elops su~tantial shear forces at the clrcult~
porcela~n inter~ace creating subs'cantial rlsk of' ~ailure. The em~odlment of ~igure 3 su~stantially ellminates these shear forces because the coef.icient of thermal expansion of the circuit foil and the metal s~strate may be substantially ~he same.
Where greater conductivity than that ~nherent in the metal or alloys producing bondable alumlna and sllica fi~ms is desired, a composite copper alloy ~o~l incorpora~ing a hi~her conductivity layer, as shown in Figure 4, may replace the solid alloy 32 as in the previous embodlment.
The embodiment o~ Figure 4 includes bondable copper alloy substrate 40 and circuit foil ~6 having inter~ace layers 41 and 43, respectively. A
~lass or cer~mlc 44 is bonded betwee~ ~he interface layer 43 on c~rcuit foil 46 and the interface layer 41 on the copper base alloy 40. Substrate 40 ls bond~d, as a composite, to a copper or high conductivity cop~er alloy thicker component 42. l~e latter provldes for super~or ther~al dissipation rom the board as compared to both conventional copper foil organic boards and 25 porcelain on steel boards. Also, foil 4~ may be bonded as a composite to a copper or high conductivity copper alloy component 47 for superior electrlcal or therma conducti~ity. It is also withln the scope o the present invention to pro~ide only one of the components - 30 42 or 4~ a~ required. It is also within the scope of the present inYen~ion to modi~y any Or the descr~bed embodiments by bonding the component, 2s a comDosite, to a metal layer having desired ~hysic~l properties.
The embodiment as sho~m in ~i~ur_ 5 pro~Jides co~pe~ alloy substrates 48 and 49 e2ch .or~in~ an inter-face layer. These interface layers are , ~2~ 72 -16 12086-~B
fused together inta layer 50 and dispense wlth the pro~slon Or ~la~s. The un~ied interface layer 50 ~ot~ adheres the metal substrates 48 and ~9 and insulates them from each other. It ls within the scope of the lnvention to substitute the glass ln the embod-iments of the present invention with fused interface laye~s as desired.
~ he c~ple~ity of the circuitry for intercon-necting the various devices mounted upon a printed 10. c~rcu~.t board a~ten req~ire~ that both surfaces of the board contain conductiYe patterns. Details of prior art tw~ sided circuit boards are described in the back-ground o~ the ~nventlon.
A two sided circ~t board on~iguration 5~, as sho~n in Figure 6, has two relatively thick layers of copper ~ase alloy co~onents 50 and 52, each having a thin interface layer 51 and 53, respectively,.
on at least one surface. The components are bonded together and insulated ~ro:~ one another by a glass or ceramic 54 which ls ~used to the interface layers 51 and 53. A circuit pattern is formed on each of the c~mponents 50 and ~2 ~y a conYentional technique. The t~lckness of each metal component ls estab~ ished in accordance with the desired stlf~ness o~ the ~inished boardO The circuit patterns on each side of the board 55 must be carefully designed to provide reasonable sti~ness and to avoid plane~ of weaknes~. Such planes might de~elop if an area o~ considerable size without any clrcuitr~ on one side o~ the board coincides with 30 a similar area on the reverse side of the ~ond.
Through-holes 56 may be provided in the circuit board by any conven~iorial technique such as drilling or punching. The through-holes may be ~ormed into z conductlve path by ~ny sul~able mearls such as electro_ 3~ less deposition o, co~er on thei~ w~lls. I~ desired, `` ~2~ 3~72 the through-holes can then ~e fillec3 with a conductive material such as solder.
Another embodiment of a two sided metal y:Lass printed cîrcuit board 57, as shown in Figure 7, includes two copper alloy substra-tes 58 and 60, each having a thin interface layer 62 and 64, respectively, bonded on at least one surface. A glass component 65 is fused to the layers 62 and 64. A grid 66, preferably metal, is bonded in the glass 65 and insulated from the alloy substrates 58 and 60. The recesses 68 of the grid may be filled with glass 65 or any other suitable inorganic filler~ q~hrough-holes 69 are formed in the board as described above. The iresult is a board with the same _ . .
aesign flexibility as conventional foil-organic boards but with the advantage of substantial elimination of thermal stresses. The metal grid both stiffens the board 57 and permits a plurality of through-holes 69-to i } pass through openings,~ of t:he grid. 'rhe through-holes must not contact the metal grid to avoid short circuits.
~he metal grid is preferably made of a copper alloy having a thin interface layer on both surfaces.
It is, however, within the scope of the present invention to use any desired material to construct the grid. ~he grid may be formed with any desired con~iguration, and a typical one is shown in Figure 8. A series of recesses 68 are stamped in a metal sheet 67~ Subsequently, the bottom ~ of the recesses are pierced leaving a pattern o~ interlocking "V" bars, as shown in Figure 8, E~or . ~ .
reinfc~rcement.
The need for still greater circuit complexity than provided by a t~to sided circuit boara leads to multi-layer circuit boards with three or more layers o copper foil. Using the concepts ~escribed hereinabove, a multi layer board composed of alternate layers of copper alloy foil having a thin interface layer -18~ 2 12086-i~
on each surface ~n contact ~ith the glass insulator ls descrlbed. As shown in Figure 10, copper foil com-ponents 70, 71 and 72 have their interface l~yers 73, 74 and 75~ respectively, bonded to glass 76.
betwPen the flnal pr~nted circuit lines. This avoids unwanted current passing between llnes, brldging o~
solde~ across the spaces bekween llnes, etc. Xn pr~ncipal, remo~al o~ residual coral copper treatmenk ~rom are~s requires addltional etching beyond that required to remo~e the base foll itself. This e~cessl~e etching leads to add~tional undercut~ing and partial de~truction of the circuit pattern~ Thus, the ~an~acturer of conventlonal copper ~oil-organlc circuit boards must strike a balance between enough etching to reliably remoYe the coral copper treatment while ~lnlmizing excessive etching to preYent under-cutting o~ the circult pattern.
The increased complexity o~ circuitry for inter-connecting various deYices mounted upon a printedcircult board often requires that both surfaces of the board contain conducti~e patterns. Some of the inter-connec~ions are provided by the clrcult pattern on the o~erse face o~ the board Cthe sur~ace to wh~ch the components zre mounted~ while other interconnections are provided upon the re~erse side of the board. The interconnection between the obverse and re~erse sides o~ the board may be provided by solder ~illed through-holes. ConYentional two sided copper ~oil-organic boards o~ th~s general configura~ion ~re widely used.
~owe~e~, in state of the art porcelain enameled steel substrate boards, two sided boards are not pract cal since the ~olid ~nd continuous steel substrate creates a continuous pa~h for elec~rical conduc~ion fr~m one throuh hole to another.
In certaln applications, the circuit require~ents include a double sided or multi-layered ~oard- ln which thermal exposure or other factors pre~ent the use of a copper ~oil organic board. An alternatiYe is a meta~
35 circuit pat ~ern on both sides of a suit~ble cer2:~ic, non-condllctiJe substrate with in~,erconnection bet,ween ~ 37~ 12086-MB
the two c~rcu~t~ h~ conductiYe through-hole~. Thls techn~ue ls used o~ speclalized printed circult boards and upon substra~es ~or h~rid package~.
As 1ntegra~ed clrcults ~ec~e larger ~more indi~dual functions on a single sillcon chip), and there ~s a corresponding increase ln the number of leads rOr lnterconnec~ion, the princlpal means o~
integrated clrcult interconnection~ the dual-in-llne CP~P~ package becomes ~mpractical. A DIP lncludes a lQ lead irame ~ith the leads emerglng ~rom the package and ~ormed ~nto "pinSn. As its n~me indlcates, the DIP
package has two rows of pins, one on either side o~ the package. The pins ~re inserted and soldered into holes in a printed c~r~uit board. Characteristically, the L~ p~ns are spaced apart on .100" centersO A relati~ely s~ple de~i¢e requiring a 20 lead package, 10 on side, w~ll b~ approximatel~ 1" long. A 40 lead DIP
pac~age ls abou~ 2Ir long and a 64 lead DTP package, about the largest now made, is appro~i~nately 3. 2" long.
For reasons relating to geometry, as the pac~ages become longer with more plns, they become wid2r.
Typically, the width o~ the completed package is approximately one-third lts length. For both mechan-ical and electronic re~sons, DIP packages with more than 64 lead~ are considered impractical to manufac~ure.
X~ever, large-scale integrated clrcuits orten require ~ore lnterconnections than proYided by DIP package~.
E~en with smaller integrated circuits, 'Ghe elrcllits are spaced together on the printed circu~t board ~ closely 30 as possi.ble~ Ob~iously, th~ package size limi-.s the closeness of ~he s~acing. Therefore, the semiconductor in~ustry has a growing interest in "chip carriersi'.
Chip carriers deal with the problems of large-scale circuits reauiring more interconnection~ khan 35 pro~ided ~y 2 DIP package 2S well as reduction of , ~
- ~L~3~72 package size for ~ntermedlate slzed integrated circults to tncrease component densit~ on the print~d clrcuit ~oard. The term chlp carrier, in lts broadest sense~
relates to packages, both ceramic and plas~ic. The con~iguratio~ o~ a chip carrier may be essentially square and leads emerge from withln the package on all ~our sides. Fur~hermore, typical center~to-center spac~ng of lead~ on a chip carrier is .050". Thusg a 64 lead de~rice ha~ing a 'Y~ootprintn of roughly 3 . 257' x 10 1,1" in a DIP package has a 1'~ootprint" of ap~ro~imately 0. 8" 3: 0 . 8" ln a chip carrler package . More impor-tarl~ly, the area coYered by the chlp carrier would be approximately 18% o~ that co~ered by the DIP package.
At thls time g ch~p carrier pac~ages with 128 and more 15 1 eads are be~ng produced.
The principal constraint in establishi~g .100'l as the normal spacing between le~ds on the DIP package is the lnsertion o~ the lead pins into holes on the prlnted circuit board. Allowing ~or the hole, a pad area around the hole ~or ~older adhesion and spacing between the holes to e7ectrlc211y isolate them from each otherJ it becomes dlf~icult to crowd them much closPr together.
Typically, the coe~flcient of thermal expansion o~
2S ~he DIP package is di~erent from that of the printed circuit board. The exten~ to which board and package d~mensions change with ~arying temperature can be accom~odated by deflection of the leads, i.e. between the printed circuit board and the package. E~fect-i~ely, the leads become spri~g members whichaccommodate the differences in coe~ficient of expansion.
State of the art chip carriers haYing .050" leads are not normally mounted by insertion of the leads into 35 holes in the printed circuit boarcs. Inst~ad, ;nost cnip carriers use a surface ..ount ing ~',ecnnlcue in which 3~
7- ~2086-MB
the lead forms a pad mounted flush to the printed clrcu1 t l~oard and is soldered in place . The metallized pads on the e~terl or sur~ace of the chip packa~e are inte~ral with the package and expand and contract wikh the package~ There is no accommodatlo~ for de~leckion of leads due to changes in board and package dimensions, as in the case of DIP packages~ durin~
thermal cycling. As a result, the solder bond between the pad and the board is sub~ected to sub~tantial stresse~. The stresses increase as the total package size becomes larger and/or the board~s operation ls in an e2panded temperature range. Repeated stressing of the solder bond leads to ~atigue failureO
As ~ith 9IP packages, chip carr~er packages may use a plastic package or may require her~etic package. Wlth the DIP package, essentially the same external con~i~uration is employed ~or a hermetic (Ceramic Dual-In~Line ~ackage~ or a plastic package.
In both con~lgurations, the ~le~ible leads accommQdate for di~erential thermal expansion.
The "sta~dard" glass cloth reinforced epoxy board material ha~ a coefficient of therm21 expans~on o~ 15.8 x 10~fC. Cer~mic chip carriers usually made ~rom an aluminum o~ide ceramic have a coeff~cient of ~hermal e~pansion of 6.4 x 10-6/C. If thermal conducti~ity is particularly important, they made be made ~rom ber-yllium ox~d~e also ha~ng a coefficient ol thermal e~pansio~ o~ 6.4 ~ 10-6~C. In either event~ there is a substantial mismatch ln co~ffic1ent of thermal expansion be~ween the board and the ch~p carrier.
Therefore, substantlal stresses ~re imposed on the solder bond when su~j ected to signif~cant ~hermal c~c lin~ O
One solution h2s been to sur~ace mount t~.e cn~p carrier to a metallized pattern on 2n aluminum oxide cer~mic substrat e . The substrate has the same . "
coe~îcient of ther~al e~cpanslorl as the ehlp carrler.
P~ns ~a~ ~e ~raæed to the alumlna substrate and plugged into holes in the prlnted circu t board. Although this sork o~ con~lgurat~ on a~oids problems assoclated wlth ~isma.~ch ~ coe~lclent of thermal e~pa.nsion, lt also has ~e e~fect o~ sacri~icing much o~ ~he space saving adsrantage of the chlp carr{ erq A descri~tion o~ the latest technology with respect to chip carriers ~s pre~ented ln an artlcle entltled "Chip-Carriers, Pin-Grid Arrays Change the PC-Board Landscape" by Jerry Lyman, Elec_ronics, Decem~er 2~, 1981, pages 65 75. AnothQr ar~i~le entitled 1'Chip Carriers: ~oming Force in Packaging" by-Er~cksong ~n Electronic Packa in~and Produ tion, March 1981, pages 64-80 discusses ~he construction and other deta1 15 concerning chlp carriers.
U.SO Patent No. 3,546,363 to Pryor et al. dls-closes a composite metal product for use as a seal to glas es and ceramics which has properties o~ a low coef~icient of e~panslon, appro~imating that of the appropriate glasses and ceramics, good thermal conducti~rit~, and ~lne graln siæe in the annealed condlt ion .
~.S~ Patent Nos. 3,546,363; 3,618,203; 3,676,292;
3,726,g87; 3,826,627; 3,826,6~9; 3,837,895; 3,852,148;
and 4,149,910 disclose glass or ceramic to metal composites or seals wherein the glass or ceramic is bonded ta a base alloy ha~ring a thln ~ilm of re~ractory 02ide on i~s sur~ace . - _ j .
, ~3~97~2 It is a problem underlying the present inven-tion to provide a printed circuit board ~Jhich can accommodate substantial thermal cycling.
It is an advantage of the present invention to provide a composite and a process which obviate one or more of the limitations and disadvantages of the described prior arrangements~
It is a further advantage of the present invention to provide a composite and a process to form a printed circuit board which substantially reduce the formation of stresses between the circuit and the substrate due to thermal cycling.
It is a still further advan~age of the present invention to provide a composite and a pro~
cess to make printed circuit boards which are rela-tively inexpensive to manufacture.
It is a further advantage of the present invention to provide a composite and a process hav-ing improved heat dissipationO
In accordance with a particular embodiment of the invention, there is provided a composite adapted to be a printed circuit board system com-prising, a first metal or alloy component and a second metal or alloy-component. A glass or ceramic 2S component is disposed between the first component and the second component for bondin~ the first and second components to each other. The glass or ceramic component further has a coefficient o~ thermal expan-sion close to the coefficient of thermal expansion of the first and second components whereby thermal stress ~etween the first, second and glass or ceramic components may be substantially eliminated.
In accordance with a further embodiment of the invention there is provided a composite adapted to be a printed circuit board system comprising, a first metal or alloy component and a second metal or alloy 3~7Z
- ~a -component. Means are disposed between the first and second components for bonding the components to each other and for electrically insulating the components from each other. Grid means are embedded in the bonding and insulating means for stiffening the composite.
From a different aspect, and in accordance with the invention there is provided a process of forming a composite adapted to be a printed circuit board system. The process includes the steps of providing a first metal or alloy component and providing a secona metal or alloy component. A
glass or ceramic component is disposed between the first and second components, the glass or ceramic component having a coefficient of thermal expansion close to the coefficient of thermal expansion of the first and second components whereby thermal stress between the first, second and glass or ceramic com-ponents may be substantially eliminated. Then, bonding the first, second and glass or ceramic components together.
In accordance wit~ a further embodiment, there is provided a process of forming a composite adapted to be a circuit board system. The process includes the steps of providing a first metal or alloy component and providing a second metal or alloy component. A bonding and insulating component is disposed between the first and second components, and the first and second bonding components are bonded together. A grid component is embedded in the bonding and insulating component for stiffening the circuit board system.
.~ '7~
between each o~ the thin refractory oxide layers of two metal base alloy components to provide rlgidity to the mult i-layer c ompo s lt e ..
The lnventlon and ~urther deYelopments o~ the invention are now el~1cidated by means Or preferred ~mbodiments shown in ~he drawings:
Figure 1 is a cross section of a prior art printed clrcuit board;
~ gure 2 is a cross section o~ a metal core prior art pr~nted cirruit board;
Figure 3 is a cross section of a printPd circuit board haYing a glass c~mponent bonded between the coating of two copper alloys in accordarlce with the present invention;
Figure 4 is a printed circuit board haYing high thermal conducti~ity su~strates bonded to copper alloy com~onents;
Figure 5 is a cross-sec~ional view of a printed circuit board with a ~used interfaced layer between two substrates, Flgure 6 is a prin~ed circuit board ha~ing clrcuits on opposite surfaces and lnterconnections there~etween;
~ igure 7 1~ a cross-sectional view o~ a printed circu~t board hav~ng circuits on o~oosite surfaces and a metal grid therebetween;
Figure 8 is a top view of a metal grid used ~or.
reinforcement o~ a printed circuit board;
Figure 9 i5 a view through 9-9 of F1gure 8;
30 Figure 10 is a side ~e~ o~ ~ mult~-12yer printed circu~t board in accord~nce with the present inventlon;
~igure 11 1~ a slde Yiew of a leadless chip carrier in accordance with ~he present in~ention;
~igure 12 i5 a ~lew through ~1-ll o~ ~igure 10;
and .
. .
3~2 12~6-~B
~ igure 13 ls a side ~iew of a leadless chlp ca~rier mounted upon a printed clrcuit board ln accordance with the present invention~
As shown ~n ~gure 1, pr~or art printe~ c~rcults 10 are produced by adhering one or more layers o~ copper foil 12 to organlc material 14 such as glass flber re~nforced epo~y, phenolic laminated paper, etc. These structures have se~eral deficiencies ~ncluding ~estricted maximum operating temperature due to the or~anic su~strate and substantial mlsmatc~ between the coefficient o~ thermal expanslon of the organic sub~
strate and that o~ the copper foil, the solder composltions to attach components to the circuitry and the components themselves~ Substantlal thermal stresses, resulting ~rom the mismatch, create failure modes such as tensile ~ailure of the copper foil, ~ailure o~ the solder attachment of components to the clrcuit and tensile ~ailure o~ the components them-~elves.
There is some use o~ metal core boards 16 fo~ld in F~gure 2. Typically, these include a metal core 18, a copper foll 22 and an epox~ insulating layer 20 bonded to both layer 20 and foil 22. Thls type o~ board pro~ides better heat dlssipatlon than the normal glass ~iber r~in~orced epoxy boards but still has the restricted ma~imum operating temperature related to the organic substra~e. Also, substantial mlsmatch between t~e coef~icient o~ ~hermal e~pans~on o~ the organic substrate and the copper ~oil causes the types of problems associated wi~h conventional printed circults as shown ln Flgure 1~
The present invention overcomes these problems by providing a composite or printed circuit board 24 as shown in Figure 3. The composite may include a first metal or metal base alloy component 26 having a thin interface layer 28 on at least a ~irst , .
~ 3~
surface 30 ther~of and a second thin interface layer 34 on at least surface 36 of a metal or metal base alloy component 32. A glass component 38 is bonded to the ~irst and second thin interface layers 28 and 34 to insulate the component 26 from the second component 32.
The preferred alloy for use in the embodi-ments of the present invention is a copper base alloy containing from 2 to 12% aluminum and the balance copper. Preferably, the alloy contains from 2 to 10%
aluminum, 0.001 to 3% silicon, and if desired, a grain refining element selected from the group con-sistiny of iron up to 4.5%, chromium up to 1%, zirconium up to 0.5%, cobalt up to 1% and mixtures o~ these grain refining elements and ~he balance copper. In particular, CDA alloy C6381 containing 2.5 to 3.1% aluminum, 1.5 to 2.1% silicon, and the balance copper is useful as a substrate for this invention. Impurities may be present which do not prevent bonding in a desired environment.
The 3110ys useful with this invention and, especially alloy C6381 are described in U. S.
Patent Nos. 3,341,369 and 3,475,227 to Caule et al.
which disclose copper base alloys and processes for 2~ preparing them.
7~
The present invention is not restricted to applications of alloy C6381 but includes the broad field of metal or alloys which have the ability to form continuous interface layers on their surface.
Several examples of other metal alloys such as nickel base and iron base alloys are dlsclosed in U. S. Patent Nos. 3,698,964, 3,730,779 and 3,810,754.
The present invention uses any suitable glass or ceramic component 38, such as cited in the patents above, preferably with a coefficient of thermal ex-pansion which closely matches the metal components.
The glass is bonded to the thin inter~ace layers 28 and 34 and functions to adhere the metal com-ponents together and electrically insulate them from each other. Since the glass and the copper alloy substrates preferably have the same or closely matched coefficients of thermal expansion, thermal stresses in the system may be essentiàlly eliminated and the problems associated with thermal stress in the finished product alleviated.
Table I lists ~arious exemplary glasses and ceramics which are adapted for US2 in accor~ance with this invention.
-14~ 1208~-M~
TABLE I
Coeff~clen~ Or Thermal Gla~s or ~eramlc Type E
Ferro Corp~l No. RN 3066-H 167 x 10-7 Ferro Corp.l No. RN-3066-S 160 ~ 10-7 lPropr~etary composit~on manufactured by Ferro Corpora-tion, CleYeland, Ohio.
Re~erring again to the embodiment as lllustrated in ~g~re 3, a ~oll layer 32 is bonded to a th~cker suppor~ive layer Z6 by means of glass 38. The foll 32 may be subsequentlally treated with a l'resist" pattern and etched to produce a prlnted circuit. The result ~s a wrought copper al~oy circuit attern bonded to and insulated from a wrought copper alloy supportive substrate 26 by a layer o~ glass 38 which serves as both an adhesiYe and an insulating materlal. This configuration has a number of advantages o~er the prior technique Or printing circuitry upon the sur~ace of porcelaln with conductiYe ink. Firstly, in the prior 20 conducti~e ~nk technology, multiple lay~rs of the conductlYe ~n~ are applled to provide an adeauate conductive pattern for the required electric current.
Xowe~er, the circuit foil 32 may be of any desired thickness and rPplaces the multiple screening and ~5 ~ring operations by a single firing operation and a single etch~ng operation. Secondly~ recent increases in circuit density of prlnted circ~lit ~oards create a need ~or narrower and more closely spaced printed "wires" or lines. The prior conducti~e in~ technology ~s limited to the minimum line width ~enerated ~y the printing process. The present invention, howeYer, e~ches copper foil and provides narrow lines and spaces 25` in conYentional etched copper ~o~ 1, org~nic sub strate circuits. Thirdly, the .~etalli~ed ~attern 35 formed on the conductiYe ~ nk-po-cel2~ n-steel ci~cult _}5_ 12o86~
board has a substantiall~ hi~her coef~tcient of thermal e~pans~on than the steel substrate. Thermal cycling de~elops su~tantial shear forces at the clrcult~
porcela~n inter~ace creating subs'cantial rlsk of' ~ailure. The em~odlment of ~igure 3 su~stantially ellminates these shear forces because the coef.icient of thermal expansion of the circuit foil and the metal s~strate may be substantially ~he same.
Where greater conductivity than that ~nherent in the metal or alloys producing bondable alumlna and sllica fi~ms is desired, a composite copper alloy ~o~l incorpora~ing a hi~her conductivity layer, as shown in Figure 4, may replace the solid alloy 32 as in the previous embodlment.
The embodiment o~ Figure 4 includes bondable copper alloy substrate 40 and circuit foil ~6 having inter~ace layers 41 and 43, respectively. A
~lass or cer~mlc 44 is bonded betwee~ ~he interface layer 43 on c~rcuit foil 46 and the interface layer 41 on the copper base alloy 40. Substrate 40 ls bond~d, as a composite, to a copper or high conductivity cop~er alloy thicker component 42. l~e latter provldes for super~or ther~al dissipation rom the board as compared to both conventional copper foil organic boards and 25 porcelain on steel boards. Also, foil 4~ may be bonded as a composite to a copper or high conductivity copper alloy component 47 for superior electrlcal or therma conducti~ity. It is also withln the scope o the present invention to pro~ide only one of the components - 30 42 or 4~ a~ required. It is also within the scope of the present inYen~ion to modi~y any Or the descr~bed embodiments by bonding the component, 2s a comDosite, to a metal layer having desired ~hysic~l properties.
The embodiment as sho~m in ~i~ur_ 5 pro~Jides co~pe~ alloy substrates 48 and 49 e2ch .or~in~ an inter-face layer. These interface layers are , ~2~ 72 -16 12086-~B
fused together inta layer 50 and dispense wlth the pro~slon Or ~la~s. The un~ied interface layer 50 ~ot~ adheres the metal substrates 48 and ~9 and insulates them from each other. It ls within the scope of the lnvention to substitute the glass ln the embod-iments of the present invention with fused interface laye~s as desired.
~ he c~ple~ity of the circuitry for intercon-necting the various devices mounted upon a printed 10. c~rcu~.t board a~ten req~ire~ that both surfaces of the board contain conductiYe patterns. Details of prior art tw~ sided circuit boards are described in the back-ground o~ the ~nventlon.
A two sided circ~t board on~iguration 5~, as sho~n in Figure 6, has two relatively thick layers of copper ~ase alloy co~onents 50 and 52, each having a thin interface layer 51 and 53, respectively,.
on at least one surface. The components are bonded together and insulated ~ro:~ one another by a glass or ceramic 54 which ls ~used to the interface layers 51 and 53. A circuit pattern is formed on each of the c~mponents 50 and ~2 ~y a conYentional technique. The t~lckness of each metal component ls estab~ ished in accordance with the desired stlf~ness o~ the ~inished boardO The circuit patterns on each side of the board 55 must be carefully designed to provide reasonable sti~ness and to avoid plane~ of weaknes~. Such planes might de~elop if an area o~ considerable size without any clrcuitr~ on one side o~ the board coincides with 30 a similar area on the reverse side of the ~ond.
Through-holes 56 may be provided in the circuit board by any conven~iorial technique such as drilling or punching. The through-holes may be ~ormed into z conductlve path by ~ny sul~able mearls such as electro_ 3~ less deposition o, co~er on thei~ w~lls. I~ desired, `` ~2~ 3~72 the through-holes can then ~e fillec3 with a conductive material such as solder.
Another embodiment of a two sided metal y:Lass printed cîrcuit board 57, as shown in Figure 7, includes two copper alloy substra-tes 58 and 60, each having a thin interface layer 62 and 64, respectively, bonded on at least one surface. A glass component 65 is fused to the layers 62 and 64. A grid 66, preferably metal, is bonded in the glass 65 and insulated from the alloy substrates 58 and 60. The recesses 68 of the grid may be filled with glass 65 or any other suitable inorganic filler~ q~hrough-holes 69 are formed in the board as described above. The iresult is a board with the same _ . .
aesign flexibility as conventional foil-organic boards but with the advantage of substantial elimination of thermal stresses. The metal grid both stiffens the board 57 and permits a plurality of through-holes 69-to i } pass through openings,~ of t:he grid. 'rhe through-holes must not contact the metal grid to avoid short circuits.
~he metal grid is preferably made of a copper alloy having a thin interface layer on both surfaces.
It is, however, within the scope of the present invention to use any desired material to construct the grid. ~he grid may be formed with any desired con~iguration, and a typical one is shown in Figure 8. A series of recesses 68 are stamped in a metal sheet 67~ Subsequently, the bottom ~ of the recesses are pierced leaving a pattern o~ interlocking "V" bars, as shown in Figure 8, E~or . ~ .
reinfc~rcement.
The need for still greater circuit complexity than provided by a t~to sided circuit boara leads to multi-layer circuit boards with three or more layers o copper foil. Using the concepts ~escribed hereinabove, a multi layer board composed of alternate layers of copper alloy foil having a thin interface layer -18~ 2 12086-i~
on each surface ~n contact ~ith the glass insulator ls descrlbed. As shown in Figure 10, copper foil com-ponents 70, 71 and 72 have their interface l~yers 73, 74 and 75~ respectively, bonded to glass 76.
5 The foll components may each be proYlded wlth circuitry as in khe em~odiments described above. Also, the components may be bonded as composites to other metals wit~ desired physical properties 2S described aboYe.
It is ~hought that the thicker multi-layer boards will 10 be suf~iciently r~gid. Where addltional rigidity ls required, grid relnforcement as descriDed and illu-strated in Fi~e 7 may be added. Also, throu~h-holes 77~78 and 79 between the circuits9 as described above~
may be provi~ed as necessary. Note that the throu~-holes may be between any number o~ circuits.
Since the power consumption o~ most board mounted~lectronic components is qulte modest, the heat generated during their operatlon is comparably small.
However, as packaging denslty becomes greater, more elaborate means for cooling must be provided. The present invention proYides for cooling of the multi-layer printed circult boards, as shown in Figure 10, by bonding high thermal condu~ti~ity layers of copper 2110y tO the circuit ~oil, as in Figure 4. This lzyer 25 Q~ copper alloy ~unctions to condurt heat ~rom the board. It ls within the scope of the invention to pro~de one or more layers of conducti~e material 80 with~n ~he multi-layer boardO Material 80 may be a solid strip o~ hlgh thermal conducti~lty material such as copper or copper alloy. Xt ~aY be desirable to use a copper alloy hav~ng an interface layer for i~pro~ed ~ondin~ to the glass 76. Naturally, an~
through-holes may reau~re insul~tion rrom the strip 80.
The con~uc~i~e materlal 80 may comprise one or ~ore tubular members e~bedded ln ~he glass ~o Dro~ide cool2nt passages. Again, lt is prefer2ble tha~ the 3~
., ~
copper tubing have a thin interface layer on its surface to bond to the glass.
Another important aspect of the present invention resides in the provision of a leadless ceramic chip carrier which can be directly mounted to the surface of a printed circuit board. This chip carrier substantially eliminates excessive stressing of the solder bond to the circui-t board which generally occurs during thermal cycling of the chip carrier-printed circuit board systems as described hereinabove. Referring to Figures 11 and 12, there is illustrated a leadless chip carrier 90 wherein a copper alloy 92 with a thin interface layer 93, such as A1203, provided on one surface thereof is substituted for the prior art alumina or beryllia ceramic. A glass 94 may be fused onto the interface layer as described above. It is, however, within the scope of the invention to use only the interface layer.
As can be seen in Figure 11, the copper alloy 92 may be shaped with a slight indentation 96, exaggerated in the drawing to better clarify the concept. It is within the scope of the present-invention to form the indentation in any desired configuration. A metal foil 98, which may be formed of thè same material as 92, having an interface layer 99, is bonded to the glass 94 or interface layer 93 and etched in any conventional manner to provide electrical leads 100. A chip 102 is preferably attached to the glass 94 by any conventional technique and lead wires connected between the circuitry on the chip and the leads 1009 ~30 The chip may be sealed within the indentation 96 by several techniques. Preferably, the sealing device 97 may be a cover plate 104 comprising a copper or copper base alloy having a thin interface layer thereon. Glass 95 is fused onto at least the edges of the cover 97~ This glass can be bonded to either -20- 120a6-~B
the interface layer 99 on the comp~nent 98 or to the glass 94 as required. The result i~ to hermetically seal t~e c~ip 102 in the leadless chip carrier gO.
~nother em~odimenk provides the se~l by ~illing the lndentatlon 96 with an epoxy. The epo~y will bond to the leads and the glass and provide an adequate but not necessar~ly hermetic seal.
~ eferrlng to Figure 13, the leadless chip carrler 90 is affi~ed to a typical printed circuit board 110.
This board has copper foil 112 and 114 separated by glass clo~h reinforced epo~y 116. A c~rcuit ls proY~ded on the foil 11~. ~ne leadless chip carrier may ~e applied direct~ onto the ~ircuitry of strip 112 ~y solder pads 118 between the lead 100 and the foil 112 i~ a co~Yentional manner.
Alloy C6381, the preferred material of alloy com~onents 92 and 98 Or the chlp carrier9 has ~
coe~ficient of thermal expansion of 17.1 ~ 10 ~C.
This is only 8 . 2% dlfferent from the coe~ficient o~
-20 thermal e2pansion o~ convent~onal glass cloth rein-forced epo~y which is 15.8 x 10 6/oC. This is a vast - improvement o~er chip carrier~ formed of alum~na cer~mic which ha~e a coef~icient o therm~l expanslon o~ 6.4 ~ 10-6fC~ i.e. aporoximztely 144p greater than 25 the thermal expansion o~ the zlumina ceramic. The result is a significant decre2se in the ~ormation of stress bet~een the solder, leads and circutt board due to thermal cyc ling .
As the number of individual Lunctions incorporated upon a slngle sil~con chip becomes larger, the amoun~
of heat generated requir~ng dissipation increzses accord~ngt~ Also, as the nu~.ber o~ ~unc~ions become -eater9 they are packed more closely`toether on ~he chip which ~urthe~ ma~nifies the D~oblem of heat - 35 dissipation. It ls 2 furth~r adYanta~e of the prosent inYention that the ther~al co~ductiv~ty of alloy C6381 is -21- 120~6-~
24 Btu~ft2J~t~hr/F. Thls is 131d greater than the thermal con~uctivlty of alumina o~ide (typlcally used for chip carrier~) which is 10.4 Btu~t2~ft/hr/F.
Also, the thermal resistance imposed between the chip and the e~ter$or means of heat dissipation is reduced because of the khinner sect~ons of the tou~her ~aterlal such as 6381 which are aDle to replace the thlcker, more fragile and brittle materials such as alumlna cer2mics~
It should ~e noted that in certain applicatlons, beryllla with a the~al conducti~ity of 100 Btu~ft2~ft/
hr/F is used as a substrate ~or better heat dissi-pation despite lts e~tremely high cost, Referring again to Figure 11, the copper alloy romponent ~2 with an interface layer may be clad upon copper or any high conductivity alloy~
Assuming that the composlte metal is appro~imately 10%
alloy C6381 clad upon gaz alloy C151~ the oYerall thermal conducti~ity is 196 Btu/ft2/~t/hr/F. This is 18~8% better than ~he thermal conductiYity of alumina ana 63~ better than that pro~ided by beryllia. In addl-tlon, there ls the additlonal ad~antage o~ a thinner chip-less carrier as comp~red to a thicker. alumina carrier~
~ e sllr~ace mounted hermetic chip carrier as described above an~ illustrated in Figure 12 will resolYe most of the normal problems associated wi~h the effect of thermal cycling on a chip ~arrier that is surface mounted to a conYent~ onal glass cloth reinforced epo:cy prin~ed circuit board. ~iowe~rer in some cases, 2 closer match of coef~icient of the~al ex~ansion may be required and/or greater heat`dissipation ca?ability may be necessary. In t~ese cases, a metal board confi~-uration Or the types descr~ bed hereinabove and ~llustrated iIl Flgures 2-~1 and 10 may be su~stituted for ~he conYent;ional printed circuit board.
In one embod~.T.ent, reduced ml smatch of ther~21 e~parlsion and ~. eal;er heat dissi~ation can be zchie~ed ~3~'~2 -22 1208~ l~B
b~ mounting a chlp carrier Or t~e type illustrated in ~lgures 11 and 12 o~ a prlor art printed circu~t board as shown ln Figure 2 where t~e core is copper or a hlgh conductl~ity copper alloy. An alloy may be desirable ~ greater stren~th is req~ired than may be provided w~th pure copper. A suitable plastic lnsulating layer 20 ls appropriately ~onded to the copper or copper alloy core and in turn, the prlnted c.ircult ~oil 22 is bonded to the lnsulating layer. The plastic must. be suitable ~or bonding with adhesi~es~ ha~e suikable dielectr~c .ch~racter~stics and the ahility to withstand processlng temperatures such as soldering. The thermally conductive plastics may be particularly usefu~ for the plastic layer. T~ese plastics typically 1~ eontatn metal powders to ~mproYe thelr thermal conduc-ti~lty while maintainlng dielectric properties since the metal powders are not in a contlnuous phase. Since the plastic is only thick enough to pro~ide the necessary dielectric properties, resistance to heat trans~er from the chip carrler to the high conductiYity copper or copper alloy core is minimized. Xt can be appreciated that the coefficient of thermal expansion of the metal board is essenti211y the same as that Or the glass coated chlp carrier and, thererore, stresses lnduced by thermal cycling of the system are substanr tially eliminated, This con~iguratlon is limited by the temperature capability o~ the plastic or plastics and th@ temperature resistance of the adhesi~es whlch are used in con~unction with the pl2stics.
To improve the m~ximum te.~per2ture c2~ability o~
the leadless chip carrier and pr~ntea circuit board combinakion, a printed circuit boa.d as illustrated in Figure 3 may be used in con~unction with the leadless chip carrier 90 shown in Figure 11. In thls config-uration, the metal core consists oi copper or a hi~h conductiYity copper alloy 26 to whicn is clad ~lloy 2~L3q~2 C6381 or an alternat~2 glass bondable copper alloy.
In turn, a printed circuit foll 32 consisting of a glass ~ondable copper alloy such as C6381 is bonded to the glass 38~ The alloy bonded to the C6381 may be selected from copper or high conductivity copper alloys so as to improve the electrical conductivity in the c1rcult or to provide optimum solderabillty character-istics. The system is completely inorganlc and will withstand temperatures much higher than systems with organic materials and further avoids va.rious modes of degradation to which organic materlals are susceptible.
An additi~re circuit may be substituted for photo-etched fc~l 48 in Figure 5O The circuit may be generated upon a glass coating applied to the interface layer on alloy C6381 or other glass bondable alloy core material 49 using con~entional techniques employed in generating addit~ve circuits.
~or exampleg the additi~e circui~ may be a pattern printed upon the surface o~ ~he glass with conductiYe ink and ~ired lnto pl~ce. It is also within the scope of t~e present invention for the alumina film which may be ~ormed by heating th~ alloy to be used as the d~electr~c layer separat~ng the metal core from the additiYe circuit~
Whereas an interface layer has been described as being ~ormed by separately heating the metal or alloy, it may be ~ormed in any manner such as during the process of bonding the me~al or alloy ~o the glass, ceramic or another ~e layer~
Whereas the chip carrier has been descrlbed as leadless~ lt is ~lso within the scope of the present invention to substitute a chip carrler with leads.
., ~
3~
Although the disclosure has thus far described embodiments using interface layers, it will be apparent to one skilled in the art that such layers are not necessary to meet the objectives of the invention.
For example, a preferred embodiment of the invention does not have any interface layer between the glass component and each of the metal or alloy component.
Another preferred embodiment of the invention com-prises at least one such interface layer made of a material other than refractory oxide, e.g. made of any oxide such as copper oxide..
It is apparent that there has been provided in accordance with this invention a composite, a chip carrier and a system of mounting the chip carrier with 1~ the composite which satisfies the objects, means, and advantages set forth hereinabove. While the invention has been described in combination with the embodiments thereof, it is evident that man~ alterna-tives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations as fall within the spirit and broad scope of the appended claims.
It is ~hought that the thicker multi-layer boards will 10 be suf~iciently r~gid. Where addltional rigidity ls required, grid relnforcement as descriDed and illu-strated in Fi~e 7 may be added. Also, throu~h-holes 77~78 and 79 between the circuits9 as described above~
may be provi~ed as necessary. Note that the throu~-holes may be between any number o~ circuits.
Since the power consumption o~ most board mounted~lectronic components is qulte modest, the heat generated during their operatlon is comparably small.
However, as packaging denslty becomes greater, more elaborate means for cooling must be provided. The present invention proYides for cooling of the multi-layer printed circult boards, as shown in Figure 10, by bonding high thermal condu~ti~ity layers of copper 2110y tO the circuit ~oil, as in Figure 4. This lzyer 25 Q~ copper alloy ~unctions to condurt heat ~rom the board. It ls within the scope of the invention to pro~de one or more layers of conducti~e material 80 with~n ~he multi-layer boardO Material 80 may be a solid strip o~ hlgh thermal conducti~lty material such as copper or copper alloy. Xt ~aY be desirable to use a copper alloy hav~ng an interface layer for i~pro~ed ~ondin~ to the glass 76. Naturally, an~
through-holes may reau~re insul~tion rrom the strip 80.
The con~uc~i~e materlal 80 may comprise one or ~ore tubular members e~bedded ln ~he glass ~o Dro~ide cool2nt passages. Again, lt is prefer2ble tha~ the 3~
., ~
copper tubing have a thin interface layer on its surface to bond to the glass.
Another important aspect of the present invention resides in the provision of a leadless ceramic chip carrier which can be directly mounted to the surface of a printed circuit board. This chip carrier substantially eliminates excessive stressing of the solder bond to the circui-t board which generally occurs during thermal cycling of the chip carrier-printed circuit board systems as described hereinabove. Referring to Figures 11 and 12, there is illustrated a leadless chip carrier 90 wherein a copper alloy 92 with a thin interface layer 93, such as A1203, provided on one surface thereof is substituted for the prior art alumina or beryllia ceramic. A glass 94 may be fused onto the interface layer as described above. It is, however, within the scope of the invention to use only the interface layer.
As can be seen in Figure 11, the copper alloy 92 may be shaped with a slight indentation 96, exaggerated in the drawing to better clarify the concept. It is within the scope of the present-invention to form the indentation in any desired configuration. A metal foil 98, which may be formed of thè same material as 92, having an interface layer 99, is bonded to the glass 94 or interface layer 93 and etched in any conventional manner to provide electrical leads 100. A chip 102 is preferably attached to the glass 94 by any conventional technique and lead wires connected between the circuitry on the chip and the leads 1009 ~30 The chip may be sealed within the indentation 96 by several techniques. Preferably, the sealing device 97 may be a cover plate 104 comprising a copper or copper base alloy having a thin interface layer thereon. Glass 95 is fused onto at least the edges of the cover 97~ This glass can be bonded to either -20- 120a6-~B
the interface layer 99 on the comp~nent 98 or to the glass 94 as required. The result i~ to hermetically seal t~e c~ip 102 in the leadless chip carrier gO.
~nother em~odimenk provides the se~l by ~illing the lndentatlon 96 with an epoxy. The epo~y will bond to the leads and the glass and provide an adequate but not necessar~ly hermetic seal.
~ eferrlng to Figure 13, the leadless chip carrler 90 is affi~ed to a typical printed circuit board 110.
This board has copper foil 112 and 114 separated by glass clo~h reinforced epo~y 116. A c~rcuit ls proY~ded on the foil 11~. ~ne leadless chip carrier may ~e applied direct~ onto the ~ircuitry of strip 112 ~y solder pads 118 between the lead 100 and the foil 112 i~ a co~Yentional manner.
Alloy C6381, the preferred material of alloy com~onents 92 and 98 Or the chlp carrier9 has ~
coe~ficient of thermal expansion of 17.1 ~ 10 ~C.
This is only 8 . 2% dlfferent from the coe~ficient o~
-20 thermal e2pansion o~ convent~onal glass cloth rein-forced epo~y which is 15.8 x 10 6/oC. This is a vast - improvement o~er chip carrier~ formed of alum~na cer~mic which ha~e a coef~icient o therm~l expanslon o~ 6.4 ~ 10-6fC~ i.e. aporoximztely 144p greater than 25 the thermal expansion o~ the zlumina ceramic. The result is a significant decre2se in the ~ormation of stress bet~een the solder, leads and circutt board due to thermal cyc ling .
As the number of individual Lunctions incorporated upon a slngle sil~con chip becomes larger, the amoun~
of heat generated requir~ng dissipation increzses accord~ngt~ Also, as the nu~.ber o~ ~unc~ions become -eater9 they are packed more closely`toether on ~he chip which ~urthe~ ma~nifies the D~oblem of heat - 35 dissipation. It ls 2 furth~r adYanta~e of the prosent inYention that the ther~al co~ductiv~ty of alloy C6381 is -21- 120~6-~
24 Btu~ft2J~t~hr/F. Thls is 131d greater than the thermal con~uctivlty of alumina o~ide (typlcally used for chip carrier~) which is 10.4 Btu~t2~ft/hr/F.
Also, the thermal resistance imposed between the chip and the e~ter$or means of heat dissipation is reduced because of the khinner sect~ons of the tou~her ~aterlal such as 6381 which are aDle to replace the thlcker, more fragile and brittle materials such as alumlna cer2mics~
It should ~e noted that in certain applicatlons, beryllla with a the~al conducti~ity of 100 Btu~ft2~ft/
hr/F is used as a substrate ~or better heat dissi-pation despite lts e~tremely high cost, Referring again to Figure 11, the copper alloy romponent ~2 with an interface layer may be clad upon copper or any high conductivity alloy~
Assuming that the composlte metal is appro~imately 10%
alloy C6381 clad upon gaz alloy C151~ the oYerall thermal conducti~ity is 196 Btu/ft2/~t/hr/F. This is 18~8% better than ~he thermal conductiYity of alumina ana 63~ better than that pro~ided by beryllia. In addl-tlon, there ls the additlonal ad~antage o~ a thinner chip-less carrier as comp~red to a thicker. alumina carrier~
~ e sllr~ace mounted hermetic chip carrier as described above an~ illustrated in Figure 12 will resolYe most of the normal problems associated wi~h the effect of thermal cycling on a chip ~arrier that is surface mounted to a conYent~ onal glass cloth reinforced epo:cy prin~ed circuit board. ~iowe~rer in some cases, 2 closer match of coef~icient of the~al ex~ansion may be required and/or greater heat`dissipation ca?ability may be necessary. In t~ese cases, a metal board confi~-uration Or the types descr~ bed hereinabove and ~llustrated iIl Flgures 2-~1 and 10 may be su~stituted for ~he conYent;ional printed circuit board.
In one embod~.T.ent, reduced ml smatch of ther~21 e~parlsion and ~. eal;er heat dissi~ation can be zchie~ed ~3~'~2 -22 1208~ l~B
b~ mounting a chlp carrier Or t~e type illustrated in ~lgures 11 and 12 o~ a prlor art printed circu~t board as shown ln Figure 2 where t~e core is copper or a hlgh conductl~ity copper alloy. An alloy may be desirable ~ greater stren~th is req~ired than may be provided w~th pure copper. A suitable plastic lnsulating layer 20 ls appropriately ~onded to the copper or copper alloy core and in turn, the prlnted c.ircult ~oil 22 is bonded to the lnsulating layer. The plastic must. be suitable ~or bonding with adhesi~es~ ha~e suikable dielectr~c .ch~racter~stics and the ahility to withstand processlng temperatures such as soldering. The thermally conductive plastics may be particularly usefu~ for the plastic layer. T~ese plastics typically 1~ eontatn metal powders to ~mproYe thelr thermal conduc-ti~lty while maintainlng dielectric properties since the metal powders are not in a contlnuous phase. Since the plastic is only thick enough to pro~ide the necessary dielectric properties, resistance to heat trans~er from the chip carrler to the high conductiYity copper or copper alloy core is minimized. Xt can be appreciated that the coefficient of thermal expansion of the metal board is essenti211y the same as that Or the glass coated chlp carrier and, thererore, stresses lnduced by thermal cycling of the system are substanr tially eliminated, This con~iguratlon is limited by the temperature capability o~ the plastic or plastics and th@ temperature resistance of the adhesi~es whlch are used in con~unction with the pl2stics.
To improve the m~ximum te.~per2ture c2~ability o~
the leadless chip carrier and pr~ntea circuit board combinakion, a printed circuit boa.d as illustrated in Figure 3 may be used in con~unction with the leadless chip carrier 90 shown in Figure 11. In thls config-uration, the metal core consists oi copper or a hi~h conductiYity copper alloy 26 to whicn is clad ~lloy 2~L3q~2 C6381 or an alternat~2 glass bondable copper alloy.
In turn, a printed circuit foll 32 consisting of a glass ~ondable copper alloy such as C6381 is bonded to the glass 38~ The alloy bonded to the C6381 may be selected from copper or high conductivity copper alloys so as to improve the electrical conductivity in the c1rcult or to provide optimum solderabillty character-istics. The system is completely inorganlc and will withstand temperatures much higher than systems with organic materials and further avoids va.rious modes of degradation to which organic materlals are susceptible.
An additi~re circuit may be substituted for photo-etched fc~l 48 in Figure 5O The circuit may be generated upon a glass coating applied to the interface layer on alloy C6381 or other glass bondable alloy core material 49 using con~entional techniques employed in generating addit~ve circuits.
~or exampleg the additi~e circui~ may be a pattern printed upon the surface o~ ~he glass with conductiYe ink and ~ired lnto pl~ce. It is also within the scope of t~e present invention for the alumina film which may be ~ormed by heating th~ alloy to be used as the d~electr~c layer separat~ng the metal core from the additiYe circuit~
Whereas an interface layer has been described as being ~ormed by separately heating the metal or alloy, it may be ~ormed in any manner such as during the process of bonding the me~al or alloy ~o the glass, ceramic or another ~e layer~
Whereas the chip carrier has been descrlbed as leadless~ lt is ~lso within the scope of the present invention to substitute a chip carrler with leads.
., ~
3~
Although the disclosure has thus far described embodiments using interface layers, it will be apparent to one skilled in the art that such layers are not necessary to meet the objectives of the invention.
For example, a preferred embodiment of the invention does not have any interface layer between the glass component and each of the metal or alloy component.
Another preferred embodiment of the invention com-prises at least one such interface layer made of a material other than refractory oxide, e.g. made of any oxide such as copper oxide..
It is apparent that there has been provided in accordance with this invention a composite, a chip carrier and a system of mounting the chip carrier with 1~ the composite which satisfies the objects, means, and advantages set forth hereinabove. While the invention has been described in combination with the embodiments thereof, it is evident that man~ alterna-tives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations as fall within the spirit and broad scope of the appended claims.
Claims (7)
1. A composite 24 adapted to be a printed circuit board system comprising:
a first metal or alloy component 26;
a second metal or alloy component 32;
a glass or ceramic component 38 disposed between said first component 26 and said second com-ponent 32 for bonding the first and second components to each other, said glass or ceramic component 38 further having a coefficient of thermal expansion of at least about 160 x 10-7 in/in/°C, said coefficient of thermal expansion being closely matched to the coefficient of thermal expansion of said first and second components whereby thermal stress between the first, second and glass or ceramic components may be substantially eliminated.
a first metal or alloy component 26;
a second metal or alloy component 32;
a glass or ceramic component 38 disposed between said first component 26 and said second com-ponent 32 for bonding the first and second components to each other, said glass or ceramic component 38 further having a coefficient of thermal expansion of at least about 160 x 10-7 in/in/°C, said coefficient of thermal expansion being closely matched to the coefficient of thermal expansion of said first and second components whereby thermal stress between the first, second and glass or ceramic components may be substantially eliminated.
2. The composite as in claim 1 comprising said first and second metal or alloy components being copper or a copper alloy.
3. The composite as in claim 2 comprising said first copper or copper base alloy component being a first thin foil 50 having a first electrical circuit pattern thereon.
4. The composite as in claim 3 comprising said second copper or copper base alloy component being a second thin foil 52 having a second electrical circuit pattern thereon.
5. The composite as in claim 4 further compris-ing conductive means 56 disposed in said glass or ceramic component and extending between said first and second components for electrically interconnecting the first and second electrical circuit patterns.
6. A process of forming a composite 24 adapted to be a printed circuit board system comprising the steps of:
providing a first metal or alloy component 26;
providing a second metal or alloy component 32;
disposing a glass or ceramic component 38 between said first and second components, said glass or ceramic component having a coefficient of thermal expansion of at least about 160 x 10-7 in/in/°C, said coefficient of thermal expansion being closely matched to the coefficient of thermal expansion of said first and second components whereby thermal stress between the first, second and glass or ceramic components may be substantially eliminated; and bonding said first, second and glass or ceramic components together.
providing a first metal or alloy component 26;
providing a second metal or alloy component 32;
disposing a glass or ceramic component 38 between said first and second components, said glass or ceramic component having a coefficient of thermal expansion of at least about 160 x 10-7 in/in/°C, said coefficient of thermal expansion being closely matched to the coefficient of thermal expansion of said first and second components whereby thermal stress between the first, second and glass or ceramic components may be substantially eliminated; and bonding said first, second and glass or ceramic components together.
7. The process as in claim 6 further comprising the step of disposing one or more conductive devices 56 in said glass or ceramic component for electrically interconnecting the first and second components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000439317A CA1213072A (en) | 1983-10-19 | 1983-10-19 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000439317A CA1213072A (en) | 1983-10-19 | 1983-10-19 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1213072A true CA1213072A (en) | 1986-10-21 |
Family
ID=4126325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000439317A Expired CA1213072A (en) | 1983-10-19 | 1983-10-19 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1213072A (en) |
-
1983
- 1983-10-19 CA CA000439317A patent/CA1213072A/en not_active Expired
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