CA1209278A - Process for removing insulating coatings from substrates - Google Patents
Process for removing insulating coatings from substratesInfo
- Publication number
- CA1209278A CA1209278A CA000477454A CA477454A CA1209278A CA 1209278 A CA1209278 A CA 1209278A CA 000477454 A CA000477454 A CA 000477454A CA 477454 A CA477454 A CA 477454A CA 1209278 A CA1209278 A CA 1209278A
- Authority
- CA
- Canada
- Prior art keywords
- substrate
- wire
- aligned
- high energy
- recited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01039—Yttrium [Y]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/20—Parameters
- H01L2924/207—Diameter ranges
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
ABSTRACT
A process for removing insulating coatings from substrates used for interconnecting components in which a filament is applied and affixed to a base in a pre-programmed pattern, the base surface and applied filaments are coated with a coating and the coating is hardened to form a sub-stantially flat surface over the base and filaments. The coated base is then positioned on a table movable along "x"
and "y" axes and the coated base is positioned under a high energy beam at pre-programmed points on the applied filament pattern and access openings are formed in the coating on the base at such points to expose the filament at each such point so that the exposed filament can be interfaced with the exposed surface of the coated base and articles for mounting and interconnecting components formed thereby.
A process for removing insulating coatings from substrates used for interconnecting components in which a filament is applied and affixed to a base in a pre-programmed pattern, the base surface and applied filaments are coated with a coating and the coating is hardened to form a sub-stantially flat surface over the base and filaments. The coated base is then positioned on a table movable along "x"
and "y" axes and the coated base is positioned under a high energy beam at pre-programmed points on the applied filament pattern and access openings are formed in the coating on the base at such points to expose the filament at each such point so that the exposed filament can be interfaced with the exposed surface of the coated base and articles for mounting and interconnecting components formed thereby.
Description
~2~
This invention relates to a process for removing insulating components from substrates which include filament-ary members and which support and interconnect components.
This application is a divisional application of Canadian application Serial No. 410,500 filed August 31, 1982.
U.S. Patent Nos. 3,674,602 and 3,674,914, both dated July 4, 1972 and applicant's Canadian Patent No. 1,102,29~, issued June 9, 1981, disclose and describe circuit boards employing filamentary members of wire, and methods and apparatus for making such boards. In such disclosures and descriptions, a wire is scribed onto the energy actuatable surface of an insulated base or board. The wire is scribed onto the surface in a predetermined pattern with a head. The head is energized, activates the surface as the wire is brought into contact there-with and bonds the wire to the board or base surface. The movement of the board, head and wire and energizing of the head are controlled in such fashion that the wire is scribed and fixed to the board in a precise pattern. The wire is cut and subsequently drilled through to expose a surface for metalli-zation. The cut wire and drilled hole are metallized to form aterminal hole in the board electrically interconnected by the wire. These electrically interconnected terminal holes may then receive component leads which may be attached and connected to the board, such as, by soldering. A precise, electronic package is thus formed.
The replacement of hand wiring by such electronic packaging using wire scribed and printed circuit boards has reduced the size and weight of electronic equipment. Further reductions have been achieved through the development and general : - 2 kh/ ~-
This invention relates to a process for removing insulating components from substrates which include filament-ary members and which support and interconnect components.
This application is a divisional application of Canadian application Serial No. 410,500 filed August 31, 1982.
U.S. Patent Nos. 3,674,602 and 3,674,914, both dated July 4, 1972 and applicant's Canadian Patent No. 1,102,29~, issued June 9, 1981, disclose and describe circuit boards employing filamentary members of wire, and methods and apparatus for making such boards. In such disclosures and descriptions, a wire is scribed onto the energy actuatable surface of an insulated base or board. The wire is scribed onto the surface in a predetermined pattern with a head. The head is energized, activates the surface as the wire is brought into contact there-with and bonds the wire to the board or base surface. The movement of the board, head and wire and energizing of the head are controlled in such fashion that the wire is scribed and fixed to the board in a precise pattern. The wire is cut and subsequently drilled through to expose a surface for metalli-zation. The cut wire and drilled hole are metallized to form aterminal hole in the board electrically interconnected by the wire. These electrically interconnected terminal holes may then receive component leads which may be attached and connected to the board, such as, by soldering. A precise, electronic package is thus formed.
The replacement of hand wiring by such electronic packaging using wire scribed and printed circuit boards has reduced the size and weight of electronic equipment. Further reductions have been achieved through the development and general : - 2 kh/ ~-
2'22~ p ~ .
1 ~2~ 8 1 ¦ availability of integrated circuits. In such integrated circuits,l a plurality of components performing different electronic func-tions are formed on a semiconductor surface which is incorporatedinto a microelectronic package. Such packages, commonly called dual-in-line packages, embody leads through.which electrical contact may be made with the integrated circuit and which also I serve to mount and connect the package to the holes in the wire ¦ scribed or printed circuit board. The leads of such dual-in-line !
I packages are commonly spaced 100 mils apart on two parallel rows ¦ extending from the plastic or ceramic body of the package. The I rows may be 400 or more mils apart and the packag~s may often be ¦~ interconnected on low density wire scribed or printed circuit boards with conductors spaced on a 50 mil grid pattern.
ll Whilst the dual-in-line package with leads on 100 mil ~I centers and boards having 50 mil grid pa~terns have found exten- I
¦~ sive use, the desire to reduce the size and weight of electronic equipment and to increase the number of functions per unit volume~
I has assumed increasing importance. Foremost in t'his drive for ¦l more electronic functions in less space are the designers and ~ makers of integrated ircuits. One of the results of increasing I
the number of functions on the integrated circuit is to increase ¦
the number of leads per microelectronic package. In complex , integrated circuirs with many leads, the geometry of the dual-in-' il line package, with its two rows of leads on 100 mil centers, makes, 25 1l the package excessively large in relation to the size of the integrated circuit. It also degrades the electrical performance of the circuit and makes insertion and removal from the printed , circuit board difficult.
,1 1 30 ,1 , . , . .
, 3 222~ ~2~27~
1 New, more compact, microelectronic packages have been developed to accommoda~e these complex integxated circuits. One I
such family of packages, commonly called chip carriers, may be surface mounted rather than being connected by leads passing through the board. These packages are square and have terminals on all four edges rather than on two sides as in the dual-in-line packages. The terminals are spaced on centers of 50 mils, 40 mils or less, thus substantially reducing the area oi the package as compared to the dual in-line package. This substantially increases the number of terminals per unit area.
The reduction in package area made posslble by the chip carrier, substantially increases the number of microelectronic packages whieh may be mounted and electrically connected by a circuit board or interconnection substrate of given area.
However, such increase in number of packages or compo-nent package density and closer terminal spacing increases the terminal density reyuirement on the board or substrate and the heat density of the system This increased termlnal density generates and requires higher conductor density. Contact pads, rather than through holes, are employed on the surface of the substrate to provide higher conductor density. Electrical contact between such sur~ace pads and the subst-ate conductors can be made in dimensions which approach that of the conductor itself.
The instant inventiou is particularly adapted to meeting the high density terminal and high density conductor requirements of chip carriers and unpackaged in.tegrated circuit chips. At the same time, the instant invention allows substrate cores to be ~l employed which possess particular properties such as good heat 1i dissipation, low cost or match the coefficient of thermal expansion with the chip carrier or integrated circuit materials.
Solder joint failure induced by temperature stress is avoided.
In the substrates used with this invention filaments are applied or scribed onto a carrier. The filaments or the carrier might have an energizable adhesive surface for bonding the filaments to the carrier. The filaments are applied or scribed to the carrier in a predetermined pattern with apparatus such as that shown and described in the aforementioned '602 or '914 U.S. patents or Canadian Patent No. 1,102,924. The filaments may be optical fibers or preinsulated wires, such as copper wire of about 2 to 4 mil diameter.
The filaments are bonded to the carrier in a high density horizontal and vertical grid with grid center lines spaced about 12.5 mils apart. A layer of material is then applied, preferably in the form of liquid, over the filaments previously bonded to the carrier in a manner so as not to move or disturb the position of the filaments previously applied relative to each other or the carrier. The liquid forms a smooth, planar surface over the carrier and the filaments.
Movement of the Eiiaments mi~ht adversely affect subsequent processing and the utility of the article and, thus, is avoided.
The liquid material applied should be capable of being hardened at room temperature or at low temperature; for example, below 100C so as to avoid temperature excursions which might also adversely disturb the position of the filaments. Preferably the material is hardened at room temperature. This may be achieved by room temperature curing agents or kh/~J
~22~ 78 1 by ultra violet radiation curing.
The surface of the applied liquid layer may be brought ¦
into temporary close contact with and the applied liquid leveled by the surface of a material which will not adhere to the surface~
of the llquid layer and the hardened surface formed thereby.
Such temporary close contact surface, such as shown and described in U.S. Patent No. 3,607,380, dated September 21, 1971, levels the liquid layer surface without disturbing the filaments there-¦ in. A substantially planar surface, with ~h~ filaments embedded therein, is thus formed. Leveling might also be accomplished with a doctor blade, roller or squeegee so long as the filaments I
are not mo~ed or disturbed~ ¦
Where the filamentary member is a wire, the hardenPd, planar surface is preferably capable of adhesion promotion by chemical or mechanical means or by ion bomb,irdment so as to form micropores or surface roughness to provide anchoring sites for I¦ the deposition of conductive material by electroless plating, i vapor deposition or other appropriate methods, at a later stage 1 of processing. This may be achieved by the inclusion of l preferentially etchable materials such as rubber or polyether-il sulfone, in the surface of the hardened, planar coatlng.
'¦ Addltional level or levels of filament grids may be I added.
¦ The carrier to which the filaments have been affixed ¦ and the planar material applied and hardened is attached to a ¦l table movable in a controlled pattern along 'X' and `Y' axes so 1~ as to locate preprogrammed points on the carrier under a high 'I -6-272~ f~,2 7~
l energy beam, such as a coherent laser~ The beam is directed perpendicular to the table ~nd to the carrier mounted thereon.
Alternatively, the carrier may be fixed and the beam moved in ~ and ~Y~ axes The location of the filaments in the hardened, ¦ planar materiel may be targeted optically so as to substanti211v eliminate location errors. The carrier is moved relative to the high energy beam so that the desired filament is in line with the beam at a predetermined point. The filament is then exposed by the bea~ at sucn point. Preferably, if the filament is ¦ metallic, a high energy beam, such as a C02 laser is used. ~nen ¦ the beam is aliOned with the desired predetermined point on the I filament, the beam is pulsed or modulated to direct energy at the filament so as to vaporize and remove the hardened material and the fila~ent insulation, leaving a precisely formed cavity with the filament substantially exposed. This is achieved with a C02 laser using the contrast between the reflective power of the metallic ~ilament to C02 laser light and the absorbative power of the largely organic insulation and hardened sur-ace coating material applied and hardened over the filaments on the carrier.
In addition to a high energy beam, such as a C02 laser~
the hardened material and wire insulation mi~htbe removed with ¦ other suitable lasers or controlled depth mechanical drills, bv a modula~ed stream of abrasive particles, a water jet or stream of chemicals or solvents. In any event, cavities of precise size, not substantially larger than the filament and no larger than that required to in~erface the filament with the surface should be formed. The hardened, planar material and ~ _7_ ;~22 q ~ 12~ 8 l insulation is removed leaving the filament substantially intact and exposed, so that its conductive characteristics are not impaired. With a wire filament size of 2 to 4 mils, the diameter of the cavity would be between 6 and 12 mils.
When all the predetermined filament points have been exposed and filament access cavities have been formed, the circuit might be finished in conventional manner. Where the filaments are metal wires, this is accomplished by adhesion promotion of the surface followed by sensitizing the cavities, exposed filaments and surface such as with a catalyst and elec-trolessly depositing metal, for example, copper. This may be carried out selectively to form surface features or metal may be deposited over the whole surface and features formed by subse-quent masking and etching. Additional thickness of metal may be built up by electroplating and surface features formed by conventional semi-additive means.
Durlng the plating operation metal is deposited on the walls of the cavities and on the surface and makes intimate contact with the exposed surface of the filament to interface the¦
~0 filament with the external surface. Metal may also be deposited in cavities which do no interface with filaments, but interface with other conductive fea~ures, such as pads, or power and ground planes, at other levels in the circuit. Alternatively, means other than plating may be used to interface the filament or other conductive feature to the external surface. Such means might Il include sputterir.g o~ metal, metal spraying, conduc;lve ?olvmeric pastes, solder pastes and conventional solder. In the case wnere the filament is not a metal wire, means appropriate and com?a~ibl ., , 222-lGQ ~ 12Q~Z~78 1 with the filament conductor may be used to interface the filament to the external surface. For example, an optoelectronic means might be employed to interface optical filaments with electronic components.
In the instant invention, the high density interconnec-tion circuit may be formed and processed on a carrier which will ' form an integral part of the article or may be formed, processed ¦
and then removed from the carrier. Where the carrier is to remain as an integral part of the article processed and formed, the carrier should, of course, be of a material suitable for ~he article and dimensionally stable for the process.
Where t for example, the article to be formed is to include metal filamen~s and a metal base, a dielectric film or coating would first be applied ~o the metal base. Such film or coating may include isolated metal pads at the points where ca~ities are to be formed to deflect the high ener~y beam and avoid short circuiting to the metal base.
Where the formed circuit after processing is to be removed from the carrier and the carrier reused, the circuit is formed, built up and processed on ~he carrier and then peeled off and rPmoved. The formed circuit, pealed from the carrier might then be laminated to a base or formed circuits might be built up or laminated one over the other to form a multi-level . circuit.
Where, for example, metal filaments are to be employed, and the article, ~ormed and processed, is ~o be removed from the carrier, the carr er may be of s~ainless steel plated with lightl~-; adherent copper. Other lightly adheren~ combinations of carrier ., .
9_ ~$~7~
and plating might be emp:Loyed. The article is built up and processed on the carrier and, with the plating, is peeled from the carrier. After removal from the carrier the plating on the article may be used in the formation of conductive features by conventional processes.
The high conductor densitv which is achievable with the filament yrid geometry of about 12 1/2 mils and more particularly with the small diameter of the filament access cavities of the instant invention, enables complex interconnect patterns to be executed with a minimum of levels. The circuit may therefore be manufactured with a thickness of about 10 to 20 mils.
The thinness of the circuit thus formed or laminated to a base allows the components to be positioned in close proximity to that base. This allows properties of the base such as coefficient of thermal expansion and heat dissipation to be imparted to the components more readily than in the instance of thicker, lower density, multiple level circuits.
The problems of heat and heat dissipation are alleviated.
Specifically, the invention relates to a process for removing insulating coatings from substrates and substantially exposing circuit wires thèreon, the steps comprising: a) affixing a substrate having circuit wires thereon on a table movable alon~ "~" and "y" axes; b) moving the table and the substrate along the axes to align the circuit wire at a predetermined point in the circuit board with a high energy beam source; c) and, with the substrate so aligned, energizing the high energy beam source; and kh/ ~,~
~?~7~
d) volatilizing the insulating material in the subs-trate area in alignment with the beam source to substantially expose the aligned circuit wire.
The present invention will be more fully described and will be better understood from the followin~ description of preferred embodiments of the invention taken with the appended drawings in which:
Figure 1 is a top plan view of an interconnection substrate useful with the present invention;
Figure 2 is an exploded view, in perspective, of a chip carrier, chip, and cover, to which the invention is particularly adapted;
Figure 3 is a perspective view of the chip carrier of Figure 2 when viewed from the bottom;
- lOa -- kh/
222~
~ 7~
1 Figure 4 is a sectional view through a section of an interconnection substrate showing the preinsula~ed conductor before high energy, ablation of the coating and insulation;
Figure 5 is a top plan view of the section of Figure 4;
Figure 6 is a sectional view similar to Figure 4 but showing the exposed conductor after formation of the interfacing ¦
cavit;
Figure 7 is a top plan view of the section of Figure 6;j F'igure 8 is a sectional view similar to Figures 4 and 6 but showing the conductor and conductor pad after plating;
Figure 9 is a top plan view of the section of Figure 8;~
Figure 10 is a schematic plan view of an apparatus for carrying out part of the process and for producing the caviti~s of the instan~ invention;
^ Figure 11 is a side view, in elevation, of the schema-¦ tic apparatus of Figure 10;
Figure 12 is a sectional view oi the interconnection ¦ substrate of the lnstant invention showing the interconnection I between the conductor or wire, a chip carrier and chip;
I Figure 13 is a sectional view of the interconnection ¦ substrate of one embodiment of th~ instant invention showing the , circuit with a metal base and surface conductor;
Figure 14 is a view similar to Figure 12 but showing I interconnection between the conductor or wire and a chip and ¦I without the chip carrier;
Figure 15 is a view similar to Figure 4 but showing the embodlmenL in which the circuit, when com~leted, is to be removec , from the metal base;
Il 2~2-]~ 7~
1 Figure 16 is a view similar to Figur~ 15 but showing the exposed conductor after formation of the cavity; and Figure 17 is a view similar to Figures 15 and 16 but showing the conductor and conductor pad after plating, with the processing metal base removed and the clrcuit bonded to permanent base.
Referring to the drawings, particularly Figure 1, the circuit generally designated 2, includes the interconnection substrate 4 having mounted thereon chip carrier, chip and cover assemblies 12. Chip carriers 12 are connected to surface pads and may be connected to power and ground bus bars 14, 16, formed on the surface of substrate 4.
Chip carriers 12 vary in size, depending upon the com-! plexity and size of the chip carried therein. As best shown~in Figure 2, chip carriers 12 is made up of a body 6, having a recessed center top portion 20 and a flat bottom portion 22, Figure 3. For purposes more apparent later herein, recessed center top portion 20 has a plurality of contacts 24 spaced there-around. Bottom 22 and the sides of body 6 are provided with a plurality of contacts 26 spaced around the carrier sides and extending onto bottom surface 22, Figure 3. Chip 10, Figure 2, has a plurality of contacts 30 extending around the top edge of the chip.
Chip 10 is assembled in recess 20 or body 6 with contac~
30 of chip lQ connected to contacts 24 in recess 20 of body 6.
With chip 10 in recess 20 and contacts 30 and 24 connected, cover 32, Figure 2, is placed over recess 20, covering the recess and lithe chip 10 thereln. As will be later described, contacts 26
1 ~2~ 8 1 ¦ availability of integrated circuits. In such integrated circuits,l a plurality of components performing different electronic func-tions are formed on a semiconductor surface which is incorporatedinto a microelectronic package. Such packages, commonly called dual-in-line packages, embody leads through.which electrical contact may be made with the integrated circuit and which also I serve to mount and connect the package to the holes in the wire ¦ scribed or printed circuit board. The leads of such dual-in-line !
I packages are commonly spaced 100 mils apart on two parallel rows ¦ extending from the plastic or ceramic body of the package. The I rows may be 400 or more mils apart and the packag~s may often be ¦~ interconnected on low density wire scribed or printed circuit boards with conductors spaced on a 50 mil grid pattern.
ll Whilst the dual-in-line package with leads on 100 mil ~I centers and boards having 50 mil grid pa~terns have found exten- I
¦~ sive use, the desire to reduce the size and weight of electronic equipment and to increase the number of functions per unit volume~
I has assumed increasing importance. Foremost in t'his drive for ¦l more electronic functions in less space are the designers and ~ makers of integrated ircuits. One of the results of increasing I
the number of functions on the integrated circuit is to increase ¦
the number of leads per microelectronic package. In complex , integrated circuirs with many leads, the geometry of the dual-in-' il line package, with its two rows of leads on 100 mil centers, makes, 25 1l the package excessively large in relation to the size of the integrated circuit. It also degrades the electrical performance of the circuit and makes insertion and removal from the printed , circuit board difficult.
,1 1 30 ,1 , . , . .
, 3 222~ ~2~27~
1 New, more compact, microelectronic packages have been developed to accommoda~e these complex integxated circuits. One I
such family of packages, commonly called chip carriers, may be surface mounted rather than being connected by leads passing through the board. These packages are square and have terminals on all four edges rather than on two sides as in the dual-in-line packages. The terminals are spaced on centers of 50 mils, 40 mils or less, thus substantially reducing the area oi the package as compared to the dual in-line package. This substantially increases the number of terminals per unit area.
The reduction in package area made posslble by the chip carrier, substantially increases the number of microelectronic packages whieh may be mounted and electrically connected by a circuit board or interconnection substrate of given area.
However, such increase in number of packages or compo-nent package density and closer terminal spacing increases the terminal density reyuirement on the board or substrate and the heat density of the system This increased termlnal density generates and requires higher conductor density. Contact pads, rather than through holes, are employed on the surface of the substrate to provide higher conductor density. Electrical contact between such sur~ace pads and the subst-ate conductors can be made in dimensions which approach that of the conductor itself.
The instant inventiou is particularly adapted to meeting the high density terminal and high density conductor requirements of chip carriers and unpackaged in.tegrated circuit chips. At the same time, the instant invention allows substrate cores to be ~l employed which possess particular properties such as good heat 1i dissipation, low cost or match the coefficient of thermal expansion with the chip carrier or integrated circuit materials.
Solder joint failure induced by temperature stress is avoided.
In the substrates used with this invention filaments are applied or scribed onto a carrier. The filaments or the carrier might have an energizable adhesive surface for bonding the filaments to the carrier. The filaments are applied or scribed to the carrier in a predetermined pattern with apparatus such as that shown and described in the aforementioned '602 or '914 U.S. patents or Canadian Patent No. 1,102,924. The filaments may be optical fibers or preinsulated wires, such as copper wire of about 2 to 4 mil diameter.
The filaments are bonded to the carrier in a high density horizontal and vertical grid with grid center lines spaced about 12.5 mils apart. A layer of material is then applied, preferably in the form of liquid, over the filaments previously bonded to the carrier in a manner so as not to move or disturb the position of the filaments previously applied relative to each other or the carrier. The liquid forms a smooth, planar surface over the carrier and the filaments.
Movement of the Eiiaments mi~ht adversely affect subsequent processing and the utility of the article and, thus, is avoided.
The liquid material applied should be capable of being hardened at room temperature or at low temperature; for example, below 100C so as to avoid temperature excursions which might also adversely disturb the position of the filaments. Preferably the material is hardened at room temperature. This may be achieved by room temperature curing agents or kh/~J
~22~ 78 1 by ultra violet radiation curing.
The surface of the applied liquid layer may be brought ¦
into temporary close contact with and the applied liquid leveled by the surface of a material which will not adhere to the surface~
of the llquid layer and the hardened surface formed thereby.
Such temporary close contact surface, such as shown and described in U.S. Patent No. 3,607,380, dated September 21, 1971, levels the liquid layer surface without disturbing the filaments there-¦ in. A substantially planar surface, with ~h~ filaments embedded therein, is thus formed. Leveling might also be accomplished with a doctor blade, roller or squeegee so long as the filaments I
are not mo~ed or disturbed~ ¦
Where the filamentary member is a wire, the hardenPd, planar surface is preferably capable of adhesion promotion by chemical or mechanical means or by ion bomb,irdment so as to form micropores or surface roughness to provide anchoring sites for I¦ the deposition of conductive material by electroless plating, i vapor deposition or other appropriate methods, at a later stage 1 of processing. This may be achieved by the inclusion of l preferentially etchable materials such as rubber or polyether-il sulfone, in the surface of the hardened, planar coatlng.
'¦ Addltional level or levels of filament grids may be I added.
¦ The carrier to which the filaments have been affixed ¦ and the planar material applied and hardened is attached to a ¦l table movable in a controlled pattern along 'X' and `Y' axes so 1~ as to locate preprogrammed points on the carrier under a high 'I -6-272~ f~,2 7~
l energy beam, such as a coherent laser~ The beam is directed perpendicular to the table ~nd to the carrier mounted thereon.
Alternatively, the carrier may be fixed and the beam moved in ~ and ~Y~ axes The location of the filaments in the hardened, ¦ planar materiel may be targeted optically so as to substanti211v eliminate location errors. The carrier is moved relative to the high energy beam so that the desired filament is in line with the beam at a predetermined point. The filament is then exposed by the bea~ at sucn point. Preferably, if the filament is ¦ metallic, a high energy beam, such as a C02 laser is used. ~nen ¦ the beam is aliOned with the desired predetermined point on the I filament, the beam is pulsed or modulated to direct energy at the filament so as to vaporize and remove the hardened material and the fila~ent insulation, leaving a precisely formed cavity with the filament substantially exposed. This is achieved with a C02 laser using the contrast between the reflective power of the metallic ~ilament to C02 laser light and the absorbative power of the largely organic insulation and hardened sur-ace coating material applied and hardened over the filaments on the carrier.
In addition to a high energy beam, such as a C02 laser~
the hardened material and wire insulation mi~htbe removed with ¦ other suitable lasers or controlled depth mechanical drills, bv a modula~ed stream of abrasive particles, a water jet or stream of chemicals or solvents. In any event, cavities of precise size, not substantially larger than the filament and no larger than that required to in~erface the filament with the surface should be formed. The hardened, planar material and ~ _7_ ;~22 q ~ 12~ 8 l insulation is removed leaving the filament substantially intact and exposed, so that its conductive characteristics are not impaired. With a wire filament size of 2 to 4 mils, the diameter of the cavity would be between 6 and 12 mils.
When all the predetermined filament points have been exposed and filament access cavities have been formed, the circuit might be finished in conventional manner. Where the filaments are metal wires, this is accomplished by adhesion promotion of the surface followed by sensitizing the cavities, exposed filaments and surface such as with a catalyst and elec-trolessly depositing metal, for example, copper. This may be carried out selectively to form surface features or metal may be deposited over the whole surface and features formed by subse-quent masking and etching. Additional thickness of metal may be built up by electroplating and surface features formed by conventional semi-additive means.
Durlng the plating operation metal is deposited on the walls of the cavities and on the surface and makes intimate contact with the exposed surface of the filament to interface the¦
~0 filament with the external surface. Metal may also be deposited in cavities which do no interface with filaments, but interface with other conductive fea~ures, such as pads, or power and ground planes, at other levels in the circuit. Alternatively, means other than plating may be used to interface the filament or other conductive feature to the external surface. Such means might Il include sputterir.g o~ metal, metal spraying, conduc;lve ?olvmeric pastes, solder pastes and conventional solder. In the case wnere the filament is not a metal wire, means appropriate and com?a~ibl ., , 222-lGQ ~ 12Q~Z~78 1 with the filament conductor may be used to interface the filament to the external surface. For example, an optoelectronic means might be employed to interface optical filaments with electronic components.
In the instant invention, the high density interconnec-tion circuit may be formed and processed on a carrier which will ' form an integral part of the article or may be formed, processed ¦
and then removed from the carrier. Where the carrier is to remain as an integral part of the article processed and formed, the carrier should, of course, be of a material suitable for ~he article and dimensionally stable for the process.
Where t for example, the article to be formed is to include metal filamen~s and a metal base, a dielectric film or coating would first be applied ~o the metal base. Such film or coating may include isolated metal pads at the points where ca~ities are to be formed to deflect the high ener~y beam and avoid short circuiting to the metal base.
Where the formed circuit after processing is to be removed from the carrier and the carrier reused, the circuit is formed, built up and processed on ~he carrier and then peeled off and rPmoved. The formed circuit, pealed from the carrier might then be laminated to a base or formed circuits might be built up or laminated one over the other to form a multi-level . circuit.
Where, for example, metal filaments are to be employed, and the article, ~ormed and processed, is ~o be removed from the carrier, the carr er may be of s~ainless steel plated with lightl~-; adherent copper. Other lightly adheren~ combinations of carrier ., .
9_ ~$~7~
and plating might be emp:Loyed. The article is built up and processed on the carrier and, with the plating, is peeled from the carrier. After removal from the carrier the plating on the article may be used in the formation of conductive features by conventional processes.
The high conductor densitv which is achievable with the filament yrid geometry of about 12 1/2 mils and more particularly with the small diameter of the filament access cavities of the instant invention, enables complex interconnect patterns to be executed with a minimum of levels. The circuit may therefore be manufactured with a thickness of about 10 to 20 mils.
The thinness of the circuit thus formed or laminated to a base allows the components to be positioned in close proximity to that base. This allows properties of the base such as coefficient of thermal expansion and heat dissipation to be imparted to the components more readily than in the instance of thicker, lower density, multiple level circuits.
The problems of heat and heat dissipation are alleviated.
Specifically, the invention relates to a process for removing insulating coatings from substrates and substantially exposing circuit wires thèreon, the steps comprising: a) affixing a substrate having circuit wires thereon on a table movable alon~ "~" and "y" axes; b) moving the table and the substrate along the axes to align the circuit wire at a predetermined point in the circuit board with a high energy beam source; c) and, with the substrate so aligned, energizing the high energy beam source; and kh/ ~,~
~?~7~
d) volatilizing the insulating material in the subs-trate area in alignment with the beam source to substantially expose the aligned circuit wire.
The present invention will be more fully described and will be better understood from the followin~ description of preferred embodiments of the invention taken with the appended drawings in which:
Figure 1 is a top plan view of an interconnection substrate useful with the present invention;
Figure 2 is an exploded view, in perspective, of a chip carrier, chip, and cover, to which the invention is particularly adapted;
Figure 3 is a perspective view of the chip carrier of Figure 2 when viewed from the bottom;
- lOa -- kh/
222~
~ 7~
1 Figure 4 is a sectional view through a section of an interconnection substrate showing the preinsula~ed conductor before high energy, ablation of the coating and insulation;
Figure 5 is a top plan view of the section of Figure 4;
Figure 6 is a sectional view similar to Figure 4 but showing the exposed conductor after formation of the interfacing ¦
cavit;
Figure 7 is a top plan view of the section of Figure 6;j F'igure 8 is a sectional view similar to Figures 4 and 6 but showing the conductor and conductor pad after plating;
Figure 9 is a top plan view of the section of Figure 8;~
Figure 10 is a schematic plan view of an apparatus for carrying out part of the process and for producing the caviti~s of the instan~ invention;
^ Figure 11 is a side view, in elevation, of the schema-¦ tic apparatus of Figure 10;
Figure 12 is a sectional view oi the interconnection ¦ substrate of the lnstant invention showing the interconnection I between the conductor or wire, a chip carrier and chip;
I Figure 13 is a sectional view of the interconnection ¦ substrate of one embodiment of th~ instant invention showing the , circuit with a metal base and surface conductor;
Figure 14 is a view similar to Figure 12 but showing I interconnection between the conductor or wire and a chip and ¦I without the chip carrier;
Figure 15 is a view similar to Figure 4 but showing the embodlmenL in which the circuit, when com~leted, is to be removec , from the metal base;
Il 2~2-]~ 7~
1 Figure 16 is a view similar to Figur~ 15 but showing the exposed conductor after formation of the cavity; and Figure 17 is a view similar to Figures 15 and 16 but showing the conductor and conductor pad after plating, with the processing metal base removed and the clrcuit bonded to permanent base.
Referring to the drawings, particularly Figure 1, the circuit generally designated 2, includes the interconnection substrate 4 having mounted thereon chip carrier, chip and cover assemblies 12. Chip carriers 12 are connected to surface pads and may be connected to power and ground bus bars 14, 16, formed on the surface of substrate 4.
Chip carriers 12 vary in size, depending upon the com-! plexity and size of the chip carried therein. As best shown~in Figure 2, chip carriers 12 is made up of a body 6, having a recessed center top portion 20 and a flat bottom portion 22, Figure 3. For purposes more apparent later herein, recessed center top portion 20 has a plurality of contacts 24 spaced there-around. Bottom 22 and the sides of body 6 are provided with a plurality of contacts 26 spaced around the carrier sides and extending onto bottom surface 22, Figure 3. Chip 10, Figure 2, has a plurality of contacts 30 extending around the top edge of the chip.
Chip 10 is assembled in recess 20 or body 6 with contac~
30 of chip lQ connected to contacts 24 in recess 20 of body 6.
With chip 10 in recess 20 and contacts 30 and 24 connected, cover 32, Figure 2, is placed over recess 20, covering the recess and lithe chip 10 thereln. As will be later described, contacts 26
3~
l 12-., .
7~
of body 6 to be connected to the circuit 2 are moun-ted on and soldered to contact pads on the substrate after the circuit is fabricated and the desired contact pads are for~ed -thereon.
As will also be described later herein, contacts 30 in chip 10 may be connected, by soldering, wire bonding or other appropriate means, directly to the contact pads on the substrate, once such contact pads are formed, and carrier body 6 with cover 32 are not used.
Referring next, to Figures 4-9, in this illustrated embodiment, base 42, which may be plastic, glass fiber re-inforced plastic, ceramic or coated metal is coated with an adhesive 44 activatable bv ultrasonic energy. Metal wire 46 coated with an insulating coating 48 is scribed onto and embedded in adhesive 44 in accordance with the teachings and disclosures of the aforementioned '602 and '914 U.S. patents and Canadian Patent No. 1,102,924. The substrate, with the wire scribed thereon in the prepro~rammed pattern, ~ay be heated and baked to furthèr cure the adhesive in which the scribed wire is embedded and to remove and drive ofr volatiles from the adhesive. A liquid material 50 is then cast over t~e scri~ed wires. The exposed surface of the liquid 50 is brou~ht into ocntact with the surface o a film, such as a polyester, which will not adhere to the coating, the coating is cured or haxdened at a temperature below 100C and the non-adherent film-is removed. Such a procedure is disclosed and described in the aforementioned '380 U.S. patent. The e~posed surface o the liquid 50 might also be spread and leveled with a knife, kh/ ~
~ !
~22~ "
.
1 doctor blade or roller or might be flowed, ponded or puddled onto the wire scribed board before the material 50 is cured or hard-ened. In any event, a smooth, flat, planar surface is thus provided on the substrate. The dried and cured coating fo~ms layer S0 over the wire scribed board. A thin adhesive coating 52, such as epoxy rubber, may be applied over layer 50 and dried or cured so as to form a coating over the board for adherlng the metal subsequently a~plied by printing, plating or the like.
10 ¦ ~eferring, next, to Figures 10 and 11, the wire scribed and adhesive coated substrate of Figure 4 is mounted on and registered with table 60 of rXI - 'Y' table machine, generally designated 62, numerically controlled, such as with a floppy disc computer controller 64, and preprogra~med to move table 60 and the substrate at~ached thereto through a preset sequence. A high energy source, capable of being focused and applied as a vertical beams to the substrate on the table, such as laser 70, is pro-jected as a laser beam through tube 72 and is applied vertically such as through a mirror and mirror head 74. An Everlase 150 Watt C02 laser manufactured by Coherent Inc., has been found to be particularly adaptable as a high energy laser source for use in the instant invention. Computer drive 64 not only controls the movement and stopplng of `'X`' - 'Y' table 62 but also controls the pulsing of laser 70. Thus, as table 60 and the scribed sub-strate mounted thereon is moved from point-to-polnt and then stopped by control 64, at each stop laser 70 is pulsed.
As best shown in Figures 6 and 7, with the wire scribed and ubber epory coated substrate of Figure 4 mounted on eable 60, 222~ ` ~2~ 78 1 table 60 and computer drive 64 are preprogrammed so as to align conductor 46 wi~h the beam from mirror head 74. When the con-ductor 46 is so aligned, table 60 and the substrate mounted thereon is stopped and the high energy .source is pulsed. The high energy source~ in ~he described embodiment a laser, may be pulsed¦
once during each stop or a series of pulses might be applied.
The power of the energy source is adjusted so a~ to apply the energy to the substrate at the desired absorption level. In any j event, the rubber epoxy coating and the coating over the conduc-tor are heated, vaporized and flashed off. Insulation 48 is exposed to the beam and with the coating is vaporized and flashed off. The metal in the sonductor or wire 46, which in the preferred e~bodiment is copper, reflects the energy beam and ¦ remains intact. Thus, as best shown in Figures 6 and 7, a sub-stantially cylindrical cavity is formed from the surface into thel substrate leaving the conductor or wire in the opening partially ¦
bare and exposed.
After the preprogrammed pattern of cavities or openingsl in the board surface has been completed, the hole walls, rubber epoxycoated sur~ace and e~osed wire are metal plated. This may be accomplished by electroless plating or with a combination of l electroless and electroplating, the c2vity and outer epoxy rubber ¦I surface belng first sensitized wi~h a catalyst applied after high ! energy `formation of the cavity ur incorporated during initial casting and coating application. The catalyst sensitized surface is first electrolessly plated ~o form a thin coating of metal or ¦¦ the surface is first electrolessly plated to form a thin coating ¦, of metal on the surface along the cavity walls and around the li l 1l 22~ ~``0 ~ ?~
1 exposed wire and then the electroless metal deposition might be built up in ~hickness by electroplating or further electroless plating.
After the substrate and cavities have been plated, conductor pads, and ground and power planes or conduct~rs might be formed on the surface by masking and etching in any of the manners conventionally followed in preparing circuit board sur-faces. Thus, as best shown in Figures 8 and 9, the walls of the conductor cavities are coated at 80 with metal, such as copper, and conductor pads 82 and planes 84, Figure 13, are formed on the board surface. As best shown in Figure 12, chip carrier 12 is electrically connected at carrier contact 26 by solder joint with conductor pad 82. As best shown in ~igure 1~, chip 10 might be mounted and cemented by cement 79 and directly connected to conductor pad 82 by solder joint 81, wire bonding or other appro-priate means to chip conduetor 30 in which case carrier 12 would not be used.
The embodiment of the invention illustrated in Figures lS ! 16, and 17, is similar to the embodiment already described ~ and is formed in subs~antially the same manner. Where the two embodiments differ is that, while the embodimen~ already describec produces a su~strate with an integral base used for s~abili~y during processing and as a part of the final product, the embodi-ment of ~igures 15, 16, and 17 utilizes a base for processing only. Thus, metal base 42 is copper plated with plating 100.
Adhesi~e 44' is adhered to copper plating 100, wires 48' are applied or scribed and coatings S0', 52` are applied in the same manner as in the aforedescribed embodiment.
7~
1 ~hen the cavities are subsequently filled with metal, as best show~ in Figure 17, metal to metal contact i5 not only provided between the hole filling metal 80' and exposed wire 48' but may also be provided with copper plating 100. Thus, when ¦ metal base 42' is removed, as shown in Figure 17, the exposed surface of plating 100 may be masked and etched to form isolated conductor pads and power or ground distribution busses. The circuit is mounted on base 102, Figure 17, which may be of metal or any other support material coated with an adhesive 104 which, in the case of a metal base, should also be dielectric.
In both embodiments of the inventio~, the dielectric base is mounted on and affixed to a rigid stable base while thc wire is scribedj the liquid coating is applied, leveled> smooth- -1 ened, flattened and cured in accordance with the teachings of the '380 U.S. patent, the cavities in the circuit to expose the wires or conductors are formed by high energy beams and the holes¦
l are electrolessly plated or electroplated. In the instance of I the embodiment of Figures 4-9, the base is permanen~ly affixed and remains a part of the finished circuit. In the embodiment of Figures 15-17, the metal base upon which the circuit is mounted and affixed for processing is removed, the processed circuit, with the high energy formed cavities filled with electroless or ~lectroplated metal is bonded to a base, which may be a dielec-11 trically coated metal base or base of dielec~ric ~aterial or some other dielectrically coated material. A plurality of processedcircuits, each affixed to and mounted on a metal base for process and subsequently removed therefrom, might be laminated ¦ and connected, one,on the other, and before or after laminating, !l 1.
` ~ZS~7~ 1 1 might be mounted and affixed to a dielectric base or a dielectric coated base.
In both embodiments of the invention, the conductor or wire extends through the high energy formed cavity at the time of plating. This provides better electrical contact and mecha-nical strength between the conductor and cavity plating metal than could be provided when attempting to drill through a 2 to 4 ¦
mil diameter wire with a 6-12 mil diameter drill.
In the practice of the instant invention~ coating 50, 50' may be cast, in situ, over the wire scribed circuit. Voids between the coating and the wire scribed circuit surface may be removed with a doctor blade or roller applied to the exposed surface of coating 50, 50'. Rather than casting coating 50, 50' in situ, the coating material may be a low temperature thermo- !
¦ setting or ultra-violet curing material, such as an epoxy, a l Ipolyamide or an acrylic, and may be cast on the surface between I the surface and a pre-formed sheet and applied over the wire ¦l scribed circuit with a doctor blade, roller or platen to level l the coating be~ween the sheet and wire scribed circuit. In any event, coating 50, 5G' forms a planar surface over the irregular wire scribed circuit and is cured or hardened before cavities are formed in the circuit. Coating 50, 50' should be of a ma-terial or contain an additive so that the coating can be cured I or hardened at low temperature or by low temperature radiation, such as ultraviolet radiation. A coating process such as dis- , closed and described in the aforementioned '380 U.S. pa~ent, is ¦I satisfactory. Additional planar coatings may, of course, be added I
I
! I
~2~7~ -` l to the circuit or the desired characteristics of these coatings, such as adhesion may be incorporated in coating 50, 50'.
Circuits produced in accordance with the instant inven-~ion, particularly the embodiment of Figures 15-17, may be lami-S nated, one over the other. In carrying out such lamination,dielectric coating or adhesives should be used between the cir-cuits to maintain circuit integrity.
In the practice of the instant invention cavity forming with a high energy beam, such as a laser, has been found to be particularly useful. However, as already noted, other means, such as a drill bit, abrasive, chemical or high speed jet might also be employed. Other high energy beams absorbable by the material being drilled, but not the conductor or wire, and capablE
of volatilizing the material and insulation on the conductor or wire, may be employed.
The ~erms and expressions which have been employed are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, OI exclud-ing any equivalents of the features shown and described or por~ions thereof, but it is re ognized that various m~difications axe possible within the scope of the invention claims.
Ii I
. , !i -19- '
l 12-., .
7~
of body 6 to be connected to the circuit 2 are moun-ted on and soldered to contact pads on the substrate after the circuit is fabricated and the desired contact pads are for~ed -thereon.
As will also be described later herein, contacts 30 in chip 10 may be connected, by soldering, wire bonding or other appropriate means, directly to the contact pads on the substrate, once such contact pads are formed, and carrier body 6 with cover 32 are not used.
Referring next, to Figures 4-9, in this illustrated embodiment, base 42, which may be plastic, glass fiber re-inforced plastic, ceramic or coated metal is coated with an adhesive 44 activatable bv ultrasonic energy. Metal wire 46 coated with an insulating coating 48 is scribed onto and embedded in adhesive 44 in accordance with the teachings and disclosures of the aforementioned '602 and '914 U.S. patents and Canadian Patent No. 1,102,924. The substrate, with the wire scribed thereon in the prepro~rammed pattern, ~ay be heated and baked to furthèr cure the adhesive in which the scribed wire is embedded and to remove and drive ofr volatiles from the adhesive. A liquid material 50 is then cast over t~e scri~ed wires. The exposed surface of the liquid 50 is brou~ht into ocntact with the surface o a film, such as a polyester, which will not adhere to the coating, the coating is cured or haxdened at a temperature below 100C and the non-adherent film-is removed. Such a procedure is disclosed and described in the aforementioned '380 U.S. patent. The e~posed surface o the liquid 50 might also be spread and leveled with a knife, kh/ ~
~ !
~22~ "
.
1 doctor blade or roller or might be flowed, ponded or puddled onto the wire scribed board before the material 50 is cured or hard-ened. In any event, a smooth, flat, planar surface is thus provided on the substrate. The dried and cured coating fo~ms layer S0 over the wire scribed board. A thin adhesive coating 52, such as epoxy rubber, may be applied over layer 50 and dried or cured so as to form a coating over the board for adherlng the metal subsequently a~plied by printing, plating or the like.
10 ¦ ~eferring, next, to Figures 10 and 11, the wire scribed and adhesive coated substrate of Figure 4 is mounted on and registered with table 60 of rXI - 'Y' table machine, generally designated 62, numerically controlled, such as with a floppy disc computer controller 64, and preprogra~med to move table 60 and the substrate at~ached thereto through a preset sequence. A high energy source, capable of being focused and applied as a vertical beams to the substrate on the table, such as laser 70, is pro-jected as a laser beam through tube 72 and is applied vertically such as through a mirror and mirror head 74. An Everlase 150 Watt C02 laser manufactured by Coherent Inc., has been found to be particularly adaptable as a high energy laser source for use in the instant invention. Computer drive 64 not only controls the movement and stopplng of `'X`' - 'Y' table 62 but also controls the pulsing of laser 70. Thus, as table 60 and the scribed sub-strate mounted thereon is moved from point-to-polnt and then stopped by control 64, at each stop laser 70 is pulsed.
As best shown in Figures 6 and 7, with the wire scribed and ubber epory coated substrate of Figure 4 mounted on eable 60, 222~ ` ~2~ 78 1 table 60 and computer drive 64 are preprogrammed so as to align conductor 46 wi~h the beam from mirror head 74. When the con-ductor 46 is so aligned, table 60 and the substrate mounted thereon is stopped and the high energy .source is pulsed. The high energy source~ in ~he described embodiment a laser, may be pulsed¦
once during each stop or a series of pulses might be applied.
The power of the energy source is adjusted so a~ to apply the energy to the substrate at the desired absorption level. In any j event, the rubber epoxy coating and the coating over the conduc-tor are heated, vaporized and flashed off. Insulation 48 is exposed to the beam and with the coating is vaporized and flashed off. The metal in the sonductor or wire 46, which in the preferred e~bodiment is copper, reflects the energy beam and ¦ remains intact. Thus, as best shown in Figures 6 and 7, a sub-stantially cylindrical cavity is formed from the surface into thel substrate leaving the conductor or wire in the opening partially ¦
bare and exposed.
After the preprogrammed pattern of cavities or openingsl in the board surface has been completed, the hole walls, rubber epoxycoated sur~ace and e~osed wire are metal plated. This may be accomplished by electroless plating or with a combination of l electroless and electroplating, the c2vity and outer epoxy rubber ¦I surface belng first sensitized wi~h a catalyst applied after high ! energy `formation of the cavity ur incorporated during initial casting and coating application. The catalyst sensitized surface is first electrolessly plated ~o form a thin coating of metal or ¦¦ the surface is first electrolessly plated to form a thin coating ¦, of metal on the surface along the cavity walls and around the li l 1l 22~ ~``0 ~ ?~
1 exposed wire and then the electroless metal deposition might be built up in ~hickness by electroplating or further electroless plating.
After the substrate and cavities have been plated, conductor pads, and ground and power planes or conduct~rs might be formed on the surface by masking and etching in any of the manners conventionally followed in preparing circuit board sur-faces. Thus, as best shown in Figures 8 and 9, the walls of the conductor cavities are coated at 80 with metal, such as copper, and conductor pads 82 and planes 84, Figure 13, are formed on the board surface. As best shown in Figure 12, chip carrier 12 is electrically connected at carrier contact 26 by solder joint with conductor pad 82. As best shown in ~igure 1~, chip 10 might be mounted and cemented by cement 79 and directly connected to conductor pad 82 by solder joint 81, wire bonding or other appro-priate means to chip conduetor 30 in which case carrier 12 would not be used.
The embodiment of the invention illustrated in Figures lS ! 16, and 17, is similar to the embodiment already described ~ and is formed in subs~antially the same manner. Where the two embodiments differ is that, while the embodimen~ already describec produces a su~strate with an integral base used for s~abili~y during processing and as a part of the final product, the embodi-ment of ~igures 15, 16, and 17 utilizes a base for processing only. Thus, metal base 42 is copper plated with plating 100.
Adhesi~e 44' is adhered to copper plating 100, wires 48' are applied or scribed and coatings S0', 52` are applied in the same manner as in the aforedescribed embodiment.
7~
1 ~hen the cavities are subsequently filled with metal, as best show~ in Figure 17, metal to metal contact i5 not only provided between the hole filling metal 80' and exposed wire 48' but may also be provided with copper plating 100. Thus, when ¦ metal base 42' is removed, as shown in Figure 17, the exposed surface of plating 100 may be masked and etched to form isolated conductor pads and power or ground distribution busses. The circuit is mounted on base 102, Figure 17, which may be of metal or any other support material coated with an adhesive 104 which, in the case of a metal base, should also be dielectric.
In both embodiments of the inventio~, the dielectric base is mounted on and affixed to a rigid stable base while thc wire is scribedj the liquid coating is applied, leveled> smooth- -1 ened, flattened and cured in accordance with the teachings of the '380 U.S. patent, the cavities in the circuit to expose the wires or conductors are formed by high energy beams and the holes¦
l are electrolessly plated or electroplated. In the instance of I the embodiment of Figures 4-9, the base is permanen~ly affixed and remains a part of the finished circuit. In the embodiment of Figures 15-17, the metal base upon which the circuit is mounted and affixed for processing is removed, the processed circuit, with the high energy formed cavities filled with electroless or ~lectroplated metal is bonded to a base, which may be a dielec-11 trically coated metal base or base of dielec~ric ~aterial or some other dielectrically coated material. A plurality of processedcircuits, each affixed to and mounted on a metal base for process and subsequently removed therefrom, might be laminated ¦ and connected, one,on the other, and before or after laminating, !l 1.
` ~ZS~7~ 1 1 might be mounted and affixed to a dielectric base or a dielectric coated base.
In both embodiments of the invention, the conductor or wire extends through the high energy formed cavity at the time of plating. This provides better electrical contact and mecha-nical strength between the conductor and cavity plating metal than could be provided when attempting to drill through a 2 to 4 ¦
mil diameter wire with a 6-12 mil diameter drill.
In the practice of the instant invention~ coating 50, 50' may be cast, in situ, over the wire scribed circuit. Voids between the coating and the wire scribed circuit surface may be removed with a doctor blade or roller applied to the exposed surface of coating 50, 50'. Rather than casting coating 50, 50' in situ, the coating material may be a low temperature thermo- !
¦ setting or ultra-violet curing material, such as an epoxy, a l Ipolyamide or an acrylic, and may be cast on the surface between I the surface and a pre-formed sheet and applied over the wire ¦l scribed circuit with a doctor blade, roller or platen to level l the coating be~ween the sheet and wire scribed circuit. In any event, coating 50, 5G' forms a planar surface over the irregular wire scribed circuit and is cured or hardened before cavities are formed in the circuit. Coating 50, 50' should be of a ma-terial or contain an additive so that the coating can be cured I or hardened at low temperature or by low temperature radiation, such as ultraviolet radiation. A coating process such as dis- , closed and described in the aforementioned '380 U.S. pa~ent, is ¦I satisfactory. Additional planar coatings may, of course, be added I
I
! I
~2~7~ -` l to the circuit or the desired characteristics of these coatings, such as adhesion may be incorporated in coating 50, 50'.
Circuits produced in accordance with the instant inven-~ion, particularly the embodiment of Figures 15-17, may be lami-S nated, one over the other. In carrying out such lamination,dielectric coating or adhesives should be used between the cir-cuits to maintain circuit integrity.
In the practice of the instant invention cavity forming with a high energy beam, such as a laser, has been found to be particularly useful. However, as already noted, other means, such as a drill bit, abrasive, chemical or high speed jet might also be employed. Other high energy beams absorbable by the material being drilled, but not the conductor or wire, and capablE
of volatilizing the material and insulation on the conductor or wire, may be employed.
The ~erms and expressions which have been employed are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, OI exclud-ing any equivalents of the features shown and described or por~ions thereof, but it is re ognized that various m~difications axe possible within the scope of the invention claims.
Ii I
. , !i -19- '
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A process for removing insulating coatings from substrates and substantially exposing circuit wires thereon, the steps comprising:
a) affixing a substrate having circuit wires thereon on a table movable along "x" and "y" axes;
b) moving said table and said substrate along said axes to align a circuit wire at a predetermined point on said substrate with a high energy beam source;
c) and, with said substrate so aligned, energizing said high energy beam source; and d) volatilizing the insulating material in the substrate area in alignment with said beam source to sub-stantially expose said aligned circuit wire.
a) affixing a substrate having circuit wires thereon on a table movable along "x" and "y" axes;
b) moving said table and said substrate along said axes to align a circuit wire at a predetermined point on said substrate with a high energy beam source;
c) and, with said substrate so aligned, energizing said high energy beam source; and d) volatilizing the insulating material in the substrate area in alignment with said beam source to sub-stantially expose said aligned circuit wire.
2. A process, as recited in claim 1, in which said wire is lacquer insulation coated and said energized beam volatilizes said lacquer coating in the area aligned with said beam source as well as the substrate insulation to substantially expose said aligned wire.
3. A process, as recited in claim 1, in which said table and said substrate are moved to a second point to align the wire in said substrate at a second predetermined point in said substrate with said high energy beam source after the wire aligned at said first predetermined point has been exposed and with said substrate so aligned with said second point energizing said high energy beam source, volatil-izing said substrate insulation material in the aligned sub-strate area and exposing said wire in the aligned area.
4. A process, as recited in claim 2, in which said table and said substrate are moved to a second point to align said wire at a second predetermined point in said substrate with said high energy beam source after the wire aligned at said first predetermined point has been exposed and with said substrate so aligned with said second point energizing said high energy beam source, volatilizing said substrate insulation material in the aligned substrate area and exposing said wire in the aligned area.
5. A process, as recited in claim 3, in which said steps are repeated until all conductors in said substrate which require interfacing to the external surface, have been accessed.
6. A process, as recited in claim 4, in which said steps are repeated until all conductors in said substrate which require interfacing to the external surface, have been accessed.
7. A process, as recited in each of claims 1 to 3, in which said high energy beam source is a laser.
8. A process, as recited in each of claims 1 to 3, in which said high energy beam source is a C02 laser.
9. A process, as recited in each of claims 1 to 3, in which said high energy beam source is a laser and said laser is pulsed while said table and said substrate are aligned with and stopped over the circuit wire to be exposed.
10. A process, as recited in each of claims 1 to 3, in which said high energy beam is a laser and said cavities formed in said substrate with said laser beam are metal plated.
11. A process, as recited in each of claims 1 to 3, in which said cavities formed in said substrate with said laser beam are metal plated, said substrate with said metal plated cavities is removed from said plated metal carrier plate, and said removed substrate is adhesively bonded to an insulating base.
12. A process, as recited in each of claims 1 to 3, in which said cavities formed in said substrate with said beam are plated metal carrier plate and said removed substrate is adhesively bonded to an insulated metal base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000477454A CA1209278A (en) | 1981-04-14 | 1985-03-25 | Process for removing insulating coatings from substrates |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/254,132 US4500389A (en) | 1981-04-14 | 1981-04-14 | Process for the manufacture of substrates to interconnect electronic components |
| CA000410500A CA1189196A (en) | 1981-04-14 | 1982-08-31 | Process for the manufacture of substrates to interconnect electronic components and articles made by said process |
| CA000477454A CA1209278A (en) | 1981-04-14 | 1985-03-25 | Process for removing insulating coatings from substrates |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000410500A Division CA1189196A (en) | 1981-04-14 | 1982-08-31 | Process for the manufacture of substrates to interconnect electronic components and articles made by said process |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1209278A true CA1209278A (en) | 1986-08-05 |
Family
ID=25669801
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000477454A Expired CA1209278A (en) | 1981-04-14 | 1985-03-25 | Process for removing insulating coatings from substrates |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1209278A (en) |
-
1985
- 1985-03-25 CA CA000477454A patent/CA1209278A/en not_active Expired
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