CA1205553A - Frequency determining apparatus for a synthesized radio - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A packaging arrangement for electronic apparatus, comprising: a support structure having first and second sides; a first circuit module having an upper edge and a lower edge and mechanically attached to the first side of said support structure; a second circuit module having an upper edge and a lower edge and mechanically attached to the second side of the support structure so that the first and second circuit modules are arranged substantially parallel to each other; a third circuit module removably situated adjacent the upper edges of the first and second circuit modules in a plane substantially normal to the first and second circuit modules; and electrical inter-connection means disposed adjacent the upper edges of the first and second circuit modules, for electrically coupling the first and second circuit modules to the third circuit module.

Description

~2~35553 FREQUENCY DETERMINING APPARATUS FOR A SYNTHESIZ D RADIO

BACKGROUND OF THE INVENTION
-This invention relates to apparatus for control-ling the fre~uency of operation of a radio frequency - receiver, and more particularly to apparatus for contain-ing information designating the frequency of operation of a synthesized radio frequency receiver.

DESCRIPT~ON OF THE PRIOR ART

In the past, discrete crystals have been ~ employed to control the operating frequency of radio frequency receivers. In such conventional receivers, a separate crystal wa~ re~uired for each received or trans-- 10- mit frequency desired. ~hus, if operation on a-large -number of frequency channels was desired, a correspond-ingly large number of crystals were employed at cQnsider-able cost.
AS technology progressed, discrete crystals were gradually replaced by discrete channel elements, that is, crystals packaged in con~unctlon with temperature compen-sation circuitry resulting in a more stable crystal performance. Of course, such channel elements tend to be , , , .. . . . .. _ . ~

~ 2f.~55S3 more expensive than mere crystals and thus the cost of transceivers with the capability of transmitting and receiving on a relatively large number of frequencies was correspondingly increased.
The offset type radio frequency synthesizer is one type of synthesizer which reduces the number of crystals required to transmit and receive on a large number of frequencies. The offset type synthesizer employs a voltage controlled oscillator, a phase lock loop, and a phase detector circuit all appropriately coupled together to generate a plurality of transmit and receive frequencies from a single reference oscillator.
A single crystal in the reference oscillator circuit may be employed to generate the plurality of radio requency transmit and receive frequencies and thus, the number of crystals employed is extremely minimal. Unfortunately, although such offset type frequency synthesizer is _ ~apab~e of generating a large number of transmit and receive frequencies, such generated frequencies are typically limited to a relatively narrow band, for example 144 through 148 M~z Accordingly, one ob~ect of the present invention i to provide a fre~uency control element for enabling a frequency s~nthes~zer to-generate transmit and receive frequencies over a relatively wide range of frequencies, for example, 134 through 176 M~z.
Another object of the present invention is to provide a frecluency control element into which infor-matlon is programmed which designate~ the frequency of operation of a synthesized radio frequency receiver.
These and other objects of the invention wlll ~ecome apparent to those skilled in the art upon consider-at~on of the following description of the invention.

3 12~5553 BRIE~ SUMMARY OF TEIE INVENTION
The present invention is directed to providing an apparatus for containing information designating the frequency of operation of a synthesized radio frequency receiver.
S In accordance with one embodiment of the invention, such apparatus includes a multilayer circuit board including upper and lower boards and at least one intermediate board disposed therebetween in sandwich-like relationship. The upper and lower circuit boards include exterior surfaces. A memory is situated on the exterior surface of the upper boara for providing freguency dàta to a multibit output port of th~ memory when a multibit input port of the memory is appropriately addressed.
Connecting members are situated on the surfaces of the irst and second boards and the at least one intermediate board. The connecting members electrically connect a plu~ality of electrical contact pads situated on the - -exterior surface of the lower board to at least the input and output ports. A plurality of interconnecting members are situated on the exterior surfaces of the lower board.
The interconnect~ng members selectively e~ectrically interconnect a portion of a first circuit external to the apparatu~ to a portion of a second circuit external to the apparatu~.
2S The features of the inventlon believed to be novel are set forth with particularity in the appended claims. The invention itself, however, both as to organization and method of operation, together with further ob~ect9 and advantages thereof, may best b~
unaerstooa by reference to the following description taken in con~unction with the accompanying drawings.

~.Z~3555;~
DESCRIPTION OF TE~E DRAWINGS
Fig. l is a side view ofthe apparatus ~f the present invention showing the multilayer nature thereof.
Fig. 2A is a top view of the upper most layer of the apparatus of Figure l.
S Fig. 2B is a top view of the conductive layer situated below the conductive layer of Figure 2A.
Fig. 2C is a top view of the electrically conductive layer situated below the electrically conductive layer of Figure 2B.
Fig. 2D is a top view of the electrically conductive layer situated below the electrically conductive l~yer of Fig. 2C.
- Fig. 3 is an exploded perspective view of the apparatus of the present invention shown in an appropriate position for connection to associated external circuitry.
Fig. 4 is a perspective view of the suppo~t member employed to facilitate mounting of the apparatus of the present invention to external circuitry.
Fig. 5 is a cross section of the structures shown in Fig. 3 after such structures are assembled together.~
j DETAILED DESCRIPTION CF THE PREF~RRED EMBODIMEN~
Fig. l illustrateg one embodiment of the information containing and transferring apparatu~ of the present inventisn a~ appar~tus 10. Apparatus 10 includes a layer 20 o~ el~trically insulative material,for example, glass epox~ re~in, such a~ the commercially available FR4. A layex 22 of electrically conductive materlal, for example, gold coated copper or nickel, i3 situated on an upper ~urface 20A of substrate 20. 'Layer 22 exhibits the predetermined geometric pattern shown in Fig. 2A in one embodiment thereof. A 256 X 8 programmable read only memory 24 i8 situated on upper , ~_ ~ZC~5553 surface 20A and is appropriately coupled to the conductive runners of layer 22 such that data relating to the desired frequency of operation of the synthesizer is supplied to memory 24 and is addressably derivable therefrom in a manner subsequently described in more detail.
A layer 30 of electrically conducti~e material exhibiting the geometric pattern shown in Fig. 2B is situ-ated on the bottom surface 20B of apparatus 10 of Fig. 1 A layer of insulative substrate material 40 is situated below layer 30 as shown in Fig. 1. Layer 40 exhibits physical properties similar to those of layer 20 and is typlcally comprised of like ma~erials. A layer 50 of electrically in~ylative substrate ~aterial is situated below layer 4D in the manner shown in Fig. 1. Iayer 50 includes upper surface 50A and lower surface 50~. A
layer 60 of electrically conductive material exhibi~ing the geometric pattern depicted in Fig. 2C is situated between surface 50B and ~u~strate ~ayer 40 as shown in Fig'. 1. A layer of electrically conduct~ve material 70 exhibiting the geometric pattern shown in Fig. 2D is fiituated on ~u~face SOA as shown ln F~g. 1. Eeat activated epoxy la~ers ~not shown) are situated between layers 20, 40 and 50 to hold such layers together ~n fixe~ xelat~Qnship, A layer of electrically insulative matexial is situAted between memory 24 ~nd the portion~ o~
electrially conductive layer 22 ~itu~ted therebelow ~5 in Fig. 1 to prevent undesired short~ng of the memory 24 to such portions of conductive layer 22.

i ZI~S55:~

Understanding the structure and operation of apparatu~ lO is facilitated by an examination of the individual portions of the conductive layer 70 shown in the bottom of apparatus lO of Fig. 2D as viewea from on surface 50A. For convenience, the bottom apparatus surface shown in Fig. 2D is divided into four sub-regions or contact subportion regions ~9OA, gOB, 90C, and 90D) as shown. Portions of electrically conductive layer 70 extend into sub-regions 90A-9OD as shown. Referrin~
momentarily to Fig. 3, electrical connections are established to ~uch portions of conductive layer 70 extending into regions 90A-9OD by respective Ampliflex ~a trademark of Amp. Inc.) connectors, lOOA, lOOB, lOOC, and lOOD which are situated in contact therewith.
It is seen that Amplifle ~connectors lOOA and iOOB
are mechAnically and electrically connected to port~ons of ~n electrical circuit llO wh~ch $s ~xternal to app~ratus 10. In a similar manner, ~mpllflex connectors lOOC and lOOD are elec~rically and mechanically connected to a circuit 120 external to apparatus 10. It is noted that Amplifle ~connectors in~lude a plur~lity of parallel, but spatially separated metallic conducting members situated on a somewh8t cyllndrically shape2 elastomeric structure.
~pparatus lO 18 operatively mountea on Amplifle ~
ccnnectors 100A, 100B, 100C, ~nd 100D such that electrlcal 12~SSs3 connectio~s are achieved between the portions of electrically conductive layer 70 extending into sub-regions 9OA, gos, 90C, and 9OD with connectors looA, lOOB, lOOC, and lOOD, respectively. Therefore, more specifically, the portions of electrically conductive layer 70 extending into regions 90A and 90B are electrically connected via Ampliflex~ connectors lOOA
and lOOB to external circuit 110. In a sinilar manner, the portions of layer 70 extending into sub-regions 90C and 30D are electrically connected via Ampliflex~
connectors lOOC and lOOD, respectively, to external c;rcuit 120. In one embodiment of the present invention, external circuit6 110 and 120 are respectively phase deteckor and controller hybrid board portions of a fre~enc~ ~ynthesized radio receiver.
As ~een in Fig. 2D, layer 70 of apparatus 10 includes interconnecting members 130 and 140 each extending from contact sub-region 90A to contact sub-region 90C. More specifically, interconnecting members 130 and 140 each include opposed ends, one end of each member being situated within region 90A and the remaining end being situated within region 90C. Thus, when apparatu 10 is situated in contact with Ampliflex~
connector6 110 and 120 in the manner of Fig. 3 J
interaonnecting member 130 ~electively couples electrica energy received from the particular portiGn of Ampliflex~
connector lOOA on circuit 110 in contact therewith *o the pox~ion of Amplifle ~ connector lOOC on circuit 120 contac~ therqwi~h. In this manner, electrical pulses ~e~igna~ed multiplex enable pulses Np are selectively coupled between portions of circuit 110 and circuit 120. In a like manner, the portion of Amplifle ~
connector lOOA in contact with interconnecting member 140 ~Z05553 and the portIon of Ampliflex connector lOOC in contact with interconnecting member 140 are selectively electrically coupled together. Thus, a portion of circuit 110 selectively electrically coupled to a portion of circuit 120 via interconnecting member 140 situated on apparatus 10. In this manner, electrical pulses such as the aforementioned multiplex enable pulses N are coupled between appropriate portions of circuits 110 and 120 via interconnecting member 140.
Referring again to Fig. 2D, ]ayer 70 includes a plurality of electrically conductive contact pads 151, 152,...158 situated extending into contact sub-region 90C.
Contacts 151-158 are designated "address contacts". These eight (8~ address contacts 151,152,...158 are respectively electrically connected to the eight (8) address input contacts ox runner~ Ao,Al,...A7 of memory 24 of Fig. 2A
via the appropriate connecting members of layers 22 of Fig. 2A, layer 30 of Fig. 2B, and layer 60 of Fig. 2C
and layer 70 of Fig. 2D. Contacts Ao,Al,...A7 form the multibit address input port of memory 24. The precise connections made between address contacts 151-158 to such 8 bit multibit input port of memory 24 are shown in detail in examinakion of these dxawings Fig.2A-Fig. 2D.
Re~errlng again to Fig. 2D, layer 70 includes a plurali~y of electrically conductive contact pads 161,162,.
.,168 situated exkending into contact sub-region 90~. Such contact pads are de ignated "requency information contact~".
Contact pads 161,162,...168 are respectively electrically aonnected to the eight (8) frequency information output contacts or runners 1~2~---8 f memory 24 of Fig. 2A via appropriate portions of layer 22 of Fig. 2A, layer 30 of Fig. 2B, layer 60 of Fig. 2C, and layer 70 of Fig. 2D as clearly seen in such drawings. Contacts B

lZ~3SSS3 1~2~---8 form the multibit frequency information output port of memory 24. The precise connections made between frequency information contacts 161,16~,...168 to such 8 bit multibit output port are shown in detail in examination of these drawings Fig. 2A-Fig. 2D. It is noted that contact pads 161-168 extend into connection region 90A in a manner whereby pads 161-168 are vertically aligned with pads 151-158 as seen in Fig~ 2D.

~o better understand the operation and structure of apparatus 10, it is helpful to examine the same when apparatus 10 is sit~ated such that pads 161-168 and ,' 151-158 are in contact with respective Ampliflex connectors lOOA and lOOC. Under these conditions, circuit 120 provides a digital 8-bit addxess signal to the multlbit input por~ of memory 24 via the Ampliflex , connector lOOC, conduct$ve padg 151-158, and the c~necting member3 of layers 70, 60, 30, and 22 situate~
therebetween. It i~ noted that in some embodiments of the invention, less than all of address pads 151-158 are , ,, , e,n~oy,ed to,conv,ey ad,dress, information to memory 24.
Memory 24 includes a look~up table of frequency information. More specifically, a different piece of frequency information is stored at each address of memory 24. Thus, when circuit 120 while functioning a~ part of a frequency synthe51zer sends a partlcular addre~ to the multibit input poxt o~ memory 24 in the above describea manner, digital indicla o~ the fxequency corresponding to such addre~s are proviaed to the multibit output port of memory 24. Such frequency information travel~ ~rom the multibit output of memory 24 through layex5 22, 30, 60, an~ 70, to Pre~uency output~ 161-16~, through Ampll~lex connectox lOOA to circuit 110 where such informat~on may be employed for frequency synthesis purposes.
.

Layer 70 includes freguency source interconnects 170 and 172. I~terconnects 170 and 172 are situatea extending from connection sub-region 90A to connection sub-region 90C in a spatially p~rallel relationship.
s Shorting bars 173 and 174 connect frequency interconnects 170 and 172 together at the opposed ends thereof such that a low resistance path i8 provided between the opposed ends thereof. Thus, when apparatus 10 is situated in contact with Ampliflex connectors lOOA and lOOC in the manner of Fig. 3, a reference frequency signal, for example 50 kRz, is fed between board 120 and board 110 via ~npliflex connectors lOOA and lOOC and interconnect structure 170-172 which contacts each of such Ampliflex connectors.
Referring again to Fig. 2D, layer 70 includes an lS electrically conductlve connection pad 180 extending into connection sub-region 90A. Connection pad 180 is connec-ted to ground when situated in contact with Ampliflex connecto~ lOOA in th~ ~anner of Fig. 3. Fu,rt~e~, cpntact pad 180 i8 electrically coupled to and provides ground to an appropriate terminal of memory 24. To accomplish this, connecting pad 180 i8 connected to a ground terminal of memory 24 by appropriate portlon~ ~designated GND in Fig.
2A) of layer 22, layer 30, layer 60, and layer 70 in the manner seen $n the multi-layer structure depic~ed,in Figs.
2A-2D.
Layer 70 of Fig. 2D includes a supply voltage ~nterconnect 190 having three ~3) parallel strips of elec-trically conductive material 191, 192, and 193, ~ach with opposed ends situated in connection ~ub-regions 90B and 90~ Shoxting bar3 194 and lg5 re~pectively electrically connect the end~ o~ bar~ 191, 192, and 193 ~ituated on ~eglon 90B together and the ends o~ bars 191, 192, and 193 situated on sub-regicn 9OB together. Thus, a relatively .. .. . _ .. _ . . . .. .

12~5S53 low resistance path is provided between the opposed ends of the component bars of voltage interconnect structure 190 such that when the opposed ends of the bars of inter-connect structure 190 are respectively broughk into 5 contact with Ampliflex connectors 100B and lOOD in the manner of Fig. 3, a supply voltage signal, for example 5.2 Volts, is provided from one of boards 120 and 110 to the other. Layer 70 includes floating contac4s 200 and 201 respectively situated in connection sub-regions 90B and 90D as shown in Fig~ 2D. Although shown in Fig. 2D, pads 200 and 201 remain electrically floating to allow versa-^tility in future applications of ~pparatus 10.
Layer 70 further includes dual, coupled together contacts 210 situated in contact sub-re~ion 90B adjacent floating contact 201. Contacts 210 are connected to a programming enable input terminal (designated El, in Fig.

2~) o~ memory 24 ViA connecting runners of layer 22, layer 30,~layer 60 and layer-70 as shown in Figs. 2A t~roug~ ~2D.
~0 ~pplication of an appropriate signal to dual contacts 210 permits programming memory 24 with desired frequency . - information at selected addresse~ thereof. Layer 70 . _ further includes dual, coupled together electrical contacts 211 situated extending within contact sub-region 90D ad~acent Ploating contact 200. Dual contacts 211 are coupled to each other and to the enable terminal of memory 24 via appropriate portions of layer~ 22, 30, 60, and 70 as shown in Fig8. 2A through 2D.
Layer 70 further include~ a memory enable interconnect 22Q~ Memoxy enable interconnect 220 i8 a bar o~ electrically conductive materlal including opposed ends. One and o memory enable interconnect 220 i8 situatea extending into contact sub-region 90B ad~acent dual contact 21G and the remaining end of memory enable ~ Z~ 55 S 3 interconnect 220 is situated extending into contact su~-region 90D adjacent dual contact 211. Thus, when apparatus 10 is situated such that interconnect 220 i5 in contact with Ampliflex connectors lOOB and lOOD in the manner suggested by Fig. 3 (discussed later in detail), an electrical interconnection is provided between circuits 110 and 120. This interconnection may be employed to pro-vide information from circuit 110 to circuit 120 to energize a high current regulator on one of such circuits such that sufficient current may be generated to turn on memory 24. It is noted that memory enable interconnect 220 is itself electrically connected to a memory enable contact pad (designated E ~ in Fig. 2A) of memory 24 via connecting members or runners of layer 22, layer 30, layer 60 and layer 70 as shown in Figs. 2A-2D. The operation of memory enable interconnect 220 should be considered in conjunction with 8upply voltage interconnect 230 situated ad3acejnt thereto a8 shown in Fig. 2D. Supply voltage interconnect 230 18 a bar of electrically conductive material having opposed endQ, o~e end of which is situated e~tending into contact sub-region 90D. m e remaining oppo~e~~end of supply voltage ~interconnect 230-extends into contact sub-region 90D. Supply voltage interconnect 230 tranfers voltage from circuit 110 to 120 or vice versa. More specifically, in this embodiment, voltage interconnect 230 connects 5.2 Volt~, Prom circuit 110 to circuit 12C At one of two selected power levels determined by the ~tate of information flowing though memory enable 220. For example, if circuits 110 and 120 have a signi~icant amount o CMOS sub-circu~t , theix power requirement~ are relatlvely low under quiescent operating condition~. However, when it i5 desired to enable memory 24 with addresses for ~he purpose of reading frequency lZ(:~SS53 information contained at such addresses, then it is appreciated that a significantly greater amount of power is required for operation of associated circuitry and memory 24 than under guiescent operating conditions.
5 Thus, when information travels between boards 110 and 120 via memory enable interconnect 220 to indicate that the memory is about to be turned on such that additional power is required, one of boards 110 and 120 includes appropriate circuitry to boost the power available at supply voltage interconnect 239. It is noted that supply voltage interconnect 230 is itself electrically connected to a supply voltage cont~ct ~designated V~n Fig. 2A) for memory 24 to supply voltage thereto via members or runners of layer 22, layer 30, layer 65 and layer 70 as shown in Fig~ 2A-2D.
Apparatus 10, and more specifically, layer 70 includes a time out timer 6tructure 240~ Time out structure includes electricai contact paas 241, i42, and 243 ~ituated within sub-region 90B as ~een in Fig. 2D.
Contact 241 is electrically connected to contact 242 via a - ~horting ~ar 245. Contact 242 i8 electrica~ly connected -to contact 243 via ~ short~ng bar 246. Time out timer structure 240 urther include8 contact pads Z50, 251, 252, and 253 all situated in contact cub-~egion 90D.
~lectrlcal contacts 251, 252, and 2S3 are vertically ~ligned with contacts 241, 242, and 243. Contact 252 is connected to contact 2S3 via ~ 8horting bar 254. Contact 241 ~s electrically connéct~d to contact 251 via a shorting bar 255 th¢~ebetween such that the combined s~ructu,re of contact 241, shorting bar 25S and contact 251 form time Ollt timer'interconnect 260. Contact 243 i~
electrically connected to contact 253 via a shorting bar 256 situated therebetween such that the comb~ned structure ~ , lZ~5553 of contact 243 shorting bar, and contact 253 forms time out timer interconnect 270. The presence or absence of time out interconnects 260 and 270 ~more specifically, shorting bars 255 and 256, respectively) is e~ployed to i~struct a time out timer located on one or both of circuits 110 and 120 whether or not to turn off a transmitter associated with a receiver wi~hin a particular preselected amount of time. More particularly, if shorting bar 255 of interconnect 260 and shorting bar 256 of interconnect 270 are present, then, no time out fe~ture is provided by associated circuits 110 and ~20.
- Similarly, no time out feature is provided by circuits 110 .
and 120 if shorting bar 255 is cut such that contact 241 and 251 are not electrically coupled to each other and if 15 at the same time shorting bar 256 of interconnect 270 remains present and uncut. However, when shorting bar 255 of interconnect 260 is present and uncut ~uch that contact ~1 and 251 are ~onnected to each other and ~ho~ting bar 256 o~ interconnect 270 i~ cut such that contact 243 and 20 253 are not connected to each other, then, a 60 second time out feature ~or e~ample, will be provlded by the clrcuitry on boards 110 or 120. However, when shorting bar 255 of interconnect 260 i~ cut such that contacts 241 and 251 are electrically disconnected from each other and 25 when ~horting bar 256 of interconnecting member 270 is cut such that electr~c~l con act 243 and 253 are not e~ectrically coupled together, then circuits 110 ~nd 120 provide ~ 3Q second tlme out e~ture, ~or example.
As seen in Figs. 2~-2D, and Fig. 3, appaxatus 10 3Q ic provided with three (3) holes ~- 300, 305, ana 310 --~r purpo~es of mounting to an external protect~ve cover ~not shown) and for pyrposes ~ubsequentlyJdiscussea.

Fig~ 3 is an exploded perspective view of apparatus 10 shown in position to be mounted to an assembly including external circuit~ 110 and 120 and support structure 390. Circuits 110 and 120 are shown as hybrid module boards and will henceforth be referred to as hybrid modules 110 and 120. As seen in Fig. 3 and in more detail in Fig. 4, support structure 390 is I beam-like shaped and includes a recessed portion 440 for receiving hybrid m~dule 120 therein. Support structure 390 includes a ridge or rim 445 which module 120 is disposed. Support 390 further includes a protrusion 430 and a spring member 435 situated on rim 445 at opposite ends of support 390 such that module 120 is held in position in support 390 by having its ends rela~ively gently squeezed between protrusion 439 and spring 435 in the manner suggested by Fig. 3. To summarize, module 120 snaps into place when situated on rim 445 between protrusion 430 and spring -i- member 43S.- Those skilled in the art will apprecia~e that module 110 i8 held to ~upport structure 390 in the ~ame ~0 manner as module 120 described above except that module llo i6 mounted to the back side of structure 390 not shown in Fig. 3, but clearly shown in the cross section of Fig.3 along line 5-5 depicted in Fiq. 5.
Referring again to Fig. 3, support structure 390 includes threaded holes 400~ 405, and ~10 respectively vertically aligQed with hole~ 300, 305 and 310, situated in apparztus 10 4~ shown. Screws inserted in the hole pairs thus ~orme~ axe employed to mount apparatu8 10 on the assembly ~ormed by support Qtructure 390 and module~
110 and 120 a~flxed thexeon a8 prevlously descrlbed. In this con~i~uration, module~ 110 and-120 ~re electrically coupled t~ approprlate interconnect~ (such as 230, for example) a~d connection polnt~ ~such as contact pads 161-16a, for example) by Ampliflex connectors lOOA, lOOB, lOOC and lOOD.

~ ;

, . ~ .

-16~ 12~QS~S3 Referring now to Fig. 4 in conjunction with Fig.

3, it is seen that support structure 390 includes rail-like metallic subsupport members or screw plates 450 and 460 running along the inner lengths of support structure 390 as shown to provide structural ~ntegrity thereto. Threaded holes 400, 405 and 410 extend into upper screw plate 460 to facilitate ~ounting of apparatus 10 to support structure 390. Threaded holes 415, 420 and a third hole (not shown for convenience of perspective drawing, but vertically aligned with hole 410) extend into lower screw plate 450 to facilitate mounting the assembly of apparatus 10 r support structure 390 with modules 110 and 120 situated therein to a mother circuit board. As ~een partially in Fig. 3 an~ Fig. 5, electrical connectionS between such assembly i9 achieved at Ampliflex connectors lOOE and 100~ on module 120 and Ampliflex connector lOOG on module 110. (Another Ampliflex connection on module 110 which is not shown is employed to achieve more of such electrical connections.) The foregoing describes an apparatus for con~ainin~ information designatin-~ t~e frëquency of oper~tion o~ a synthesized radio fre~uency receiver in a progra~mable manner. ~he apparatus of the invention provide5 Por synthes1zed radio operation over a relatively wide range o~ radio frequencie~.
While only certain pre~erred feature~ of the invention have been shown by way of illustration, man~
modi~icAtions ~nd chan~es will occur to those ~killed in the art. It i8 ~ thereor~, to be understood that the present claims are intended to cover all such modifi-cationS and changes as fall within the true spirit of the invention.

Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A packaging arrangement for electronic apparatus, comprising:
a support structure having first and second sides;
a first circuit module having an upper edge and a lower edge and mechanically attached to the first side of said support structure;
a second circuit module having an upper edge and a lower edge and mechanically attached to the second side of said support structure so that said first and second circuit modules are arranged substantially parallel to each other;
a third circuit module removably situated adjacent the upper edges of said first and second circuit modules in a plane substantially normal to said first and second circuit modules; and electrical interconnection means disposed adjacent said upper edges of said first and second circuit modules, for electrically coupling said first and second circuit modules to said third circuit module.

2. The packaging arrangement of claim 1 further including fastening means for removably mechanically fastening said third circuit module to said support structure.

3. The packaging arrangement of claim 1 further including electrical connector means disposed adjacent said lower edges of said first and second circuit modules for electri-cally communicating with a mother board.