CA1200617A - Microelectronic shadow masking process for reducing punchthrough - Google Patents

Abstract

Abstract:
The present invention relates to a process for fabricating a MOS integrated circuit structure at a predetermined portion of a substrate. The process includes the steps of forming a continuous silicon layer on the substrate, forming a continuous silicon oxide layer on the silicon layer covering at least the predetermined portion and forming a polycrystalline silicon layer on the oxide layer such that the silicon layer is insulated from the portion. A conducting layer is formed on the poly-crystalline silicon layer and a resist layer is formed over the conducting layer. The resist layer is etched to form a mask having a truncated pyramidal shape. The conducting layer and the polycrystalline silicon layer is milled using the resist layer as a mask in order to form a gate element having a shape corresponding to the truncated pyramidal shape of the resist layer mask. A dopant is implanted into the silicon layer using the gate element as a mask so that lighter and shallower degenerately doped areas are formed under the edges of the gate element.

Description

6~7' MICROELECTRONIC S~L~DOW MASKING
PROCESS FOR REDUCING PU~CHTEIROUGH

This is a division of copending Canadian Patent ~pplication Serial No. 407,811 which was filed on July 22, BACKGROUND OF THE INVENTION
Field of the Invention The invention relates to shadow masking processes in microelectronic fabrication, particularly those emplo~ed in silicon-on-sapphire (SOS) processes.
Description of the Prior Art The fabrication of integrated circuits such as metal oxide semiconductor (MOS) circuits employing a mask and photolithographic techniques is well known in the art.
One of these methods, known as the self-aligned gate procedure, utilizes a gate conductor pattern to shield the channel region of the devi~e from N~ or P+ ion implantation during formation of the source and drains of the device.
In such processes, the entire dimension of the gate, L, shields the channel region which has an area L by W
(wherein W is within the channel region) from the N~ or P+
ion implantation due to the thickness of the gate conductor. The source and drain regions of the device fabricated according to such a self-aligned gate process are not appreciably overlapped by the gate and therefore the Miller capacitance of the device is minimiæed.
Although such a procedure is adequate for many standard commercial products, when the channel Gf the device is reduced to submicrometer dimensions, such as VLSI
or highly integrated devices, the depletion layers in the source and drain regions overlap to a certain extent depending upon the doping concentration distribution of the channel region of the device. ~t should be noted that in the enhancement mode, depletion mode, or deep depletion mode of operation of the device, the channel region will be bounded by a vertical N~ and P-~ region for the source and drain down to at least a distance of 0.25 micrometers from the silicon/silicon dioxide interface and usually through the entire Si film to the sapphire. This bound is due to ~3~

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the vertical slope of the etches o the ~ate conductor.
Immediately below the channel region, the depletion layers overlap more and punchthrough is enhanced. Punchthrough is symptomiz~d by a drain-source voltage dependence o the subthreshold current. It i5 also known as a short channel effect.
One approach to a channel making process for forming the source and drain regions as a MOS device is shown in U.S. Patent No. ~,198,250, which utilizes a gate masking member which is etched and the gate oxide beneath the gate undercut to form overhangs. ~hen a substrate is subjected to ion implantation with such a mask, a much shallower concentration of impurities is implanted in the substrate beneath the overhangs than in the substrate region not protected by the masking member. Such a process provides self alignment for the gate and the source and drain regions will be overlapped by the gate more than with the plain self~aligned gate process. The Miller capacitance will be increased slightly compared to the usual S.A.G.
(Self-Aligned Gates) process, but, the likelihood for punchthrough is reduced.
The disadvantage of the process described in the above noted patent is that the amount o~ undercut for sub-microme~er gate dimensions i5 uncontrollable. The prior art describes a process for 2 4 ~m gate lengths where the undercut is typically 0.2~ to 0.5 ~m on each side. However, it is obvious that any undercut of a 0.5 ~m gate length will be too significant, e.g., only 300 Angstroms on a side undercut is 12~ and is not uniform from wafer to wafer and on an individual wafer because of the isotropic etches required by the prior art.
Summary of the Invention In accordance with an aspect of the invention there is provided a process for abricating a MOS
integrated circuit structure at a predetermined portion of a s~bstrate comprising the steps o forming a continuous silicon layer on said substrate; forming a continuous silicon oxide layer on said silicon layer covering at least said predetermined portion; forming a polycrystalline 0~7

- 2~ -silicon layer on said oxide layer such that said silicon layer is insulated from said portion; forming a conducting layer on said polycrystalline silicon layer; forming a resist layer over said conducting layer; etching said resist layer to form a mask having truncated pyramidal shape; milling said conducting layer and said poly-crystalline silicon layer using said resist layer as a mask in order to form a gate element having a shape corresponding to the truncated pyramidal shape of said resist layer mask;
and implanting dopant into said silicon layer using said gate element as a mask so that lighter and shallower degenerately doped areas are formed under the edges of said gate element.
Briefly and in general terms, the present invention describes a process for forming a doped region in a substrate which is in alignment with a circuit member.
More particularly, the invention includes the steps of forming a masking member on a upper layer portion of the substrate, the masking member defining the outline of the circuit member; and etching the layer employing the masking member as a mask to define the circuit member, the etching continuing such that the circuit member includes sloping side faces. An impurity is then ion implanted into the substrate so as to form the doped region, the dosage and

- 3 -energy of ions implanted being selected such that ions are partially blocked by the portions of the circuit member beneath the sloping side faces, thereby providing a more lightly doped and more shallow distribution of implanted species in the substrate region under the sloping side faces which is an extension of the doped region, than in the doped region.
The novel features which are considered as char-acteristic for the invention are set ~orth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
Brief Description of the Grawings The present invention taken in conjunction with the invention of copending Canadian Patent Application Serial No. 407,811 which was Eiled on July 22, 1982, will be described herebelow in detail with the aid of the accompanying drawings, in which:
Figure 1 is a cross-sectional view of a silicon-on-sapphire structure according to the prior art;
Figure 2 is a cross-sectional view of a silicon-on~
sapphire structure employing the truncated pyramidal gate element according to the present invention;
Figures 3a through 3e are cross-sectional views of a silicon-on-sapphire structure illustrating the sequence of steps for forming the doped source and drain regions in ~he said layer according to the present invention.
Description of the Preferred Embodiment Figure 1 is a cross-sectional view of a silicon-on-sapphire structure using a self-aligned gate (S~A.G.) process. The Figure shows the sapphire (A12O3) substrate, a silicon layer thereover with heavily implanted regions (P~ and N~) shown cross-hatched, and the shape and position of the gate conductor. The gate oxide is not shown for simplicity, although the gate oxide thickness tgateoX is represented in the Figure, as well as the thickness of the gate tg.

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- 4 -The fabrication process according to the present inYention is based upon an analysis of the submicrometer gate length structure of the depletion layers ~hich ls predicted, or analyzed, by such device per-formance computer programs as GEMINI (GEMINI Program, Stanford University Electronics Laboratory) and others which calculate the electric field distribution ln two d~mensions ln the channel and are capable of using fabrication process paramete~ data from computer programs such as SUPREM (SUPREM Program, Stanford Unlversity Electronics Labroatory).
If the length of ~he channel region is somehow increased in the channel reg;on approx;mately 0.25~m below the Si-SiO2 interface (where the total SOS film thickness is < 0.5~m), the conditions for punchthrough are reduced and the short channel behavior of the device can be eliminated under proper design constraints w~th respect to the channel dopant concentration profiles.
Turning next to F;gure 2, there is shown a cross-sectional view of a CMOS/SOS device fabricated according to the technique of the present invention. It is noted that the gate elements in both the N-MOS and P-MOS transistors are depicted in the cross-sectional view are in the shape of a trapezoid. In three dimens~ons, the shape of the gate element would be a truncated pyramid. ~t is noted fron Figure 2 that the sldes of the pyramid are slopped away from the normal or perpendicular direction to the surface by an angle of ~
where ~ is greater than 30. The truncated portion of the pyram;d has a top major surface with a length equal to "L", approxlmately 0.5 to 0.75 microns. The~thickness of the gate tg is typically between 3000 and 4000 Angstroms. The length of the base of the pyramid is L , which is L ~ 2tg Tan ~. The typical experimental data shows L -0.7u, (with tg = 3050 Angstroms). The distance between the bottom surface of the gate element and the upper major surface of the silicon structure, which is equivalent to the thickness of the gate oxide is toX, which is approximately 100 to 350 Angstroms.

- 5 -The fabrication process according to the present invention focuses upon the mask;ng property of a circuit member, such as the gate conductor, as a ~unction of its thickness w;th respect to the N+ and P+ ion implants, and also upon the slope of the gate conductor edges deviat;ng from the vert;cal. Although if the thickness,;t, of the gate conductor at any point on the dimenslon of the gate conductor is less than that required to shield, or mask, the channel region from the N~
or P+ S.A.G. implants, tg~ the dopant ions w;ll penetrate ;nto the silicon i~mediately beneath the Si-5~02 interface to an extent depend~ng upon the extent that the gate conductor thickness is 1ess than tg~ A
gate conductor with edges that deviate from the vertical by some angle, , will therefore have a degenerately doped S and D region that will extend beneath the maximum dimension, Lm~ of the gate with a depth distribution that will depend on ~ as shown in the cross~sectional view of ~he device according to the present invent;on in Figure 2.
The etch procedure requires a defini~ely anisotropic characteristic such that the sloped resist edge profile of the gate pattern is faith-fully reproduced in the gate conductor. There is no masking member of the gate conductor other than the resist hence there is one less oxidation and etch step than the prior art. The gate oxide (100-350 Angstroms) is not etched. It is most important to point out from this figure that the channel dimension at about 0.25um below the Si-SiO2 interface where punchthrough of the S and D depletion regions was formerly a problem, is now increased to a dimension, L~ > L. Therefore>
the principal source of the short channel behavior of submicrometer MOSFET devices can be eliminated or at least greatly reduced in the structure formed by the process according to the present inventlon.

- 6 -Turning next to the s;licon structure itself, it is noted that the source and drain reg;ons are determ~ned by ion lmplant;ng through the gate oxide layer with the region under the gate pyramid being masked from the implant by the gate materlal of thickness, tg~ The areas ion implanted are indicated by the cross hatched reglons in Figure 2 to indicate that the amount of implantation or concentratlon of the dopant species is controlled so that some imp1antation occurs through the thin tapered edges of the gate element to form a l~ghter and shallower degenerately doped region directly under the tapered 3 edges of the gate adjacent to the top major surface of the silicon semiconductor. The Figure lndicates that th;s shallower degenerately doped region extends into the semiconductor body a distance of approximdtely 0.25 microns. Most of the ion ~mplantation is implanted into the semiconductor body in the regions not protected by the masking ~ember formed by the gate element. Directly underneath the center portion of the gate element there i5 effectively no ion implantation into the semiconductor body.
The GEMIMI Program can be used ts predict the device behavior with respect to the short channel effect and is based similar to the O "Bell Criterion." (J. R. Brews et al, IEDM Washington, D.C., December 1979). If La or L is large enough such that the subthreshold MOSFET
current will have a negligible dependence on the drain supply voltage, VD, the crlterion for L or La belng large enough depends upon the channel dopant concentration and its profile with respect to depth : L2~6~l7 into the silicon from the Si-SiO2 interface.
A sloped gate edge connector can readily be fabricated by the technique according to ~he present invention. An image reversal resist technique using electron beam exposure of a positive photo-resist followed by an optical UV flosd exposure results in the pos;tive photoresist behaving as a negative resist. (W. G. Oldham, E. ~eike, IEEE Trans. EDL-l (10), 217, 1980). The resist edge profiles using this method are sloped with some angle, ~, from the vertical. If a dry etching technique (Fineline Lithography, Roger Newman ed., North Holland Publishing Co., Amsterdam, 1980 (Chap. 4., R. L. ~addox, M. R. Splinter)), such as ion milling, reactive ion etching, parallel plate plasma etching, or reactive ion beam etching is used, an etched gate conductorSprofile with ~lope of angle, ~, can be faithful~y reproduced from the resist profile.
l~ In addition, the characteristic of sloped ~ate conductor edge profiles ~llows for a much relaxed step coverage condition in consideration of conductor layers deposlted on top of the gatP con-ductor pattern which criss cross and still maintain continuity such as is required for VLSI.
One possible drawback regarding the present configuration is the increased Miller capacitance caused by the gate electrode overlapping the sloped gate edges. ~his overlap will be equal to X = tg tan ~.
With an angle on the order of 45, the current tg is about 0.3~m.
Therefore, a Miller capacitance of about 30X of the channel gate input ~5 capacitance would be the result. However, ~or su~micrometer devices,~he gate input capacitance is no longer the domlnant factor compared to the interconnect capacitance and, hence, the speed of the device would not be nearly as affected as if the situation were directly scaled up to a 4~m gate length,for ex~mple. Note also that ~
can be adjusted by the Electron Beam Lithographlc~ EBL, or other resist processing variables wlth respect to the image reversal technique (W. G. Oldham, E. Heinke, IEEE Trans, EDL-l (10), 217, 1980) such that the overlap capacitance ~s less than 30~. Also, tg can be adjusted for a reduction. However, reducing the Miller capacitance will reduce La and a co~promise must be made.

Turning next to Figures 3a through 3e, there is shown the sequence of steps for forming the gate elements and the implanted source and drain regions according to the present invention.
Turning ~irst to Figure 3a, there is shown a composite of a S silicon-on-sapphire structure which may be used for ~on implanting according to the present invention. The silicon layer on the sapphire substrate typically has a thickness between 4500 and 6000 Angstroms. The structure includes a gate oxide layer on the top major surface of the silicon layer, followed by a :polycrystalline silicon (polysilicon) layer over the oxide layer. The polys~licon layer is typically doped with phosphorous 50 that it is N~ conductivity and has a thickness between 300 and 1200 Angstroms. A molysilicide layer is applied over the P~ or N+ polysilicon layer, and a photoresist layer applied over the molysilicide layer. The use of any suitable refractory metal silicide (e.g. tantalum silicide, tungsten~silicide or tltanium silicide) is also within the scope of the present invention. The use of a poly-silicon-molysilicide layer is used in the preferred embodiment because of the greater conductivity provided by such a structure and its suitability for ultra large scale integrated devlces. Other conductive layers can be used as well. According to the techniques of the present invention, the photoresist layer is a positi~e photoresist layer.
Turning next to Figure 3b, there is shown the step in which the photoresist layer is selectively exposed to an electron beam in a predetermined pattern. The layer of photoresist is exposed where the electron beam passes and this photoresist layer portion is to remain after further processing.
The electron beam is directed to the reslst substantially normal to the surface of the resist layer. As it penetrates into the thickness of the layer, the e1ectron beam scatters, and diverges from the surface.
The net affect of the scattering of the electrons in the resist layer is the exposure of the resist in a cross-section representing a trapezoid such as that shown in Figure 3b. Since the area exposed by ~L2~ 6~7 g the electron beam is typically that of a gate element, or other channel structure in a self-aligned MOS-MIS-MES dev~ce, the actual geometric structure exposed in the resist layer is that of a truncated pyramid.
The use of an electron beam for exposure of a positiYe resist is also described in the article W. G. Oldham, E. Heinke, IEEE Trans. EDL-l (10), 217, 1980.
Following exposure to the electron beam, the entire photoresist layer is flooded with ultraviolet light. The ultraviolet light reacts differently with the portions of the resist exposed by the electron beam than the portions which have not been exposed. The net effect is that after the layer of photoresist is etched, the portions which have been exposed to the electron beam remain, such as shown in Figure 3c. The truncated pyramidal resist structure is then used as a mask for re~oving portions of the conductive layer which do not lie under the mask. The removal of these portions of the conductor layer is achieved by a standard etch1ng process such as reactive ion etching or ion milling.
The etching process leaves truncated pyram;dal elements consisting of a top layer of resist, followed by a lower conductive layer or layers. Such truncated pyramidal structures lie on the silicon oxide surface of the body as is shown in Figure 3d.
The next process step is to remove the remaining resist 1ayer from the top of the pyramid. This is performed by the process of plasma ashing.
2s The structure which remains ;s shown in Figure 3e which consists of a truncated pyramidal gate type element which overlies the silicon semiconductor body. Such a structure is then used as a mask for ion implanting the source and drain regions of the semiconductor body in a self-aligned manner as is known in the techniques according to the art. The impurity profiled distribution in the source and drain regions and in the channel after ion implantation ~s substantially as shown in Figure 3e. The net effect is that the distance between the source 9~z~a6~7 and drain regions are closest at the surface of the semiconductor body and spaced further apart as the distance from the surface increases.
It ls noted that some implantation occurs in the substrate region below the sloping side faces of the gate-type circuit element.
Such implantation results in the formation of a more lightly doped source and drain regions beneath such side faces, while more heav~ly doped suurce and drain regions are provided in the silicon regions unprotected by the masking member. The doses and energy of the ions implanted are so selected such that the ions are partially blocked by the portion of the gate struc~ture beneath the sloping side faces, so as to provide a more shallow distribution of the implanted species in the region directly underneath the sloping side faces than in other regions.
The result of the formation of the gate element aecording to the present invention is a self-aligned process in which the distance between the source and the drain regions in the depth of the semi-conductor body (;.e., semiconductor regions deeper than 0.25~ from the top major surface) are relatively spaced apart a greater distance than at the surface, thus minimizlng the problem of punchthrough.
While the invention has been illustrated and described as embodied in a microelectronic shadow masking process for reducing punchthrough, it is not intended to be limited to the detalls shown, since various ~odifications and structural changes may be made without departing in any way from the spirit of the present invention.
It will be obvious to those skilled in the art that the semiconductor device according to the present invent~on can be implemented with various semiconductor technologies and different comb~nations of known process steps, and that the preferred embodiments illustrated here are merely exemplary. The depth of penetration of the various zones and regions and in particular the configuration and distance between the active zones of the transistor devices, as well as the concentrations of dopant species, and/or their concentration profiles, can be chosen depending upon the desired properties. These and other variations can be further elaborated by those ski11ed in the art without departing from the scope of the present invention.

The present invention is moreover not restricted to the particular embodiments of a microelectronic shadow masking process for reducing punchthrough described. For example, it may be pointed out that semi-conductor materials other than silicon, for example, AIII~B~ compounds may be used. Furthermore, the conductivity types in the embodiment ~ay be interchanged and corresponding to such change, the voltage level and the static or dynamic nature of the signals applied to the various terminals and gates of the device, as well as the voltage sources, may be suitably selected as desired for a particular application. Other types of semiconductor circuits including bipolar junction field effect transistor, MNOS (metal electrode-silicon nitride, silicon oxide-semiconductor), MAOS (metal aluminum oxide, silicon oxide, semiconductor), MAS (metal, aluminum oxide, semiconductor), floating gate FETs, and AMOS FETs (avalanche MOS FETs), may be used as well.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitutes essential characteristics of the generlc or specific aspects of this invention, and, therefore, such adaptations should and are intended to be comprehended within the meaning and range of equivalence of the following claims.

Claims (4)

Claims:

1. A process for fabricating a MOS integrated circuit structure at a predetermined portion of a substrate comprising the steps of:
forming a continuous silicon layer on said substrate;
forming a continuous silicon oxide layer on said silicon layer covering at least said predetermined portion;
forming a polycrystalline silicon layer on said oxide layer such that said silicon layer is insulated from said portion;
forming a conducting layer on said polycrystalline silicon layer;
forming a resist layer over said conducting layer;
etching said resist layer to form a mask having truncated pyramidal shape;
milling said conducting layer and said poly-crystalline silicon layer using said resist layer as a mask in order to form a gate element having a shape corresponding to the truncated pyramidal shape of said resist layer mask;
and implanting dopant into said silicon layer using said gate element as a mask so that lighter and shallower degenerately doped areas are formed under the edges of said gate element.

2. The process defined by claim 1 wherein said polycrystalline silicon layer is doped with phosphorus.

3. The process defined by claim 1 wherein said silicon layer is between 4,500 and 6,000 Angstroms in thickness.

4. The process defined by claim 3 wherein said silicon oxide layer is between 100 and 350 Angstroms in thickness.