CA1199734A - Process and apparatus for the exchange of data between processing modules and at least one common memory in a data processing system - Google Patents
Process and apparatus for the exchange of data between processing modules and at least one common memory in a data processing systemInfo
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- CA1199734A CA1199734A CA000418356A CA418356A CA1199734A CA 1199734 A CA1199734 A CA 1199734A CA 000418356 A CA000418356 A CA 000418356A CA 418356 A CA418356 A CA 418356A CA 1199734 A CA1199734 A CA 1199734A
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- bus
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- signal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
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- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
Process for the exchange of data between processing modules and at least one common memory. It comprises multiplexing, on a common connecting bus bet-ween these modules and the common memory, at least address set (BA0 to BA31) and at least one data set (BD0 to BD31) corresponding to these addresses, in such a way that the data set is synchronously transmitted after the address set.
Process for the exchange of data between processing modules and at least one common memory. It comprises multiplexing, on a common connecting bus bet-ween these modules and the common memory, at least address set (BA0 to BA31) and at least one data set (BD0 to BD31) corresponding to these addresses, in such a way that the data set is synchronously transmitted after the address set.
Description
73~
PROCESS AND APPARATUS FOR THE EXCHANGE OF
DATA BETWEEN PROCESSING MODULES AND AT LEAST
ONE COMMON ~EMORY IN A DATA PROCESSING SYSTEM
~ACKGROUND OF THE INVENTION
The present invention relates to a process for the exehange of data between proeessing mo~ules and a-t least one common memory in a data processing system, as well as to an apparatus for performing this proeess.
The invention is applieable to -the exehange of data between processing modules and at least one memory, whieh ~s eommon to all these modules by means of a eollecting bus. Generally, these proeessing modules comprise a proeessor or mieroproeessor assoeiated with a local memory.
In the field of processors and more particularly mieroproeessors, it is often possible to solve in a eomplex and costly manner the problems of exchanging data and signals between several processors conneeted to the same bus making it possible for these to have acc~ss to a common resource, such as e.g. a memory. It is obvious that increased importance has been attached to this sinee the appearance of microprocessors beeause, in view of the relatively high power thereof, their eost and -their relatively small overall dimensions, it is inereasingly in-ter-esting to ~esign multiproeessor systems in which the proeessors have aceess -to common resources by means of a eommon bus. In a multiprocessor system, the different modules of the system are physically on different printed cireuits. The interconneetion bus or buses between these modules have a very great influenee on the performance of the system. It is also known that the known buses do not make it 3~
possible in a relatively easy manner to inter-connect modules having incompatible operating characteristics. Thus, any designer of a multiprocessor system must constantly look for a compromise between the compatibility of the modules which he has to interconnect by means of a bus, and the performance of the system as a result of this interconnection.
The problem of operating compatibility between processing modules from different manufacturers has not played an important part in the design of the last generation of computers because, in general, no effort was generally made to interconnect computers made by different companies. In fact, manufacturers had no interest in making their computers compatible with those of competitors, because in multiprocessor systems, the same manufacturer supplied all the modules to be inierconnected.
However, the arrival of minicomputers, micro-computers and microprocessors has made it possible to develop multiprocessor systems but, as in the past, it is generally only possible to interconnect several processors by means of a separate bus for each multiprocessor system. Thus, the designers of multiprocessor systems respectively develop their own exchange bus between processing modules and the common memory. The recent arrival of ~6 bit and even 32 bit microprocessors has made the old exchange buses incompatible with the specifications of these new microprocessors and all -the previously designed huses can no~ no longer be used. Sometimes the buses designed for the earlier multiprocessor systems have become standard buses and, for new ~973~
systems using microprocessors, it is necessary to add functions to the standard buses to make them compatible with the new generation of microprocessors. This is costly and leads to buses with poor performance levels.
Finally, most data exchange buses in multiprocessor systems require very complicated exchange proce~ures and their construction makes them very onerous. Generally, these buses have operating parameters which are very difficult to respect, as werr as a very poor adaptation between the number of data exchange lines in each bus, the number of addresses and the volume of data to be transmitted. These buses cannot be produced in integrated form.
BRIF.F SUMMARY OF THE INVENTION
The object of the invention is to obviate these disadvantages. It therefore relates to a pro~ess for the exchange of data between processing modules and a common memory in a data processing system, as well as to an apparatus -for performing this process. As a result of the process and apparatus according to the invention 5 it is possible to interconnect processors or microprocessors of different types, by making the dialogue of these various microprocessors on the bus independent of -the operating ;signals required by the microprocessor manufacturer. The data exchange apparatus according to the invention makes it possible, in the manner to be shown hereinafter, not only -to exchange data between di~ferent processors or microprocessors, but also to exchange arbitration signals o~ access requests of the processors to the bus, multiprocessor system interruption signals, synchronization signals ;973~
between different processors, etc.
Thus, tl~e present invention firstly rela-tes to a process for the exchange of` data between processing modules and at least one common memory in a data processing system, wherein it comprises multiplexing, on a common connecting bus between these modules and the common memory, at least one address set (BA0 to BA31), and at least one data set (BD0 to BD 31) corresponding to these addresses, in such a way that the data set is transmitted after the address set in a synchronous manner.
According to another feature of the present process, it also comprises multiplexing on the bus, on the one hand the arbitration of access requests to the bus ~a to R7) coming from arbitration means corresponding respectively to the processing modules and which are connected to the bus and, on the other hand the address set (BA0 to BA31) and the data set (BD0 to BD31), in sucn a way that the arbitration requests are transmitted to the bus af`ter the data set.
According to another feature, the process consists of transmitting on the bus, control signals (BRZT, BUS HALT, BUS ALARME, BTST) from the modules o~ the system.
According to another feature, the system module control signals comprise signals (BRZT) indicating that power has been res-tored a~ter interrupting the power supply to -the modules, signals (B HALT) indicating the stopping of one or more modules7 signals (B ALARME) indicating an alarm due to an operating fault on one or more modules and signals (BTST) for the interruption of` all the modules for testing purposes.
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According to another feature, the process also consists of synchronizing the different modules by interruption signals transmitted on the bus.
According to another feature 7 the interruption signals comprise an overall system interrup-tion signal ~B APPEL1~, said signal being supplied by one mod~le and is transmitted to all the others in order to be stored in a receiver of each of these modules, an overall interruption signal (B APPEL2) at the end of the task performed by the system, sai~ signal being stored in a transmitter of one of the modules9 a signal (BMASQ) supplied by one module for masking the interruption signals supplied by the other modules, a signal (BRTAS) for resetting the local flip-flops in each module ~or indicating that the common memory is not available.
Finally, according to another feature, the pro~ess also consists of transmitting on the bus 9 a signal (BCBM) for switching the common memory to a duplicated memory thereof, a signal ~BVC) for validating the signal (BRZT) for indicati.ng that power has been restored after the interruption of the electric power supply of the modules an~ a signal (BVP) for validating the parity of the data transmitted on the bus.
The invention also relates to an apparatus for the exchange of data be-tween processing modules and at least one common memory in a data processing system, wherein said apparatus comprises a bus common to these modules and to the memory and, -for each module, a system for arbitrating access re~ues-ts to the bus, transmitted by each module, wherein it also comprises for each module, multiplexing means 73~
connected to the said module and to the bus for multiplexing the addresses (BA0 to BA31) and the data (BD0 to BD31) to be read or written into the common memory, and a time base generator connected to the corresponding arbitration system and to the multiplexing means, said time base generator and said multiplexing means being designed in such a way that a data set (BD0 to BD31) is transmitted on the bus ~ollowing a corresponding address set (BA0 to BA31) in a synchronous manner.
According to another ~eature9 the time base generator and the multiplexing means are also dssigned for multiplexing on the bus, on the one hand the arbitration of the access requests (R0 to R7) to the bus, coming from the arbitration ~ means, and on the other each data set (BD0 to BD31), i in such a way that these arbitration requests are transmitted to the bus, after each data set in a sy~chronous manner.
According to another ~eature, the apparatus also comprises system control means connected to the bus for transmitting control signals ~rom the modules.
According to another ~eature, the apparatus also comprises synchronization means connected to the bus and -~or synchronizing the modules by the transmission of interruption and masking signals to the bus.
Finally, according to another ~eature, the apparatus also comprises protec-tion means connected to the bus for transmitting a signal (BCLM) ~or switching the common memory with a duplicated memory, ~or transmitting signals (BVC) ~or validating the signals (BRZT) indicating the restoration of power to the modules a~ter an interruption to the power 73~
supply thereof, and for validating data circulating on the bus and accompanied by parity information.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described in greater detail hereinaPter relative to non-limitative embodiments and the attached drawings, wherein show:
Fig. 1 diagrammatically a multiprocessor system using a data exchange apparatus according to the invention. 0 Fig. 2 certain o~` the signals circulating on the bus, during data exchange, for a reading operation in the common memory.
Fig. 3 certain o~ the signals circulating on the bus, during a data exchange, ~or a writing operation in the common memory.
Fig. 4 certain of the signals circulating on the bus, during a data exchange, for a reading and writing modificatlon operation in the common memory. 0 DETAILED DE~CRIPTION OF THE PR~FERRED_EMBODIMENTS
Figo ~ diagrammatically shows a multiprocessor system using a data exchange apparatus according to the invention. This multiprocessor system comprises processing modules 1, 2, whose number has been limited to two in order not to overburden the drawing. These processing modules respectively comprise microprocessors or processors 3, ~, respectively associated with local memories 5 7 6.
The apparatus according to the invention permits a data exchange on the one hand between the different processing modules and on the other hand between said modules and a common memory 7. The apparatus also comprises a bus, which is common to all these modules and to the memory and, for each 73~
module ? a system for arbitrating on the access requests to the bus coming from each modu]e. These arbitration systems or means are designated 8 7 9 in the drawing. The access requests are formulated at outputs lO, 11 of microprocessors 3, ~. They are transmitted to the arbitration means 8, 9, which make it possible to arbitrate on the requests from each module. These arbitration means are not described in detail here, becuase they are described in CanadianPatent Application 410,780 filed on September 3rd, 1982 in the name of the present Applicant. ~or each module, the apparatus also comprises multiplexing means, shown at 12, 13. These multiplexing means are connected to the corresponding modules, as well as to the first address line 17 of the bus. They make it possible to multiplex the addresses (BAO to BA31) and the data (BD0 to BD31) to be wri-tten or read in the common memory 7.
The number of these addresses obviously corresponds to the characteristics of the microprocessors used which, in the embodiment shown in the drawing, are assumed to be 32 bit microprocessors. However9 it is obvious that this number can differ. The apparatus also comprises~ for each of the modules, a time base generator connected to the arbitration means and to the corresponding multiplexer.
In the drawing, the time base generators are represented as 15, 16. The time base generator and the multiplexing means are designed in such a way that, as will be shown hereinafter, a data set (BDO to BD31) is transmitted on the bus after a corresponding address set (B~O to BA31) and in a synchronous manner. The arbitration means ~, 9 are connected to the third line 19 of the bus. The time base generator, as well as the multiplexing means are also designed for multiplexing on the bus, on the first line thereof, on the one hand the arbitration of access requests (R0 to R7) to the bus coming from the various arbitration means and, on the other hand, each data set (BD0 to BD31).
The arbitration requests are transmitted on the bus, a~ter each data set and in a synchronous manner.
The access requests (R0 to R7~ are transmit-ted on the first line 17 of the bus, which also transmits _. .
the addresses and data. In the present embodiment, it has been assumed that the multiprocessor system comprises seven interconnected microprocessors on the bus, although only two of these are shown in the drawing. Thus, seven access requests to the bus have~ to be arbitrated. The signals BES
circulating in the first line 17 of the bus are not involved in the performance of the process according to the invention. These signals are already used in the known buses and make it possible to corli~rol the input - output operations.
The apparatus also comprises the control means 23 of the system, which are connected to the fourth line 20 of the buso These control means are common to all the modules and supply the signals indicated in the drawing and which w~ll be described hereina~ter. These signals make it possible to perform certain module control operations.
The apparatus also coMprises synchronization means 2~ connected to the fifth line of the bus for synchronizing, in the manner to be shown hereinafter, the various modules by the transmission of in-terruption and masking signals on the bus. Finally, the apparatus comprises protection means 25 connected to ~9~73~
the bus for transmitting a signal BCLM for switching the common memory 7 with a duplicated memory 26, said means also making it possible to transmit a signal BVC (-for validation of signals BCS and BRZT) indica-ting an interruption o-f the power supply or a restoration of power to the modules. Finally, these protection means also supply a signal BVP making it possible to validate data circulating on the bus and which are accompanied by parity information. Other signals circulate in the lines of the bus described hereinbefore. These signals are already used in known buses and will be described hereinafter.
Bus control means 27, 28 are also shown and are respectively connected to each o~ the modules and to the second line 18 of the bus. These means are known in the art and make it possible to supply bus control signals, which will be described hereinafter.
In the apparatus shown in the drawing, it is assumed that the outputs` 29, 30, 31 of the microprocessor respectively supply addressing information, data and reading/writing information.
It is also assumed that the input 32 o-f each time base generator 15 receives from the corresponding arbitration means 8 in-~ormation indicating that an access request to the bus -from the processor has been accepted.
Figs. 2, 3 and 4 are chronograms of the signals involved in an exchange of data by means of the bus.
Fig. 2 shows the slgnals in the case where ~he data exchange relates to a data reading operatio~
in the common memoryO It can be seen in Fig. 2 that the data (BDO to ~D31) are transmitted synchronously ;
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after the addresses (BA0 -to BA31) on the first line 17 of the bus. The other signals involved in this drawing are signals transmitted by -the second bus line 13 and which will be described hereinafter.
Fig. 3 shows the chronogram of the signals involved on -the bus in the case of a writing operation in the common memory. As in Fig. 2, the other signals shown in Fig. 3 are signals circulating 0 in the second bus line 18.
Finally, Eig. 4 shows a data exchange on the bus, in the case of a data reading operation, followed by a writing operation in the common memory. The other signals shown in Fig. ~ are once again signals circulating in the second bus line 18. It can also be seen that the read or written data are transmitted on the bus of the addresses in a synchronous manner. References 01, ~2, a3, a4~ 05 represent the time intervals having the following durations:
- duration 01 of close to 60 ns corresponds to a prepositioning of addresses with respect to the signal BAL;
- duration ~2 of close to 60 ns corresponds to the maintainance of the addressing time with respect to signal BAL, said duration also corresponding to a time lag between signals BUDS and BLDS;
- duration ~3 is also close to 60 ns and corresponds to the time interval between the transmission of the addresses and the synchronous transmission of the da-ta of the bus;
- duration e4 can be regulated and corresponds 73~
to the time lag of signal BDTACK compared with signals BUDS and BLDS;
- finally, duration ~5 corresponds to the maximum data transmission maintaining time with respect to the switching of signal BEC~
A description will be given hereinafter of signals BAL, BUDS, BLDS, BDTACK, BQDS.
A more detailed description will now be given o-~ the signals appearing on the different lines o~ the bus, by indicating in a more specific manner which are involved in the apparatus and process according to the invention.
Signals on the first line of the bus -reference 17 (addresses, data, access request,input - output).
(BD0 to data exchanged on the bus and transmitted, BD31) according to the invention, after the addresses in a synchronous manner.
(BA0 to addresses of data and these addresses ) must be stored by BAJ;.
BES: input - outpu-t signalO Active if its logic level = 0 - equivalent to one supplementary address line. Makes it possible to address 16M memory octets and 16M input - output octets, ~or exampleO
This signal occurs in the known buses.
During the second phase of an exchange~
certain address lines and BES are available and are used for carrying the access requests to the buses of the different processing modulesO
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Signals on the second line of the bus -(reference 18 - bus control signals).
BECH: exchange bus: active if level = 0.
Signal has three states. Indicates that the signals on the bus are valid.
BAL: latch address bus (locking of addresses on the bus): ac-tive if level = 0.
Signal has three states and makes it possible to store addresses BAO to BA31 and BES.
BW: writ~ng bus: active if level = 0.
Signal with three states. Indicates the direction of trans~er on the bus:
writing if level = 0, reading if level = 1.
BUDS: "Bus upper date strobe" (upper sampling of data on bus): active if level - 0.
Signal with three states. Validates the exchange for the more significant data.
BLDS: "Bus low data strobe" (lower sampling of data on bus): active if level = 0.
Signal has three states. Validates the exchange for less signi~icant data.
BDTACK: acceptance of less significant data transfer on bus: active if level = 00 Signal has three states. Supplied asynchronously by -the module, which recognizes that arbitration is taking place and accepts the trans~er. 0 BBERR: error bus: active if level = 0, collector open. Active if a module or a memory detects an uncorrected error and the cycle ta~ing place must be aborted.
A11 these signals occur in the known buses, 3~
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I'hird line of the bus (reference 19 -arbitration signals).
BNA: designation of a new arbitrator of the bus, collector open, active if level = 0.
BM1 to designation of the coded number of the BM3: master module of the bus, collector open.
BM4: validation of BM1 to BM3 - active if level = 0, collector open. If BM4 = 0, the data BM1 to BM3 are validated.
BREQ: request for access to bus - active if level = 0. Collector open, access request to common-bus.
15 BAP: possible arbitration bus - active i~
level = 1, collector open.
All these signals are described in the aforementioned French Patent Application.
Fourth line of the_bus (reference 20 - control signals of the system).
BRZT: restoration of power supply 9 active if level = 0, duration exceeds 100 ms.
BHALT: bus stop: active if level = 0, collector open. Indicates that one or more modules are in the stop state.
BALARME: alarm bus: active if level = 0, collector open. Indicatés an alarm state on one or more modules.
BMA: stop - go signal.
30 BCS: interruption of power supply active if level = 0, collector open.
BTST: test interruption - active if level = 0, collector open~ Interruption of system.
Starts up all the modules for testing purpo-ses.
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Signals BUS ~IALT, BUS ALARME, BTST are used in -the process and appara-tus according to the invention, whereas the others are known.
Fifth line of the bus (reference 21 - module .
synchronization signals and interruption signals).
~APPELi: interruption - active if level = 09 collector open. Overall interruption;
Call from one processing module to the other processing modules. Stored a-t the module receivers.
BAPPEL2: interruption - active if level = O, collector open. Overall interruption at the end of the operations started by one module towards another processing module. Stored at the transmitter of the module supplying the signals in a local flip-flop thereo-f and not shown in the drawings.
BM~SQ: Overall masking of t~e BAPPEL2 signals -active if level = O, collector open.
B~TAS: resetting of local flip-flops - active if level = O, collector open.
All these signals are used in the process and apparatus according to the invention~
Sixth line of the bus (re-~erence 21 - protect-ion signals: memory s~itching, power restoration validation, etc.).
BCLM: switching the common memory to a duplicated memory.
30 BPM: memory protection. Inhibits writing in the case where the oommon memory is protected from interruptions to power supplies.
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BVC: control valida-tion. Confirms the state of signals BRZT and BCS.
BVP: parity validation. Signal wi-th three sta-tes. This signal is active if a parity accompanies the data.
BP0 BP1 these signals indicate the parities of BP2, BP3 the addressing information multiplexed with the data.
Signals BCLM, BVC, BVP are used in a process according to the invention, whilst the other signals existin the known buses.
The process and apparatus described hereinbefore make it possible to achieve the aforementioned objectives: the introduction of data on the bus is carried out synchronously with the introduction of addresses, whilst the overall operation o~ the system can be asynchronous. The arbitration of the access requests to the bus of the dif~erent modules takes place directly on the ad~ress lines and during the data e.~change phase.
Moreover, the apparatus described hereinbe~ore makes it possible to directl~- manage the interrupticns from the bus, which is impossible with the existing exchange means. Thus, in the existing means, there are interruption lines between the different modules, whereas in the means according to the invention, specialized management lines make it possible to carry out an overall management of the interruptions, as a result of masking procedures. As indicated herein-before, as a result of the signal BRTAS J one line ofthe bus makes it possible to release resources on all the modulesO Finally9 the lines of the bus and which are used in -the apparatus are not grouped according to functionality criteria and are instead distributed 73~
as a function of their sensitivity to noise, which makes it possible to obtain much less complicated line terminations. The bus in~olved in the apparatus is a high availability bus with good performance features.
PROCESS AND APPARATUS FOR THE EXCHANGE OF
DATA BETWEEN PROCESSING MODULES AND AT LEAST
ONE COMMON ~EMORY IN A DATA PROCESSING SYSTEM
~ACKGROUND OF THE INVENTION
The present invention relates to a process for the exehange of data between proeessing mo~ules and a-t least one common memory in a data processing system, as well as to an apparatus for performing this proeess.
The invention is applieable to -the exehange of data between processing modules and at least one memory, whieh ~s eommon to all these modules by means of a eollecting bus. Generally, these proeessing modules comprise a proeessor or mieroproeessor assoeiated with a local memory.
In the field of processors and more particularly mieroproeessors, it is often possible to solve in a eomplex and costly manner the problems of exchanging data and signals between several processors conneeted to the same bus making it possible for these to have acc~ss to a common resource, such as e.g. a memory. It is obvious that increased importance has been attached to this sinee the appearance of microprocessors beeause, in view of the relatively high power thereof, their eost and -their relatively small overall dimensions, it is inereasingly in-ter-esting to ~esign multiproeessor systems in which the proeessors have aceess -to common resources by means of a eommon bus. In a multiprocessor system, the different modules of the system are physically on different printed cireuits. The interconneetion bus or buses between these modules have a very great influenee on the performance of the system. It is also known that the known buses do not make it 3~
possible in a relatively easy manner to inter-connect modules having incompatible operating characteristics. Thus, any designer of a multiprocessor system must constantly look for a compromise between the compatibility of the modules which he has to interconnect by means of a bus, and the performance of the system as a result of this interconnection.
The problem of operating compatibility between processing modules from different manufacturers has not played an important part in the design of the last generation of computers because, in general, no effort was generally made to interconnect computers made by different companies. In fact, manufacturers had no interest in making their computers compatible with those of competitors, because in multiprocessor systems, the same manufacturer supplied all the modules to be inierconnected.
However, the arrival of minicomputers, micro-computers and microprocessors has made it possible to develop multiprocessor systems but, as in the past, it is generally only possible to interconnect several processors by means of a separate bus for each multiprocessor system. Thus, the designers of multiprocessor systems respectively develop their own exchange bus between processing modules and the common memory. The recent arrival of ~6 bit and even 32 bit microprocessors has made the old exchange buses incompatible with the specifications of these new microprocessors and all -the previously designed huses can no~ no longer be used. Sometimes the buses designed for the earlier multiprocessor systems have become standard buses and, for new ~973~
systems using microprocessors, it is necessary to add functions to the standard buses to make them compatible with the new generation of microprocessors. This is costly and leads to buses with poor performance levels.
Finally, most data exchange buses in multiprocessor systems require very complicated exchange proce~ures and their construction makes them very onerous. Generally, these buses have operating parameters which are very difficult to respect, as werr as a very poor adaptation between the number of data exchange lines in each bus, the number of addresses and the volume of data to be transmitted. These buses cannot be produced in integrated form.
BRIF.F SUMMARY OF THE INVENTION
The object of the invention is to obviate these disadvantages. It therefore relates to a pro~ess for the exchange of data between processing modules and a common memory in a data processing system, as well as to an apparatus -for performing this process. As a result of the process and apparatus according to the invention 5 it is possible to interconnect processors or microprocessors of different types, by making the dialogue of these various microprocessors on the bus independent of -the operating ;signals required by the microprocessor manufacturer. The data exchange apparatus according to the invention makes it possible, in the manner to be shown hereinafter, not only -to exchange data between di~ferent processors or microprocessors, but also to exchange arbitration signals o~ access requests of the processors to the bus, multiprocessor system interruption signals, synchronization signals ;973~
between different processors, etc.
Thus, tl~e present invention firstly rela-tes to a process for the exchange of` data between processing modules and at least one common memory in a data processing system, wherein it comprises multiplexing, on a common connecting bus between these modules and the common memory, at least one address set (BA0 to BA31), and at least one data set (BD0 to BD 31) corresponding to these addresses, in such a way that the data set is transmitted after the address set in a synchronous manner.
According to another feature of the present process, it also comprises multiplexing on the bus, on the one hand the arbitration of access requests to the bus ~a to R7) coming from arbitration means corresponding respectively to the processing modules and which are connected to the bus and, on the other hand the address set (BA0 to BA31) and the data set (BD0 to BD31), in sucn a way that the arbitration requests are transmitted to the bus af`ter the data set.
According to another feature, the process consists of transmitting on the bus, control signals (BRZT, BUS HALT, BUS ALARME, BTST) from the modules o~ the system.
According to another feature, the system module control signals comprise signals (BRZT) indicating that power has been res-tored a~ter interrupting the power supply to -the modules, signals (B HALT) indicating the stopping of one or more modules7 signals (B ALARME) indicating an alarm due to an operating fault on one or more modules and signals (BTST) for the interruption of` all the modules for testing purposes.
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;J~3~
According to another feature, the process also consists of synchronizing the different modules by interruption signals transmitted on the bus.
According to another feature 7 the interruption signals comprise an overall system interrup-tion signal ~B APPEL1~, said signal being supplied by one mod~le and is transmitted to all the others in order to be stored in a receiver of each of these modules, an overall interruption signal (B APPEL2) at the end of the task performed by the system, sai~ signal being stored in a transmitter of one of the modules9 a signal (BMASQ) supplied by one module for masking the interruption signals supplied by the other modules, a signal (BRTAS) for resetting the local flip-flops in each module ~or indicating that the common memory is not available.
Finally, according to another feature, the pro~ess also consists of transmitting on the bus 9 a signal (BCBM) for switching the common memory to a duplicated memory thereof, a signal ~BVC) for validating the signal (BRZT) for indicati.ng that power has been restored after the interruption of the electric power supply of the modules an~ a signal (BVP) for validating the parity of the data transmitted on the bus.
The invention also relates to an apparatus for the exchange of data be-tween processing modules and at least one common memory in a data processing system, wherein said apparatus comprises a bus common to these modules and to the memory and, -for each module, a system for arbitrating access re~ues-ts to the bus, transmitted by each module, wherein it also comprises for each module, multiplexing means 73~
connected to the said module and to the bus for multiplexing the addresses (BA0 to BA31) and the data (BD0 to BD31) to be read or written into the common memory, and a time base generator connected to the corresponding arbitration system and to the multiplexing means, said time base generator and said multiplexing means being designed in such a way that a data set (BD0 to BD31) is transmitted on the bus ~ollowing a corresponding address set (BA0 to BA31) in a synchronous manner.
According to another ~eature9 the time base generator and the multiplexing means are also dssigned for multiplexing on the bus, on the one hand the arbitration of the access requests (R0 to R7) to the bus, coming from the arbitration ~ means, and on the other each data set (BD0 to BD31), i in such a way that these arbitration requests are transmitted to the bus, after each data set in a sy~chronous manner.
According to another ~eature, the apparatus also comprises system control means connected to the bus for transmitting control signals ~rom the modules.
According to another ~eature, the apparatus also comprises synchronization means connected to the bus and -~or synchronizing the modules by the transmission of interruption and masking signals to the bus.
Finally, according to another ~eature, the apparatus also comprises protec-tion means connected to the bus for transmitting a signal (BCLM) ~or switching the common memory with a duplicated memory, ~or transmitting signals (BVC) ~or validating the signals (BRZT) indicating the restoration of power to the modules a~ter an interruption to the power 73~
supply thereof, and for validating data circulating on the bus and accompanied by parity information.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is described in greater detail hereinaPter relative to non-limitative embodiments and the attached drawings, wherein show:
Fig. 1 diagrammatically a multiprocessor system using a data exchange apparatus according to the invention. 0 Fig. 2 certain o~` the signals circulating on the bus, during data exchange, for a reading operation in the common memory.
Fig. 3 certain o~ the signals circulating on the bus, during a data exchange, ~or a writing operation in the common memory.
Fig. 4 certain of the signals circulating on the bus, during a data exchange, for a reading and writing modificatlon operation in the common memory. 0 DETAILED DE~CRIPTION OF THE PR~FERRED_EMBODIMENTS
Figo ~ diagrammatically shows a multiprocessor system using a data exchange apparatus according to the invention. This multiprocessor system comprises processing modules 1, 2, whose number has been limited to two in order not to overburden the drawing. These processing modules respectively comprise microprocessors or processors 3, ~, respectively associated with local memories 5 7 6.
The apparatus according to the invention permits a data exchange on the one hand between the different processing modules and on the other hand between said modules and a common memory 7. The apparatus also comprises a bus, which is common to all these modules and to the memory and, for each 73~
module ? a system for arbitrating on the access requests to the bus coming from each modu]e. These arbitration systems or means are designated 8 7 9 in the drawing. The access requests are formulated at outputs lO, 11 of microprocessors 3, ~. They are transmitted to the arbitration means 8, 9, which make it possible to arbitrate on the requests from each module. These arbitration means are not described in detail here, becuase they are described in CanadianPatent Application 410,780 filed on September 3rd, 1982 in the name of the present Applicant. ~or each module, the apparatus also comprises multiplexing means, shown at 12, 13. These multiplexing means are connected to the corresponding modules, as well as to the first address line 17 of the bus. They make it possible to multiplex the addresses (BAO to BA31) and the data (BD0 to BD31) to be wri-tten or read in the common memory 7.
The number of these addresses obviously corresponds to the characteristics of the microprocessors used which, in the embodiment shown in the drawing, are assumed to be 32 bit microprocessors. However9 it is obvious that this number can differ. The apparatus also comprises~ for each of the modules, a time base generator connected to the arbitration means and to the corresponding multiplexer.
In the drawing, the time base generators are represented as 15, 16. The time base generator and the multiplexing means are designed in such a way that, as will be shown hereinafter, a data set (BDO to BD31) is transmitted on the bus after a corresponding address set (B~O to BA31) and in a synchronous manner. The arbitration means ~, 9 are connected to the third line 19 of the bus. The time base generator, as well as the multiplexing means are also designed for multiplexing on the bus, on the first line thereof, on the one hand the arbitration of access requests (R0 to R7) to the bus coming from the various arbitration means and, on the other hand, each data set (BD0 to BD31).
The arbitration requests are transmitted on the bus, a~ter each data set and in a synchronous manner.
The access requests (R0 to R7~ are transmit-ted on the first line 17 of the bus, which also transmits _. .
the addresses and data. In the present embodiment, it has been assumed that the multiprocessor system comprises seven interconnected microprocessors on the bus, although only two of these are shown in the drawing. Thus, seven access requests to the bus have~ to be arbitrated. The signals BES
circulating in the first line 17 of the bus are not involved in the performance of the process according to the invention. These signals are already used in the known buses and make it possible to corli~rol the input - output operations.
The apparatus also comprises the control means 23 of the system, which are connected to the fourth line 20 of the buso These control means are common to all the modules and supply the signals indicated in the drawing and which w~ll be described hereina~ter. These signals make it possible to perform certain module control operations.
The apparatus also coMprises synchronization means 2~ connected to the fifth line of the bus for synchronizing, in the manner to be shown hereinafter, the various modules by the transmission of in-terruption and masking signals on the bus. Finally, the apparatus comprises protection means 25 connected to ~9~73~
the bus for transmitting a signal BCLM for switching the common memory 7 with a duplicated memory 26, said means also making it possible to transmit a signal BVC (-for validation of signals BCS and BRZT) indica-ting an interruption o-f the power supply or a restoration of power to the modules. Finally, these protection means also supply a signal BVP making it possible to validate data circulating on the bus and which are accompanied by parity information. Other signals circulate in the lines of the bus described hereinbefore. These signals are already used in known buses and will be described hereinafter.
Bus control means 27, 28 are also shown and are respectively connected to each o~ the modules and to the second line 18 of the bus. These means are known in the art and make it possible to supply bus control signals, which will be described hereinafter.
In the apparatus shown in the drawing, it is assumed that the outputs` 29, 30, 31 of the microprocessor respectively supply addressing information, data and reading/writing information.
It is also assumed that the input 32 o-f each time base generator 15 receives from the corresponding arbitration means 8 in-~ormation indicating that an access request to the bus -from the processor has been accepted.
Figs. 2, 3 and 4 are chronograms of the signals involved in an exchange of data by means of the bus.
Fig. 2 shows the slgnals in the case where ~he data exchange relates to a data reading operatio~
in the common memoryO It can be seen in Fig. 2 that the data (BDO to ~D31) are transmitted synchronously ;
3~
after the addresses (BA0 -to BA31) on the first line 17 of the bus. The other signals involved in this drawing are signals transmitted by -the second bus line 13 and which will be described hereinafter.
Fig. 3 shows the chronogram of the signals involved on -the bus in the case of a writing operation in the common memory. As in Fig. 2, the other signals shown in Fig. 3 are signals circulating 0 in the second bus line 18.
Finally, Eig. 4 shows a data exchange on the bus, in the case of a data reading operation, followed by a writing operation in the common memory. The other signals shown in Fig. ~ are once again signals circulating in the second bus line 18. It can also be seen that the read or written data are transmitted on the bus of the addresses in a synchronous manner. References 01, ~2, a3, a4~ 05 represent the time intervals having the following durations:
- duration 01 of close to 60 ns corresponds to a prepositioning of addresses with respect to the signal BAL;
- duration ~2 of close to 60 ns corresponds to the maintainance of the addressing time with respect to signal BAL, said duration also corresponding to a time lag between signals BUDS and BLDS;
- duration ~3 is also close to 60 ns and corresponds to the time interval between the transmission of the addresses and the synchronous transmission of the da-ta of the bus;
- duration e4 can be regulated and corresponds 73~
to the time lag of signal BDTACK compared with signals BUDS and BLDS;
- finally, duration ~5 corresponds to the maximum data transmission maintaining time with respect to the switching of signal BEC~
A description will be given hereinafter of signals BAL, BUDS, BLDS, BDTACK, BQDS.
A more detailed description will now be given o-~ the signals appearing on the different lines o~ the bus, by indicating in a more specific manner which are involved in the apparatus and process according to the invention.
Signals on the first line of the bus -reference 17 (addresses, data, access request,input - output).
(BD0 to data exchanged on the bus and transmitted, BD31) according to the invention, after the addresses in a synchronous manner.
(BA0 to addresses of data and these addresses ) must be stored by BAJ;.
BES: input - outpu-t signalO Active if its logic level = 0 - equivalent to one supplementary address line. Makes it possible to address 16M memory octets and 16M input - output octets, ~or exampleO
This signal occurs in the known buses.
During the second phase of an exchange~
certain address lines and BES are available and are used for carrying the access requests to the buses of the different processing modulesO
~4~739~
Signals on the second line of the bus -(reference 18 - bus control signals).
BECH: exchange bus: active if level = 0.
Signal has three states. Indicates that the signals on the bus are valid.
BAL: latch address bus (locking of addresses on the bus): ac-tive if level = 0.
Signal has three states and makes it possible to store addresses BAO to BA31 and BES.
BW: writ~ng bus: active if level = 0.
Signal with three states. Indicates the direction of trans~er on the bus:
writing if level = 0, reading if level = 1.
BUDS: "Bus upper date strobe" (upper sampling of data on bus): active if level - 0.
Signal with three states. Validates the exchange for the more significant data.
BLDS: "Bus low data strobe" (lower sampling of data on bus): active if level = 0.
Signal has three states. Validates the exchange for less signi~icant data.
BDTACK: acceptance of less significant data transfer on bus: active if level = 00 Signal has three states. Supplied asynchronously by -the module, which recognizes that arbitration is taking place and accepts the trans~er. 0 BBERR: error bus: active if level = 0, collector open. Active if a module or a memory detects an uncorrected error and the cycle ta~ing place must be aborted.
A11 these signals occur in the known buses, 3~
1~
I'hird line of the bus (reference 19 -arbitration signals).
BNA: designation of a new arbitrator of the bus, collector open, active if level = 0.
BM1 to designation of the coded number of the BM3: master module of the bus, collector open.
BM4: validation of BM1 to BM3 - active if level = 0, collector open. If BM4 = 0, the data BM1 to BM3 are validated.
BREQ: request for access to bus - active if level = 0. Collector open, access request to common-bus.
15 BAP: possible arbitration bus - active i~
level = 1, collector open.
All these signals are described in the aforementioned French Patent Application.
Fourth line of the_bus (reference 20 - control signals of the system).
BRZT: restoration of power supply 9 active if level = 0, duration exceeds 100 ms.
BHALT: bus stop: active if level = 0, collector open. Indicates that one or more modules are in the stop state.
BALARME: alarm bus: active if level = 0, collector open. Indicatés an alarm state on one or more modules.
BMA: stop - go signal.
30 BCS: interruption of power supply active if level = 0, collector open.
BTST: test interruption - active if level = 0, collector open~ Interruption of system.
Starts up all the modules for testing purpo-ses.
7~9~
Signals BUS ~IALT, BUS ALARME, BTST are used in -the process and appara-tus according to the invention, whereas the others are known.
Fifth line of the bus (reference 21 - module .
synchronization signals and interruption signals).
~APPELi: interruption - active if level = 09 collector open. Overall interruption;
Call from one processing module to the other processing modules. Stored a-t the module receivers.
BAPPEL2: interruption - active if level = O, collector open. Overall interruption at the end of the operations started by one module towards another processing module. Stored at the transmitter of the module supplying the signals in a local flip-flop thereo-f and not shown in the drawings.
BM~SQ: Overall masking of t~e BAPPEL2 signals -active if level = O, collector open.
B~TAS: resetting of local flip-flops - active if level = O, collector open.
All these signals are used in the process and apparatus according to the invention~
Sixth line of the bus (re-~erence 21 - protect-ion signals: memory s~itching, power restoration validation, etc.).
BCLM: switching the common memory to a duplicated memory.
30 BPM: memory protection. Inhibits writing in the case where the oommon memory is protected from interruptions to power supplies.
739~
BVC: control valida-tion. Confirms the state of signals BRZT and BCS.
BVP: parity validation. Signal wi-th three sta-tes. This signal is active if a parity accompanies the data.
BP0 BP1 these signals indicate the parities of BP2, BP3 the addressing information multiplexed with the data.
Signals BCLM, BVC, BVP are used in a process according to the invention, whilst the other signals existin the known buses.
The process and apparatus described hereinbefore make it possible to achieve the aforementioned objectives: the introduction of data on the bus is carried out synchronously with the introduction of addresses, whilst the overall operation o~ the system can be asynchronous. The arbitration of the access requests to the bus of the dif~erent modules takes place directly on the ad~ress lines and during the data e.~change phase.
Moreover, the apparatus described hereinbe~ore makes it possible to directl~- manage the interrupticns from the bus, which is impossible with the existing exchange means. Thus, in the existing means, there are interruption lines between the different modules, whereas in the means according to the invention, specialized management lines make it possible to carry out an overall management of the interruptions, as a result of masking procedures. As indicated herein-before, as a result of the signal BRTAS J one line ofthe bus makes it possible to release resources on all the modulesO Finally9 the lines of the bus and which are used in -the apparatus are not grouped according to functionality criteria and are instead distributed 73~
as a function of their sensitivity to noise, which makes it possible to obtain much less complicated line terminations. The bus in~olved in the apparatus is a high availability bus with good performance features.
Claims (12)
1. A process for the exchange of data between processing modules and at least one common memory in a data processing system, wherein it comprises multiplexing, on a common connecting bus between these modules and the common memory, at least one address set (BA0 to BA31), and at least one data set (BD0 to BD31), corresponding to these addresses, in such a way that the data set is transmitted after the address set in a synchronous manner, each module accepting a data transfer on the bus supplying an acceptance signal (BDTACK) in an asynchronous manner.
2. A process according to claim 1, wherein it also comprises multiplexing on the bus, on the one hand the arbitration of access requests to the bus (R0 to R7) coming from arbitration means corresponding respectively to the processing modules and which are connected to the bus and, on the other hand the address set (BA0 to BA31) and the data set (BD0 to BD31), in such a way that the arbitration requests are transmitted to the bus after the data set.
3. A process according to claim 2, wherein it also consists of transmitting on the bus system module control signals (BRZT, BUS HALT, BUS ALARME, BTST).
4. A process according to claim 3, wherein the system module control signals comprise signals (BRZT) indicating that power has been restored after interrupting the power supply to the modules, signals (B HALT) indicating the stopping of one or more modules, signals (B ALARME) indicating an alarm due to an operating fault on one or more modules and signals (BTST) for the interruption of all the modules for testing purposes.
5. A process according to claim 4, wherein it also consists of synchronizing the different modules by interruption signals transmitted on the bus.
6. A process according to claim 5, wherein the interruption signals comprise an overall system interruption signal (B APPEL1), said signal being supplied by one module and is transmitted to all the others in order to be stored in a receiver of each of these modules, an overall interruption signal (B APPEL2) at the end of the task performed by the system, said signal being stored in a transmitter of one of the modules, a signal (BMASQ) supplied by one module for masking the interruption signals supplied by the other modules, a signal (BRTAS) for resetting the local flip-flops in each module for indicating that the common memory is not available.
7. A process according to claim 6, wherein it also comprises transmitting on the bus, a signal (BCLM) for switching the common memory to a duplicated memory thereof, a signal (BVC) for the validation of the signals (BCS and BRZT) for indicating the interruption and restoration of power after an interruption to the power supply of the modules and signals (BVP) for validating the parity of the data transmitted on the bus.
8. An apparatus for the exchange of data between processing modules and at least one common memory in a data processing system, wherein said apparatus comprises a bus common to these modules and to the memory, and, for each module, a system for arbitrating access requests to the bus, transmitted by each module, wherein it also comprises for each module, multiplexing means connected to the said module and to the bus for multiplexing the addresses (BA0 to BA31) and the data (BD0 to BD31) to be read or written into the common memory, and a time base generator connected to the corresponding arbit-ration system and to the multiplexing means, said time base generator and said multiplexing means being designed in such a way taat a data set (BD0 to BD31) is transmitted on the bus following a corresponding address set (BA0 to BA31) in a synchronous manner.
9. An apparatus according to claim 8, wherein the time base generator and the multiplexing means are also designed for multiplexing on the bus, on the one hand the arbitration of the access requests (R0 to R7) to the bus, coming from the arbitration means, and on the other each data set (BD0 to BD31), in such a way that these arbitration requests are transmitted to the bus, after each data set in a synchronous manner.
10. An apparatus according to claim 9, wherein it also comprises system control means connected to the bus for transmitting module control signals.
11. An apparatus according to claim 10, wherein it also comprises synchronizing means connected to the bus for synchronizing the modules by transmitting interruption and masking signals on the bus.
12. An apparatus according to claim 11, wherein it also comprises protection means connected to the bus for transmitting a signal (BCLM) for switching the common memory with a duplicated memory, for transmitting signals (BVC) for validating the signals (BRZT) indicating the restoration of power to the modules after an interruption to the power supply thereof, and for validating data circulating on the bus and accompanied by parity information.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR8124506A FR2519165B1 (en) | 1981-12-30 | 1981-12-30 | METHOD FOR EXCHANGING DATA BETWEEN PROCESSING MODULES AND A COMMON MEMORY IN A DATA PROCESSING SYSTEM AND DEVICE FOR CARRYING OUT SAID METHOD |
| FR8124506 | 1981-12-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1199734A true CA1199734A (en) | 1986-01-21 |
Family
ID=9265529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000418356A Expired CA1199734A (en) | 1981-12-30 | 1982-12-22 | Process and apparatus for the exchange of data between processing modules and at least one common memory in a data processing system |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0083283B1 (en) |
| JP (1) | JPS58119066A (en) |
| CA (1) | CA1199734A (en) |
| DE (1) | DE3271220D1 (en) |
| FI (1) | FI77125C (en) |
| FR (1) | FR2519165B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3235739C2 (en) * | 1982-09-27 | 1984-07-12 | Nixdorf Computer Ag, 4790 Paderborn | Method for preparing the connection of one of several data processing devices to a centrally clock-controlled multiple line arrangement |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5427741A (en) * | 1977-08-03 | 1979-03-02 | Toshiba Corp | Information processing organization |
| US4290102A (en) * | 1977-10-25 | 1981-09-15 | Digital Equipment Corporation | Data processing system with read operation splitting |
| JPS5679353A (en) * | 1979-11-30 | 1981-06-29 | Hitachi Ltd | Memory bus data transfer method of multiprocessor |
| NL8002344A (en) * | 1980-04-23 | 1981-11-16 | Philips Nv | MULTIPROCESSOR SYSTEM WITH COMMON DATA / ADDRESS BUS. |
-
1981
- 1981-12-30 FR FR8124506A patent/FR2519165B1/en not_active Expired
-
1982
- 1982-12-22 CA CA000418356A patent/CA1199734A/en not_active Expired
- 1982-12-22 DE DE8282402362T patent/DE3271220D1/en not_active Expired
- 1982-12-22 EP EP82402362A patent/EP0083283B1/en not_active Expired
- 1982-12-29 FI FI824508A patent/FI77125C/en not_active IP Right Cessation
-
1983
- 1983-01-04 JP JP58000014A patent/JPS58119066A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FI77125C (en) | 1989-01-10 |
| EP0083283A2 (en) | 1983-07-06 |
| JPS58119066A (en) | 1983-07-15 |
| DE3271220D1 (en) | 1986-06-19 |
| EP0083283A3 (en) | 1983-08-03 |
| FI824508L (en) | 1983-07-01 |
| FR2519165B1 (en) | 1987-01-16 |
| FR2519165A1 (en) | 1983-07-01 |
| FI77125B (en) | 1988-09-30 |
| EP0083283B1 (en) | 1986-05-14 |
| FI824508A0 (en) | 1982-12-29 |
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