CA1199399A - Apparatus to display graphic messages transmitted by videotext systems - Google Patents
Apparatus to display graphic messages transmitted by videotext systemsInfo
- Publication number
- CA1199399A CA1199399A CA000406121A CA406121A CA1199399A CA 1199399 A CA1199399 A CA 1199399A CA 000406121 A CA000406121 A CA 000406121A CA 406121 A CA406121 A CA 406121A CA 1199399 A CA1199399 A CA 1199399A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- output
- interlaced
- data
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Abstract
ABSTRACT OF THE DISCLOSURE
The apparatus for displaying graphic messages transmitted by videotext systems on a television receiver screen which is comprised of a data separator, a page memory, a character generator, a management circuit, a service definition keyboard connected to the management circuit, internal synchronization generation circuitry, a circuit to separate the external synchronization of the broadcasting network, and circuitry for controlling interlaced and noninterlaced sweeping. It also is comprised of phase locking apparatus, first switching apparatus to connect the phase locking apparatus to the internal synchronization generation circuitry, and switching apparatus to selectively switch the interlaced and non-interlaced sweep control circuitry. A working state indicator output is provided in the data demodulator in addition to the data output. A first byte type identification circuit is provided in the management circuit to recognize the type of synchronization in the bytes of the first row of each page. First logic circuitry is arranged between the first identification circuit and the output of the working state indicator of the data demodulator, on one hand, and the first and second switching circuit, on the other hand, to control the first and second switching circuit in relation to the state of the first identification circuit and the state output of the demodulator. The management circuit may also be comprised of a second identification circuit for subtitle bytes among the bytes of the first row of each page, whose output is connected by third logic circuitry to control the switching of the normal video-graphic video switch during insertion lines.
The apparatus for displaying graphic messages transmitted by videotext systems on a television receiver screen which is comprised of a data separator, a page memory, a character generator, a management circuit, a service definition keyboard connected to the management circuit, internal synchronization generation circuitry, a circuit to separate the external synchronization of the broadcasting network, and circuitry for controlling interlaced and noninterlaced sweeping. It also is comprised of phase locking apparatus, first switching apparatus to connect the phase locking apparatus to the internal synchronization generation circuitry, and switching apparatus to selectively switch the interlaced and non-interlaced sweep control circuitry. A working state indicator output is provided in the data demodulator in addition to the data output. A first byte type identification circuit is provided in the management circuit to recognize the type of synchronization in the bytes of the first row of each page. First logic circuitry is arranged between the first identification circuit and the output of the working state indicator of the data demodulator, on one hand, and the first and second switching circuit, on the other hand, to control the first and second switching circuit in relation to the state of the first identification circuit and the state output of the demodulator. The management circuit may also be comprised of a second identification circuit for subtitle bytes among the bytes of the first row of each page, whose output is connected by third logic circuitry to control the switching of the normal video-graphic video switch during insertion lines.
Description
s~
01 The present inven-tion concerns an apparatus for 02 displaying on a television recei-ver screen graphic message6 03 transmitted by videotext sys-tems, comprising a data separator, 04 a data demodulator, a page memory, a charac-ter generator, a 05 normal video~graphic video switch, a management circuit, a 06 service definition keyboard connected to the management 07 circuit, internal sync generation means, a circuit to separate 08 the external sync of the broadcas-ting network, and control 09 means for the interlaced and noninterlaced sweeping.
A videotext system is a system that transmi-ts digital 11 data and displays text on a television screen. More specific-12 ally, the invention concerns an improvement to the ANTIOPEtm 13 teletext system which has been described in Canadian pa-tent 14 application 330,924, filed June 29, 1979, and Canadian Pa-tent 1,147,845 issued June 7, 1983, assigned to -the same assignee as 16 this patent application. However, the u-tility of the apparatus 17 in accordance with the invention is not limited to the 18 videotext syste~ described in the above application and patent, 19 but can be applled to all videotext systems, such as that known under the name CEEFAXtm. More generally, the invention is 21 applicable to all interactive or broadcasted videotexts.
22 The display of texts on a television receiver 23 screen in which a two-frame interlaced sweep is used results 24 in a flickering which causes considerable visual fatigue.
One aim of the invention consists in providing an 26 apparatus which suppresses, in most cases, the ~lickering of 27 texts displayed on a -television screen.
~8 Broadcast videotext receivers are comprised of 29 receiver circuits which deliver the external sync signals and the received video, a videotext decoder in which, using the 31 external synchronization the received video signal is 32 treated, a character genera-tor controlled by the decoder and 33 delivering a synthetic video signal to the display~tube of a 34 television receiver. To date, the display tube was operated with the e~ternal sync signals in exac-tly the same way as -to 36 obtain a conventional picture. This results in an interlaced 37 frame picture and thus a flickering. However, it is possible 38 to operate a telev:ision tube with a noninterlaced ~rame 39 ~
'~ .'~......
.~
~:' ~ 3~
01 synchronizatioll, which results in a considerably red~ced 02 flickexing.
03 It has alrea~y been envisayed, ag c~escribed in 04 U~S. Patent 4,096,524, to use an internal synchronizacion 05 instead of an external synchronization when the latter ls not 06 normally received. However, in the U.S. patent 4,096,524, 07 internal synchronization is used only ~o mitiga~e the absence 08 of external synchronization and, in particular, it is used to 09 reestablish an interlaced Erame sweeping.
In patent FR (French) 2/404,359, we have also 11 described a videotext receiver setup in which separated sync 12 signals and locally generated sync signals are available, ]3 with a selectable usage of one or ~he other of these two 14 forms of synchronization signals, this selection not being uniquely controlled by the fact that the separated sync 16 signal may not be available resulting from the absence of or 17 a failure to adapt to the received broadcasted signal. In 18 this French patent, an apparatus is provided in which the 19 separated sync signals are used to display a picture on the television screen when the user decides to look at a normal 21 television picture, an apparatus in which the locally 22 generated sync signals are used for display on the television 23 screen when the user chooses to look at information messages 24 and an apparatus to guarantee the phase hookup of the locally generated sync signals with respect to the separate sync 26 signals when an adequate video signal is received.
27 In the letters patent FR 2,447,122, it has also 28 been proposed to avoid flickering and jitter in -the pictures 29 produced by character generators, such as those of videotext systems. The means utili2ed to achieve this result, is 31 comprised of a frame interpolating circuit, which implies the 32 use of a considerable amount of memory and thus a 33 substantially expense.
34 In the letters patent DE 2,9~9,020, it has also been proposed to avoid flickering by modifying the vertical 36 deviation such that the lines of even and odd frames overlap.
37 One object of the present inven-tion consists in 3~ 2 ~ .~
01 providing an apparatus, which, with regard -to the 02 earlier apparatus mentioned above, allows -the 03 selection of a local synchronization each time it is 04 advantageous to do so and each time this is 05 possible.
06 Ano-ther object oE the invention consists 07 in providing an apparatus which, each time a local 08 synchronization is selected, allows the removal of 09 flickering by using a small number of ~irnple means, and in particular, simpler than those which were 11 mentioned above.
12 The objects of the invention are 13 achieved by utilizing the apparatus which are 14 defined in the attached claims 1 to 3.
In general, the invention is an 16 apparatus for displaying graphic messages 17 transmitted by the video~ext systems on a television 18 receiver screen comprising a data separator, a data 19 demodulator, a page memory, a character generator, a normal video-graphic video switch, a management 21 circuit, a service definition keyboard connected to 22 the management circuit, internal sync generation 23 circuitry, a circuit to separate the external sync 24 from the network broadcasted signal, and circuitry ~or controlling the interlaced and non~interlaced 26 sweeping. The invention is characterized in that it 27 is al~o comprised of phase locking circuitry, first 28 switching circuitry to connect the phase locking 29 circui~ry to the internal synchronization circuitry, second switching circuitry for selectively switching 31 -the interlaced and non-interlaced sweep control 32 circuitry, and in the data demodulator, in addition 33 to its data output, an output is included for 34 indicating it~ working state. ~le invention i~
further charactarized in that a first byte type 36 recognition circuit is included in the management 37 circuit for recognizing ~he type oE synchronization 38 in the bytes o the first row of each page, and a :
. .;
3~
01 first logic circuit is placed between the first 02 recognition circuit and -the output oE the wor]cing 03 status indicator of the data demodulator, on one 04 hand, and the first and se~ond switching circuitry, 05 on the other hand, to control -the first and second 06 switching circuitry in relatlon -to the s-tate of -the 07 circuit and the state output of the demodulator.
08 The characteristics of the 09 above-mentioned invention as well as others, will appear more clearly upon reading the following 11 embodiment, the said description being made in 12 relation to the one attached figure.
13 The apparatus of the only figure is 14 comprised of a television receiver circuit 1 connected to an antenna 2 and which delivers sound 16 to a speaker 3 and video and chrominance information 17 to a matrixing circuit 4, w~ich transmits the 18 l~ninance Ll and the chrominance signals Bl, Vl and 19 Rl, through a switch 5 to a screen tube 6. The video output of circuit 1 is also connected to the 21 input of a data separator 7 which feeds a 22 demodulator 8 similar to that which is described in 23 the French patent 2,313,825.
24 The output of circui~ 1 is also connected to a sync separation circuit 36 whose 26 output is connected -to the first input o an AND
27 gate 9 whose output is connected to the first input 28 of a phase comparator 10. The output of the phase 29 comparator 10 is connected to the input of a phase locking circuit 11 whose output is connected by an 31 electric switch 12 to -the input of a pilot generator 32 13. I'he output of the pilot generator 13 is 33 connected to the input of a time base 14 which 34 locally generates the synchro~iæation signals which are conventionally applied to the tube 6, via link 36 15. The apparatus of -the only figure ls also 37 comprised of a subscriber telephone operator 38 associated with a modem 17, 39 - 3a -01 which is, on one hand, connected to a telephone :Line 18 and, 02 on the other hand, to a data inter:Eace 19.
03 The apparatus is also completed by a management 04 circuit 20 whi.ch is connected by a data exchange bus BU5 to a 05 demodulator 8, to interface 19, to an operator keyboard 21 06 and to a page memory 22. The data output of memory 22 is 07 connected to the input of a character generator 23 whose 08 output transmits the lumi.nance L2 and the chrominance signals 09 B2, V2 and R2 to the second input of switch 5 which according to its state, transmits them to the screen tube 6.
11 An output link 24 from time base 14 i5 co~nected to 12 the clock inputs of circuits 20, 22 and 23 as well as -the 13 second input of the phase comparator 10.
14 The management circuit 20 has a first control output connected, on one hand, to the second input of AND
16 gate 9 and, on the other hand, through an inverter 41, to the 17 first input of an OR gate 26, and a second control output 18 connected to the first input of an AND gate 27 whose output 19 is connected to the second input of OR gate 26.
The output of OR gate 26 is connected to the 21 control input of electronic switch 12. When OR gate 26 does 22 not produce a signal, switch 12 connects the input of 23 generator 13 to the output of the phase locking circuit ll.
24 When OR gate 26 procluces a signal, switch 12 cuts the link between the generator 13 and the circuit ll.
26 The phase locking circuit ll yields a continuous 27 signal which is related to the output signal of the phase 28 comparator generator 10 r the continuous signal acting on the 29 frequency of the pilot generator to reduce the phase difference between the input signals to comparator 10. It is 31 apparent that, when contact 12 is open, generator 13 operates 32 at its own proper frequency, which can be 12 MHz. In 33 practice, generator 13 is quartz stabilizedO
34 The time base 14 is comprised of a set of frequency dividers 28 which deliver, via 24 t the necessary clock 36 signals to the management circuit 20, ~o the page memory 22 37 and to the character generator 23, a set of frequency 38 _ ~ _ g~
~ ~ lc3~ 9~
01 dividers 29 which deliver, via 15, the Erame an~ llne sync 02 signals to the tube 6 deviation circuit 30, and a switching 03 circuit 31. In practice, the dividers of set 29 operate as 04 down counters from an initial value which is applied to their 05 control input, which is itself connected to the output of 06 switching circuit 31. In switching circuit 31 are provided 07 two memory registers 32 and 33 whose read outputs are 08 respectively connected ~o the Eixed terminals of a switch 34 09 whose movable contact is connected to the output of 31. The control input of circuit 31, that is -to say of swi-tch 34, is 11 connected to the output of OR ga-te 26.
12 Register 32, is furthermore, associated wi~h a 13 flip-flop 35 which changes state each time register 32 is 14 read. In its first state, flip-flop 35 reduces the contents of register 32 by 1 and, in its other state, adds 1 to the 16 contents. If the contents of the register associated with 17 set 29 is n, the contents of 32 is chosen to be initially at 18 (n - 312), which causes counter 29 to alternately count 312 19 and 3134 The reading of 32 is carried out at each zero crossing of coun-ter 29. As a result, we obtain the 21 interlaced sweeping corresponding to the 625 line norm.
22 The contents of register 33 is fixed and chosen to 23 be 312. The result is that the signals applied to 30 via 39 24 in this case correspond to a non-interlaced sweeping, which is emphasized by a sequence of identical 312 line frames.
26 The memories 32 and 33 have the same conten-ts to within a 27 binary digit. These memories can advantagesouly be replaced 28 by a resistance memory, for example, delivering the code
01 The present inven-tion concerns an apparatus for 02 displaying on a television recei-ver screen graphic message6 03 transmitted by videotext sys-tems, comprising a data separator, 04 a data demodulator, a page memory, a charac-ter generator, a 05 normal video~graphic video switch, a management circuit, a 06 service definition keyboard connected to the management 07 circuit, internal sync generation means, a circuit to separate 08 the external sync of the broadcas-ting network, and control 09 means for the interlaced and noninterlaced sweeping.
A videotext system is a system that transmi-ts digital 11 data and displays text on a television screen. More specific-12 ally, the invention concerns an improvement to the ANTIOPEtm 13 teletext system which has been described in Canadian pa-tent 14 application 330,924, filed June 29, 1979, and Canadian Pa-tent 1,147,845 issued June 7, 1983, assigned to -the same assignee as 16 this patent application. However, the u-tility of the apparatus 17 in accordance with the invention is not limited to the 18 videotext syste~ described in the above application and patent, 19 but can be applled to all videotext systems, such as that known under the name CEEFAXtm. More generally, the invention is 21 applicable to all interactive or broadcasted videotexts.
22 The display of texts on a television receiver 23 screen in which a two-frame interlaced sweep is used results 24 in a flickering which causes considerable visual fatigue.
One aim of the invention consists in providing an 26 apparatus which suppresses, in most cases, the ~lickering of 27 texts displayed on a -television screen.
~8 Broadcast videotext receivers are comprised of 29 receiver circuits which deliver the external sync signals and the received video, a videotext decoder in which, using the 31 external synchronization the received video signal is 32 treated, a character genera-tor controlled by the decoder and 33 delivering a synthetic video signal to the display~tube of a 34 television receiver. To date, the display tube was operated with the e~ternal sync signals in exac-tly the same way as -to 36 obtain a conventional picture. This results in an interlaced 37 frame picture and thus a flickering. However, it is possible 38 to operate a telev:ision tube with a noninterlaced ~rame 39 ~
'~ .'~......
.~
~:' ~ 3~
01 synchronizatioll, which results in a considerably red~ced 02 flickexing.
03 It has alrea~y been envisayed, ag c~escribed in 04 U~S. Patent 4,096,524, to use an internal synchronizacion 05 instead of an external synchronization when the latter ls not 06 normally received. However, in the U.S. patent 4,096,524, 07 internal synchronization is used only ~o mitiga~e the absence 08 of external synchronization and, in particular, it is used to 09 reestablish an interlaced Erame sweeping.
In patent FR (French) 2/404,359, we have also 11 described a videotext receiver setup in which separated sync 12 signals and locally generated sync signals are available, ]3 with a selectable usage of one or ~he other of these two 14 forms of synchronization signals, this selection not being uniquely controlled by the fact that the separated sync 16 signal may not be available resulting from the absence of or 17 a failure to adapt to the received broadcasted signal. In 18 this French patent, an apparatus is provided in which the 19 separated sync signals are used to display a picture on the television screen when the user decides to look at a normal 21 television picture, an apparatus in which the locally 22 generated sync signals are used for display on the television 23 screen when the user chooses to look at information messages 24 and an apparatus to guarantee the phase hookup of the locally generated sync signals with respect to the separate sync 26 signals when an adequate video signal is received.
27 In the letters patent FR 2,447,122, it has also 28 been proposed to avoid flickering and jitter in -the pictures 29 produced by character generators, such as those of videotext systems. The means utili2ed to achieve this result, is 31 comprised of a frame interpolating circuit, which implies the 32 use of a considerable amount of memory and thus a 33 substantially expense.
34 In the letters patent DE 2,9~9,020, it has also been proposed to avoid flickering by modifying the vertical 36 deviation such that the lines of even and odd frames overlap.
37 One object of the present inven-tion consists in 3~ 2 ~ .~
01 providing an apparatus, which, with regard -to the 02 earlier apparatus mentioned above, allows -the 03 selection of a local synchronization each time it is 04 advantageous to do so and each time this is 05 possible.
06 Ano-ther object oE the invention consists 07 in providing an apparatus which, each time a local 08 synchronization is selected, allows the removal of 09 flickering by using a small number of ~irnple means, and in particular, simpler than those which were 11 mentioned above.
12 The objects of the invention are 13 achieved by utilizing the apparatus which are 14 defined in the attached claims 1 to 3.
In general, the invention is an 16 apparatus for displaying graphic messages 17 transmitted by the video~ext systems on a television 18 receiver screen comprising a data separator, a data 19 demodulator, a page memory, a character generator, a normal video-graphic video switch, a management 21 circuit, a service definition keyboard connected to 22 the management circuit, internal sync generation 23 circuitry, a circuit to separate the external sync 24 from the network broadcasted signal, and circuitry ~or controlling the interlaced and non~interlaced 26 sweeping. The invention is characterized in that it 27 is al~o comprised of phase locking circuitry, first 28 switching circuitry to connect the phase locking 29 circui~ry to the internal synchronization circuitry, second switching circuitry for selectively switching 31 -the interlaced and non-interlaced sweep control 32 circuitry, and in the data demodulator, in addition 33 to its data output, an output is included for 34 indicating it~ working state. ~le invention i~
further charactarized in that a first byte type 36 recognition circuit is included in the management 37 circuit for recognizing ~he type oE synchronization 38 in the bytes o the first row of each page, and a :
. .;
3~
01 first logic circuit is placed between the first 02 recognition circuit and -the output oE the wor]cing 03 status indicator of the data demodulator, on one 04 hand, and the first and se~ond switching circuitry, 05 on the other hand, to control -the first and second 06 switching circuitry in relatlon -to the s-tate of -the 07 circuit and the state output of the demodulator.
08 The characteristics of the 09 above-mentioned invention as well as others, will appear more clearly upon reading the following 11 embodiment, the said description being made in 12 relation to the one attached figure.
13 The apparatus of the only figure is 14 comprised of a television receiver circuit 1 connected to an antenna 2 and which delivers sound 16 to a speaker 3 and video and chrominance information 17 to a matrixing circuit 4, w~ich transmits the 18 l~ninance Ll and the chrominance signals Bl, Vl and 19 Rl, through a switch 5 to a screen tube 6. The video output of circuit 1 is also connected to the 21 input of a data separator 7 which feeds a 22 demodulator 8 similar to that which is described in 23 the French patent 2,313,825.
24 The output of circui~ 1 is also connected to a sync separation circuit 36 whose 26 output is connected -to the first input o an AND
27 gate 9 whose output is connected to the first input 28 of a phase comparator 10. The output of the phase 29 comparator 10 is connected to the input of a phase locking circuit 11 whose output is connected by an 31 electric switch 12 to -the input of a pilot generator 32 13. I'he output of the pilot generator 13 is 33 connected to the input of a time base 14 which 34 locally generates the synchro~iæation signals which are conventionally applied to the tube 6, via link 36 15. The apparatus of -the only figure ls also 37 comprised of a subscriber telephone operator 38 associated with a modem 17, 39 - 3a -01 which is, on one hand, connected to a telephone :Line 18 and, 02 on the other hand, to a data inter:Eace 19.
03 The apparatus is also completed by a management 04 circuit 20 whi.ch is connected by a data exchange bus BU5 to a 05 demodulator 8, to interface 19, to an operator keyboard 21 06 and to a page memory 22. The data output of memory 22 is 07 connected to the input of a character generator 23 whose 08 output transmits the lumi.nance L2 and the chrominance signals 09 B2, V2 and R2 to the second input of switch 5 which according to its state, transmits them to the screen tube 6.
11 An output link 24 from time base 14 i5 co~nected to 12 the clock inputs of circuits 20, 22 and 23 as well as -the 13 second input of the phase comparator 10.
14 The management circuit 20 has a first control output connected, on one hand, to the second input of AND
16 gate 9 and, on the other hand, through an inverter 41, to the 17 first input of an OR gate 26, and a second control output 18 connected to the first input of an AND gate 27 whose output 19 is connected to the second input of OR gate 26.
The output of OR gate 26 is connected to the 21 control input of electronic switch 12. When OR gate 26 does 22 not produce a signal, switch 12 connects the input of 23 generator 13 to the output of the phase locking circuit ll.
24 When OR gate 26 procluces a signal, switch 12 cuts the link between the generator 13 and the circuit ll.
26 The phase locking circuit ll yields a continuous 27 signal which is related to the output signal of the phase 28 comparator generator 10 r the continuous signal acting on the 29 frequency of the pilot generator to reduce the phase difference between the input signals to comparator 10. It is 31 apparent that, when contact 12 is open, generator 13 operates 32 at its own proper frequency, which can be 12 MHz. In 33 practice, generator 13 is quartz stabilizedO
34 The time base 14 is comprised of a set of frequency dividers 28 which deliver, via 24 t the necessary clock 36 signals to the management circuit 20, ~o the page memory 22 37 and to the character generator 23, a set of frequency 38 _ ~ _ g~
~ ~ lc3~ 9~
01 dividers 29 which deliver, via 15, the Erame an~ llne sync 02 signals to the tube 6 deviation circuit 30, and a switching 03 circuit 31. In practice, the dividers of set 29 operate as 04 down counters from an initial value which is applied to their 05 control input, which is itself connected to the output of 06 switching circuit 31. In switching circuit 31 are provided 07 two memory registers 32 and 33 whose read outputs are 08 respectively connected ~o the Eixed terminals of a switch 34 09 whose movable contact is connected to the output of 31. The control input of circuit 31, that is -to say of swi-tch 34, is 11 connected to the output of OR ga-te 26.
12 Register 32, is furthermore, associated wi~h a 13 flip-flop 35 which changes state each time register 32 is 14 read. In its first state, flip-flop 35 reduces the contents of register 32 by 1 and, in its other state, adds 1 to the 16 contents. If the contents of the register associated with 17 set 29 is n, the contents of 32 is chosen to be initially at 18 (n - 312), which causes counter 29 to alternately count 312 19 and 3134 The reading of 32 is carried out at each zero crossing of coun-ter 29. As a result, we obtain the 21 interlaced sweeping corresponding to the 625 line norm.
22 The contents of register 33 is fixed and chosen to 23 be 312. The result is that the signals applied to 30 via 39 24 in this case correspond to a non-interlaced sweeping, which is emphasized by a sequence of identical 312 line frames.
26 The memories 32 and 33 have the same conten-ts to within a 27 binary digit. These memories can advantagesouly be replaced 28 by a resistance memory, for example, delivering the code
2~ 10011100X, the value of X determined by 34, being either zero, or the content of flip-flop 35 which changes state at 31 each zero crossing of counter 2g.
32 Similar to switch 12, when OR gate 26 delivers no 33 signal, contact 34 connects memory 32 to the output oE 31 34 and, in the opposite case, it is register 33 which is connected to the output of 31.
36 The management element 20 is, preferably, 37 implemented in the forrn of a microprGce~sor which is capable .~ , 01 in terms of the commands delivered by keyboard 21, which is 02 at the disposition of the operator, to select the data 03 transmitted on the BUS, either by demodu:Lator 8, or by 04 interface 19. The microprocessor of management circuit 20 is 05 comprised of means to receive and analyze each byte of row 0 06 of each page oE broadcasted or interactive videotext. In 07 particular, it has a sync byte identification circuit 37 and 08 a subtitle service recognition circuit 38. When the contents 09 of the synchronizaiton type identiEication byte indicates that display is to be done with external synchronization, 11 circui-t 37 activates lts output towards AND yate 9 and 12 towards the first input oE an OR gate 39. In the opposite 13 situation, the output of 37 is not activated which opens 14 gates 25 and 27, by inver~er 41. When the subti~le byte is recognized, the output of circuit 38, which is connected to a 16 line counter 40, is activated. The purpose of counter 40 is 17 to determine the lines of the Erame in which the subtitle is 18 to be inserted. Normally, the output of 40, which is 19 connected to the second input of gate 3~, is set which opens gate 40. The output of gate 39 is connected to the control 21 input of switch 5. When the output of 39 is activated, 22 switch 5 transmits the signals coming from circuit 4, in the 23 opposite case, it transmits the signals coming from the 24 character generator 23. During the insertion lines, the output of 40 is not activated, which resets gate 39.
~6 The second inputs of AND ga~es 25 and 27 are 27 respectively connected to -the state outputs of circuits 8 and 28 19, which are activated when these circuits are in use.
29 When the service requested is a normal television program, the management circuit activates its output to gate 31 9, but leaves the outputs to 25 and 27 inactive. Thus, OR
32 gate 26 delivers no signal and comparator 10 assigns 33 generator 13 to the broadcast network synchronization. The 34 time base 14 controls an interlaced sweep on the tube 6. In other respects, gate 39 i5 open and normal video is applied 36 to tube 6.
37 When the service requested is a hroadcasted .,~
32 Similar to switch 12, when OR gate 26 delivers no 33 signal, contact 34 connects memory 32 to the output oE 31 34 and, in the opposite case, it is register 33 which is connected to the output of 31.
36 The management element 20 is, preferably, 37 implemented in the forrn of a microprGce~sor which is capable .~ , 01 in terms of the commands delivered by keyboard 21, which is 02 at the disposition of the operator, to select the data 03 transmitted on the BUS, either by demodu:Lator 8, or by 04 interface 19. The microprocessor of management circuit 20 is 05 comprised of means to receive and analyze each byte of row 0 06 of each page oE broadcasted or interactive videotext. In 07 particular, it has a sync byte identification circuit 37 and 08 a subtitle service recognition circuit 38. When the contents 09 of the synchronizaiton type identiEication byte indicates that display is to be done with external synchronization, 11 circui-t 37 activates lts output towards AND yate 9 and 12 towards the first input oE an OR gate 39. In the opposite 13 situation, the output of 37 is not activated which opens 14 gates 25 and 27, by inver~er 41. When the subti~le byte is recognized, the output of circuit 38, which is connected to a 16 line counter 40, is activated. The purpose of counter 40 is 17 to determine the lines of the Erame in which the subtitle is 18 to be inserted. Normally, the output of 40, which is 19 connected to the second input of gate 3~, is set which opens gate 40. The output of gate 39 is connected to the control 21 input of switch 5. When the output of 39 is activated, 22 switch 5 transmits the signals coming from circuit 4, in the 23 opposite case, it transmits the signals coming from the 24 character generator 23. During the insertion lines, the output of 40 is not activated, which resets gate 39.
~6 The second inputs of AND ga~es 25 and 27 are 27 respectively connected to -the state outputs of circuits 8 and 28 19, which are activated when these circuits are in use.
29 When the service requested is a normal television program, the management circuit activates its output to gate 31 9, but leaves the outputs to 25 and 27 inactive. Thus, OR
32 gate 26 delivers no signal and comparator 10 assigns 33 generator 13 to the broadcast network synchronization. The 34 time base 14 controls an interlaced sweep on the tube 6. In other respects, gate 39 i5 open and normal video is applied 36 to tube 6.
37 When the service requested is a hroadcasted .,~
3~
01 videotext, such as the ANrrIopEtm service, the man~gement 02 circuit 20 detects, in a circuit which receives the first row 03 bytes of each page 37, that the sync type byte clesignates 04 internal synchronization, which opens gate 25. Thus, OR gate 05 26 opens switch 12 and changes the state of swi-tch 34. The 06 time base 14 operates on internal sync and controls an 07 interlaced sweeping.
08 When the service requested is an interac~ive 09 videotext, such as the TELETELtm service, circuit 20 detects once again, in 37, that the sync type byte designates once 11 again internal syncrhonization, which opens gate 27~ We 12 regain the case of broadcasted videotext.
13 In another variation, the selectlon of modem 17 and 14 its interface 19 as data input device could directly induce the opening of switch 12. In this case, gate 27 could be 16 removed, the second input of gate 26 beiny directly connected 17 to the appropriate output of interface 19~
18 When the broadcasted service is an insertion in a 19 normal television picture, the management circuit 20 detects that the sync type byte designates external synchronization, 21 which opens gate 9. Thus, the time base operates on a phase 22 locked synchronization and controls an interlaced sweeping.
23 Furthermore, circuit 38 recognizes the subtitle byte which 24 activates counter 40 and guarantees, by 39, the switching oE
5 between 4 and 23.
26 In practice, the management circuit was reallzed in 27 the form o~ a microprocessor, circui-t 37 is implemented by a 28 simple memory cell.
~,~
01 videotext, such as the ANrrIopEtm service, the man~gement 02 circuit 20 detects, in a circuit which receives the first row 03 bytes of each page 37, that the sync type byte clesignates 04 internal synchronization, which opens gate 25. Thus, OR gate 05 26 opens switch 12 and changes the state of swi-tch 34. The 06 time base 14 operates on internal sync and controls an 07 interlaced sweeping.
08 When the service requested is an interac~ive 09 videotext, such as the TELETELtm service, circuit 20 detects once again, in 37, that the sync type byte designates once 11 again internal syncrhonization, which opens gate 27~ We 12 regain the case of broadcasted videotext.
13 In another variation, the selectlon of modem 17 and 14 its interface 19 as data input device could directly induce the opening of switch 12. In this case, gate 27 could be 16 removed, the second input of gate 26 beiny directly connected 17 to the appropriate output of interface 19~
18 When the broadcasted service is an insertion in a 19 normal television picture, the management circuit 20 detects that the sync type byte designates external synchronization, 21 which opens gate 9. Thus, the time base operates on a phase 22 locked synchronization and controls an interlaced sweeping.
23 Furthermore, circuit 38 recognizes the subtitle byte which 24 activates counter 40 and guarantees, by 39, the switching oE
5 between 4 and 23.
26 In practice, the management circuit was reallzed in 27 the form o~ a microprocessor, circui-t 37 is implemented by a 28 simple memory cell.
~,~
Claims (3)
1. An apparatus to display graphic messages transmitted by videotext systems on a television receiver screen comprising a data separator, a data demodulator, a page memory, a character generator, a normal video-graphic video switch, a management circuit, a service definition keyboard connected to the management circuit, internal sync generation means, a circuit to separate the external sync from the network broadcasted signal, means to control the interlaced and non-interlaced sweeping, characterized in that it also is comprised of:
phase locking means, first switching means to connect the phase locking means to the internal synchronization means, second switching means to selectively switch the interlaced and non-interlaced sweep control means, in the data demodulator, in addition to its data output, an output for indicating its working state, in the management circuit, a first byte type recognition circuit to recognize the type of synchronization in the bytes of the first row of each page, and first logic means placed between the first recognition circuit and the output of the working status indicator of the data demodulator, on one hand, and the first and second switching means, on the other hand, to control the first and second switching means in relation to the state of circuit and the state output of demodulator.
phase locking means, first switching means to connect the phase locking means to the internal synchronization means, second switching means to selectively switch the interlaced and non-interlaced sweep control means, in the data demodulator, in addition to its data output, an output for indicating its working state, in the management circuit, a first byte type recognition circuit to recognize the type of synchronization in the bytes of the first row of each page, and first logic means placed between the first recognition circuit and the output of the working status indicator of the data demodulator, on one hand, and the first and second switching means, on the other hand, to control the first and second switching means in relation to the state of circuit and the state output of demodulator.
2. An apparatus in accordance with claim 1, comprising an interactive videotext receiver, with a modem and a data interface in series, whose output is connected to a management circuit, characterized in that it is comprised of a second logic means placed between the first byte type recognition circuit and the data interface, on one hand, and the first and second switching means, in relation to the state of the first byte type recognition circuit and the state of the data interface to control the first and second switching means.
3. An apparatus in accordance with claim 1 or 2 characterized in that the management circuit also is comprised of a second recognition circuit, for identifying subtitle bytes among the bytes of the first row of each page, having an output which is connected by third logic means to control the switching of the normal video-graphic video switch during the insertion lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000406121A CA1199399A (en) | 1982-06-28 | 1982-06-28 | Apparatus to display graphic messages transmitted by videotext systems |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000406121A CA1199399A (en) | 1982-06-28 | 1982-06-28 | Apparatus to display graphic messages transmitted by videotext systems |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1199399A true CA1199399A (en) | 1986-01-14 |
Family
ID=4123107
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000406121A Expired CA1199399A (en) | 1982-06-28 | 1982-06-28 | Apparatus to display graphic messages transmitted by videotext systems |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1199399A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9147312B2 (en) | 2008-03-13 | 2015-09-29 | Aristocrat Technologies Australia Pty Limited | Method and system of distributing progressive gaming |
-
1982
- 1982-06-28 CA CA000406121A patent/CA1199399A/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9147312B2 (en) | 2008-03-13 | 2015-09-29 | Aristocrat Technologies Australia Pty Limited | Method and system of distributing progressive gaming |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5579057A (en) | Display system for selectively overlaying symbols and graphics onto a video signal | |
| KR100288459B1 (en) | Data demodulation device | |
| US5325183A (en) | OSD circuit for displaying advertising picture data | |
| US3743767A (en) | Transmitter and receiver for the transmission of digital data over standard television channels | |
| US4486779A (en) | Apparatus to display graphic messages transmitted by videotext systems | |
| US5602600A (en) | Device for transparently displaying characters in a video system by forming a weighted average of a video signal and the video signal after text has been inserted | |
| JPH05304641A (en) | Television receiver | |
| JPS60219883A (en) | Cable television circuit network | |
| EP0553910B1 (en) | Television receiver | |
| CA1153461A (en) | Raster manipulated television receiver | |
| WO1990014732A1 (en) | Data transmission in the active picture period | |
| US3649749A (en) | Apparatus permitting reliable selection of transmitted television message information | |
| CA1199399A (en) | Apparatus to display graphic messages transmitted by videotext systems | |
| AU577494B2 (en) | Teletext / viewdata decoder with computer interface | |
| KR0145472B1 (en) | Picture transmission of wide screen display system | |
| US4661798A (en) | Video field decoder | |
| US4618888A (en) | Scrambling system of television signal | |
| US4524387A (en) | Synchronization input for television receiver on-screen alphanumeric display | |
| EP0141459B1 (en) | Television receiver arrangements | |
| EP0119751B1 (en) | Scrambling system of television signal | |
| EP0129648B1 (en) | Television receiver with text insertion | |
| GB1593424A (en) | Television receiver arrangement | |
| GB2063627A (en) | Arrangement for determining a data slicing level for a bi-amplitude data pulse signal | |
| KR19990014760A (en) | Time division still picture television system | |
| KR0141806B1 (en) | Signal bit reinserting apparatus of pal+vcr |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |