KR0141806B1 - Signal bit reinserting apparatus of pal+vcr - Google Patents

Abstract

The present invention relates to a method and an apparatus for reinserting a signal bit of a PAL Plus V-CAL, which includes an optical screen signal on the 23rd line of a video signal transmitted from a broadcasting station at a point 11 에서 at the falling point of the synchronization signal. It will be reinserted automatically.

As described above, the present invention provides a method for separating a composite synchronization signal and data from an input video signal, and including data and synchronization separation means; Marker generating means for generating a line 23 marker signal, a signal bit marker signal, and a high-frequency marker signal having the separated composite synchronization signal; High frequency processing means for delaying an input video signal according to the generated high frequency marker signal; Reinsertion delay compensation means for delay-compensating the signal bit marker signal obtained by the marker generating means having a difference between the video signal before the high pass processing and the high pass processed video signal; Data decoding means for detecting and outputting optical screen data in a line 23 marker section obtained by the marker generating means; And signal bit reinserting means for inserting and outputting the optical screen data decoded by the data decoding means into the high frequency processed video signal by using the signal bit marker signal obtained by the reinsertion delay compensation means as a switching control signal. do.

Description

PALPLUS V-SR Signal Bit Reinsertion Device

1 is a diagram showing the position of optical screen data on the 23rd line of a normal vertical retrace period. (A) is a diagram showing a video signal before inserting a signal bit, and (b) is a signal bit marker. (C) shows the video signal after the signal bits are inserted.

2 is a format configuration diagram of the optical screen data of FIG.

3 shows a state in which the bit phase data of FIG. 2 is encoded.

Figure 4 is a block diagram of the signal bit re-insertion device of the present invention Pal Plus V.

5 is a diagram illustrating in detail the reinsertion delay compensation unit of FIG.

FIG. 6 shows the position state of the optical screen data on the 23rd line of the vertical retrace period according to FIG. 4. (a) shows a video signal before inserting a signal bit, and (b) shows a signal bit marker. (C) is a delayed video signal, and (d) is a delayed signal bit marker.

Figure 7 is another embodiment configuration of the signal bit re-insertion device of the present invention PAL Plus V.

* Explanation of symbols for main parts of the drawings

100: data and synchronization separation unit 101: marker generation unit

102: high-frequency processing unit 103: reinsertion delay compensation unit

104: data decryption unit 105: signal bit reinsertion unit

The present invention relates to the reinsertion of a wide screen signal (WSS) of a Palm Plus V-CAL, and more specifically, to a signal when reinserting data of an optical screen signal in an NTS broadcast method and a Palm Plus broadcast method. The present invention relates to a signal bit reinsertion apparatus of PAL Plus VSR which prevents a delay between a video signal used when generating a bit marker and a video signal to be reinserted and reinserted into a color burst.

In general, in the NTSC broadcasting system and the PAL-Plus broadcasting system, the letter box form blacks the upper and lower sides of the remaining screens with 3/4 of the original active video section as an image. The image is sent in a letter box.

This is to transmit an image having a 16: 9 aspect ratio such as a movie without distortion of the screen in a TV receiver having an aspect ratio of 4: 3.

However, the development of a wide screen TV receiver having an aspect ratio of 16: 9 has led to the necessity of displaying a 16: 9 image on a wide TV set in full screen.

Accordingly, in accordance with the trend of widespread use of wide TV receivers, the number of broadcast programs including a 4: 3 program and a 16: 9 program is increasing in order to revolve between 4: 3 TV receivers and optical screen TV receivers.

In addition, the receiving side needs to detect whether the program transmitted from each broadcasting station is 16: 9 or 4: 3, and inform the TV receiver, and there is also a need to transmit a status of service improvement of each broadcasting station.

Accordingly, the European Telecommunications Standards Institute (ETSI) has standardized the regulations for optical screen signals (WSS), and all broadcasters are following them.

The optical screen signal WSS is transmitted according to the standard, which is transmitted on the 23rd line of the vertical retrace period in the 625-line system, and the amplitude of the signal is 500 Hz at the black level.

The optical screen signal WSS is filtered in the form of sin ² and transmitted from the broadcasting station, and the data rate is transmitted at a rate of 5 Mbps (bit per second).

The 5 MHz clock is also locked and transmitted at the line frequency.

FIG. 1 shows the position of the signaling bits (SB) with respect to the optical screen signal WSS on the 23rd line in the general optical screen signal standard specification.

As shown in (a) of FIG. 1, the data of the signal bit SB for the optical screen signal WSS shown in FIG.

The data structure of the signal bit SB transmitted from the broadcasting station is composed of 137 elements when viewed with a 5 MHz clock as shown in FIG. 2, and the first 29 elements are run-in for clock recovery. The next 24 elements are transmitted as start codes, and the remaining 84 elements are composed of 14 data bits by encoding 6 elements into 1 bit of biphase data as shown in FIG.

Thus, to generate the signal bit marker and the 23rd marker as shown in (b) of FIG. 1 to process the optical screen signal (WSS) indicating whether the program transmitted from the broadcasting station is a 4: 3 program or a 16: 9 program. To separate it from the video signal.

After decoding the signal bit data in the separated 23rd marker section, the signal bit (SB) data is reinserted into the video signal as shown in (c) of FIG. 1 to automatically expand the screen on the wide TV receiver. It is.

However, in the current 4: 3 TV receiver or the 16: 9 wide TV receiver, when re-inserting the signal bit (SB) data for the optical screen signal WSS into the video signal, as shown in FIG. There is a delay of a predetermined time (t1) between the video signal used to make the signal bit marker and the video signal to be reinserted, and the reinsertion is performed by violating the color burst (CB) containing the reinsertion signal bit data in the 11 ms section The problem arises.

Accordingly, the object of the present invention is to reinsert the data of the optical screen signal on the 23rd line of the video signal transmitted and received from the broadcasting station at the point 11 에서 at the falling point of the synchronization signal in view of such a conventional problem. It is to provide a signal bit re-insertion device of Pal Plus V-AL.

In order to achieve the object of the present invention, a first process of generating a line 23 marker signal, a signal bit marker signal, and a high frequency marker signal necessary for detecting an optical screen signal with a complex synchronous signal obtained separately from an input video signal; ; A second process of delaying a video signal due to the generated high pass marker signal; A third step of delay-compensating the signal bit marker signal obtained in the first step by obtaining a difference between the video signal before the high pass and the high pass processed video signal; A fourth process of decoding the optical screen data in the line 23 marker section obtained in the first process; And a fifth step of inserting the decoded optical screen data into the high pass processed video signal based on the signal bit marker signal obtained in the third step.

Another means for achieving the object of the present invention is data and sync separation means for separating the video composite sync signal and data from the video signal transmitted from the broadcasting station and generating a system clock, and obtained in the data and sync separation means Marker generating means for generating a line 23 marker signal for detecting an optical screen signal, a signal bit marker signal for reinserting a signal bit, and a high frequency marker signal for high frequency component processing with a video composite synchronization signal; A high pass processing means for processing a high frequency component of the luminance signal in the input video signal according to a high pass marker signal, and a difference between the video signal before high pass processing and the video signal processed high frequency in the high pass processing means Reinsertion delay compensation means for delay-compensating the signal bit marker signal; A data decoding means for decoding and outputting optical screen data in a line of 23 marker lines obtained by the marker generation means, and a signal bit marker signal obtained from the reinsertion delay compensation means as a switching control signal and decoded by the data decoding means. Signal bit re-insertion means for inserting and outputting signal bit data into a high-pass processed video signal, and achieved by the following with reference to the accompanying drawings, the present invention is as follows.

FIG. 4 is a block diagram of the signal bit reinserting apparatus of PAL + V in accordance with the present invention. As shown in FIG. 4, the video composite synchronization signal (SV) is transmitted from a broadcasting station and input through the input terminal 106. The data and sync separator 100 separating the VCS and the data DATA and generating a system clock CLK, and the width of the video composite sync signal VCS separated from the data and sync separator 100. Counting the system clock CLK to generate the line 23 marker signal L23 necessary for the detection of the high frequency marker signal HM and the optical screen signal WSS, and counting the generated line 23 marker signal L23 to generate the optical screen data. A marker generation unit 101 for generating a signal bit marker signal SBM having only a high section, and the input terminal 106 according to the high-frequency marker signal HM generated by the marker generation unit 101. High frequency processing unit 102 for delaying the video signal input through And a signal bit marker signal SBM obtained by the marker generator 101 having a difference between the video signal VS through the input terminal 106 and the video signal VS 'delayed by the high pass processor 102. A reinsertion delay compensation unit 103 for compensating the signal bit and outputting the compensated signal bit marker signal SBM ', and the marker generation unit 101 among the data DATA separated from the data and the synchronization separator 100. A data decoding unit 104 which decodes and outputs the optical screen data SBD in the line 23 marker signal L23 section generated by the signal generator; and a signal bit marker signal compensated by the reinsertion delay compensation unit 103; The output terminal 107 is inserted by inserting the optical screen data SBD decoded by the data decoding unit 104 into the video signal VS 'processed by the high pass processing unit 102 using SBM') as a switching control signal. It consists of a signal bit reinsertion unit 105 to output through.

The signal bit reinsertion unit 105 may use the optical screen data decoded by the data decoding unit 104 by using the signal bit marker signal SBM 'compensated by the reinsertion delay compensation unit 103 as a switching signal. The data generator 105 is switched according to the data generator 105a for reconfiguring the SBD in synchronization with the system clock CLK, and the signal bit marker signal SBM 'compensated by the reinsertion delay compensation unit 103. And the switching unit 105b for inserting the optical screen data generated in the 105a into the video signal processed by the high pass in the high pass processing unit 102.

As shown in FIG. 5, the reinsertion delay compensator 103 receives a video signal VS from the input terminal 106 and discriminates and outputs a field signal. A second field discrimination signal generator 103b for receiving a video signal VS 'processed by the high pass processor 102 and discriminating and outputting a field signal, and the first and second field discriminations; A delay coefficient 103c for counting the difference between the two field discrimination signals input from the signal generators 103a and 103b as a system clock and outputting the counted clock number as the selection control signal D1, and the marker generator A delayed signal generator 103d for counting the signal bit marker signal SBM generated at 101 by the system clock CLK and delaying the signal from 1 to a maximum number of clocks; and obtained by the delayed signal generator 103d. Among the signal bit markers, the select control signal D1 obtained by the delay coefficient 103c is used. Dangneun select signal bit marker to constitute a selecting section (103e) for outputting.

If described in detail with reference to Figure 4 to Figure 6 the effect of the present invention configured as described above.

First, when the video signal VS carrying the optical screen signal WSS is transmitted from the broadcasting station and input to the data and the synchronization separator 100 through the input terminal 106, the data is transmitted. And the sync separator 100 separates and outputs the data DATA and the video composite sync signal VCS from the video signal VS input through the input terminal 106 and generates a system clock CLK. .

The data DATA separated by the data and sync separator 100 are input to the data decoder 104 at a later stage and the video composite sync signal VCS is input to the marker generator 101.

The marker generation unit counts the width of the video composite synchronization signal (VCS) separated from the data and sync separation unit (100) by the system clock (CLK) to detect the high frequency marker signal (HM) and the optical screen signal (WSS). A line 23 marker signal L23 is generated and the generated line 23 marker signal L23 is counted to generate a signal bit marker signal SBM having only a high optical screen data section as shown in FIG. Done.

The high frequency (Helper) marker signal (HM) generated by the marker generator (101) is input to the high frequency processor (102), and the signal bit marker signal (SBM) is input to the reinsertion delay compensation unit (103). The signal L23 is input to the data decryption unit 104.

The high pass processor 102, i.e., the helper processor displays the high pass component of the luminance signal from the video signal VS inputted through the input terminal 106 according to the input high pass marker signal HM. As described above, the delay processing process is input to the signal bit reinsertion unit 105 and the reinsertion delay compensation unit 103.

The reinsertion delay compensation unit 103 is a video signal VS as shown in FIG. 6 (a) through the input terminal 106, and as shown in FIG. 6C as delayed by the high pass processor 102. Compensating the signal bit marker signal SBM obtained by the marker generation unit 101 with the difference from the video signal VS 'as shown in (d) of FIG. 6, and the compensated signal bit marker signal SBM' is signal bit. The reinsertion portion 105 is provided.

The operation of the insertion delay compensation unit 103 will be described in more detail with reference to FIG. 5. First, the video signal VS and the high pass processor 102 as shown in FIG. 6A through the input terminal 106 are described. If the video signal VS 'such as (c) of FIG. 6 delayed by the input signal is input to the first and second field discrimination signal generators 103a and 103b of the reinsertion delay compensation unit 103, The first and second field discrimination signal generators 103a and 103b discriminate the fields of the video signal before the high pass processing and the video signal after the high pass processing to provide the field discrimination signal to the delay coefficient 103c. The delay coefficient 103c is a delay that is a difference between the field discrimination signal input from the first field discrimination signal generator 103a and the field discrimination signal input from the second field discrimination signal generator 103b. The signal is counted as a clock, and the delayed clock number is used as the selection control signal D1 to provide to the selection section 103e at a later stage.

In this case, the delay coefficient n is as follows.

Can be calculated as

For example, if there is a delay of 2 때 at 5 MHz, the delay coefficient Becomes

Therefore, if the signal bit marker signal SBM is delayed by 10 clocks, the delay compensated signal bit marker signal SBM 'can be obtained.

The delay signal generation unit 103d of the reinsertion delay compensation unit 103 counts the signal bit marker signal SBM input from the marker generation unit 101 as a system clock CLK, thereby counting the maximum clock from 1. The signal bit marker signals are inputted to the selector 103e by delaying by a few.

The selector 103e selects a signal bit marker signal corresponding to the selection control signal D1 input from the delay coefficient generator 103c among the signal bit marker signals input from the delay signal generator 103d, That is, as shown in (d) of FIG. 6, the compensated signal bit marker signal SBM 'is provided to the signal bit reinsertion unit 105 as a switching signal.

On the other hand, the data decoding unit 104 is optical screen data in the section of the line 23 marker signal (L23) generated by the marker generation unit 101 of the data (DATA) separated from the data and the synchronization separator 100 The SBD is synchronously decoded in synchronization with the system clock CLK and provided to the data generation unit 105a of the signal bit reinsertion unit 105.

The data generation unit 105a of the signal bit reinsertion unit 105 is enabled by the signal bit marker signal SBM 'compensated by the reinsertion delay compensation unit 103 and decoded by the data decoding unit 104. The optical screen data SBM is reconfigured in synchronization with the system clock CLK and then provided to the switching unit 105b.

The switching unit 105b is switched by the signal bit marker signal SBM 'input from the reinsertion delay compensation unit 103 to reconstruct the optical screen data SBD reconfigured by the data generation unit 105a, that is, the signal bit. The SB is inserted into the video signal processed by the high pass of the high pass 102 to be output to the output terminal 107.

FIG. 7 is a diagram illustrating another embodiment of the signal bit reinsertion apparatus of the present invention PalPlus V. Here, the signal bit reinsertion unit 105 is omitted without using the reinsertion delay compensation unit 103 of FIG. ) Is provided between the input terminal 106 and the high pass processing unit 102 and the signal bit marker signal SBM generated by the marker generation unit 101 is used as the switching signal of the switching unit 105b. And the switching unit 105b first inserts the optical screen data generated by the data generating unit 105a into the video signal input from the input terminal 106 and then processes it in the high pass processing unit 102. .

In other words, when the optical screen data SBD in the line 23 marker signal L23 section is decoded from the data decoding unit 104 and input to the data generating unit 105a of the signal bit reinserting unit 105, the data is transmitted. As described above, the generation unit 105a enables the optical screen data SBM which is enabled by the signal bit marker signal SBM generated by the marker generation unit 101 and decoded by the data decoding unit 104. After reconfiguring in synchronization with the clock CLK, it is provided to the switching unit 105b.

The switching unit 105b of the signal bit reinsertion unit 105 is switched by the signal bit marker signal SBM generated by the marker generation unit 101 and reconstructed and input by the data generation unit 105b. The data is inserted into the video signal of the input terminal 106 and provided to the high pass processor 102.

Accordingly, the high pass processor 102 performs high pass processing of the video signal into which the optical screen data is inserted by the switching unit 105b of the signal bit reinsertion unit 105 and outputs the video signal to the output terminal 107.

As described in detail above, according to the present invention, by re-inserting the data for the optical screen signal on the 23rd line from the video signal transmitted from the broadcasting station to the point 11㎲ from the falling point of the synchronization signal, The effect is that the insert data is automatically reinserted without invading the color burst.

Claims (9)

Data and sync separating means for separating the composite sync signal and data from the input video signal and generating a system clock; Marker generation means for generating a line 23 marker signal, a signal bit marker signal, and a high-frequency marker signal, which are required for the optical screen signal detection, with the composite synchronization signal obtained in the data and synchronization separation means; High frequency processing means for delaying the input video signal according to the high frequency marker signal obtained by the marker generating means; Reinsertion delay compensation means for delay-compensating the signal bit marker signal obtained by the marker generating means having a difference between the video signal before the high pass processing and the high pass processed video signal; Data decoding means for detecting and outputting optical screen data in a line 23 marker section obtained by said marker generating means; And a signal bit reinserting means for inserting and outputting the optical screen data decoded by the data decoding means into a high frequency processed video signal by using the signal bit marker signal obtained by the reinsertion delay compensation means as a switching control signal. Re-insertion of the signal bit of PALPLUS V-SR. 2. The marker generating means according to claim 1, wherein the marker generating means counts the width of the input composite synchronization signal to generate a high frequency marker signal and a line 23 marker signal, and counts the line 23 marker signal to generate a signal bit marker signal during the optical screen data period. Signal bit re-insertion device of PAL Plus V characterized in that the generation. 2. The reinsertion delay compensation means according to claim 1, further comprising: first field discrimination signal generating means for discriminating and outputting a field signal from an input video signal; Second field discrimination signal generating means for discriminating and outputting a field signal from the high pass processed video signal; Delay coefficient means for counting a delay signal, which is a difference between two field discrimination signals obtained by said first and second field discrimination signal generating means, as a system clock; Delay signal generation means for counting and outputting the signal bit marker signal generated by the marker generation means; And a selection means for selecting and outputting a signal bit marker according to the coefficient value obtained by the delay coefficient means among the signal bit markers obtained by the delay signal generating means. 4. The apparatus of claim 3, wherein the delay coefficient means obtains a delay coefficient value by dividing the delay time and the system clock time by the high pass processing means. 4. The signal bit reinserting apparatus according to claim 3, wherein the selecting means selects a value corresponding to a coefficient value obtained by the delay coefficient means from among the signal bit markers obtained by the delay signal generating means. 4. The apparatus of claim 3, wherein the delay signal generating unit counts and outputs a signal bit marker signal input from the marker generating unit to a value set by a system clock. The signal bit reinserting means according to claim 1, further comprising: data generating means for reconstructing the optical screen data obtained by the data decoding means in synchronization with a system clock by a signal bit marker signal obtained by the reinsertion delay compensation means; And a switching means for switching the optical screen data obtained from the data generating means and the high pass processed video signal according to the signal bit marker signal obtained from the insertion delay compensation means. The method according to claim 1, wherein instead of deleting the reinsertion delay compensation means, a signal bit reinsertion means is provided in front of the high pass processing means to reconstruct and insert the optical screen data decoded by the data decryption means into the input video signal. The signal bit re-insertion device of the palplus V-AL. The method of claim 1 or 8, wherein the signal bit reinserting means receives a signal bit marker signal obtained from the marker generating means as a switching signal and inserts optical screen data into the video signal. Signal bit reinsert.