CA1187186A - Digital-to-analog converter with nonideal analog-to- digital converter - Google Patents
Digital-to-analog converter with nonideal analog-to- digital converterInfo
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- CA1187186A CA1187186A CA000403138A CA403138A CA1187186A CA 1187186 A CA1187186 A CA 1187186A CA 000403138 A CA000403138 A CA 000403138A CA 403138 A CA403138 A CA 403138A CA 1187186 A CA1187186 A CA 1187186A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/19—Arrangements for performing computing operations, e.g. operational amplifiers for forming integrals of products, e.g. Fourier integrals, Laplace integrals, correlation integrals; for analysis or synthesis of functions using orthogonal functions
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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Abstract
METHOD FOR ANALYZING A DIGITAL-TO-ANALOG CONVERTER
WITH A NONIDEAL ANALOG-TO-DIGITAL CONVERTER
ABSTRACT OF THE DISCLOSURE
A method for statistically calibrating a digital-to-analog converter with an electronic test system. The digital-to-analog converter is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by an analog-to-digital con-verter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals.
The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weight-ing coefficients are weighted by the reciprocal of the pre-measured weighting coefficients to obtain the unbiased weight of each bit of the digital-to-analog converter under test. A
preferred set of excitation signals is a set of Walsh func-tion signals representing the digital equivalent of a linear ramp function.
WITH A NONIDEAL ANALOG-TO-DIGITAL CONVERTER
ABSTRACT OF THE DISCLOSURE
A method for statistically calibrating a digital-to-analog converter with an electronic test system. The digital-to-analog converter is excited with two state signals at each input bit which together represent a single signal with uniform amplitude probability with respect to time, and wherein each excitation signal is orthogonal with respect to all other excitation signals. The output of the digital-to-analog converter is detected by an analog-to-digital con-verter which has been calibrated by premeasured weighting coefficients with respect to two-state orthogonal signals.
The digital time domain output signals are then mapped into a transform domain to obtain weighting coefficients of each bit of the output response. Finally the transform domain weight-ing coefficients are weighted by the reciprocal of the pre-measured weighting coefficients to obtain the unbiased weight of each bit of the digital-to-analog converter under test. A
preferred set of excitation signals is a set of Walsh func-tion signals representing the digital equivalent of a linear ramp function.
Description
~1~71~36 METHOD FOR ANALYZING A DIGITAL-TO-ANALOG CONVERTER
WITM A NONIDEAL ANALOG-TO-DIGITAL CONVERTER
BACKGRQUND OF THE INVENTION
1. Field of Invention This invention relates to auto~atic test systems for digital electronic converters and particularly to statistical methods and related electronic apparatus for testing digital-to-analog converters.
Con~irerters between the digital and analog signal domains are employed to interface digital electronic circuitry and analog devices. Accuracy of conversion, gain and repeatability in the process of conversion are matters of concern. One method of testing a digital-to-analog converter is to apply a digital signal to its input to obtain an analog output signal, and then to apply the analog output signal to the input of an analog-to-digital converter to recover a digital signal and then to compare the digital output signaI with a standard such as the digital input signal or to process the output signal to determine its statistical characteristics. The characteristics of the output signal in terms of a statistical description provide an indication of the accuracy of the digital-to-analog converter.
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WITM A NONIDEAL ANALOG-TO-DIGITAL CONVERTER
BACKGRQUND OF THE INVENTION
1. Field of Invention This invention relates to auto~atic test systems for digital electronic converters and particularly to statistical methods and related electronic apparatus for testing digital-to-analog converters.
Con~irerters between the digital and analog signal domains are employed to interface digital electronic circuitry and analog devices. Accuracy of conversion, gain and repeatability in the process of conversion are matters of concern. One method of testing a digital-to-analog converter is to apply a digital signal to its input to obtain an analog output signal, and then to apply the analog output signal to the input of an analog-to-digital converter to recover a digital signal and then to compare the digital output signaI with a standard such as the digital input signal or to process the output signal to determine its statistical characteristics. The characteristics of the output signal in terms of a statistical description provide an indication of the accuracy of the digital-to-analog converter.
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2 Des~ription_of the Prior Art State of the art testing techniques for digital converters are generally limited to testing, in the case of digital-to-analog converters, a few states such as the sirnple binary weights and full-scale amplitude.
Substantially all tes-ts are static in nature and are incapable of providing a complete statistical evaluation of a converter.
Recently dynamic testing techniques have been suggested for limited purposes. An example is a method proposed by L. F. Pau and presented in a paper entitled "Fast Testing and Trimrning o~ A/D and D/A Converters in Automatic Test Systems" at the 1978 IEE~ Autotest Conference. Pau suggested analyzing the error signal with Walsh functions. The error signal is obtained by comparing to a reference device. Other known evaluation methods also presupposecl the use of an ideal reference device, such as an analog to-digital converter having a linear transfer characteristic, the output response of which is employed with the output response of a device under test to generate an error signal from which an evaluation of performance is made. A device built according to the technique suggested hy Pau is therefore limited by the accuracy of the reference device.
On~ of the concerns of prior art converter testing methods has been an ina~ility to distinguish between signal-induced biases or errors and biases or errors inherent in the testing devices. Accordingly, much effort has been devoted to linearization of the excitation signals and of the transfer characteristics of the measuring devices, such as the analog to-digital converter used to detect the output oE the digital-to-analog converter under test. The present invention represents a departure from this effort to idealize the testing equipment.
Substantially all tes-ts are static in nature and are incapable of providing a complete statistical evaluation of a converter.
Recently dynamic testing techniques have been suggested for limited purposes. An example is a method proposed by L. F. Pau and presented in a paper entitled "Fast Testing and Trimrning o~ A/D and D/A Converters in Automatic Test Systems" at the 1978 IEE~ Autotest Conference. Pau suggested analyzing the error signal with Walsh functions. The error signal is obtained by comparing to a reference device. Other known evaluation methods also presupposecl the use of an ideal reference device, such as an analog to-digital converter having a linear transfer characteristic, the output response of which is employed with the output response of a device under test to generate an error signal from which an evaluation of performance is made. A device built according to the technique suggested hy Pau is therefore limited by the accuracy of the reference device.
On~ of the concerns of prior art converter testing methods has been an ina~ility to distinguish between signal-induced biases or errors and biases or errors inherent in the testing devices. Accordingly, much effort has been devoted to linearization of the excitation signals and of the transfer characteristics of the measuring devices, such as the analog to-digital converter used to detect the output oE the digital-to-analog converter under test. The present invention represents a departure from this effort to idealize the testing equipment.
3 Cros_-Re~er_nce_to Related Ap~ication In United States Patent No. 4~419,656 entitled "Method and Apparatus for Digital Converter Tes~ing", a method and apparatus are disclosed for dynarnically testin~
the overall performance characteristics of both digital-to-analog converters and analog-to-digital converters. The ,.~
37~6 method comprises dynamically exercising an analog oe digital converter with, respectively, analog or digital signal patterns which can be characterized as the sum of a set of mutually orthogonal two-state functions of defined amplitudes, the sum having substantially uniform amplitude distribution over the allowable states of the amplitude range in order to exercise substantially all allowable converter states of concern at random times. Thereafter, the response of the converter under test is examined for a number of basic performance parameters, including total distortion, linearity and optimum gain. The method described therein yields a relatively complete statistical description of the performance characteristics.
SUMMA~Y OF T~E INVENTION
It is a general object of the ~resent invention to provide a new method and apparatus for analyzing digital-to-analog converters.
This and other objects are attained, in accordance with one aspect of the invention, by a method for calibrating a digital-to-analog converter (DAC) comprising the steps of: exciting inputs of the DAC under test from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC under test and each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform amplitude probability, said DAC under test producing an analog output signal; providing said analog output signal of the DAC under test at an analog input of an analog-to-digital converter (ADC~, the transfer function of said ADC
having been characterized by premeasured weighting values of a set of binary orthogonal functions, said ADC
producing digital output signals; transforming said digital output signals from time domain digital signals into binary tranform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and correcting each said output response weighting coefficient for bias errors induced by said ~DC by multiplying each output response weighting coefficient by the reciprocal of each correspondiny said premeasured weighting values in a bias correction means in order to obtain unbiased weighting values o each bit specifying the transfer characteristic of the digital-to-analog converter under test.
Another aspect of the invention includes anapparatus for calibrating a digital-to-analog converter (DAC) comprising: means for exciting inputs of the DAC
~ under test from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform a~plitude probabilityr said DAC under test producing an analog output signal at an analog output signal terminal; an analog-t~-digital converter (ADC) adapted to be coupled to said analog output signal 37~
terminal, the transfer function of said ADC having been characterized by premeasured weighting values o~ a set of hinary orthogonal functions, said ADC being operative to produce digital output signals in response to said analog output signal; means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and means for correcting each said output response weigbting coefficient for bias errors induced by said ADC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the digital-to-analog converter under test.
This invention will better understood by reference to the following detailed description of specific embodimer.ts taken in connection with the ac~ompanying drawings.
8RIEF DFSCRIPTION OF THE DR~WINGS
Figure l is a block diagram of an apparatus operative according to the method of the invention.
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Figure ~ is more detailed block diagram or an apparatus opera~ive according to the method of the invention.
DETAILED DESCRIPTION OF SPECI~IC E~130DI~IENTS
. Figure l illustrates, in bloc~ diagram fo~m~ a ~est S appara~us l0 which might operate according to the present in~en~ion to test a digi~al~to-analog converter ~DAC) device under test ~DUT) 14~ The apparatus l0 comprises two essen-tial elements, namely, a digital generator 12 having a spéci-icially-defined outpu~ signal ~nd a characterized analog--to-digital conver~er tADC) 16. By "charac~erized~ is mean~that the ADC 16 has a transer characteris~ic kno~ for each bit in terms of a set of orthogonal ~wo-state ~unc~ions, such as Walsh ~unctions. The ~oefficients of the unctions, which are real numbers, are thereafter emLployed in a coefficient lS proc~ssor l~ to analyze the Device under Test (DUT) 14, as hereinater.explained. A clock 20 provide~ overall syn-chronization or the test apparatus 10.
The generator 12 must be operati~e to generate a digital output signal representing a set: o~ two-state or~hogonal func~ions ln a maximum ~ntropy sequence. Examples of two-sta~e orthogonal func~ions are the sequences 0,l,0,l,0,l,0,l; 0,0,Z,~,0,0,2,2; and 0,0,0,0,~,4,~,4, which is a set of three Wal~h fu~ctions, l,0~0,l,l,0,l,0;
2,0,Z,0,0,2,2,0; and 0,4,0,0,4t4,4,0, ~hich is a set o or~hogGnal unctions which ean be obtained by permuting the order of ~he Walsh function maximum entropy sequence. The sum.of each se~ of three is an integer func~ion ~hat is .
uniformly distributed on the interval 0 to 7. Specifically, a maximum en~ropy sequence might be a discrete digitized si~nal de~ining a repetitive. ~amp or any other signal havina u~iform amplitude distribu~ion over the- sampling period of i~terest, as shown a~ove. The ou~pu~ of he generator lZ is ~ia a digital bus 22 wherei~ each signal lin~ is a bit signal li~e ~ a dif~erent order of magni~ude. Each b~t o ~he ~igita~ bu~ 22 is excited by a different bînary or~hogun~l functionO Si~ce eac~ bit i5 separately and inde-pendently weight~d, depending on the bit assig~ment~ the o~erall output 4~ the generator 12 is a se~ o~ binary _._.. __.__:_ .~.. __.,_."_,_:~.,_, .__"".,7,,.,~__.,___~_~,_."__~.___.. _,_.,_~,_~7", .,~_"_,__,.. ___.. _____ ,_~. _.. ~__._.______._ ._. _. _ ,_._.__,_ _,, ,., _.,_____ ., orthogonal functions. ~ preferred set of binary orthogonal functions is the Walsh func~ions although other binary orthogonal functions having essentially equivalent character-istics are also suitable in ~he invention. A specific embodi-ment is described in reference to the Walsh functisns forsimplicity.
The ou~put on bus 22 is applied to the input of the DAC device under test (DUT) 14. Each input bit of the DUT 14 is exci~ed by a single orthogonal function. Bec~use the generator 12 provid-es a pure digital signal, the binary weishts at the input form an ideal inpu~ signal from which an an~log ou~put is ob~ained which can be analy~ed. The analog output signal must be analyzed to determine the dynamic transfer function o the DUT 14. When the bit pattern ap-plied to each one of the input bits o the DUT 1h is a Walshfunction, the analog output sîgnal can al50 be descxibed in texms o~ a set of Walsh unctions. Since each such bit pa~tern is applied to a diferent input ~it, there is an impliçit relative bina~y weight of 2m for each coeficient am of ~e Walsh functions which represent the output o the DUT
14, wh~re m corresponds to the order of the ~it to which the .
input Walsh function is applied ~y means of the bus 2~, The objec:t o~ the invention is to obtain the set of coe~icients am of the out~ut ~alsh functlons which charac-teriz~ ~he outpu~ transfer function of the D~T 14, ~here amis ~h~ weight of ~he mth bit of the DUT 14.
According to the in~ention, the transfer character-istic o the DU~ l~ is obtained after first detenmining ~he txansfer characteristic of the ADC 16 and then measuring the digital ou~put at each bit output c~ the ADC 16. To this end ~he.coef~icient processor 18 comprises a Walsh ~ransform processor 24 having its output coupled to a bias- corrPctor 26 which Ln tNr~ has its outpu~ coupled to an output utilization devic~ 28 (Figure Z).
35 . ~he signal out o ~he DU~ 14 and into ~he ADC 16 is ~ fu~tion x(t~. ~he siçnal out o~ the ADC 16 resulting from t~ input a~alog function x(t) is ~ output digi~al function y(t), whe~e y(~ ~ f{x(t)}.
Significantl~, the ~rar~s~r characteristic o~ ~he ADC 16 can be expresse~ in terms of Walsh functions wi~h ~87~6 coefficients dependent upon identifiable nonlinearities which are independent of any excitation sequence. This result follows because the special digital generator 12 is a maximum entropy e~citer. The bias factors introduced by the ADC 12 are invariant with respect to the choice ot the set of orthogonal functicns used as a specific excitation pattern as long as the excitation bit pattern constitutes a maximum entropy sequence.
It is also significant to the inventon and not imm~diately apparent that the number of bias factors corresponds to the number of bits, i.e., the number of input lines to the DUT 14, and not to the number of allowable states of the DUT 1~. The characterized bias factors are compensated for in a bias corrector 26 to which the output oi the ADC 16 is applied.
The output of the bias corrector 26 is the set of output Walsh coef~icients am which characterize the DUT
14 signal. The signal processing of the output Walsh coefficients, as well as the characteristics of orthogonality and of Walsh functions, have been taught elsewhere, as for example in my paper entitled "Application o~ Walsh Functions to Converter Testing"
presented No~ilember 11, 1~8~ and published in Procee~in~s of the 1980 Auto Test Conference (IEEE 80-CE11608-9)~ The outpuk of the processed Walsh coefficients is a~plied to an output utilization device 28 such as a display device or the like.
Because it is not immediately apparent that the bias factors can be determlned independen~ly of the particular maximum entropy excitakion signal, the following theoretical analysis and explanation is presentedc This discussion shows the bias introduced by a nonlinear, non-ideal ADC is substantially independent of the aevice, even in dynamic testing, so long as the excitation signal is a maximum entropy sequence and khe DUT 14 nonlinearities are moderate n Analyzing a maximum entropy sequence signal applied to an ADC 16 through an unknown linear transfer function where the input is x(t), the output y(t) may be expressed ~,,~, .
y(t) = f{x(t)} (l~
x(t) being a~ lnput maximum entropy sequence.
Assume that the function y(t) is defined as the sum of distortion and a se~uence of weighted Walsh functions.
y(t) m-0 âm~,m(t) ( ) (2) where ~(t) is the Walsh function;
~ is the order of the Walsh function;
m is the bit index;
M is the number of bits o the converter associated with the mth bit;
â is the weight of the mth bit after passing through the transfer . 15 function-~(x); and (t) is a term representins residual distortion.
It follows therefor~ that ~he coefficient âm is the integral of the product of the ~unction y(t) and the Q
order Walsh unction corres~onding.to -the m~h bit o~e~ time ~
am ~ ~ S~ y(t) ~Q m(t)dt = ~ r~ f{xtt)} ~Q m~t)dt By ~he Ergodic ~ypothesis which esta~lishes the equi~alence of time and statlstical averages, it can be shown ~hat the coef~icient âm is the expected value of the ~roduc~
of the function f(x) and the ~ order W~lsh fu~ction for the mth bit. ~his expected value is equ21 ~o ~he double integral over x and ~-of the product of W~ f(x), and the joinc amplitude densi~} fun~tian o~ ~ and ~ m~t) or âm = E {f(x) ~Q mtX)}
- 3 - r~ Q m(X)P~ ,m } d~Qd~ (4) where E{ ~ is ~he expected value of the product; and p{ } is the joint amplitude probability density function .
The joint amplitude proDability density function is a two-dimensional distribution that describes the probability t:hat the ~wo state Walsh func.ion ~Q m~x) is on or off for a given value of x. Inasmuch as the variable x(t) is substan- -tially uniformly distributed in amplitude according to the invention, ~hen permu~ing ~he order of the e~citation sequences does not change ~he probability tha~ a given bit ~ill be on or off for a given e~itation value.
It therefore follows that the dens.ity function p~x,`Y~, m) is equal to the joint density of a given value of ~c occurring when the binary order, or 2m order, Walsh func~
tion is on or off or P( ~ ~,m) p(x, ~2m) (5) or unifor~ly distri~uted x.
~ence from equation (4) a~ove, ~he coeficient âm is the expected value of the product o the 2mth order Walsh function and the function f(x) or ~m E{f(X)~2m(~)}
= ~ff(x)~ m(X)P~X~ ~2m) d~ (6a) = r~ r~2m(X)p(x~ ~2m d~ ~
By examination of ~he zctivity of each ~it o the excitation sequence it is possible to derive the densit~
u~ction p(x~ ~2~) and then integrate the density function ov~r all possible Yalues of x~
Table I shows ~he densi~y function p(x,~) for a ramp x=-l ~o +1 for a four-~it range, or the sum of four Walsh functions:
~137~6 TABLE: I
_ ~2 ~2~ 2 ~23 x ~ 1 +1 -1 f~
5*15/16 0 ~/16 ~ l/16 0 1/16 0 l/16 ~13/16 0 1/16 0 1/1~ 0 1/16 1/16 0 0 1~16 0 1/16 1/16 0 0 1/16 -~9Jl6 0 1/16. û l/16 1/16 o 1/16 0 ~7/16 ~ l/16 1/16 0 0 1/16 Q l/16 10t ~/~6 0 l/16 1~16 ~ O l/16 l/16 0 +3Jl6 0 l/16 1/16 0 1/16 0 0 1/16 ~l/16 0 1~16 1~1~ . 0 1/16 0 1/16 0 ~l/16 1/16 a ~ 1/16 0 1~16 0 ~/16 -3/16 1/16 a o 1~16 0 ~/16 1/16 155fl6 1/16 0 0 1/16 1/16 0 0 1/16 7/16 l/16 0 0 1/16 1/16 0 1/16 ~) -~16 l/16 0 }/16 0 0 l/16 ~ 1~16 '16 ~ o l/16 0 0 1/16 l/16 o -I3~16 1/16 0 1/16 0 1/16 0 0 1/15 20~15/1~ l/13 û 1/16 0 1/16 0 :Referring- tQ Table I, i~ integration ~f ~ is ar-rie~l ou~ in equatio~ 6(a) over ~he Y' dimension, then the eval~lation o:f~ equation t6a) simply becomes X.
âm 2X ~ ~) `Y m(x)dx (~b) The transIer unction f ¢x) of ~e ~haracteri ed ADC
3a 16 may }~e represented as a sum of Walsh ~unctions weighted by c:oefficients an ar , .
O
~8~7~
c~
n-O ~ ~
Substituting equation (7) and the solution to the density function into equation (6b) or integration over all values of x, the coefficient aM is determined to be the sum of ~he weighted integrated produc~s of two Walsh functions in x normalized by the span of x, or X
~m ~ 2X n~O an ~X ~n~x) ~2m(x)dX (~) Since the Walsh functions are orthogonal, the .product thereo~ is e~ual to unity whenever the order is e~ual, and is zero otherwise, i.e., r Y~ 2m(X)dX - 1 (9~
or n = 2m.
f ~D.(g) '~ m(X~ o ( ~ o 20 ~or n ;~ 2m.
It follows immediately from equa.ion (~) ~hat ~he estimated weight am is egual to the weighting coefficien~ a of the 2m~h order Walsh unction that describes ~he txansfer characteristic f~x) or â = a (11) m 2~
~ quation (11) implies that the nonlineaxity in the ~DC 16 appears as a time-independent bias in the estimate of am. Specifi~ally, the unbiased estimate of ~he m~h bit weight of the A~C 16 is th2 biased estimate of ~he weight due to all known and unk~ow~ factors i~troduced betwee~ the ~not~
l~pUt an~ t~ mea~ured ou~put at the i~put of the coefficient processor 18 and the scaled product of ~he reciprocal of the related weighti~g coe~fic7 ent ~m or ~8~
a _ m (12) m 2ma According to the invention, the bias correction terms 2ma2m o the ~DC 16 are kIlOWR values stored in the ADC
bias corrector 26 (Fig. 2). The output signals of the Walsh transormer 4, which are the coefficients âm f the Walsh transform of the output y(t) sign~ls are corrected by the bias correction terms 2~a2m according to the relationship in equ~tion (12) to produce the unbiased coefficients am~ For example, if a2m equals am, then the bit weight o the coeffi-cient am is simply 2m. The unbiased coefficients am specify the tran~ex characteristic of the DUT 1~. More particular~
ly, the unbiased weighting coefficients am appear in the x(t) functio~ of ~he DUT 14 as follows:
~--1 x(t) ~ ~0 am ~Q,m( (13) Because the ~ m(t) is ahsolutely ~nown (since it is the digital excitation function o the digi~al genexator 14), ~t) is k~own and the DUT 1~ is calibrated.
Many forms of digital excitation signals axe suit-able in the invention. A sigllal particularly well suited is 25 the set of individual binary signals which represents a linear amplitude ramp which may be repeated.
The invention has now been explained in respect of specific embodiments. Other embodiments will be apparent to those of~ ordinary s}~ll in this art~ It is ~erefore no~
30 intended that th~ inventioIl be limited except as indicated in the appended claims.
the overall performance characteristics of both digital-to-analog converters and analog-to-digital converters. The ,.~
37~6 method comprises dynamically exercising an analog oe digital converter with, respectively, analog or digital signal patterns which can be characterized as the sum of a set of mutually orthogonal two-state functions of defined amplitudes, the sum having substantially uniform amplitude distribution over the allowable states of the amplitude range in order to exercise substantially all allowable converter states of concern at random times. Thereafter, the response of the converter under test is examined for a number of basic performance parameters, including total distortion, linearity and optimum gain. The method described therein yields a relatively complete statistical description of the performance characteristics.
SUMMA~Y OF T~E INVENTION
It is a general object of the ~resent invention to provide a new method and apparatus for analyzing digital-to-analog converters.
This and other objects are attained, in accordance with one aspect of the invention, by a method for calibrating a digital-to-analog converter (DAC) comprising the steps of: exciting inputs of the DAC under test from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC under test and each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform amplitude probability, said DAC under test producing an analog output signal; providing said analog output signal of the DAC under test at an analog input of an analog-to-digital converter (ADC~, the transfer function of said ADC
having been characterized by premeasured weighting values of a set of binary orthogonal functions, said ADC
producing digital output signals; transforming said digital output signals from time domain digital signals into binary tranform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and correcting each said output response weighting coefficient for bias errors induced by said ~DC by multiplying each output response weighting coefficient by the reciprocal of each correspondiny said premeasured weighting values in a bias correction means in order to obtain unbiased weighting values o each bit specifying the transfer characteristic of the digital-to-analog converter under test.
Another aspect of the invention includes anapparatus for calibrating a digital-to-analog converter (DAC) comprising: means for exciting inputs of the DAC
~ under test from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform a~plitude probabilityr said DAC under test producing an analog output signal at an analog output signal terminal; an analog-t~-digital converter (ADC) adapted to be coupled to said analog output signal 37~
terminal, the transfer function of said ADC having been characterized by premeasured weighting values o~ a set of hinary orthogonal functions, said ADC being operative to produce digital output signals in response to said analog output signal; means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and means for correcting each said output response weigbting coefficient for bias errors induced by said ADC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the digital-to-analog converter under test.
This invention will better understood by reference to the following detailed description of specific embodimer.ts taken in connection with the ac~ompanying drawings.
8RIEF DFSCRIPTION OF THE DR~WINGS
Figure l is a block diagram of an apparatus operative according to the method of the invention.
~7~
Figure ~ is more detailed block diagram or an apparatus opera~ive according to the method of the invention.
DETAILED DESCRIPTION OF SPECI~IC E~130DI~IENTS
. Figure l illustrates, in bloc~ diagram fo~m~ a ~est S appara~us l0 which might operate according to the present in~en~ion to test a digi~al~to-analog converter ~DAC) device under test ~DUT) 14~ The apparatus l0 comprises two essen-tial elements, namely, a digital generator 12 having a spéci-icially-defined outpu~ signal ~nd a characterized analog--to-digital conver~er tADC) 16. By "charac~erized~ is mean~that the ADC 16 has a transer characteris~ic kno~ for each bit in terms of a set of orthogonal ~wo-state ~unc~ions, such as Walsh ~unctions. The ~oefficients of the unctions, which are real numbers, are thereafter emLployed in a coefficient lS proc~ssor l~ to analyze the Device under Test (DUT) 14, as hereinater.explained. A clock 20 provide~ overall syn-chronization or the test apparatus 10.
The generator 12 must be operati~e to generate a digital output signal representing a set: o~ two-state or~hogonal func~ions ln a maximum ~ntropy sequence. Examples of two-sta~e orthogonal func~ions are the sequences 0,l,0,l,0,l,0,l; 0,0,Z,~,0,0,2,2; and 0,0,0,0,~,4,~,4, which is a set of three Wal~h fu~ctions, l,0~0,l,l,0,l,0;
2,0,Z,0,0,2,2,0; and 0,4,0,0,4t4,4,0, ~hich is a set o or~hogGnal unctions which ean be obtained by permuting the order of ~he Walsh function maximum entropy sequence. The sum.of each se~ of three is an integer func~ion ~hat is .
uniformly distributed on the interval 0 to 7. Specifically, a maximum en~ropy sequence might be a discrete digitized si~nal de~ining a repetitive. ~amp or any other signal havina u~iform amplitude distribu~ion over the- sampling period of i~terest, as shown a~ove. The ou~pu~ of he generator lZ is ~ia a digital bus 22 wherei~ each signal lin~ is a bit signal li~e ~ a dif~erent order of magni~ude. Each b~t o ~he ~igita~ bu~ 22 is excited by a different bînary or~hogun~l functionO Si~ce eac~ bit i5 separately and inde-pendently weight~d, depending on the bit assig~ment~ the o~erall output 4~ the generator 12 is a se~ o~ binary _._.. __.__:_ .~.. __.,_."_,_:~.,_, .__"".,7,,.,~__.,___~_~,_."__~.___.. _,_.,_~,_~7", .,~_"_,__,.. ___.. _____ ,_~. _.. ~__._.______._ ._. _. _ ,_._.__,_ _,, ,., _.,_____ ., orthogonal functions. ~ preferred set of binary orthogonal functions is the Walsh func~ions although other binary orthogonal functions having essentially equivalent character-istics are also suitable in ~he invention. A specific embodi-ment is described in reference to the Walsh functisns forsimplicity.
The ou~put on bus 22 is applied to the input of the DAC device under test (DUT) 14. Each input bit of the DUT 14 is exci~ed by a single orthogonal function. Bec~use the generator 12 provid-es a pure digital signal, the binary weishts at the input form an ideal inpu~ signal from which an an~log ou~put is ob~ained which can be analy~ed. The analog output signal must be analyzed to determine the dynamic transfer function o the DUT 14. When the bit pattern ap-plied to each one of the input bits o the DUT 1h is a Walshfunction, the analog output sîgnal can al50 be descxibed in texms o~ a set of Walsh unctions. Since each such bit pa~tern is applied to a diferent input ~it, there is an impliçit relative bina~y weight of 2m for each coeficient am of ~e Walsh functions which represent the output o the DUT
14, wh~re m corresponds to the order of the ~it to which the .
input Walsh function is applied ~y means of the bus 2~, The objec:t o~ the invention is to obtain the set of coe~icients am of the out~ut ~alsh functlons which charac-teriz~ ~he outpu~ transfer function of the D~T 14, ~here amis ~h~ weight of ~he mth bit of the DUT 14.
According to the in~ention, the transfer character-istic o the DU~ l~ is obtained after first detenmining ~he txansfer characteristic of the ADC 16 and then measuring the digital ou~put at each bit output c~ the ADC 16. To this end ~he.coef~icient processor 18 comprises a Walsh ~ransform processor 24 having its output coupled to a bias- corrPctor 26 which Ln tNr~ has its outpu~ coupled to an output utilization devic~ 28 (Figure Z).
35 . ~he signal out o ~he DU~ 14 and into ~he ADC 16 is ~ fu~tion x(t~. ~he siçnal out o~ the ADC 16 resulting from t~ input a~alog function x(t) is ~ output digi~al function y(t), whe~e y(~ ~ f{x(t)}.
Significantl~, the ~rar~s~r characteristic o~ ~he ADC 16 can be expresse~ in terms of Walsh functions wi~h ~87~6 coefficients dependent upon identifiable nonlinearities which are independent of any excitation sequence. This result follows because the special digital generator 12 is a maximum entropy e~citer. The bias factors introduced by the ADC 12 are invariant with respect to the choice ot the set of orthogonal functicns used as a specific excitation pattern as long as the excitation bit pattern constitutes a maximum entropy sequence.
It is also significant to the inventon and not imm~diately apparent that the number of bias factors corresponds to the number of bits, i.e., the number of input lines to the DUT 14, and not to the number of allowable states of the DUT 1~. The characterized bias factors are compensated for in a bias corrector 26 to which the output oi the ADC 16 is applied.
The output of the bias corrector 26 is the set of output Walsh coef~icients am which characterize the DUT
14 signal. The signal processing of the output Walsh coefficients, as well as the characteristics of orthogonality and of Walsh functions, have been taught elsewhere, as for example in my paper entitled "Application o~ Walsh Functions to Converter Testing"
presented No~ilember 11, 1~8~ and published in Procee~in~s of the 1980 Auto Test Conference (IEEE 80-CE11608-9)~ The outpuk of the processed Walsh coefficients is a~plied to an output utilization device 28 such as a display device or the like.
Because it is not immediately apparent that the bias factors can be determlned independen~ly of the particular maximum entropy excitakion signal, the following theoretical analysis and explanation is presentedc This discussion shows the bias introduced by a nonlinear, non-ideal ADC is substantially independent of the aevice, even in dynamic testing, so long as the excitation signal is a maximum entropy sequence and khe DUT 14 nonlinearities are moderate n Analyzing a maximum entropy sequence signal applied to an ADC 16 through an unknown linear transfer function where the input is x(t), the output y(t) may be expressed ~,,~, .
y(t) = f{x(t)} (l~
x(t) being a~ lnput maximum entropy sequence.
Assume that the function y(t) is defined as the sum of distortion and a se~uence of weighted Walsh functions.
y(t) m-0 âm~,m(t) ( ) (2) where ~(t) is the Walsh function;
~ is the order of the Walsh function;
m is the bit index;
M is the number of bits o the converter associated with the mth bit;
â is the weight of the mth bit after passing through the transfer . 15 function-~(x); and (t) is a term representins residual distortion.
It follows therefor~ that ~he coefficient âm is the integral of the product of the ~unction y(t) and the Q
order Walsh unction corres~onding.to -the m~h bit o~e~ time ~
am ~ ~ S~ y(t) ~Q m(t)dt = ~ r~ f{xtt)} ~Q m~t)dt By ~he Ergodic ~ypothesis which esta~lishes the equi~alence of time and statlstical averages, it can be shown ~hat the coef~icient âm is the expected value of the ~roduc~
of the function f(x) and the ~ order W~lsh fu~ction for the mth bit. ~his expected value is equ21 ~o ~he double integral over x and ~-of the product of W~ f(x), and the joinc amplitude densi~} fun~tian o~ ~ and ~ m~t) or âm = E {f(x) ~Q mtX)}
- 3 - r~ Q m(X)P~ ,m } d~Qd~ (4) where E{ ~ is ~he expected value of the product; and p{ } is the joint amplitude probability density function .
The joint amplitude proDability density function is a two-dimensional distribution that describes the probability t:hat the ~wo state Walsh func.ion ~Q m~x) is on or off for a given value of x. Inasmuch as the variable x(t) is substan- -tially uniformly distributed in amplitude according to the invention, ~hen permu~ing ~he order of the e~citation sequences does not change ~he probability tha~ a given bit ~ill be on or off for a given e~itation value.
It therefore follows that the dens.ity function p~x,`Y~, m) is equal to the joint density of a given value of ~c occurring when the binary order, or 2m order, Walsh func~
tion is on or off or P( ~ ~,m) p(x, ~2m) (5) or unifor~ly distri~uted x.
~ence from equation (4) a~ove, ~he coeficient âm is the expected value of the product o the 2mth order Walsh function and the function f(x) or ~m E{f(X)~2m(~)}
= ~ff(x)~ m(X)P~X~ ~2m) d~ (6a) = r~ r~2m(X)p(x~ ~2m d~ ~
By examination of ~he zctivity of each ~it o the excitation sequence it is possible to derive the densit~
u~ction p(x~ ~2~) and then integrate the density function ov~r all possible Yalues of x~
Table I shows ~he densi~y function p(x,~) for a ramp x=-l ~o +1 for a four-~it range, or the sum of four Walsh functions:
~137~6 TABLE: I
_ ~2 ~2~ 2 ~23 x ~ 1 +1 -1 f~
5*15/16 0 ~/16 ~ l/16 0 1/16 0 l/16 ~13/16 0 1/16 0 1/1~ 0 1/16 1/16 0 0 1~16 0 1/16 1/16 0 0 1/16 -~9Jl6 0 1/16. û l/16 1/16 o 1/16 0 ~7/16 ~ l/16 1/16 0 0 1/16 Q l/16 10t ~/~6 0 l/16 1~16 ~ O l/16 l/16 0 +3Jl6 0 l/16 1/16 0 1/16 0 0 1/16 ~l/16 0 1~16 1~1~ . 0 1/16 0 1/16 0 ~l/16 1/16 a ~ 1/16 0 1~16 0 ~/16 -3/16 1/16 a o 1~16 0 ~/16 1/16 155fl6 1/16 0 0 1/16 1/16 0 0 1/16 7/16 l/16 0 0 1/16 1/16 0 1/16 ~) -~16 l/16 0 }/16 0 0 l/16 ~ 1~16 '16 ~ o l/16 0 0 1/16 l/16 o -I3~16 1/16 0 1/16 0 1/16 0 0 1/15 20~15/1~ l/13 û 1/16 0 1/16 0 :Referring- tQ Table I, i~ integration ~f ~ is ar-rie~l ou~ in equatio~ 6(a) over ~he Y' dimension, then the eval~lation o:f~ equation t6a) simply becomes X.
âm 2X ~ ~) `Y m(x)dx (~b) The transIer unction f ¢x) of ~e ~haracteri ed ADC
3a 16 may }~e represented as a sum of Walsh ~unctions weighted by c:oefficients an ar , .
O
~8~7~
c~
n-O ~ ~
Substituting equation (7) and the solution to the density function into equation (6b) or integration over all values of x, the coefficient aM is determined to be the sum of ~he weighted integrated produc~s of two Walsh functions in x normalized by the span of x, or X
~m ~ 2X n~O an ~X ~n~x) ~2m(x)dX (~) Since the Walsh functions are orthogonal, the .product thereo~ is e~ual to unity whenever the order is e~ual, and is zero otherwise, i.e., r Y~ 2m(X)dX - 1 (9~
or n = 2m.
f ~D.(g) '~ m(X~ o ( ~ o 20 ~or n ;~ 2m.
It follows immediately from equa.ion (~) ~hat ~he estimated weight am is egual to the weighting coefficien~ a of the 2m~h order Walsh unction that describes ~he txansfer characteristic f~x) or â = a (11) m 2~
~ quation (11) implies that the nonlineaxity in the ~DC 16 appears as a time-independent bias in the estimate of am. Specifi~ally, the unbiased estimate of ~he m~h bit weight of the A~C 16 is th2 biased estimate of ~he weight due to all known and unk~ow~ factors i~troduced betwee~ the ~not~
l~pUt an~ t~ mea~ured ou~put at the i~put of the coefficient processor 18 and the scaled product of ~he reciprocal of the related weighti~g coe~fic7 ent ~m or ~8~
a _ m (12) m 2ma According to the invention, the bias correction terms 2ma2m o the ~DC 16 are kIlOWR values stored in the ADC
bias corrector 26 (Fig. 2). The output signals of the Walsh transormer 4, which are the coefficients âm f the Walsh transform of the output y(t) sign~ls are corrected by the bias correction terms 2~a2m according to the relationship in equ~tion (12) to produce the unbiased coefficients am~ For example, if a2m equals am, then the bit weight o the coeffi-cient am is simply 2m. The unbiased coefficients am specify the tran~ex characteristic of the DUT 1~. More particular~
ly, the unbiased weighting coefficients am appear in the x(t) functio~ of ~he DUT 14 as follows:
~--1 x(t) ~ ~0 am ~Q,m( (13) Because the ~ m(t) is ahsolutely ~nown (since it is the digital excitation function o the digi~al genexator 14), ~t) is k~own and the DUT 1~ is calibrated.
Many forms of digital excitation signals axe suit-able in the invention. A sigllal particularly well suited is 25 the set of individual binary signals which represents a linear amplitude ramp which may be repeated.
The invention has now been explained in respect of specific embodiments. Other embodiments will be apparent to those of~ ordinary s}~ll in this art~ It is ~erefore no~
30 intended that th~ inventioIl be limited except as indicated in the appended claims.
Claims (10)
1. A method for calibrating a digital-to-analog converter (DAC) characterized by the steps of:
exciting inputs of the DAC under test from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC under test and each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform amplitude probability, said DAC under test producing an analog output signal;
providing said analog output signal of the DAC
under test at an analog input of an analog-to-digital converter (ADC), the transfer function of said ADC having been characterized by premeasured weighting values of a set of binary orthogonal functions, said ADC producing digital output signals; transforming said digital output signals from time domain digital signals into binary tranform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test and correcting each said output response weighting coefficient for bias errors induced by said ADC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in a bias correction means in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the digital-to-analog converter under test.
exciting inputs of the DAC under test from an excitation means generating known digital excitation signals, each said excitation signal being applied at a single digital bit input of the DAC under test and each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform amplitude probability, said DAC under test producing an analog output signal;
providing said analog output signal of the DAC
under test at an analog input of an analog-to-digital converter (ADC), the transfer function of said ADC having been characterized by premeasured weighting values of a set of binary orthogonal functions, said ADC producing digital output signals; transforming said digital output signals from time domain digital signals into binary tranform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test and correcting each said output response weighting coefficient for bias errors induced by said ADC by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in a bias correction means in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the digital-to-analog converter under test.
2. The method according to Claim 1 characterized in that the excitation signals are Walsh function signals.
3. The method according to Claim 2 characterized in that the transforming step comprises transforming time domain digital signals into corresponding Walsh transform domain signals.
4. The method according to Claim 3 charatereized in that said digital excitation signals comprise together a digital representation of a linear amplitude ramp.
5. The method according to Claim 1 characterized in that the unbiased weighting coefficient of the Mth bit of a digital-to-analog converter under test is represented by:
where ?m is the output response weighting coefficient of the mth bit, and .alpha.2m is the premeasured weighting coefficinet of the 2mth order output of said analog-to-digital converter, and wherein said correcting step comprises multiplying each output response weighting coefficient by the corresponding premeasured weighting value 2m/.alpha.2m.
where ?m is the output response weighting coefficient of the mth bit, and .alpha.2m is the premeasured weighting coefficinet of the 2mth order output of said analog-to-digital converter, and wherein said correcting step comprises multiplying each output response weighting coefficient by the corresponding premeasured weighting value 2m/.alpha.2m.
6. An apparatus for calibrating a digital-to-analog converter (DAC) characterized by:
means for exciting inputs of the DAC under test from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform amplitude probability, said DAC under test producing an analog output signal at an analog output signal terminal;
an analog-to-digital converter (ADC) adapted to be coupled to said analog output signal terminal, the transfer function of said ADC having been characterized by premeasured weighting values of a set of binary orthogonal functions, said ADC being operative to produce digital output signals in response to said analog output signal;
means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and means for correcting each said output response weighting coefficient for bias errors induced by said ADC
by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the digital-to-analog converter under test.
means for exciting inputs of the DAC under test from an excitation means operative to generate known digital excitation signals at selected digital excitation signal outputs, each said excitation signal output being adapted to be coupled to a single digital bit input of the DAC under test each said excitation signal being binary and orthogonal with respect to all other ones of said excitation signals, the sum of said excitation signals consisting of a maximum entropy sequence of uniform amplitude probability, said DAC under test producing an analog output signal at an analog output signal terminal;
an analog-to-digital converter (ADC) adapted to be coupled to said analog output signal terminal, the transfer function of said ADC having been characterized by premeasured weighting values of a set of binary orthogonal functions, said ADC being operative to produce digital output signals in response to said analog output signal;
means for transforming said digital output signals from time domain digital signals into binary transform domain digital signals to obtain an output response weighting coefficient for each bit of the converter under test; and means for correcting each said output response weighting coefficient for bias errors induced by said ADC
by multiplying each output response weighting coefficient by the reciprocal of each corresponding said premeasured weighting values in order to obtain unbiased weighting values of each bit specifying the transfer characteristic of the digital-to-analog converter under test.
7. The apparatus according to Claim 6 characterized in that said exciting means is a Walsh function signal generator.
8. The apparatus according to Claim 7 characterized in that the transforming means comprises means for transforming time domain digital signals into corresponding Walsh transform domain signals.
9. The apparatus according to Claim 8 characterized in that said digital excitation signals comprise together a digital representation of a linear amplitude ramp.
10. The apparatus according to Claim 6 characterized in that said unbiased weighting coefficient of the mth bit of a digital-to-analog converter under test is represented by:
where ?m is the output response weighting coefficient of the mth bit; and .alpha. 2m is the premeasured weighting coefficient of the 2mth order output of said analog-to-digital converter, and wherein said correcting means is operative to multiply the output response weighting coefficient of the mth bit by the stored value 2m/.alpha. 2m for each mth bit in order to obtain the unbiased weighting coefficient of the mth bit which is the calibratiion of the DAC under test.
where ?m is the output response weighting coefficient of the mth bit; and .alpha. 2m is the premeasured weighting coefficient of the 2mth order output of said analog-to-digital converter, and wherein said correcting means is operative to multiply the output response weighting coefficient of the mth bit by the stored value 2m/.alpha. 2m for each mth bit in order to obtain the unbiased weighting coefficient of the mth bit which is the calibratiion of the DAC under test.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US264,928 | 1981-05-18 | ||
| US06/264,928 US4335373A (en) | 1980-11-07 | 1981-05-18 | Method for analyzing a digital-to-analog converter with a nonideal analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1187186A true CA1187186A (en) | 1985-05-14 |
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ID=23008228
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000403138A Expired CA1187186A (en) | 1981-05-18 | 1982-05-17 | Digital-to-analog converter with nonideal analog-to- digital converter |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4335373A (en) |
| EP (1) | EP0066504B1 (en) |
| JP (1) | JPS5820031A (en) |
| CA (1) | CA1187186A (en) |
| DE (1) | DE3274939D1 (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4591828A (en) * | 1981-05-07 | 1986-05-27 | Cambridge Consultants Limited | Digital-to-analog converter |
| DE3218066A1 (en) * | 1981-07-08 | 1983-01-27 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR TESTING ANALOG-DIGITAL CONVERTERS AND / OR DIGITAL-ANALOG CONVERTERS OR MESSAGE-TECHNICAL TRANSMISSION SECTIONS THAT CONTAIN SUCH CONVERTERS OR ARE IN SERIES WITH THEM, ESPECIALLY TO MAKE A CUTTER PROCEDURE |
| US4673917A (en) * | 1984-07-18 | 1987-06-16 | Fairchild Semiconductor Corporation | Method and apparatus for minimizing digital-to-analog converter correction trims |
| US4688198A (en) * | 1984-12-24 | 1987-08-18 | Schlumberger Technology Corporation | Entropy guided deconvolution of seismic signals |
| JPS621324A (en) * | 1985-06-27 | 1987-01-07 | Toshiba Corp | Evaluating method for linearity of digital-analog converter |
| US4758781A (en) * | 1985-12-06 | 1988-07-19 | Hitachi, Ltd. | DA converter testing system |
| US4813001A (en) * | 1987-05-29 | 1989-03-14 | Schlumberger Systems, Inc. | AC calibration method and device by determining transfer characteristics |
| US4839651A (en) * | 1987-07-24 | 1989-06-13 | Hewlett-Packard Company | Apparatus for measuring the dynamic characteristics of an analog-digital converter |
| JPH01101734A (en) * | 1987-10-15 | 1989-04-19 | Hitachi Ltd | Signal converting circuit |
| US4897650A (en) * | 1988-04-05 | 1990-01-30 | General Electric Company | Self-characterizing analog-to-digital converter |
| US5043931A (en) * | 1989-06-19 | 1991-08-27 | International Business Machines Corporation | Wrap test system and method |
| US5248970A (en) * | 1991-11-08 | 1993-09-28 | Crystal Semiconductor Corp. | Offset calibration of a dac using a calibrated adc |
| FR2746243B1 (en) * | 1996-03-15 | 1998-06-05 | METHOD FOR PROVIDING A REPRESENTATION OF AN OPTICAL SCENE BY WALSH-HADAMARD TRANSFORMATION AND IMAGE SENSOR USING THE SAME | |
| US5631649A (en) * | 1996-12-22 | 1997-05-20 | Mitsubishi Denki Kabushiki Kaisha | Digital-to-analog converter test method and apparatus |
| US8314725B2 (en) * | 2010-09-15 | 2012-11-20 | Intel Corporation | On-die digital-to-analog conversion testing |
| US10581447B1 (en) * | 2018-09-28 | 2020-03-03 | Apple Inc. | Method and apparatus for measuring phase response |
| WO2021110268A1 (en) | 2019-12-05 | 2021-06-10 | Telefonaktiebolaget Lm Ericsson (Publ) | Dac weight calibration |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US3816813A (en) * | 1972-01-24 | 1974-06-11 | Spacetac Inc | Automatic converter tester |
| US4061017A (en) * | 1975-11-17 | 1977-12-06 | Time/Data Corporation | Structural analysis system |
| JPS5447410A (en) * | 1977-09-21 | 1979-04-14 | Oki Electric Ind Co Ltd | Monitor system for pcm communication system |
| US4266292A (en) * | 1978-11-20 | 1981-05-05 | Wescom Switching, Inc. | Method and apparatus for testing analog-to-digital and digital-to-analog code converters |
-
1981
- 1981-05-18 US US06/264,928 patent/US4335373A/en not_active Expired - Lifetime
-
1982
- 1982-05-17 CA CA000403138A patent/CA1187186A/en not_active Expired
- 1982-05-18 JP JP57082525A patent/JPS5820031A/en active Granted
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| Publication number | Publication date |
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| DE3274939D1 (en) | 1987-02-05 |
| JPH0357655B2 (en) | 1991-09-02 |
| EP0066504A1 (en) | 1982-12-08 |
| US4335373A (en) | 1982-06-15 |
| EP0066504B1 (en) | 1986-12-30 |
| JPS5820031A (en) | 1983-02-05 |
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