CA1186072A - High voltage metal oxide semiconductor transistors - Google Patents
High voltage metal oxide semiconductor transistorsInfo
- Publication number
- CA1186072A CA1186072A CA000421886A CA421886A CA1186072A CA 1186072 A CA1186072 A CA 1186072A CA 000421886 A CA000421886 A CA 000421886A CA 421886 A CA421886 A CA 421886A CA 1186072 A CA1186072 A CA 1186072A
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- Prior art keywords
- oxide
- drain
- gate
- source
- region
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 230000004888 barrier function Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 230000015556 catabolic process Effects 0.000 abstract description 14
- 230000005684 electric field Effects 0.000 abstract description 7
- 108091006146 Channels Proteins 0.000 description 10
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 239000000969 carrier Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005315 distribution function Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTORS
Abstract of the Disclosure A high voltage metal-oxide-semiconductor (MOS) transistor has a source, a drain, a channel extending between the source and drain, an oxide layer overlying the channel, a gate electrode overlying the oxide, and a drift region surrounding the drain. Adjacent the source, the oxide layer is thin and adjacent the drain it is thick. Between the thin and thick oxide regions, at a location overlying part of the drift region, the oxide is of intermediate thickness. In operation the voltage applied to the drain is distributed along the length of the drift region and the high electric field which normally exists at the drain end of the thin gate oxide is reduced. The voltages applied to the gate, substrate and drain electrodes combine to deplete the drift region, first beneath the intermediate oxide and secondly as the drain voltage is further increased depletion occurs beneath the thick barrier oxide thereby distributing the drain voltage in a controlled manner. By grading the thickness of the oxide layer between the source and drain and by covering a portion of this oxide with a gate electrode, avalanche breakdown of the device can be avoided up to an operating voltage exceeding that of diffused junctions.
Indeed using the graded oxide thicknesses and optimizing other structural parameters, plane junction breakdown at the junction between the drift region and the substrate is attained instead of the surface aided curved junction breakdown usually obtained with high voltage MOS power transistors of this type.
- i -
Abstract of the Disclosure A high voltage metal-oxide-semiconductor (MOS) transistor has a source, a drain, a channel extending between the source and drain, an oxide layer overlying the channel, a gate electrode overlying the oxide, and a drift region surrounding the drain. Adjacent the source, the oxide layer is thin and adjacent the drain it is thick. Between the thin and thick oxide regions, at a location overlying part of the drift region, the oxide is of intermediate thickness. In operation the voltage applied to the drain is distributed along the length of the drift region and the high electric field which normally exists at the drain end of the thin gate oxide is reduced. The voltages applied to the gate, substrate and drain electrodes combine to deplete the drift region, first beneath the intermediate oxide and secondly as the drain voltage is further increased depletion occurs beneath the thick barrier oxide thereby distributing the drain voltage in a controlled manner. By grading the thickness of the oxide layer between the source and drain and by covering a portion of this oxide with a gate electrode, avalanche breakdown of the device can be avoided up to an operating voltage exceeding that of diffused junctions.
Indeed using the graded oxide thicknesses and optimizing other structural parameters, plane junction breakdown at the junction between the drift region and the substrate is attained instead of the surface aided curved junction breakdown usually obtained with high voltage MOS power transistors of this type.
- i -
Description
6~)7~
This invention relates to n-channel high voltage MOS
transistors~
~ ligh voltage MOS integrated circuits are becoming increasingly important as drivers in a variety of display application.
High voltage devices integrated along with low voltage logic circuits and combined with advances in display technology are finding applications in a diverse range of office and telecommunications terminal products.
In order to avoid device breakdown occurring owing to generation of a very high electric field within the device, the high voltage MOS devices are designed so that, in operation, high fields are not present at critical regions such as the silicon surface.
Devices in which surface field is minimized so as to redirect breakdown to a location within the bulk material are known. So-called reduced surface field tResurf) devices are characterized by an epitaxial layer which fulfils the requirement Nepj x depj ~ 10 2cm 2, where Nepj (in cm 3) and depj (in cm) are the doping concentration and the thickness of the epitaxial layer respectively~ With this particular doping concer,tration and layer thickness, the surface electric field is reduced and breakdown occurs across the plane of the junction (so-called bulk breakdown) rather than at the curved junction edges. It has been recognized that a Resurf layer can be used to advantage in high voltage devices. It has also been suggested that current carrying capabilities of such devices might be increased without lowering the breakdown voltage by suitabl~y shaping the Resurf layer.
r~, ~L~L&6~7Z
In a structure more conducive to standard NMOS transistor fabrication process, the Resurf epitaxial layer is replaced by an n~type diffusion to create a pn junction surrounding the drainO Such structures are disclosed for example in "Process and Device Design of a 1000 - Volt MOS IC", by T. Yamaguchi et al9 IEDM Technical Digest, page 255, 1981 and in "400 V MOS IC for EL Display"J by K. Fujii et al9 ISSC Technical Digest, page ~69 1981. DMOS devices utilizing a Resurf epitaxial layer have been made which show bulk rather than surface breakdown. "Lateral DMOS Power Transistor Design" by S. Colak et al, IEEE Electron Device Letters, page 51, 1980.
A known high voltage MOS transistor has a p-type silicon substrate9 n -type diffused regions forming the device source and drain and a more lightly doped n-type region, the so-called "drift" region, surrounding the drain. A layer of oxide overlies a channel region extending between the source and drain, the oxide layer in a gate region, where it overlies the p-type substrate next to the source being considerably thinner than a barrier oxide region which overlies the n-type drift region next to the drain, A polysilicon gate electrode overlaps the thin gate oxide and partially overlaps the barrier oxide nearest the source end. Finally, a field plate which is electrically connected to the source but is isolated from the gate electrode by an oxide layer9 overlaps the gate electrode and extends partially out onto the barrier oxide toward the drain region~ In operation it has been found that the field plate and gate electrode together work to reduce the electric field in the drift region near the point where the thin gate oxide and barrier oxide meet.
~.~L&6~'72 Although premature junction breakdown can be controlled using this structure, it requires optimization of at least two dielectric thicknesses and the extension toward the drain over drift region of both the gate electrode and field plate.
In order to improve operation of high voltage ~OS transistors of this type while maintaining compatibility with low voltage control circuits, there is proposed according to the present invention a lateral MOS device comprising a p-type substrate, an n -type source and an n -type drain, an n-type drift region surrounding the drain, an oxide layer overlying a fhannel region extending between the source and drain, the oxide layer having a thin gate region next to the source, a thick barrier region next to the drain, and a region of intermediate thickness between the gate and barrier oxide, and a gate electrode extending over part at least of the gate ~xide, the intermediate oxide and part at least of the barrier oxide.
The gate electrode functions to control conduction in the channel region and together with the graded thickness oxide layer perform field distribution functions which have hitherto required an additional field plate. For a particular choice of drift junction position, drift dopant level, drift length and the gate electrode extension over intermediate and barrier oxide, the gate electrode acts through oxide thicknesses to deplete the drift region in a controlled manner thereby mitigating the high electric field conditions which would cause surface avalanche junction breakdownu An embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:-1 1~i()72 Figure 1 is a longitudinal section through a high voltage MOStransistor according to the invention;
Figure 2 illustrates the depletion region conditions operating in a linear regime with a low drain-source voltage;
Figure 3 illustrates the depletion region conditions for drain-source voltage sufficient to cause the active channel to pinch-off;
Figure 4 illustrates the depletion region conditions for still higher drain-source voltage sufficient to deplete the drift region directly beneath the intermediate oxide;
Figure 5 illustrates the depletion region conditions existing for an increased drain-source voltage sufficient to deplete the drift region directly beneath the barrier oxide; and Figure 6 is a graphical illustration showing the variation of drain current with increasing drain-source voltage for a constant gate voltage sufficiently large to cause channel conduction.
Referring to the drawings in detail, Figure 1 shows a cross-section of an n-channel high voltage metal-oxide semiconductor (MOS) transistor, The device has a p-type silicon substrate 10 and an n-type drift region 12. A device well is formed between field oxide regions 14 which are underlain by p -type channel stop regions 16. The +
device has n -type diffused regions 18, 20 functioning as the transistor source and drain respectively. Overlying a channel region 22 extending between the source and drain is an oxide layer which is graded from a comparatively thin gate oxide region 24 next to the source 18 through an intermediate thickness oxide 26 over the centre of the channel 22 to a thick barrier oxide 28 next to the drain 20. A device gate 30 overlies the gate oxide 24, the intermediate oxide 26 and part at least of the barrier oxide 28. A deposited SiO2 layer 32 overlying the complete wafer has vias through it in order that aluminum contacts 34 can be made to the source, drain and gate. The gate contact i5 not shown in the Figures.
Referring to Figures 2 to 5 and the associated graphical representations of device characteristics (Figure 6) the operation of the device is shown for drain voltages extending from O to approximately 250 volts for a structure with a 10Q-cm substrate resistivity.
In the MOS transistor normal operating mode shown at zone A
in Figure 6, a drain voltage between O and 0.5 volts and a gate voltage of approximately 1 volt is applied. Minority carriers within the p-type substrate 10 are attracted towards the gate 30 and accummulate within a top layer of the substrate to form an n-type inversion layer or channel 22. Conduction along the channel occurs when a positive voltage is applied to the drain 20 with respect to the source 18. The drain current, Id, increases linearly with increase in Vd in this normal operating mode.
As the drain voltage is increased beyond a certain threshold, VpO, the surface of the p-type substrate 10 beneath the gate oxide 24 is depleted of carriers at the end nearest to the drain (Figure 3)0 The device is now said to be saturated and Id is no longer directly dependent on Vd. A pinched-off region 36 lengthens as Vd increases and the corresponding channel shortening phenomenon &~72 causes Id to increase with Vd, zone B, at a reduced rate compared to that of zone A. The pinched-off region continuously lengthens until Vd is at a voltage Vpl whereupon the drift region directly beneath intermediate oxide 26 is depleted of carriers and a secondary pinched-off region 42 exists (Figure 4~. At this point, the potential drop along this portion of the drift region remains fixed, stable and as shown in Figure 63 zone C, Id saturates. Referring to Figure 5 in order to prevent high electric fields from concentrating at the drain end of the intermediate oxide, higher drain-source voltage causes depletion of the drift region 44 directly beneath the gate-barrier oxideD
With the structural configuration shown the mechanism responsible for the depletion of free carriers in the drift region is the same for both intermediate and barrier oxide where it is covered by the gate. The combination of the n-type drift region, p-type substrate metallurgical junction, and the gate voltage acting through the graded oxide thicknesses with gate and substrate held at or near 0 volts as the drain voltage increases, tends to deplete the drift region at a controlled rate as shown in Figures 2 to 5 by depletion zone limits 38.
The rate at which depletion and therefore fixing of the potential drop within the device channel takes place is dependent on structural parameters such as drift region doping, depth, length and the length of intermediate and barrier oxide covered by the gate. Controlling the potenkial drop along the surface in the drift region as described maintains the electric field to less than that required to initiate avalanche breakdown. With the structural parameters suitably optimized, 0~2 breakdown eventually occurs, at a high voltage Vbr at the planar drift region-substrate junction beneath the drain, producing so-called plane junction breakdown of the type referred to earlier in the cliscussion of Resurf devices.
A specific example of high voltage NMOS transistor embodying the invention has the following characterizing quantitative features and has been driven by a voltage of 250 volts without showing avalanche breakdown.
Gate oxide thickness 0.1~m Intermediate oxide thickness 0.5~m Barrier oxide thickness l.O~m Drift region dopant level 2 x 1o15Qcm~3 Drift region depth 5.0~m Substrate resistivity 1OQ-C
Drift region length 24~m Overlap of gate electrode onto barrier oxide 4.0~m Fabrication of the transistor is accomplished by utilizing an industry standard semi-recessed oxide-isolated NMOS process technology.
The technology features a polysilicon gate with one level of metal interconnect. The only modifications to standard NMOS process are an ion implantation and drive-in sequence in an oxidizing ambient to form the drift region and the intermediate oxide layer. These steps are implemented at the beginning of the process in order to make the high voltage device compatible with, and to protect the integrity of~ low voltage MOS control circuits. Graduation of the oxides is achieved by standard successive oxidations performed to provide gate and barrier oxides.
~1~6a~7~
The embodiment described has a single gake electrode, a drift region with a graded dopant level and an oxide layer which has a thin gate region of uniform thickness, an intermediate region of uniform thickness and a thick barrier region of uniform thickness.
While still retaining a graded oxide thickness, all of the above features could be changed. Thus the gate electrode can be formed as several discrete vertically or horizontally arranged regions to which differing voltages can be applied. Also the dopant level and grading within the drift region can be varied to achieve similar operation. And lastly, the oxide layer can be grown with more than three steps or as a tapered layer.
This invention relates to n-channel high voltage MOS
transistors~
~ ligh voltage MOS integrated circuits are becoming increasingly important as drivers in a variety of display application.
High voltage devices integrated along with low voltage logic circuits and combined with advances in display technology are finding applications in a diverse range of office and telecommunications terminal products.
In order to avoid device breakdown occurring owing to generation of a very high electric field within the device, the high voltage MOS devices are designed so that, in operation, high fields are not present at critical regions such as the silicon surface.
Devices in which surface field is minimized so as to redirect breakdown to a location within the bulk material are known. So-called reduced surface field tResurf) devices are characterized by an epitaxial layer which fulfils the requirement Nepj x depj ~ 10 2cm 2, where Nepj (in cm 3) and depj (in cm) are the doping concentration and the thickness of the epitaxial layer respectively~ With this particular doping concer,tration and layer thickness, the surface electric field is reduced and breakdown occurs across the plane of the junction (so-called bulk breakdown) rather than at the curved junction edges. It has been recognized that a Resurf layer can be used to advantage in high voltage devices. It has also been suggested that current carrying capabilities of such devices might be increased without lowering the breakdown voltage by suitabl~y shaping the Resurf layer.
r~, ~L~L&6~7Z
In a structure more conducive to standard NMOS transistor fabrication process, the Resurf epitaxial layer is replaced by an n~type diffusion to create a pn junction surrounding the drainO Such structures are disclosed for example in "Process and Device Design of a 1000 - Volt MOS IC", by T. Yamaguchi et al9 IEDM Technical Digest, page 255, 1981 and in "400 V MOS IC for EL Display"J by K. Fujii et al9 ISSC Technical Digest, page ~69 1981. DMOS devices utilizing a Resurf epitaxial layer have been made which show bulk rather than surface breakdown. "Lateral DMOS Power Transistor Design" by S. Colak et al, IEEE Electron Device Letters, page 51, 1980.
A known high voltage MOS transistor has a p-type silicon substrate9 n -type diffused regions forming the device source and drain and a more lightly doped n-type region, the so-called "drift" region, surrounding the drain. A layer of oxide overlies a channel region extending between the source and drain, the oxide layer in a gate region, where it overlies the p-type substrate next to the source being considerably thinner than a barrier oxide region which overlies the n-type drift region next to the drain, A polysilicon gate electrode overlaps the thin gate oxide and partially overlaps the barrier oxide nearest the source end. Finally, a field plate which is electrically connected to the source but is isolated from the gate electrode by an oxide layer9 overlaps the gate electrode and extends partially out onto the barrier oxide toward the drain region~ In operation it has been found that the field plate and gate electrode together work to reduce the electric field in the drift region near the point where the thin gate oxide and barrier oxide meet.
~.~L&6~'72 Although premature junction breakdown can be controlled using this structure, it requires optimization of at least two dielectric thicknesses and the extension toward the drain over drift region of both the gate electrode and field plate.
In order to improve operation of high voltage ~OS transistors of this type while maintaining compatibility with low voltage control circuits, there is proposed according to the present invention a lateral MOS device comprising a p-type substrate, an n -type source and an n -type drain, an n-type drift region surrounding the drain, an oxide layer overlying a fhannel region extending between the source and drain, the oxide layer having a thin gate region next to the source, a thick barrier region next to the drain, and a region of intermediate thickness between the gate and barrier oxide, and a gate electrode extending over part at least of the gate ~xide, the intermediate oxide and part at least of the barrier oxide.
The gate electrode functions to control conduction in the channel region and together with the graded thickness oxide layer perform field distribution functions which have hitherto required an additional field plate. For a particular choice of drift junction position, drift dopant level, drift length and the gate electrode extension over intermediate and barrier oxide, the gate electrode acts through oxide thicknesses to deplete the drift region in a controlled manner thereby mitigating the high electric field conditions which would cause surface avalanche junction breakdownu An embodiment of the invention will now be described by way of example with reference to the accompanying drawings in which:-1 1~i()72 Figure 1 is a longitudinal section through a high voltage MOStransistor according to the invention;
Figure 2 illustrates the depletion region conditions operating in a linear regime with a low drain-source voltage;
Figure 3 illustrates the depletion region conditions for drain-source voltage sufficient to cause the active channel to pinch-off;
Figure 4 illustrates the depletion region conditions for still higher drain-source voltage sufficient to deplete the drift region directly beneath the intermediate oxide;
Figure 5 illustrates the depletion region conditions existing for an increased drain-source voltage sufficient to deplete the drift region directly beneath the barrier oxide; and Figure 6 is a graphical illustration showing the variation of drain current with increasing drain-source voltage for a constant gate voltage sufficiently large to cause channel conduction.
Referring to the drawings in detail, Figure 1 shows a cross-section of an n-channel high voltage metal-oxide semiconductor (MOS) transistor, The device has a p-type silicon substrate 10 and an n-type drift region 12. A device well is formed between field oxide regions 14 which are underlain by p -type channel stop regions 16. The +
device has n -type diffused regions 18, 20 functioning as the transistor source and drain respectively. Overlying a channel region 22 extending between the source and drain is an oxide layer which is graded from a comparatively thin gate oxide region 24 next to the source 18 through an intermediate thickness oxide 26 over the centre of the channel 22 to a thick barrier oxide 28 next to the drain 20. A device gate 30 overlies the gate oxide 24, the intermediate oxide 26 and part at least of the barrier oxide 28. A deposited SiO2 layer 32 overlying the complete wafer has vias through it in order that aluminum contacts 34 can be made to the source, drain and gate. The gate contact i5 not shown in the Figures.
Referring to Figures 2 to 5 and the associated graphical representations of device characteristics (Figure 6) the operation of the device is shown for drain voltages extending from O to approximately 250 volts for a structure with a 10Q-cm substrate resistivity.
In the MOS transistor normal operating mode shown at zone A
in Figure 6, a drain voltage between O and 0.5 volts and a gate voltage of approximately 1 volt is applied. Minority carriers within the p-type substrate 10 are attracted towards the gate 30 and accummulate within a top layer of the substrate to form an n-type inversion layer or channel 22. Conduction along the channel occurs when a positive voltage is applied to the drain 20 with respect to the source 18. The drain current, Id, increases linearly with increase in Vd in this normal operating mode.
As the drain voltage is increased beyond a certain threshold, VpO, the surface of the p-type substrate 10 beneath the gate oxide 24 is depleted of carriers at the end nearest to the drain (Figure 3)0 The device is now said to be saturated and Id is no longer directly dependent on Vd. A pinched-off region 36 lengthens as Vd increases and the corresponding channel shortening phenomenon &~72 causes Id to increase with Vd, zone B, at a reduced rate compared to that of zone A. The pinched-off region continuously lengthens until Vd is at a voltage Vpl whereupon the drift region directly beneath intermediate oxide 26 is depleted of carriers and a secondary pinched-off region 42 exists (Figure 4~. At this point, the potential drop along this portion of the drift region remains fixed, stable and as shown in Figure 63 zone C, Id saturates. Referring to Figure 5 in order to prevent high electric fields from concentrating at the drain end of the intermediate oxide, higher drain-source voltage causes depletion of the drift region 44 directly beneath the gate-barrier oxideD
With the structural configuration shown the mechanism responsible for the depletion of free carriers in the drift region is the same for both intermediate and barrier oxide where it is covered by the gate. The combination of the n-type drift region, p-type substrate metallurgical junction, and the gate voltage acting through the graded oxide thicknesses with gate and substrate held at or near 0 volts as the drain voltage increases, tends to deplete the drift region at a controlled rate as shown in Figures 2 to 5 by depletion zone limits 38.
The rate at which depletion and therefore fixing of the potential drop within the device channel takes place is dependent on structural parameters such as drift region doping, depth, length and the length of intermediate and barrier oxide covered by the gate. Controlling the potenkial drop along the surface in the drift region as described maintains the electric field to less than that required to initiate avalanche breakdown. With the structural parameters suitably optimized, 0~2 breakdown eventually occurs, at a high voltage Vbr at the planar drift region-substrate junction beneath the drain, producing so-called plane junction breakdown of the type referred to earlier in the cliscussion of Resurf devices.
A specific example of high voltage NMOS transistor embodying the invention has the following characterizing quantitative features and has been driven by a voltage of 250 volts without showing avalanche breakdown.
Gate oxide thickness 0.1~m Intermediate oxide thickness 0.5~m Barrier oxide thickness l.O~m Drift region dopant level 2 x 1o15Qcm~3 Drift region depth 5.0~m Substrate resistivity 1OQ-C
Drift region length 24~m Overlap of gate electrode onto barrier oxide 4.0~m Fabrication of the transistor is accomplished by utilizing an industry standard semi-recessed oxide-isolated NMOS process technology.
The technology features a polysilicon gate with one level of metal interconnect. The only modifications to standard NMOS process are an ion implantation and drive-in sequence in an oxidizing ambient to form the drift region and the intermediate oxide layer. These steps are implemented at the beginning of the process in order to make the high voltage device compatible with, and to protect the integrity of~ low voltage MOS control circuits. Graduation of the oxides is achieved by standard successive oxidations performed to provide gate and barrier oxides.
~1~6a~7~
The embodiment described has a single gake electrode, a drift region with a graded dopant level and an oxide layer which has a thin gate region of uniform thickness, an intermediate region of uniform thickness and a thick barrier region of uniform thickness.
While still retaining a graded oxide thickness, all of the above features could be changed. Thus the gate electrode can be formed as several discrete vertically or horizontally arranged regions to which differing voltages can be applied. Also the dopant level and grading within the drift region can be varied to achieve similar operation. And lastly, the oxide layer can be grown with more than three steps or as a tapered layer.
Claims (5)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A high voltage metal-oxide-semiconductor transistor comprising a p-type substrate, an n+-type source and an n+-type drain, an n-type drift region surrounding the drain, an oxide layer overlying a channel region extending between the source and drain, the oxide layer having a thin gate region next to the source, a thick barrier region next to the drain and a region of intermediate thickness between the gate and barrier oxide, and a gate extending over part at least of the gate oxide, the intermediate oxide, and part at least of the barrier oxide.
2. A high voltage MOS transistor as claimed in claim 1 in which each of the three regions of the oxide layer is of uniform thickness.
3. A high voltage MOS transistor as claimed in claim 1 in which the thin gate oxide is about 0.1µm thick, the intermediate oxide is about 0.5µm thick and the barrier oxide region is about 1.0µm thick.
4. A high voltage MOS transistor as claimed in claim 1 in which the drift region doping is in the range 1 to 5 x 1015cm-3, the drift region depth is in the range 3 to 8µm and the substrate resistivity is in the range 5 to 50.OMEGA.-cm.
5. A high voltage metal-oxide-semiconductor transistor comprising a substrate of one conductivity type, a heavily doped source and drain of opposite conductivity type and a drift region surrounding the drain of opposite conductivity type, an oxide layer overlying a channel region extending between the source and drain, the oxide layer having a thin gate region next to the source, a thick barrier region next to the drain and a region of intermediate thickness between the gate and barrier oxide, and a gate extending over part at least of the gate oxide, the intermediate oxide, and part at least of the barrier oxide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000421886A CA1186072A (en) | 1983-02-17 | 1983-02-17 | High voltage metal oxide semiconductor transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000421886A CA1186072A (en) | 1983-02-17 | 1983-02-17 | High voltage metal oxide semiconductor transistors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1186072A true CA1186072A (en) | 1985-04-23 |
Family
ID=4124588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000421886A Expired CA1186072A (en) | 1983-02-17 | 1983-02-17 | High voltage metal oxide semiconductor transistors |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1186072A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0487022A2 (en) * | 1990-11-23 | 1992-05-27 | Texas Instruments Incorporated | A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor |
| EP0504992A2 (en) * | 1991-03-22 | 1992-09-23 | Philips Electronics Uk Limited | A lateral insulated gate field effect semiconductor device |
| EP2131399A3 (en) * | 2008-05-23 | 2009-12-30 | NEC Electronics Corporation | Insulated gate semiconductor device and method of manufacturing the same |
-
1983
- 1983-02-17 CA CA000421886A patent/CA1186072A/en not_active Expired
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0487022A2 (en) * | 1990-11-23 | 1992-05-27 | Texas Instruments Incorporated | A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor |
| US5275961A (en) * | 1990-11-23 | 1994-01-04 | Texas Instruments Incorporated | Method of forming insulated gate field-effect transistors |
| EP0487022B1 (en) * | 1990-11-23 | 1997-04-23 | Texas Instruments Incorporated | A method of simultaneously fabricating an insulated gate-field-effect transistor and a bipolar transistor |
| EP0504992A2 (en) * | 1991-03-22 | 1992-09-23 | Philips Electronics Uk Limited | A lateral insulated gate field effect semiconductor device |
| EP0504992A3 (en) * | 1991-03-22 | 1993-06-16 | Philips Electronics Uk Limited | A lateral insulated gate field effect semiconductor device |
| EP2131399A3 (en) * | 2008-05-23 | 2009-12-30 | NEC Electronics Corporation | Insulated gate semiconductor device and method of manufacturing the same |
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