CA1178370A - High performance bubble chip architecture - Google Patents
High performance bubble chip architectureInfo
- Publication number
- CA1178370A CA1178370A CA000399144A CA399144A CA1178370A CA 1178370 A CA1178370 A CA 1178370A CA 000399144 A CA000399144 A CA 000399144A CA 399144 A CA399144 A CA 399144A CA 1178370 A CA1178370 A CA 1178370A
- Authority
- CA
- Canada
- Prior art keywords
- replicator
- mode switch
- path
- decision
- write channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0858—Generating, replicating or annihilating magnetic domains (also comprising different types of magnetic domains, e.g. "Hard Bubbles")
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/02—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
- G11C19/08—Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using thin films in plane structure
- G11C19/0866—Detecting magnetic domains
Abstract
HIGH PERFORMANCE BUBBLE CHIP ARCHITECTURE
Abstract of the Disclosure A major/minor loop bubble memory system architecture includes a passive replicator in the major loop read chan-nel which is connected by a first path to a mode switch-annihilator and a merge point in the major loop write channel and by a second path to an off-chip decision-making means and the merge point in the write channel. The decision-making means is positioned the same or fewer propa-gation steps than the mode switch-annihilator is from the replicator. The decision making means is activated to cause either the replicated data to pass through the mode switch-annihilator into the write channel or the replicated data to be annihilated in the mode switch-annihilator and the data from a generator to pass into the write channel.
Abstract of the Disclosure A major/minor loop bubble memory system architecture includes a passive replicator in the major loop read chan-nel which is connected by a first path to a mode switch-annihilator and a merge point in the major loop write channel and by a second path to an off-chip decision-making means and the merge point in the write channel. The decision-making means is positioned the same or fewer propa-gation steps than the mode switch-annihilator is from the replicator. The decision making means is activated to cause either the replicated data to pass through the mode switch-annihilator into the write channel or the replicated data to be annihilated in the mode switch-annihilator and the data from a generator to pass into the write channel.
Description
, 3 '7 ~
HIGH PERFORMANCE BUBBLE C~IP ARCHITECTURE
DESCRIPTION
Technical Field This invention relates to a major/minor loop bubble memory chip architecture and more paxticularly to an architecture that provides improved data writing and storage capability.
Background Art = _ Several different major/minor loops memory organi-~ations or architectures are described in U. S. Patent Nos. 3,618,054; 3,838,407 and 3,999,172. Typically, both the major loop and the minor loop are established by an arrangement of chevron or C-bar permalloy type circuits on a film of a magnetic garnet material. The bubble domains or bubbles are moved around the loop by a magnetic field which rotates in the plane of the magnetic material. The major loop is generally elongated such as to allow a number of minor loops to be aligned along the side. The major loop may be closèd as shown in U.S. Patent 3,618,054. With a closed major loop, two~way transfer gates permit the trans-fer of bubbles from the minor loops to the major loop and from the major loop to the minor loops.
Major loops may also be of the open type disclosed in U.S. Patent Nos. 3,838,407 and 3,999,172 as is shown in Fig.
1. With the open type of major loop, one-way transfer gates from the write channel 10 of the major loop transfer bubbles into one side 12 of the minor loops and another transfer gate permits bubbles to be ~ransferred out of the other end 14 of the minor loops into the read channel 16 of the major loop. Data information stored in the minor loop is circu-lated until the desired block of data consisting of on~ bit from each loop reaches the transfer points. On command of a ~ ~783'70 read transfer signal from the decision-making means or control center 18, the information is trans~erred to the read channel of the major loop whereupon it is read by a detector 20. The detected information, or alternatively new information is used to control the generation of bubbles at generator 22 which are subsequently propagated along the write channel of the major loop to the write transfer switches. On command of a write transfer signal from con-trol center 18, the information is transferred from the write channel l0 into the minor loops l2. This organi~ation has the following disadvantages. Any arbitrarily referenced bit or byte cannot be positioned at the detector for future reading without using the off chip signal path or without losing information that precedes the bit or byte. Upon reading a stream of information that ends on an arbitrary bit or byte, the information that follows must either be passed through the off chip signal pakh or lost. Another disadvantage is that the use of the off chip signal path prior to and after a stream of information degrades the performance, i.e. throughput, of a multimodule bubble store.
A further disadvantage is that the information that is read from the chip, passed through the signal path and then returned to the chip is exposed to data loss when it is in the signal pathO
Another open major loop type architecture was described by Bonyhard in 1978 at the Indian Wells 3M Annual Meeting and is shown in Figure 2. This organization has a repli-cator/annihilator 24 with one path going to the detector 20.
Another path 26 goes from the replicator 24 to the generator/
merge point 22 that is in the write channel l0. In this organization, a merge point 28 connects the read channel 16 and the write channel l0. With the system shown in Figure
HIGH PERFORMANCE BUBBLE C~IP ARCHITECTURE
DESCRIPTION
Technical Field This invention relates to a major/minor loop bubble memory chip architecture and more paxticularly to an architecture that provides improved data writing and storage capability.
Background Art = _ Several different major/minor loops memory organi-~ations or architectures are described in U. S. Patent Nos. 3,618,054; 3,838,407 and 3,999,172. Typically, both the major loop and the minor loop are established by an arrangement of chevron or C-bar permalloy type circuits on a film of a magnetic garnet material. The bubble domains or bubbles are moved around the loop by a magnetic field which rotates in the plane of the magnetic material. The major loop is generally elongated such as to allow a number of minor loops to be aligned along the side. The major loop may be closèd as shown in U.S. Patent 3,618,054. With a closed major loop, two~way transfer gates permit the trans-fer of bubbles from the minor loops to the major loop and from the major loop to the minor loops.
Major loops may also be of the open type disclosed in U.S. Patent Nos. 3,838,407 and 3,999,172 as is shown in Fig.
1. With the open type of major loop, one-way transfer gates from the write channel 10 of the major loop transfer bubbles into one side 12 of the minor loops and another transfer gate permits bubbles to be ~ransferred out of the other end 14 of the minor loops into the read channel 16 of the major loop. Data information stored in the minor loop is circu-lated until the desired block of data consisting of on~ bit from each loop reaches the transfer points. On command of a ~ ~783'70 read transfer signal from the decision-making means or control center 18, the information is trans~erred to the read channel of the major loop whereupon it is read by a detector 20. The detected information, or alternatively new information is used to control the generation of bubbles at generator 22 which are subsequently propagated along the write channel of the major loop to the write transfer switches. On command of a write transfer signal from con-trol center 18, the information is transferred from the write channel l0 into the minor loops l2. This organi~ation has the following disadvantages. Any arbitrarily referenced bit or byte cannot be positioned at the detector for future reading without using the off chip signal path or without losing information that precedes the bit or byte. Upon reading a stream of information that ends on an arbitrary bit or byte, the information that follows must either be passed through the off chip signal pakh or lost. Another disadvantage is that the use of the off chip signal path prior to and after a stream of information degrades the performance, i.e. throughput, of a multimodule bubble store.
A further disadvantage is that the information that is read from the chip, passed through the signal path and then returned to the chip is exposed to data loss when it is in the signal pathO
Another open major loop type architecture was described by Bonyhard in 1978 at the Indian Wells 3M Annual Meeting and is shown in Figure 2. This organization has a repli-cator/annihilator 24 with one path going to the detector 20.
Another path 26 goes from the replicator 24 to the generator/
merge point 22 that is in the write channel l0. In this organization, a merge point 28 connects the read channel 16 and the write channel l0. With the system shown in Figure
2, one needs to make a decision before he reads the data whether the data is to be annihilated at the replicator or not. Hence, this has the disadvantages of lack of flex-ibility. One cannot read information from the bubble chip SA9 80 04~
\
1 ~83'~0 and then on the basis of this information make a decision to restore it unchanged, change it or replace it on the chip.
In addition, one cannot read information from the bubble chip and then on the basis of this information make a decision to change or leave unchanged the bits or bytes that immediately follow the information read.
Summary of the Invention A major/minor loop bub~le memory system architectuxe includes a passive replicator in the major loop read channel which is connected by a first path to a mode switch-annihilator and a merge point in the write loop and by a second path to an off chip decision-making means and the merge point in the major loop write channel. The decision-making means is positioned the same or fewer propagation steps than the mode switch-annihilator is from the replicator. The decision-making means is activated to cause either the replicated data to pass through the mode switch-annihilator into the write channel or the replicated data to be annihilated in the mode switch-annihilator and the data from a generator to pass into the write channel.
This architecture allows a number of functions to be per-formed. One function is that any bit or byte can be posi-tioned within the module to the detector for future reading or writing without the use of an off chip data path and without the loss of data stored on the chip. Another func-tion is that this system permits the reading of a varia~le length group of bits from the chip before a decision is made to write or leave unchanged the bits that follow or the bits that already have been read. A third function is that following a read or a write of a variable length of bits, the propagation of these and any adjacent bits from the read channel and replicate path into the write channel and minor loops can be done without the use of an off chip path.
l 1~8~"70 For a further understanding of the invention, and of the advantages thereof, reference will be had to the follow-ing description and accompanying drawings, and to the ap-; pended claims, in which the various novel features o~ the invention are more particularly set forth.
Brief Des_ription of the Drawings FIGURE 1 and FIGURE 2 are schematic views of prior artmajor/minor loop bubble memory system architectures;
FIGURE 3 is a schematic view of one embodiment of the major/minor loop bubble memory system in accordance T~ith this invention; and FIGURE 4 is a schematic view of a second embodiment of the major/minor loop bubble memory system in accordance with this invention.
Descrlption of the Preferred Embodiment As shown in Figure 3, a major/minor loop bubble memory system architecture in accordance with this inven-tion has a write channel 30 positioned on one side of minor loops 32 with read channel 33 positioned on the other side.
The bubble domains in read channel 33 go to replicator 34.
From replicator 34, there are two paths for bubbles. The first path 36 goes to the detector 37 where the presence or absence of a bubble is detected~ The information from the detector 37 is communicated electrically along path 36 off the chip to decision-making means or control center means 38. The information may be altered, replaced or removed in the control center 38. The path 36 then continues to the bubble generator 40 which is on the bubble chip.
The bubbles replicated by bubble replicator 34 proceed along a second path 42 to a mode switch/annihilator ~4.
The decision-making means 38 is activated to cause the i 1783'70 replicated bubbles either to pass through the mode switch-annihilator 44 and continue along path 42 to the generator/
merge point 40 and into write channel 30, or the replicated bubbles to be annihilated in the mode switch-annihilator 44 and the bubbles generated by the generator 40 pass into the write channel 30.
The bubble memory architecture shown in Figure 3 allows the following functions to be performed. (a) Any bit or byte can be positioned within the bubble module to the detector for future reading or writing without the use of an off chip data path and without the loss of data stored on the chip. (b) The reading of a variable length group of bits from the chip before a decision is made to write or leave unchanged the bits that follow or the bits that have already been read is possible with this system. (c) Fol-lowing a read or a write of a variable length of bits, the propagation of these and any adjacent bits from the read channel and replicate path into the write channel and minor loops without the use of an off chip path is feasible.
Another embodiment is shown in Figure 4. In this embodiment the generator 52 is positioned at a point other than the merge point 56 in write channel 30. In addition there is a mode switch/annihilator 54 positioned between the generator 52 and the merge point 56 to provide for a proper control of bubbles passing beyond merge point 56.
This embodiment is particularly useful in multi-module bubble systems since it provides flexibility and permits multiplexing.
While I have illustrated and described a preferred embodiment of my invention, it is understood that I do not limit myself to the precise descriptions herein and the right is reserved to allow changes and modifications coming within the scope of the invention as defined in the appended claims.
I claim:
\
1 ~83'~0 and then on the basis of this information make a decision to restore it unchanged, change it or replace it on the chip.
In addition, one cannot read information from the bubble chip and then on the basis of this information make a decision to change or leave unchanged the bits or bytes that immediately follow the information read.
Summary of the Invention A major/minor loop bub~le memory system architectuxe includes a passive replicator in the major loop read channel which is connected by a first path to a mode switch-annihilator and a merge point in the write loop and by a second path to an off chip decision-making means and the merge point in the major loop write channel. The decision-making means is positioned the same or fewer propagation steps than the mode switch-annihilator is from the replicator. The decision-making means is activated to cause either the replicated data to pass through the mode switch-annihilator into the write channel or the replicated data to be annihilated in the mode switch-annihilator and the data from a generator to pass into the write channel.
This architecture allows a number of functions to be per-formed. One function is that any bit or byte can be posi-tioned within the module to the detector for future reading or writing without the use of an off chip data path and without the loss of data stored on the chip. Another func-tion is that this system permits the reading of a varia~le length group of bits from the chip before a decision is made to write or leave unchanged the bits that follow or the bits that already have been read. A third function is that following a read or a write of a variable length of bits, the propagation of these and any adjacent bits from the read channel and replicate path into the write channel and minor loops can be done without the use of an off chip path.
l 1~8~"70 For a further understanding of the invention, and of the advantages thereof, reference will be had to the follow-ing description and accompanying drawings, and to the ap-; pended claims, in which the various novel features o~ the invention are more particularly set forth.
Brief Des_ription of the Drawings FIGURE 1 and FIGURE 2 are schematic views of prior artmajor/minor loop bubble memory system architectures;
FIGURE 3 is a schematic view of one embodiment of the major/minor loop bubble memory system in accordance T~ith this invention; and FIGURE 4 is a schematic view of a second embodiment of the major/minor loop bubble memory system in accordance with this invention.
Descrlption of the Preferred Embodiment As shown in Figure 3, a major/minor loop bubble memory system architecture in accordance with this inven-tion has a write channel 30 positioned on one side of minor loops 32 with read channel 33 positioned on the other side.
The bubble domains in read channel 33 go to replicator 34.
From replicator 34, there are two paths for bubbles. The first path 36 goes to the detector 37 where the presence or absence of a bubble is detected~ The information from the detector 37 is communicated electrically along path 36 off the chip to decision-making means or control center means 38. The information may be altered, replaced or removed in the control center 38. The path 36 then continues to the bubble generator 40 which is on the bubble chip.
The bubbles replicated by bubble replicator 34 proceed along a second path 42 to a mode switch/annihilator ~4.
The decision-making means 38 is activated to cause the i 1783'70 replicated bubbles either to pass through the mode switch-annihilator 44 and continue along path 42 to the generator/
merge point 40 and into write channel 30, or the replicated bubbles to be annihilated in the mode switch-annihilator 44 and the bubbles generated by the generator 40 pass into the write channel 30.
The bubble memory architecture shown in Figure 3 allows the following functions to be performed. (a) Any bit or byte can be positioned within the bubble module to the detector for future reading or writing without the use of an off chip data path and without the loss of data stored on the chip. (b) The reading of a variable length group of bits from the chip before a decision is made to write or leave unchanged the bits that follow or the bits that have already been read is possible with this system. (c) Fol-lowing a read or a write of a variable length of bits, the propagation of these and any adjacent bits from the read channel and replicate path into the write channel and minor loops without the use of an off chip path is feasible.
Another embodiment is shown in Figure 4. In this embodiment the generator 52 is positioned at a point other than the merge point 56 in write channel 30. In addition there is a mode switch/annihilator 54 positioned between the generator 52 and the merge point 56 to provide for a proper control of bubbles passing beyond merge point 56.
This embodiment is particularly useful in multi-module bubble systems since it provides flexibility and permits multiplexing.
While I have illustrated and described a preferred embodiment of my invention, it is understood that I do not limit myself to the precise descriptions herein and the right is reserved to allow changes and modifications coming within the scope of the invention as defined in the appended claims.
I claim:
Claims (6)
1. A major/minor loop bubble memory system comprising:
a bubble chip having a major loop write channel with a merge point positioned therein and a major loop read channel with a detector positioned therein, A signal path off said chip from said detector to said merge point, a replicator positioned in said read channel, said replicator having first and second output paths with an equal number of propagation steps, said first path going to said merge point, said second path passing to said detector and then to said signal path and then to said merge point in said write channel, a mode switch-annihilator means positioned in said first path, and decision-making means positioned in said signal path, said decision making means spaced from said replicator by up to and including the same number of propagation steps as said mode switch is spaced from said replicator wherein said decision-making means is activated to cause the replicated data to pass through the mode switch means into said write channel or to be annihilated in the mode switch means.
a bubble chip having a major loop write channel with a merge point positioned therein and a major loop read channel with a detector positioned therein, A signal path off said chip from said detector to said merge point, a replicator positioned in said read channel, said replicator having first and second output paths with an equal number of propagation steps, said first path going to said merge point, said second path passing to said detector and then to said signal path and then to said merge point in said write channel, a mode switch-annihilator means positioned in said first path, and decision-making means positioned in said signal path, said decision making means spaced from said replicator by up to and including the same number of propagation steps as said mode switch is spaced from said replicator wherein said decision-making means is activated to cause the replicated data to pass through the mode switch means into said write channel or to be annihilated in the mode switch means.
2. A system as described in claim 1 wherein said decision-making means is spaced from said replicator by the same number of propagation steps as said mode switch is spaced from the replicator.
3. A system as described in claim 1 wherein said decision-making means is spaced from said replicator by a fewer number of propagation steps as said mode switch is spaced from the replicator.
4. A major/minor loop bubble memory system comprising a bubble chip having a major loop write channel with a generator and a merge point positioned therein and a major loop read channel with a detector positioned therein, a signal path off said chip from said detector to said generator, a replicator positioned in said read channel, said replicator having first and second output paths with an equal number of propagation steps, said first path going to said merge point, said second path passing to said detector and then to said signal path and then from said generator in said write channel to said merge point, a mode switch-annihilator means positioned in said first path, and decision-making means positioned in said signal path, said decision making means spaced from said replicator by up to the same number of propagation steps as said mode switch is spaced from said replicator wherein said decision-making means is activated to cause the replicated data to pass through the mode switch means into said write channel or to be annihilated in the mode switch means so that data from said generator passes into said write channel.
5. A system as described in claim 4 including a second mode-switch annihilator means positioned in said first path.
6. A major/minor loop bubble memory system having a replicator in the major loop read channel connected to a first path leading to a detector and a decision-making means and a merge point in the major loop write channel, said replicator connected to a second path leading to the merge point on the write channel, the improvement characterized by a mode switch-annihilator means positioned in said second path, said decision making means spaced from said replicator by up to the same number of propagation steps as said mode switch is spaced from said replicator wherein said decision making means is activated to cause the replicated data to pass through the mode switch means into said write channel or to be annihilated in the mode switch means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US280,024 | 1981-06-30 | ||
| US06/280,024 US4386417A (en) | 1981-06-30 | 1981-06-30 | High performance bubble chip architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1178370A true CA1178370A (en) | 1984-11-20 |
Family
ID=23071308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000399144A Expired CA1178370A (en) | 1981-06-30 | 1982-03-23 | High performance bubble chip architecture |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4386417A (en) |
| EP (1) | EP0068129B1 (en) |
| JP (1) | JPS5858753B2 (en) |
| CA (1) | CA1178370A (en) |
| DE (1) | DE3278258D1 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
| US7178004B2 (en) | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
| US7123532B2 (en) | 2003-09-16 | 2006-10-17 | Saifun Semiconductors Ltd. | Operating array cells with matched reference cells |
| US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
| JP4479788B2 (en) | 2007-12-20 | 2010-06-09 | 株式会社デンソー | Coil forming method and coil forming die |
| US10311464B2 (en) | 2014-07-17 | 2019-06-04 | The Nielsen Company (Us), Llc | Methods and apparatus to determine impressions corresponding to market segments |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3618054A (en) * | 1969-11-10 | 1971-11-02 | Bell Telephone Labor Inc | Magnetic domain storage organization |
| US3781833A (en) * | 1972-08-29 | 1973-12-25 | Bell Telephone Labor Inc | Single wall magnetic domain generator |
| US3838407A (en) * | 1973-12-28 | 1974-09-24 | Texas Instruments Inc | Bubble memory organization with two port major/minor loop transfer |
| US3999172A (en) * | 1974-11-29 | 1976-12-21 | Texas Instruments Incorporated | Magnetic domain memory |
| US4081861A (en) * | 1975-02-10 | 1978-03-28 | Texas Instruments Incorporated | Matrixed magnetic bubble memories |
| JPS51118341A (en) * | 1975-04-11 | 1976-10-18 | Hitachi Ltd | Shift register type memory |
| US4090251A (en) * | 1977-06-09 | 1978-05-16 | Texas Instruments Incorporated | Bubble memory redundancy storage |
| US4225944A (en) * | 1978-05-01 | 1980-09-30 | Burroughs Corporation | Bubble memory chip organization-folded loop type |
| US4238836A (en) * | 1979-03-07 | 1980-12-09 | Bell Telephone Laboratories, Incorporated | Fail safe magnetic bubble memory |
-
1981
- 1981-06-30 US US06/280,024 patent/US4386417A/en not_active Expired - Lifetime
-
1982
- 1982-03-19 JP JP57043066A patent/JPS5858753B2/en not_active Expired
- 1982-03-23 CA CA000399144A patent/CA1178370A/en not_active Expired
- 1982-05-14 DE DE8282104235T patent/DE3278258D1/en not_active Expired
- 1982-05-14 EP EP82104235A patent/EP0068129B1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| EP0068129A2 (en) | 1983-01-05 |
| EP0068129A3 (en) | 1986-05-07 |
| EP0068129B1 (en) | 1988-03-16 |
| JPS586583A (en) | 1983-01-14 |
| US4386417A (en) | 1983-05-31 |
| DE3278258D1 (en) | 1988-04-21 |
| JPS5858753B2 (en) | 1983-12-27 |
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| MKEC | Expiry (correction) | ||
| MKEX | Expiry |