CA1169535A - Circuit interrupter with digital trip unit and automatic reset - Google Patents

Abstract

66 49,049 ABSTRACT OF THE DISCLOSURE
A circuit interrupter includes a microprocessor based trip unit having a plurality of output control lines and a power supply for providing operating power to said trip unit. Interlock means are provided to maintain the output control lines in a predetermined inactive status for a predetermined time period following energization of the power supply to allow time for operating power to rise to a level sufficient to enable the microcomputer to assert positive control over the status of the control lines. An automatic reset circuit is provided to reset the microcomputer program counter to an initialization routine unless a pulse pattern produced by proper execu-tion of the microcomputer instructions is received by the automatic reset circuitry.

Description

s 1 4g,049 CIRCUIT INTERRUPTER WITH DIGITAL TRIP
UNIT AND AUTOMATIC RESET
CROSS-REFERENCE TO RELATED AP.P;LICATIONS
me present invention is rela-ted to material disclosed in the following Canadian applications 9 all of which are assigned to the same assignee o~ the present appl~-cation~
Canadian Serial No. 374,787, "Circuit Interrupter With Solid State Digital Trip Unit'~ ~iled ~pril 6, 1981 by J~ C. Engel;
Canadian Serial No. 374,755, "Circuit Intcrrupter With Front Panel Numeric ~isplay" filed April 69 1981 by J. C. Engel, R. T. Elm~, and G. F. Sal~tta;
Cana~ian Serial No. 374,764, "Circuit Interrupter With Solid State Digital Trip Unit And Positi~e Power-Up Feature" filed April 6, 1981 by R. T. Elms, G. F. Saletta7 : 15 and B. J. Mercier;
Canadian Serial No. 374,776, "Circuit Interrupter With Digital Trip Unit And Optlcally-Coupled Data Input/
Output System" filed April 6, 1981 by J. C. Engel, J. A.
Wafer, J. T~ Wilson, and R. T. Elms;
Canadian Serial No. 374,716, "Circuit Interrupter With Energy Management Functions" ~iled April 6, 1981 by J. T. Wilson, J. A. Wafer, and J. C. Engel;
Canadian Serial No. 374,735, "Circuit Interrupter With Digital Trip Unit And Style Designator Circuit" filed April 6, 1981 by J. J. Matsko, E. W. Lange, J. CO Engel, and B. J. Mercier;
Canadian Serial No. 374,742, "Circuit I~terrupter ~th t 53S ~g,049 Overtemperature Trip Device" filed April 6, 19~1 by J. J.
Matsko, and J~ A. Wafer;
Canadian Serial Mo. 374,754 "Circuit Interrupter ~Jith Digital Trip Unit ~nd Means To Enter Trip Settings"
~iled l~pril 6, 1981 by R. T. Elms, J. C. Engel, B~ J~
Mercier, G. F. SalettaJ and J T. lrilson;
Canadian Serial No. 374,792, "Circult In~errupter With Digital Trlp Unit And Power Supply" ~iled April 6, 1981 by J. C. Engel, J A. Wafer, R. T. Elms J and G~ F. Saletta;
Canadian ~erial No. 3749696, "Circuit Interrupter With Mul-tiple Display And Parameter Entry ~Ieans" filed April 6, 1981 by J. J. ~Iatsko, J. A. Wafer, J. C. Engel, and B. J.
Mercier;
Canadian Serial No. 374,771, "Circuit Interrupter Wlth Remote Indicator And Power ~Supply'l .~iled April 6, 1981 by J~ C. Engel, J. A~ Wafer, B~ J. Mercier, and J J. Mat~ko;
and Canadian Serial No. 374,748, "Circuit Interrup-ter With ~igital Trip Unit And Potentiometers For P~rameter Entry"
~iled April 6, 1981 by J. C. Engel, B. J. Mercler, and R~ T.
Elms.
BACKGRO~ND OF THE INVENTION
Field of the Invention-The invention relates to circuit interrupters having means ~or electronlcally analyzing the electrical conditions on the circuit being protected and for auto-matically opening to interrupt the current flow ~1henever electrical conditions exceed predetermined l~mits.
Description of the Prior Art:
Circuit breakers are widely used in industrial and commercial applications for protecting electrical conductors and apparatus connected thereto ~rom damage due to excessive current ~low. Although initially used as direct replacements for ~uses, circuit breakers were gradually called upon to provide more sophisticated types of protection other than merely interrupting the circuit when the current flow exceeded a certain level. More elaborate r~
3 49 ~ 049 time-current trip characteristics were required such that a circuit breaker would rapidly open upon very high over-load conditions but would delay interruption upon detec-tion of lower overload currents, the delay time being roughly inversely proportional to the degree of overload.
Additionally, circuit breakers were called upon to inter-rupt upon the detection of ground fault currents. ~s the complexity of electrical distribution circuits increased, the control portions of circuit breakers were intercon-nected to provide selectivity and coordination. Thisallowed the designer to specify the order in which the various circuit breakers would interrupt under specified fault conditions.
During the late 1960's, solid state electronic control circuits were developed for use in high power low voltage circuit breakers~ These control circuits perform-ed functions such as instantaneous and delayed tripping which were traditionally achieved by magnetic and thermal means. The improved accuracy and flexibility of the solid state electronic controls resulted in their wide-spread acceptance, even though the electronic control circuits were more expensive than their mechanical counterparts.
The earliest electronic control circuit designs utilized discrete components such as transistors, resist-ors, and capacitors. More recent designs have includedintegrated circuits which have provided improved product performance at a slightly reduced cost.
As the cost of energy continues its rapid rise, there is increasing interest in effectively controlling the usage of electrical energy through the design of more sophisticated electrical distribution circuits. There-fore, there is required a circuit breaker providing a more complex analysis of electrical conditions on the circuit being protected and even greater capability for coordina-tion with other breakers. As always, it is extremelydesirable to provide this capability at the same or lower cost.
The use of a microcomputer may aid in achieving i'3~S
. ,,~
~t ' 4 49,049 these objectives. However, when power is first applied to a microcomputer, the output control lines thereof are in an uncertain state until the power supply voltages settle to their nominal va]ues. This can cause undesirable effects such as excessive power supply drain or even accidental tripping of the circuit breaker itself or of other interconnected circuit breakers.
Another problem may occur under unusual condi-tions such as those produced by severe electrical system transients, whereupon the microcomputer may execute an improper instruction sequence. It is therefore desirable to provide means for restoring the proper instruction execution sequence following such a system transient.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention there is provided a circuit interrupter includ-ing interrupter means operable to interrupt current flow through an associated circuit on command, sensing means Eor sensing current flow through the interrupter means, microcomputer trip means connected to the interrupter means and the sensing means for comparing current flow through the interrupter means to a predetermined time-current trip characteristic and for operating the inter-rupter means whenever current flow therethrough exceeds the time-current trip characteristic. The microcomputer trip means comprises output control lines, a power supply connected to ~he microcomputer trip means, and interlock means connected to the power supply and to the output lines for maintaining the output lines in a predetermined inactive state following energization of the power supply until such time as operating power to the microcomputer rises to a level sufficient to enable the microcomputer to execute positive control over the output control lines.

49,001; ~9,002; 49~00~ 9,006; 49,009; 49,010; 49,013;
49,04g; 49,049; 49~050 BRIEF_~SCRIP~ION OF _HF D_AWINGS
Figure 1 is a perspective view of a circuit breaker embodying the prin~iples of the present invention;
Fig. 2 is a functional block diagram of the circuit breaker of Fig. l;
Fig. 3 is a block diagram of a typical electri-cal distribution system utilizing circ:uit breakers of the type shown in Fig. l;
Fig. 4 is a graph of the time-current ~ripping characteristic of the circuit ~reaker shown in Fig. 1 plotted on a log-log scale;
Fig. 5 is a detailed frontal view of the trip unit panel of the circuit breaker of Figs. 1 and 2;
Fig. 5A is a block diagram of the microcomputer shown in Fig. 2;
Fig. 6 is a detailed schematic diagram of the panel display system of Fig. 5; and Fig. 7 is a detailed schematic diagram of the parameter input system of Fig. 2;
Fig. 8 is a detailed schematic diagram of the Style Number ~esignator System of Fig. 2;
Fig. 9 is a schematic diagram of the Remote Indicator and Power Supply of Fig. 2;
Fig. 10 is a diagram of the waveforms present at various locations in the Remote Indicator and Power Supply of Fig. 9;
Fig. ll is a block diagram of the System Power Supply shown in Fig. ~ ;
Fig. 12 is a schematic diagram of the System Power Supply shown in Fig. 11;
Fig. 13 is a diagram of the switching levels occurring at various locations in the System Power Supply of Figs. 11 and 12;
Fig. 14 is a schematic diagram of the Data Input Output System and Power Supply of Fig. 2;
Fig. 15 is a diagram of the waveforms present at 49,001; ~,002; ~9,004; ~9,006; 49,009; 49,010; ~9,013;
~ 49,048; 49,049; 49,050 ! ``~ ~
.~ , various loca~ions in the system of ~ig. 14;
Fig. 16 is a schematic dia~ram of a power-on hardware initialization and automatic reset circuit;
Fig~ 17 is a flowchart of the main instruction loop stored in read-only memory of the microcomputer shown in Fig. 2;
Fig. 18 is a 1Owchart of the first function of the main instruction loop shown in Fig. 17;
Fig. 19 is a flowchart of the second function of the main instruction loop shown in Fig. 17;
Fig. 20 is a flowchart of the third function of the main instruction loop shown in Fig. 17;
Fig. 21 is a flowchart of the fourth function of the main instruction loop shown in Fig. 17;
15Fig. 22 is a flowchart of the fifth function of the main instruction loop shown in Fig. 17;
Fig. 23 is a flowchart of the sixth function of the main instruction loop shown in Fig. 17;
Fig. 24 is a flowchart of the seventh function of the main instruction loop shown in Fig. 17;
Fig. 25 is a flowchart of the eighth function of the main instruction loop shown in Fig. 17;
Fig. 26 is a flowchart of the common display subroutine of Fig. 17;
25Fig. 27 is a flowchart of the trip subroutine of Fig. 17; and Fig. 28 is a flowchart of tne subroutine to obtain setting values from the potentiometers of Fig. 5.
DESCRIPTION OF THE PREFERRED EMBODIMENT

A. Use of a Circuit Breaker in an Electrical Power Distribution System Before explaining the operation of the present invention, it will be helpful to describe in greater detail the function of a circuit breaker in an electrical power distribution circuit. Fig. 3 shows a typical elec--s~s 49,0~1; 4q~0~; 49,00~; 49,006; 49,009; 49,010; ~9,013;
7 49,048; 49,049; 49,050 ~~J -~
trical distribution system. A plurality of electrical loads 48 are supplied through circuit breakers 50, 52 and 54 from either of two sources of electrical energy 56 and 58. The sources 56 and 58 could be transformers connected to a high voltage electrical feeder line, a diesel-powered emergency generator, or a combination of the two. Power from the first source 56 is supplied through a first main circuit breaker 50 to a plurality of branch circuit break-ers 60-66. Similarly, power from the second source 58 may 1~ be supplied through a second main circuit breaker 52 to a second plurality of branch circuit breakers 68-74. Al-ternatively, power from either source 56 or 58 may be supplied through the tie circuit breaker 54 to the branch circuit breakers on the opposite side. Generally, the main and tie circuit breakers S0, 52 and 54 are coordin-ated so that no branch circuit is simultaneously supplied by both sources. The capacity of the main and tie circuit breakers 50, 52 and 54 is usually greater than thac of any branch circuit breaker.
If a fault (abnormally large current flow) should occur a~t, for example, the point 76, it is desira-ble that this condition be detected by the branch circuit breaker 62 and that this breaker rapidly trip, or open, to isolate the fault from any source of electrical power.
The fault at the point 76 may be a large over-current condition caused, for example, by a short circuit between two of the phase conductors of the circuit, or an overload only slightly above the rating of the breaker caused by a stalled motor. Alternatively, it might be a ground fault caused by a breakdown of insulation on one of the conduc-tors, allowing a relatively small amount of current flow to an object at ground potential. In any case, the fault would also be detected by the main or tie breakers 50, 52 or 54 through which the load fed by branch breaker 62 is supplied at the time of the fault. However, it is desir-able that only the branch circuit breaker 62 operate to t~ S

~,001; 49l002; 49,004; ~9,006; 49,009; 49l010; 49,013;
~ 49,0~ 9,049; ~9,050 isolate the fault fro~ the source of electrical power rather than the main or tie breakers. The reason for this is that if the main or tie circuit breaker should trip, electrical power would be lost to more than just the load attached in the branch circuit on which the fault oc-curred~ It is therefore desirable that the main and tie circuit S0, 52 and 5~ breakers should have a longer delay period following detection of a fault before they initiate a tripping operation. The coordination of delay times among the main, tie and branch circuit breakers for vari-ous types of faults is a maJor reason for the need to provide sophisticated control in a trip unit.
B. Time-Current Tripping Characteristics:
In order to achieve the coordination between circuit breakers as described above, the time vs. current tripping characteristics of each circuit breaker must be specified. Circuit breakers have traditionally exhibited characteristics similar to that shown in Fig. 4, where both axes are plotted on a logarithmic scale. When cur-rent below the maximum continuous current rating of thebreaker is flowing, the breaker will, of course, remain closed. As current increases, however, it is desirable that at some point, for example the point 300 of Fig. 4, the breaker should trip if this overload current persists for an extended period of time. Should a current flow equal to the maximum continuous current rating as speci-fied by point 300 persist, it can be seen from Fig. 4 that the breaker will trip in approximately 60 seconds.
At slightly higher values of current, the time required for the breaker to trip will be shorter. For example at 1.6 times maximum continuous current as speci-fied by point 302, the breaker will trip in about 20 seconds. The portion of the curve between the points 300 and 304 is known as the long delay, or thermal, character-3~ istic of the breaker, since this characteristic was pro-vided by a bimetal element in traditional breakers. It is -- , ', .

~ ~35~
, ~ ...~
4~,001; 49,002; ~9,004; 49,006; ~9,009; ~9,010; 49,013;
~ ~9,0~; 49,0~9; 49,050 desirable that both the current level at which the long delay portion begins and the trip time required for any point on that portion be adjustable. These parameters are known as long delay pick-up and long delay time, respec-tively, and are indicated by the arrows 306 and ~.3~, At very high overcurrent levels, for example 12 times the maximum continuous current and ab~ve, it is desirable that the circuit breaker trip as rapidly as possible. This point 312 on the curve is known as the "instantaneous"~or magnetic, trip levell since traditional breakers employed an electromagnet in series with the contacts to provide the most rapid response. The instan-taneous pick-up level is usually adjustable, as indicated by the arrow 314.
To aid in coordinating breakers within a dis-tribution system, modern circuit breakers ha~e added a short delay trip characteristic 316 between the long delay and instantaneous portions. The present invention allows adjustment of both the short delay pick-up level and the short delay trip time as indicated by the arrows 318 and 320, Under certain conditions it is desirable that the trip time over the short delay portion also vary inversely with the square of the current. This is known as an I t characteristic and is indicated in Fig. 4 by the broken line 310.
- II. PHYSICAL AND OPERATIONAL DESCRIPTION
A. Circuit Breaker Reference may now be had to the drawings, in which like reference characters refer to corresponding components. A perspective view and a functional block diagram of a molded case circuit breaker 10 employing the principles of the present invention is shown in Figs. 1 and 2, respectively. Although the circuit interrupter 10 is a three-pole circuit breaker for use on a three-phase electrical circuit, the invention is, of course, not so r' ~
31.:~,~35 limlted ~nd could be used on a ~ingle-phase clrcuit or another type of mll~tlphase circuit. A power aource such as a tran~for~er or ~witchboard bus is connected to input terminal~ 12 and an electrical load i~ connected to output ter~inals 140 Internal conductors 16 connected to the terminals 12 and 14 nre al~o connected to lnterrupting contacts 18 which ~erve to selectively open and clo~e an electrical c~rcult through the circuit breaker. The contacts 18 are mechanically operated by a mechani~m 20 10 . which responds to manuslly or automatically-lnitiated comn~nds to op~n or ¢1Q~e ~he contacts 18.
Current transformers 24 ~urround each of the internal phase conductors 16 to detect the level o~ cur-- rent ~low through the conductor~ 16. me output 8ignal ~rom the current tr~ns~ormer~ 24 i~ supplied to a trip u~lt 26, along with the output 8ignal ~rom a current tran8~0rmer 28 which d~tect~ the l~vel of ground ~ault current flowing in the circult. The trip unlt 26 con-stantlg ~onltor~ the level of ph~se and ground fault currents n ownng ln the cir¢uit to whlch the breaker 10 i3 conn~cted and lnlt~ates a command ~lgnal to a trip coil 22 which actuates the mechanism 20 to open the contacts ta whe~ever electric~l condttion~ on the c~rcult belng pro-t~cted exceed predetermlned llmlt8 stored in the trlp unit 26. During normal condltlon~, the mech~ni3m 20 c~n be comm~nded to ope~ and close the contacts 18 through:man-ually-inltiated co~m~nd3 applled through the manual con-trola 32.
Re~errlng to Flg. 1, 1t can be seQn that the circult bre~ker 10 ~nclud~s a mold~d ln3ulatlng houslng 34~ Thc t~mlnals 12 and 14 are on th~ r~ar o~ the hou~-~ng 34 and ar~ thus not shown 1~ Flg. 1. A handl~ 36 18 ~ounted on the right-hand R de o~ the hou3ing 34 to allow an operator tc manually charge a spring ~not shown) in ~h~
mechanism 20~ The m~nual control~ 32 are positloned in t~e center o~ the hou~lng 34. Wlndows 38 ar~d 40 indicate the ~tate of charge o~ the ~prlng and the positlon o~ the contacts lB~ re~3pectively. A push-button 42 a}lows an operator to cau~e an ~ntemal electrlc motor to mechanic-5 ally charge the ~pr~ng 1~ the same manner ~ the ma~ualc~rging operation w~ch can be performed by the handle 36. A pu3hbutton 44 allow~ a~ operator to c~use the sprlng to operate the mechanism 20 to clo~e the contacts 18. S~milarly, a pu~hblltton 46 allows an operator to 10 cause the spr~ng and mechanism 20 to open the contact~ 18.
B- ~
1. Front Panel q~he panei of the trip unit 26 i5 positloned on the leît side of the houslnl3 34 a~ c~n be seen in Fig. 1.
Tqlis panel, ~hown in more deta~ Figa 5~ lncludes a plurality o~ indica~or llghts~ potentiometers~ ~umerio display devic~s, and switche~, to permlt an operator to obs~rve the electrlc~l pnrameters on the cirouit being protected and the llmlt ~alues pre~ently stored 1~
~he tr~p unlt, and to enter new llmit ~alue~ i~ 80 de-3i~ed.
A rating plug 78 1~ lnsertsd into the ~rontpan~l of the trip unit 26 to ~peclfy the maximum cont~n-uou~ current to be allowed in the clrcuit beinB protected by the circuit bre~ker. Thl~ may be le~ than th~ actual capacity of the clrcult breaker, wh~ch 1~ ~nown as the fra~e slze. For ex~ple, ~he fra~e slze for the circuit __ _ breaXcr m~y be 1~600 amperes; howe~er9 when the break~r 18 lnl~ ly ~nstalled the circult being protected may need to ~upply ~nlyl,000 ampQres of ~lectric~l current~
There~or~, a rating plug ~ay be lnserted in the trlp unit to e~ure that the max~mum contlnuous curr~nt allowed ~y the c$rcuit breaker will be only 1 t amperes even thouBh the circuit breaker itself is capable of sRfely carrying 1,600 amperes.
An auxiliary AC power receptacle 132 i3 loc~ted 3 ~
'? 49,001, 49,002; 4~,004; 49,~06; 49,009; l~9,010; 49,013;
~9,048; 49,0~t9; l~9,050 at the upper right of the trip unit panel, as seen in Fig.
5. This soeket is used to supply auxiliary alternating current operating power (separate from the electrical circuit being protected) to the circuitry of the trip unit. The operation of this auxiliary AC power supply will be d~seribed more completely in section Ill.E.

2. Block Diagram Referring to Fig. 2, it can be seen that the trip eoil 22 is supplied with power through a conductor 136 from the power supply 144. The flow of current through the trip coil is eontrolled by a non-latching switehing device such as a switehing field effect tran-sistor 192 actuated by the main trip unit circuitry. The use o a non-latehing switeh deviee instead oE an SCR or other type of latehing deviee as usedIthe prior art ~>ro-vides greater noise immunity.
In addition, the eireuit breaker 13 includes three parallel-eonneeted normally-open thermally activated switehes 141 eonneeted in parallel with FET 192. These switehes are physieally mounted on the eonduetors 16 in proximity to the eontacts 18, with one switeh mounted on eaeh phase conduetor 16.~l Each switch/comprises a bimetal elemènt which closes the switeh eontacts when the temperature of the assoeiated eonduetor rises to 150C and resets when the eonductor temperature falls below 130C. Although a bimetallie switeh is employed in the disclosed embodiment, other types of thermally aetivated switehes such as ther-mistors could be mounted on the conductor. Alternatively,

3~ radiation sensors could be used. Infrared detectors eould monitor the heat generated on the contacts orconductors, while ultraviolet or RF detectors could sense radiation generated by arcing contaets or terminals.
The switches 141 serve to directly energize the trip coil 22 upon high temperature_conditions. In addi-tion, the hardware interrupt line/of the microcomputer is connected through the trip coil 22 to the high side of the switches 141 to ~ignal the microcomputer 154 th~t a trip operation has occurred. mi~ cau~es execution of approprlate in~truction~ in internal read-only memory (ROM) o~ the microcomputer 154 to generate output data to a remo~e lndicator 145, Since the mechani~m 20 requires somewhat more than 30 ms.
to open the contacts following a trlp command, power 19 avail-abl~ for trip unit 26 to execute 2 comp:Lete operation cycle~
of ~he ma~n loop progra~ even ~f no external power l~ ~upplied.
Alter~stiYely, the switches 141 could be wired solely to ~he m~crocomputer 154 to allow it to in$tia-te the trip operation ~nd generate output data in the same manner as an overcurrent trip.
In~ormation concerning electr~cal parameter~ on the clrcuit is provided by the three pha~e current trans-formers 24, each of which monitors current ~low through the indi~idual phase conductors of the circult. The tran~ormer 28 surrounds the three phase conductor~ o~ the circuit and detects current~ whlch n ow outward ~rom a ~ource through the phase conductors and then return through unauthorized paths through ground, commonly known a~ ground fault current3.
m e si~nal~ from the current trans~ormers 24 are ~upplied to a rectlfier and auctioneering circult 142 which provides a DC current proportional to the highe~t instantaneous AC current on any o~ the three phases. The clrcult 142 provides normal operatlng power for the trip unit through a power supply 144. The trans~ormers 24 and 28 act as current sources and are llmited to supply power to the circult 142 ~ approxlmately 40 Yolts. mls is converted by the power 3upply 144 to three operstlng volt~g~s: a 1.67 volt ref~rence voltage labelled VREF, a 5 volt operating voltage for the mlcrocomputer And asso ciated circuitry of the trip unlt~ and a 40 ~olt s~pply which operates the trip coil 22. Information from the rectlfier and auctioneering circuit 142 which is propor-tional to the present value of phase current is also ;9~i35 suppli2d to the pealc detector 160 o~ the maln trip clrcuitsy as indicated ln Fig. 2.
me ~l~al ~rom ~e ground trans:Eormer 28 i8 supplied to a recti~ier clrcult 146 whlch prov~de~ an 5 alternate ~ource o:f operating power ~or th~ trlp ~lt throu~h the power s~pply 144, and al~o ~upplies infor~-tion pr~port~onal to the present va}ue of gro~d current to t~e peak detector 162 o~ the trip unit circuitry. An exter~ ource 148 o~ operating power on ~e order of ~10 about 40 Yolt8 msy ~B0 be s~pplied,to th~ power supply 144, a~ ~ay be an extsr~al A~ sol~ce 150 Or operatlng power 8upp:Ued t~ough the trip unit front panel ~ocket 132 to a rectlîier l52 and t~en to th~ power supply 144, The main trip unit clrc~try lncludes an in~orm-ation processor and sequance controller 154 w~ich may be, for example, a type 8048 microcomputer obtainable in commeralal quantitie~ ~rom the Intel Corporation, A block diagr~ Or t~e corltroller 154 i8 sho~n ~n Fig. 5A; howev~r, a de~ailed de~cription of the 8048 microcomputer may be obt~lned ~rom the MCS-48 Microcon~puter U~er~ Manual, published by t~e Intel CorporationO
An ana~og-to-alglt~l converter 156 such l38 the type ADC3084 obt~lnabl~ in commerclal quantiti~s :~2 the Natlon~l Semlconductor Co~poration i8 connected to t~e data bu~ 172 of th~ mlcrocomputer 154, ~y o~ eight in-puts to the analog-to-digltal converter (ADC) 156 ~re ~e-l~ct~d throu~h ~ multiplexer 158 such as the typo CD4()51B
acco~g to an address s~pplied by the microcom~uter via port 1 to ~e multiplexer 158. mese lnput~ include pe~k detectors 160 ~nd 162 i`or pha~e ~nd gs~ound current YalU~8, an a~eraglng clrcult 164 ior a~erage pha~e current9 a pa~r o~ ~ultiplexers 166 and 168 ~or reading panel switch~ and potentlometer~ address~d and selected by the mlcrocomputcr ~1~ port 2, and ~our lines from a Style Number D~slgnator circuit 170. The des~enator circuit ~70 allows m~nurac-~uring personnel to provide the microcomputer 154 with .613S3~

~9,001; ~,0~2; ~,004; 49,006; 49,009; 49,010; ~9,013;
~9,048; 4~,049i ~9,050 . ~ /~,S

information concerning the optional features and modes, such as ground fault detection and serial I/O capability, with which the specific trip unit will be swpplied. Use of such a designator circuit allows a single microcomputer configuration to be provided for a plurality of different models of the trip unit 26.
Also connected to the microcomputer data bus 172 is an external read-only memory (ROM) 151 and a data in-put/output system 174 which allows the trip unit to inter-act with other components and circuit breakers of theelectrical distribution system. Power for the data input/
output system is provided by a separate power supply 176 derived from the five-volt bus of the power supply 144.
As will be more completely described in a later section, the data input/output power supply 176 is a pulse-type power supply activated by a line 178 connected to port 1 of the microcomputer 154.
Input to the microcomputer 1S4 from the limit value potentiometers and switches of the trip unit panel, shown in Fig. 2, is supplied through multiplexers 166 and 168 to multiplex~er 158. Output information to the panel ` display systemlincluding the LED's 84-100 and numeric dis-play indicators 80 and 82 is supplied from the micropro-cessor 154 through port 2. Port 2 also supplies address and SE~ECT information to the multiplexers 166 and 168.
Port 1 of the microcomputer 154 provides a plurality of functions. Control of the ADC 156 is pro-vided by a line 180 from porL 1 to a switching t~ansiStQr 182 which varies the reference voltage/to ~he ADC. Input 3~ to the ADC 156 from the multiplexer 158 is controlled through a line 184 from port 1 to a switching transistor 186 to selectively ground the multiplexer output to the ADC 156 under control of the program of the microcomputer 154 as will be described hereinafter. Grounding of the 3~ multiplexer 158 output while either of the peak detectors 160 and 162 are selected causes a reset of the peak detec-7 49~049 tors.
Address information allowing the multiplexer 158 to select from its various input sources 160, 162, 164, 166~ 168 or 170 is provided from port 1 of the micro-computer through address lines 188.
Control o~ the trip coil 22 is provided from the microcomputer 154 through port 1 and a SrRIP line 190.
Thus, when it is determined that a trippin~ operation is called for, the microcomputer 154 sendsl through port 1, a signal on the trip line 190 causing the switchlng tran-sistor 192 to energize the trip coil 22V activate the mechanism 20, and separate the contacts 18.

Mode 1. Low Power This mode is performed under conditions of ~ery low current flow through the breaker (les~ than 25~ of ~rame rating) 9 when external power is not being supplied to the trip unit. Under these conditions su~flcient operating power cannot be continuously supplied to the trip unit, and some o~ its normal functions cannot be reliably performed. There~ore, the power supply generates a pulse of operating power to the trip unit circuitry sufficient to execute the normal operating cycle of the trip unit but to display only the present phase current through the breaker on the numeric display 80. This value is flashed by the display at a rate which increases as load current increases. At load current values above 25%
of frame rating~ Mode 2 operation is per~ormed. Fractions of rating values will hereinafter be indicated by per unit notation; e.g. 25% - .25 PU.
Mode 2: Normal This mode of operation is performed when load current is greater than .25 PU of frame rating but less than 1.0 PU of the rating plug value, or when external power is being supplied to the trip unit.
As can be seen in Fig. 5, the trip unit panel contains a number of adjustment potentiometers, light-emitting diode indicators (LED's), pushbutton switches, X~S;3~;
,.1 49,~01; ~9,00~; 49,004; ~9,006; 49~009; 49,010, 49,013;
49,048; 49,049; 49,050 , ~ ~
and two-position switches. The panel also inc]udes a pair of numeric display indicators 80 and 82. The electronic circuitry internal to the trip unit causes the numeric display indicators 80 and 82 to sequen~ially display the present value of electrical conditions on the circuit being protected and the various limit settings defining the time-current trip curve of the breaker as currently set. The LED's, when lighted, indicate by the legends associated with each indicator, what value is being dis-played at any time by the numeric displays 80 and 82. Ifso desired, the numeric values displayed on the numeric indicators 80 and 8~ may also be sent to a remote location A via the SERIAL OUT terminal of the Data I/O Sys~m 174\
Beginning at the top of the trip unit panel as l~ shown in Fig. 5, the LED indicator 84 is labelecl PHASE
CURRENT on the left and GROUND CURRENT on the right. When this LED is li~hted, it indicates that the present per unit valuc of current flowing in the three-phase circuit being protected is displayed in the left-hand numeric dis-play indicator 80, and the present per unit value ofground current on the circuit being protected is indicated in the right-hand digital display indicator 82. In a similar manner, the LED 86 is labeled PEAK KW SETTING and PEAK KW SINCE LAST RESET. When this LED is lighted, the value appearing in the left-hand numeric display 80 is that value of kilowatts delivered by the circuit being protected which will cause a DEMAND signal to be generated by the data input/output system. The peak value of kilo-watts drawn through the breaker since the display was last reset (by the pushbutton ~ immediately to the right) is presented~ on the numeric display indicator 82. The LED ! 5 88 and ~ correspondingly indicate PRESENT KW and MW x HOURS, and power factor multiplied by line voltage as follows:

.3~ii3~i PRESENT KW = pre ~ent ~e al~ntx~(powerI~ctorxline volt~ge)~
a~ entered by operator on front panel aetual megawatt-hour~ = (MW x HourRs) x ~rame rating In th~s Dlanner, a user c~n more readily p~r~orm energy ~anagem~nt ~or hi~ sys~em. Not only i~ a continu-OU3 d$~play o~ present demand, pea3c demand, and tot~l energy usage pro~rid2d~, but ln addi~ont alarm~ or auto-~at~c load ~h2ddl~g may be initiated ~y the ou~put 8igtl pro~rlded ~hroug~ the dat~ I/0 sy~te~ ~n respo~se to the PEA~ KW ~onitoring functl~n.
If de~lred~ a po~eIltial tran~former could be added to the circ~it breaker 10 to monltor llne voltRge and eli~ina~e the need ~or mar~ual op~rator entry o~ a v~llua OI lin~ voltage. Furthermore, a hi8h-~peed A/D conv~rter could be added to ~ple line voltage and ph~e currant at a high enough rate to permit dlrect calculation of power factor and eliminate the need ~or an operator to enter the power Iactor.
Below the rating plug ln Fig~ 5 can be 6eerl a number of LED'~ labelled INSTANTANEOUS, LONG DELAY, SHORT
DELAY, and GROUND FAULT, To the le~t of this serle~ of LED18 :L~ the legend CUR~T PICIS~ nd to the r~ght is ~he lege~d TI~ IN. When the LED 92 labelled INSTANTANEOUS i8 lighted, thi8 indicates that the value of current whlch will result lrl an iY~stantaneous trip l~ pre~ent1y belng di~plsyed in thc }~t-hand dlgltal di play indicator 80. By deri~
tiOi~19 1;he ln~tantarlcou~ trip will occur immediat~ly, ~UB
1;hers i~ ~o correspo~ding tlme to be dl~layed9 end ~o d~play 82 18 b~ n t~he LED 94 lab~ ELAY
iB llght~d, this indlcat~R that the lert-Aand num~ric di~play indlcator 80 18 pre~e~tly sho~rlng the current value nt whlch a long-delay tripping operation will be lnitiated, wh~l~ the ri~ht-hand numeric di~play indlcator 82 $8 showing the t~me parameter in seconds of a long delay tr$pping operatio~. mese time and current value~

correspond to the long delay tripping operation discussed above with regard to the time-current tripping curve of the circuit breaker.
When the LED 96 labeled SHORT DELAY is lighted, 5 the left-hand numeric display lndicator 80 is showing the current value which will cause a short delay tripp~ng operation to be initiated, while the right-hand numeric display indicator 82 is showing the duration, in cycles, of a short delay tripping operation. Similarly, when the LED 98 labeled GROUND FAULT is lighted, the left-hand ~umeric display 80 will show the value of ground current - which will cause a ground fault tripping operation and the right-hand digital display 82 will show the number of cycles between the detection of the ground ~ault current and the command to cause the circuit breaker to trip.
As can be seen in Fig. 5, some of the legends have a solid circular symbol associated therewith, while other legends are associated with a solid squar~ symbol.
The circular symbols indicate that the parameter desig-nated by the associated legend will be displayed as a per unit multiple of frame ratin~. Similarly, those -parameters associated with a square symbol will be dis-played as per unit multiples of ~ rating. For example, assume the displays 80 and 82 were presenting values of 0.61 and 0~003, respectively, and the LED indicator 84 is lighted. This represents a present phase current of 976 amperes (0.61 x frame rating = 0.61 x 1600 amps = 976) and a present ground current of 3.6 amperes (0.003 x plug rating = 0.003 x 1200 amps = 3.6 amps).
A pair of miniature switches 102 and 104 labeled I2T RESPONSE are used to vary the shape of the time-current tripping curve in the short delay and ground fault areas, respectively. When the switches 102 and 104 are in the lower position, this indicates the Ground Fault and Short Delay portions of the curve will not exhibit an I2T
slope, but will instead be horizontal. When the switches :l~b~3~35 ~o 102 an~ 104 ~re in the upper posltion, th~ I2T character-ist~c will be employ~d, And the character~stic ior the Short Delay tripp~ng operation will have the shape a~
~hown ln Fig. 4.
A potential trans~orm~r connected to the as~o-ci~ted circuit could be used to obtaln line voltage data, and r~pid s~mpl~ng and direct multlplication o~ the in-stantaneouæ values of phase current and llne voltAge used to calculate real powerD However, the Idisclo~ed m~thod pro~dss a convenlent and cost-e$fecti~e method which aYoid~ ~solat~on problems associated wlth potentlal trans-formers.
Summarizing, in normal operation, the following - operations will be calculated sequentlal-ly, wlth the entire c~lculatlon sequence repeated 60 times per second: peak KW, MW-HR integration, in~tantaneou~ ~rip, long delay trLp, ~hort delay trip, and ground ~ault trip.
In addltion the ~ollowing values w~ll be sequentially ln palrs, w1th each ~ a~ sting 4 second~:
ZO PRESENT PHA5E CU ~ T - PRESENT GROUND CURRENT, PEAK KW
setting (demand) - PEAK KW SINCE RESET, PRESENT KW - MWHR, POWER FACTOR x LINE VOLTAGE, INSTANTANEOUS PICKUP - TIME, LONG DELAY PIC~UP - TIME, SHORT DELAY PICKUP - TIME, AND
GROUND FAULT PICKUP TIME.
Mode ~_ Overcurrent ~nd Trip Mode Thls mode ls per~ormed when either phase current i8 above the Long Delay Pickup value or ground ~urrent i8 above the Ground Current P~ckup value. Sequenclng of display values and LED lndication thereof continue~ as in Mode 2 even through the breaker i8 overloaded. In addi-tion, the Lo~g Delay Plckup LED 94 will bP llghted.
If the overcurrent or ground fault conditlon per~ists, the trlp unit will in~tiate a tripping operation accordlng to the time-current trip character~stl~ loaded therein by the user. When tripping occurs, the f~mction which lnitiated the trip ~long delay, short delay, instan-'~.,;,~

s~5 t' 2l ~ 49,049 taneous~ or ground fault) will be indicated on the front panel by energization of the appropriate LED 92, 94, 96, or 98~ The cause-of-trip in~ormation will be sent out by the data I/O system to the remote indicator 145, In addi-tion, the per u~it phase or ground fault current thatcaused the trip will be displayed and ~rozen on -the numer-ic display 80.
In addition to the microcomputer trip capabili-ty~ the trip circuit breaker includes 1;he thermal switches 141 as a back-up system. Should this system lnitiate a trip operation, the Instantaneous ~ED 92 will be lighted, a value o~ o~ 15.93 PU current Yalue will ~e displayed on the numeric display 80~ and an INST~NTANEOUS signal sent by the data I/O system.
Mode 4 _ Parameter Ad~s~ment As can be seen in Flg~ 5, the trip unit panel also includes a plurality of limit value potentiometers assoaiated with the various l~gend~ on the trip unit panel. Th~se potent~ometers are provided to allow an 20 operator to ad~ust the circuitry o~ the trip unit to vary the shape of the time-current trip curve and produce the type o~ tripping characteristics required by the design of the entire electrical distribution system. When an operator adjusts one of the potentiometers (for example, the INSTANTANEOUS CURRENT PICK-UP potentiometer 112) this adjustment is detected by the trip unit circuitry and the sequential display of values is interrupted. me parameter value being adjusted is immediately displayed in the correspond-ing numeric display indicator, and the corresponding LED indi-cator is lighted. For example, if it is desired to adjust theinstantaneous current pick-up value, an operator inserts a scre~driver or other tool into the potentiometer 112 and begins to turn it. Immediately, the INSTANT.4NEOUS LED indi-cator 92 lights and the present value of the instantaneous ~5 current pick-up is displayed in the numeric display indicator 80. This number is in per unit format, that is, a multiplier ii3S
~9,001; 49,002; 49,00~; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 . . . --2~

times the frame rating, as specified by the solid round symbol. Thus, as the potentiometer 112 is rotated, the value displayed in the indicator 80 would begin to slowly increase in discrete steps from, for example, 1.00 up to the maximum allowable value as stored internally in the trip unit, which is 10Ø ~len the desired value is achieved, adjustment of ~he potentiometer is ceaséd and the trip unit resumes its sequential scan and display of present values and settings. In a similar manner, any of the potentiometers on the trip unit front panel may be ad-justed to achieve the desired parameter setting.
In the past, adjustment of parameter values using potentiometers in conjunction with digital circuitry has presented problems. There was a tendency, for exam-ple, for each minute change in the value of a potentio-meter~to produce a different value which would be immedi-ately displayed. This produced an annoyingly rapid varia-tion of the display which rendered adjustment difficult.
Furthermore, temperature variations and other minor per-turbations in the circuitry would cause variation in the display and value of the potentiometer even when no ad-justment was being made. In addition, failure of the potentiometer in the past would sometimes prevent the designated parameter from being read at all.
In order to avoid these problems, the present invention employs the potentiometers to select one of ~r eight predetermined parameter values stored within ROM of the trip unit microcomputer. Thus, the potentiometer acts as a discrete multiposition switch rather than a continu-ously variable adjustment device. In the event of a potentiometer failure, the trip unit selects the most conservative value of the parameter associated with the malfunctioning potentiometer for use in its monitoring functions.
To add further convenience to an adjustment operation, the trip unit includes a hysteresis feature which is de~cribed in detail in Sect~on III.C.
Parameter3 may alfiO be entered by an external circuit over the ~ERIAL IN terminal (Fig. 14) of the data I/0 system 174.
~ T~st_Mod~
A TEST mode i8 al~o provided tn the trlp unit herein di~clo~ed. ~y pre~ing either of the mo~entary-cont~ct pushbutton ~w~tches 128 or 13~ an overcurrent cond1tion or ground-~ault condition, re~pectively, may be ~imulated~
If the swltch 106 is i~ the N0 TRIP po~ition, th8 fault cur-rent ~alue to be s$mNlat2d i~ determ~ned by the ad~u~tme~t o~
the potentio~eter 120 whll~ either o~ the ~wltches 128 or 1~0 are depressed. With the ~itch 106 in the TRIP posi-tlon, fixed ~alue~ o~ ~ault current are ~im~lat~d. Thl8 slmulated oYercurrent or ground-~ault condition wlll or will ~ot result in actual opening o~ the contacts 18 o~ the ~lrcuit breaker, ~ determl~ed by the sett~ng o~ the TRIP/NO TRIP ~wltoh 106, In elther casel ~he te~t 18 lnitiated upon rele~e o~ the pu~hbutton~ 128 or 130, causing ~he TEST MODE LED 100 t~ be lighted~ When the d~lay per~od ex~r~s, the appropriate LED 92, 94, or 96 w~ll light, thu3 lndicating the succesfiful completion o~
~he te~t. I~ the ~wltch 106 ha~ be~n se* to th~ TRIP
position, the contacts of ~he circult breaker will actu~lly op~nO
mrough the u~ o~ the TEST mode with the 3wltch 106 in the N0 qRIP po~it~n9 an operator can chec~c any d~slred polnt on the tiDIe-current tripplng charac-terl~ttc.
He does thl~ by pre~ng the desired test button 128 or 130, uld dlaling ln, on the lq~ST potentiomet~r 120, any d~sir~d 0ult~pl~ o~ the D~ax~ continuou~ current. H~
th~n releas~s t,h~ dasired phase or gro~d i'ault test button 128 or 130. ~e trip unit will simulate ~ rault st that le~lrel of the multiple of maxim~ contlnuous current ~5 which was entered via lq~:ST potentiometer 120, and will ~imulat~ a tr~pping operat~on without actually openlng the contact~.
At the coD~pletiorl o~ the te6t, LE~ 92, 94, 96 or 98 w~ll be ll~tad tc indicate whether the br~ r tripp~d under lnstantarleou~, long d~lay, ~hort delay, or ground ~ault modes. me dl~play ~0 will show the per unit cur-rent ~ralue at ~ich the bre~ker tripped (which will be th~ ~ame as the value entered via potentiometer 120) and d~splay 8? wlll show t}le number o~ second~ or cycl~s (w~ich i~ ~pecif1ed by LEDI8 92, 949 96 or 98) ~ollowing ~nltlatio~ of the te~t in ~ich the break~r trlpped.
During execution Q:f~ a te~t, a dete~in~tion 19 made ~ to which i8 ~arg~r: ac tual pha~e tor ground) CUrr~nt Or ~ U1ated PhaSe (Or grOUnd~ CUrrent, and the 1arger Oî the ~WO COmP~r~d tO the Var~OU8 Setting ~a~LUe~.
mU~ a te8t Can t~ke P1aCe W1th nO 1088 oî prot9ctlon.
Further~Ore, ~ ~imU1ated CUrrent i8 1arger than aCtl1a1 CUrrent~ but bOth are 1arger than LOng De1RY Plck-l~p, a trip oper~tlon will be performed ~t the end o~ ~he te~t, r~gardless o~ the po~ition o~ the TRIP/N0 TRIP switch 106.
me operator can then plot the time-currrent value dlSplayed tO see if thl~ point lle~ on tha de~ired ti~e-current tripplng characteri~t~c curve. Any nuMber of po~nts can be 80 tested, allowlng co~plete ver~icat~on o~
the tripplng characterlstlc ~ entered ln ~he tr~p unit.
C. ~
A re~ote lndicat~r~nd power supply 145 ~ay al30 be conn~cted to the tr~p unit 26. Thl~ devlce, shown sch~mat~cally in Fig. 9, provldes the capab~lity o~
dicatlng at a loc~tlon ra~ote ~rom the circult break~r 10 whe~ th~ br~aker ha~ trlpped a~d what caused the trlp~
In additlon, the ~evic~ 145 c~n lndlcate whe~ p8ak po~sr de~a~d ha8 exceeded a pre~et llmlt. The~s lndlcatlo~s are provided by four LED~8 correspond~ng to ~EAK KW DEM~ND
EXCEEDED, ~VER~URRENT TRIP (long delay), SHORT CIRCUIT TRIP
(instantaneou~t short delay, or thermal) and GRQUMD FAULT
TRIP~
Two relay~ are al~o provided in the remote indi-i3S
~J
49,001; 49,00~ ,004; 49,006; 49,009; ~9,010; 49,013;
~S 49,048; 49,0l~9; ~9,050 cator l~. One relay is actuated on receipt of a peak KW
demand indication, to provide the capability of automatic load shedding. The other relay is actuated on receipt of any type of trip indication to trigger an alaral bell, light, or other desired function.
The device 145 also includes a power supply energized from the AC line which provides 32 volts DC.
The output of this power supply is connected to the EXTER-NAL UC terminal 148 of Fig. 2.
A detailed description of the circuitry of the remote indicator and power supply is contained in Section III.E.
III. ELECTRICAL DESCRIPTION
A. Arithmetic, Logic, and_Control Proc ssor The arithmetic, logic, and control processor 154 is a type 8048 microcomputer manufactured by the INTEL
Corporation. As seen in Fig. 5A, the single 40-pin pack-age includes the following functions: an eight-bit arith-metic logic uni~, a3 control unit, a lK x eight-bit ROM
program memory ~ , 64 x eight-bit RAM data memory 157, an eight-bit bi-directional data bus 172, and two quasi bi-directional eight-bit ports Port 1 and Port 2. Addi-tional control lines are also provided. A more detailed description may be obtained from the previously referenced MCS-48 Microcomputer Users Manual. Referring to the figures, and especially Figure 2, the interconnections to the microcomputer 154 will now be described.
The eight-line data bus 172 is connected to the eight output terminals of the ADC 156. The eight-bit digital values supplied by the ADC are thus read by the microcomputer 154 by the following sequence: a pulse is sent out on the WR line of the microcomputer 154 to the ADC 156, commanding the ADC to convert the analog quantity appearing at its input terminals into an eight-bit digital quantity. Upon completion of the conversion process, the ADC 156 generates a pulse over the line connected to the s~s ~ 49,049 T1 test terminal of the microcomputer,, The microcomputer then generates a pulse on the RD line, which transfers the bit pattern produced by the ADC to the accumulator of the microcomputer 154.
The data bus 172 is also connected to the data input/output systeM 174 7 -to allow the trip unlt 26 to communicate ~ith other clrcuit breakers and with the remote indicator/power supply 145, The data input/output system will be more completely described in Sectlon IIIG.
Port 1 and port 2 of the mlcrocomputer provide the capability to communicate and control the other compo-nents of the trip u~it 26. The speci~ic connections will now be described. Line nu~bers correspond to the notation used in the MCS-48 Microcomputer Users Manual~
Port 1:
Line 0, line 1, llne 2--These lines prQvide the channel address in~ormation ~rom the Micrcocomputer 154 to the multlplexer 158, as indicated at 188 on Figure 2.
Line 3--This line~ lndicated at 180 in Figure 2, actuates the FET 182 to change the referenc~ voltage de-li~ered to the ADC ~56, thereby increa~ing the resolution for the Long Delay phase current measurement.
Line 4--mis line activates the transistor 192 to energize the trip coil 22 and cause the mechanism 20 to open the contacts 18 to the breaker. Line 4 is indicated at 190 in Figure 2.
Line 5--Thls line actuates the FET 186 to ground the output of the multiplexer 158, which also grounds the individual input to the multiplexer 158 which happens to be selected at that time. Thus, activating line 5, (inclicated at 184 in Figure 2) can reset the peak detectors 160 and 162, when these are selected by the multiplexer 158, L~ne 6--This line activates the Chip Select terminal on the external ROM when performing a read oper-ation.
Line 7--This line, ind~cated at 178 in Figure 2, periodically energi~es the power supply 176 o~ the data r input~output system 174.
Port 2-Line OJ Ll2le 1, Ilne 2, Line ~--'rhese llne~ car-ry the data sent ~rom the mlcrocomputer 154 to the panel 5 ~play sy~tem 155. As can be seen ln Fl~,ure 6, th~ diglt ~alue~ are ~upplied o-rer these llne~ to the l~tch decoder 194 ~or display on the ntlmaric indlcators 80 a~d ~ Line 0, llne 1, and l~ne 2 ~ndlcated as 207 in Figure 6 and Flgure 7) al~o supply ch~ l addre~s information to mult~plexer3 206, 166 and 168. Line 3 (~ndicated as 216 in Fil3ure 7~ l~ connect~d to the I~aHIBIT termin~l3 o~ the D~ultiple~cers 166 and 168 and ser~es to toggle or selec tiY~ly ~ctivate the multiplexers 166 and 168.
Llne 4, ldentifled ~ 2~ irl Fig. 6,~ line actu~tes the tr~U18i8tOr 198 to light the decimal poiLnt on the numer~c indicators 80 and 82.
Llne 5~ e l~ ¢onnected to the Latch Esl-~ble termin~l of the latch decoder 194 and serves ~o l~tch the d~ta Va1UC8 appearing on line~ 0 through ~ in the latch decoder 1g4.
Llne 6~ llne ensrgizes the tran~istor 208 whioh, in c~nJunction with tha output line~ oi ~he latch decod~r 194 ~erve~ to eIlerglze the IE:D indlcators 84 ~rough 98.
Llne 7--lrnis line i8 connected to the INHIBIT
ter~nal o~ ~tlplexer 206 and i8 indicated at 212 ln Figu~e 6.
The Interrupt termlnal I~IT of the mlcrocomput~r i connected to th~ high voltage ~ide of th~ ther~al switches 141. Acti~ration of these swi~ches thu~ calls~s the I~tem~t te~inal 143 to go LO and lnltiate the Intarr~t ~118tnlCtiOI18 iII ROM 155 w~ch processes t~e th~rmal trip operation, and lndicate~ ~n lnstantaneous d~splay trip a ~5 B. D~
A detailed ~chematic dlagram of the panel dls-s s~
49,001; 49~02; ~ Q4; ~9,~06; 49,009; 49,010; 49,013;
9,~48; 49,049; 49,050 play syste~ of Fig. 2 is shown in Fig, 6~ As can be seen,a seven-segment latch decoder circuit 194 such as a type CD4511B is provided. A our-bit input signal is provided by lines 0-3 of port 2 of the microcomputer 154. The de-coder circuit 194 provides a seven-line outp~t signal through a load resistor array 196 to the pair of four digit seven-segment LED digital display indicators 80 and 82. An eighth line for activating the decimal point of the digital display indicators 80 and 82 is also provided through a transistor 198 which is actuated by a line 200 also connected to port 2 of the microcomputer 154. A
driver circuit 202 and transistor 204 are provided under control of a multiplexer circuit 206, which may be for example, a type CD4051B. A three-bit SELECT signal, also driven by three lines 207 from port 2 of the microproces-sor is supplied as input to the multiplexer circuit 2~6.
The LED indicators 84, 86, 88, 90, 92, 94, 96, 98 and 100 are actuated through the -transistor 208 by a line from port 2 of the microcomputer 15~ in conjunction with the digital display indicators 80 and 82. The TEST LED 100 is also driven by the tr~ansistor ~ ~and an additional tran-sistor 210 in conjunction with an INHIBIT line 212 also supplied to the multiplexer 206 from port 2 of the micro-computer.
C. Parameter Input Limit values for the trip unit 26 are provided by the potentiometers 108-120, as shown in Figs. 2, 5, and 7. Each of the potentiometers has one end of its resis-tance element connected to the VREF supply, and the other 3o end of the resistance element grounded. The wiper of each potentiometer is connected to an input terminal of one of the multiplexers 166 and 168 which may be, for example, a type CD4051B. Thus, each of the potentiometers provides an analog voltage signal to its appropriate multiplexer input terminal. These i~nput terminals are selected by a three-bit address line ~ plus an INHIBIT line 216 con--49~001i 49,002; ~,004, 49,00~ 9,00~; 49,010; 49,013;
~ ~ 49,048; 49,049i 49.050 nected ~o port 2 of the microprocessor.
The two-position switches l0~, 104 and 106 correspond respectively to I T IN/OUT switches for phase current and ground current, and a TRIP/NO TRIP function for the test mode. As can be seen, these switches serve to construct a variable voltage divicler between VREF and ground which provides any of six analog voltage values to a terminal of the multiplexer 168. In a similar manner, the pushbutton switches 107, 105, 128 and 130 correspond-ing respectively to DISPLAY RESET, DEMAND RESET, PHASETEST, and GROUND TEST, serve to place any of eight analog voltage signals on another terminal of the multiplexer 16~.
D. Style_Number Designator Figure 8 shows in detail the style number desig-nator circuit 170 shown in Fig. 8. Each four-digit: deci-mal style number e~r~e4e~ ~ dg~ to a particular option combination~ As can be seen in Fig. 8, the style desig-nator circuit provides input to four terminals of multi-plexer 158. Each of these terminals represents one digit of the decimal style number and may be connected to any of four positions on a voltage divider formed by the resist-ors 218, 220, and 222 connected between ground and VREF.
These connections are selected and made by jumper connec-tions wired at the factory to provide each of the termin-als of multiplexer 158 with any of four possible analog voltage signal values. The multiplexer 158, on command, then supplies these values to the ADC 156 which converts them to the 8-bit digital code which is read by the micro-~0 computer and interpreted as the style number, allowing the microcomputer to determine which of the many option com-binations for the trip unit 26 are actually present in that particular trip unit.
E. Remote Indicator And Power Supply - 35 The data input/output system 174 supplies pulse coded output signals, over a single optically coupled pair 5~;35 o~ w$res, to the Remote Indicator 145 sho~ ~ Flg. 9 pro-~riding a remote indioation that the load being supplied uBl the circuit breaker has exce~ded a predete~ned power limit. In addlt~on, csuse-of-tr~p indicatlons of 5 c~rercurrent, short circuit, or ground fault are pravided.
~he circult to be de~cribed decodes the corre~ponding ~our lnput slgnals to provide both LED indlcations and relsy c108u2~39.
In additlon, the circuit provide~ a re~ote 80U~C8 of' power, from both the AC line and fro~ batteries, 10 to the power supply 144. l~hi8 capabill~ ls needed ln tho~e applications wllich require continuous r~tentlon o~e data 3~0h as cause-oî-trip ~ndicators and energy ~unctl<~ns $noludirg megawatt-hour~ and peak demancl power.
~ As can be seen in Figure 9, input power i~ 8Up~
plled throu~h a tr~nsformer 602, rect1fier clrcult 604;
~nd ~ilter ~apacitor 606 at a level of approximately 32 ~olts~ A currant limlting resi~tor 60~ i~ provided to protect aga~nst accidental shortlng of the output termin~l 610. Term~nal 610 i5 connected to the EX~ERNAL DC INPU~
148 ~Figure 2) ~nd terminal 612 18 connected to the digl-tsl grou~d termlnal of the trlp unit 26. I~ a ~umper i~
co~cted betwaen te~minal 610 ~nd terminal 614, the three internal 8-volt nic~el-cadmium batterlss 616 can be acti-~at~d to ~upport the output voltage at 24 volts, should the AC input ~oltage be lnterrupted. A 10 K "trickle charge~ resl~tor 618 ~ proY~ded for battery chargi~g.
An 8.2 volt power ~upply l~ pro~ided by res1stor 620, Zoner diode 622, and capac$tor 624 for the decodl~g and alarm clrcuit.
The data I/O output tQrminal 508 of Figur~ 14 labelled R~mote Indicator Out i8 connected to termin~l 626 o~ Flgure 9, and th~ I/O COMMON terminal 500 o~ Figure 14 i~
connected to terminal 628 of Flgure 9, The 100 mlcro-second, 4 volt output pul~es applied to term~nals ~26 and 628 produce an 8 milllampere current flow through the optical coupler 630. Thi3 current turns on the coupler 53.5 . .
49,001; 49,002; 4~,00~; 49,006; ~9,009; 49,010; 49,013;
~/ 49,048; 49,049, 49,050 ". ~
transistor which produces an 8 volt pulse across resistor 632.
The microcomputer 154 can produce one 100 micro-second pulse every two millisecon~s, or a maxi~um of eight pulses per cycle of AC power. A coding technique is used, with one pulse out of eight denoting a DEMAND alarm. If a trip has occurred, two consecutive pulses out of eight denote a ground fault trip, three consecutive pulses out of eight denote overcurrent (long delay) trip, and five consecutive pulses out of eight denote a short circuit (either instantaneous or short delay) trip condition. The ~ s ~ ~f~r pulse coding scheme is shownJin Figure 10.
~ he input pulses provide trigger inputs for a retriggerable 3 millisecond monostable flip-flop output Ql of integrated circuit 634 which may bel for example) an RCA CD4098 device. The retriggerable feature means that any pulse which occurs during the 3 millisecond timing interval will cause a new 3 millisecond interval to start.
Waveforms B of ~igure 10 show the resulting Q1 output for one, two, three, and four consecutive input pulsès, corre-sponding to a DEMAND ALARM, a ground fault trip, a long delay trip, and a short circuit trip, respectively. The amplitude of the Ql pulses is equal to the supply voltage supplied to the integrated circuit 634. When the Ql output is averaged by resistor 636 and capacitors 638, a DC voltage C is produced whose value is the following fraction of the supply voltage;either 3/16 volts, 5/16 volts, 7/16 volts, or 11/16 volts, rèspectively. This value is fed to the inverting input terminals of quad comparator 640 which compare the filtered value C to fixed fractions of the supply voltage of 1/8 volts, 1/4 volts, 3/8 volts, and 9/16 volts, which are developed by the divider network including resistors 642, 644, 646, 648, and 650. The comparator then provides outputs which indicate which of four possible pulse patterns were ap-plied at input terminals 626 and 628. If, for example, a f ~;r~3 5 49,001; 49~002; 49,004; 49,006; ~9,009; 49,010; 49,013;
49,048; 49,0~9; 49,050 3~

DEMAND condition exists, producing a pulse pattern of one out of eight pulses, the DC voltage at the inverting terminal of comparator A of 640 will be 3/16 of the supply volts, which is greater than 1/8 of the supply volts but smaller than 1/4 of the supply volts. As a result, the output terminal of comparator A will be LO while other inputs willJ HIGH. Transistor 652 and relay 654 will be turned on by current flow through resistor 656 which also lights the demand LED 658.
An overcurrent trip condition will cause three consecutive pulses to appear at the input terminals 626 and 628, and an averaged value of 7/16 of the supply will appear at the inverting terminals of the co~lparators of 640. This value is greater than 3/8 of the supply volts but less than 5/8 of the supply volts In this case, the output terminals of comparators A, B, and C will be LO. Transistor 660 and relay 662 will be on, because of current flow through the over~urrent LED 664 and re-sistor 666. Transistor 652 and the DEMAND LED will be off because of the shorting effect of transistor 668. The GROUND LED 670 is also off because of the shorting effect of the OVERCURRENT LED 664. In this way, the highest level comparison always dominates. A function of inte-grated circuit 672~which may be, for example, an RCA type CD040)and Ql is to provide a 1/2 second ON delay for the comparators, which is required to allow the ~oltage on capacitor 638 to stabilize. The Ql pulses occur every 1/60 seconds. These are counted by counter 672 until thirty-two pulses occur and output Q6 goes HIGH. At this time, output Ql is turned on, and additional pulse inputs are inhibited by diode 674.
Approximately 30 milliseconds after the last pulse is received by optical isolator 630, the Q~ terminal of the retriggerable monostable flip-flop 634 will go HIGH. This resets the output Q6 of 672 and turns Ql off.
The function of counter 672 and Ql is to provide positive ~ S
on~o~f operation of the LED indicators and the ALARM/LOCK-OUT and DEMAND RELAYS 662 and 654.
F. ~ata In~ut/Out~ut S~stem and Associated Power Supply As hereinbefore explained, it is contemplated that a cirouit breaker employlng the principles of ths pre~ent invention will be employed in ~n el~ctrical dis-tribution ~ystem ~n coordinatlon with a number of other circui~ breakers. It i~ sometimes deslred that various command~ and information be sent ~rom th~s circult breaker and that varlous para~eters 3ent by other a~sociated breakers ~e sensed by thi~ breaker. This information ls u~ed to construct thP desired interlocking ~cheme as speci~ied by the system architect or designer.
The Data I~O System, shown in detall in Fig~ 14, lnclude~ ~our output line~: 5hort Delay Interlock Out 502, Ground Interlock ~ut 504, Ser~l Out 506, and Remote Indlcator Out 508~
m ree lnput terminals are also provided: Short Delay Interlock In 510, Ground Interlock in 512, and Serial In 514. The Serial Out and Serial In terminal~ are us~d to co~municate digital data between the microcomputer 154 and a remote dig~tal clrcuit. The Remote Indicator Out terminal provides a o~e-o~-~our coded pulse output for cau~e-of-trip indication (overcurrent, short circuit, or ground)9 and peak demand alarm indication to the Remote Indicator, as described ln Section IIIF. The ~nput and output ~nterlock terminals allow direct interlock connec-t~ons between breakers w~thout any additional components.
I~ typlc 1 optical coupling circ~itry were used, 400 mllllwatts of power ~ould be requlred (12 milllamperes at 5 VDC for e~ch of seven l~nes). me power whlch th~
current transformer~ 24 are capable of supplying ls only about 500 mill~watts (100 milliamperes at 5 VDC), most of which is required by the microcomputer 154. Conventional optical coupllng circultry thus cannot be used.
me power supply for the data input~output sys-tem 174 includes a pulse transformer 501 connected through a transistor 228 to lins 7 of port 1, indicated as 178 in 5;~

Figures 2 ~nd 14. 1~ ~crocomputer provldes a lOt) mlcrosecond pul~e every 2000 ~icros~conda, a8 coDImanded in the common dl~play ~ubroutine~ th~reby reduc~slg the power supply r~qulr~-~nt o~ th~ data ~nput~out~ut ~y~tem 174 by a ~actor Or n~arly 20 to 1, or about 20 ~illiwatta (4 D~illia~peres ~verage at S V~C). q~hi.3 i8 sDIall enou~h to be ea~ily suppliod ~rom the pow~r ~pply 144.
T~2 wa,r~forms app~aring ln the power ~pply 176 are shown ~n Fi~ lS. Wave~orm A i8 that goIl~rat~d on line 7 o~ port 1 by the ~icrocomput~r 154. For approxi-~ately 100 ~lcro~econds out o~ sbout ~very 200D ~lcro~ec-onds (actually 1~8 x 1/60 ~econds) line 7 o~ port 1 18 held low at mlcrocomputer circult ground. Thl8 turn8 on - tran~1stor 228, ~hereby applying ~5 volt~ to the input o~
tran~or~er 50~, ~8 Been $n ~ave~or~ B of Figur~ 15. A
corresponding waveform i9 prod~ced on the output termlnal of trAn~ormer 501 relative to ~h~ 3ystem co~mon terminal of the ~ata lnput/output sy~tem 174~
I~ ~n output ~s desired from, ~or example, the R~ot~ Indicator Out ter~inal 508, the corre~ponding ~lcrocomputer output llne, line 3 of the data bu~ 172 18 held at clrcuit ground, aY ~ho~n in wave~orm C ~n Figure 15. L~d 516 ~ turned on by current flow through trans~s-tor 228. m e phototran~lstor 517 then turn~ tran~stor 518 on, produclng output ~oltag~ wa~orm D~ I~ lino 3 o~
data bu~ 172 (wav~orm C) is HICH, then the corrospo~d~ng ou~put iro~ tran~lstor 518 18 zero, a~ ~hown by wa~efor~ D.
The lnput c~rcuitry l~ des~g~sd to work ~lth both a dlrectly coupl~d ~C 81~n~l ~rom an older clrcu~t ~reaker, or ~ pul8e ~nput Juch a~ th~t pr~v~ou~ly d~scrlbed ln thl~ ~ect$on. An lnput dgnal at, ~or ~xE2ple~ ~he Serl~ ~nput t~ al 514 a8 aho~ ln wa~rofor~ 13, ~rlll ~150 Qppear a~ gat~ o~ FET 236, a~- ~hown ln waverorm F.
the pulse ~olt~ge appear~ at the output o~ pul~e tran~rormer 501 curren~ will nOw ~n LED 23Bg ~nd then through FET 236 which has been tu~ned on ~y the input 3S35i signal at the Serial Input terminal 514. The FET 236 has a turn-on gate voltage of 2.5 volts and internal gate-to-source 15 volt Zener diode protection. This range is required to meet the 4 volt pulse input provided by a microcomputer type circuit and a 12 volt DC signal pro-vided by the older type of solid state trip unit.
FET 236 provides two functions. First, it pro-vides a memory element when the input signal is a pulse.
It does this in connection with the capacitor 232 which is charged through resist~r 230 by the 100 microsecond input pulse. The values of capacitor 232 and resistor 230 are chosen so as to give a 15 microsecond time constant.
Capacitor 232 discharges through resistor 23~, sized to give a 10 millisecond time constant. The capacitor 237.
.
cannot discharge through 230, since the input signal is provided by ~he emitter of an NPN transistor. Thus, the gate of transistor 236 is held high as long as input pulses occur every two milliseconds. Approximately 10 milliseconds after the input pulses disappear, transistor 236 will be turned off.
The second purpose of transistor 236 is cuxrent gain. The optical coupler 226 requires nèarly 10 milli-amperes to turn the associated phototransistor on. This current is provided by transistor 236 The high DC input impedance at the input terminal is required, since the older trip unit control circuits can provide only a small DC input current.
The presence or lack of an input signal on terminal 514 is read by the microcomputer at line 0 of the data bus, waveform G, which is high during the 100 microsecond pulse period if, and only if, an input signal is present at the ter-minal 514. A pull-down resistor 237 is provided to maintain the data bus lines connected to the data input terminals at circuit ground when no input signal is present at the terminal 514. In this manner, a signal from a circuit breaker, emergency power generator, or other associated ` ' l~.~.s~353S

comp~n~nt o~ the el~ctric~l pow~r di3tribution ~y~tem can b~ ~ensed by the microcomput~r 154 and the circuit brea~er 10 can be comm~nded to perfor~ appropriate actlon. Fur-tl~er~ore, parameter va}ues c~n al~o be ~upplled, through 5 t~he gERIAL IN ter~ln~l 514, from a remote locatlon. A~-propriate in~tructions ln ROM then decode the lncoming in~oro~ation ar~d stor~ lt ln RAM ~or u8e by the li~nlt checklng functlon~.
G. ~S~
1. Block DlagraD~ Dcscripti~n l~e power 3t~pply 144 of Fig. 2 is shown i~ block dl~gra~ ~os~m in Flg. 11. It can be powered by one of ~our 80UrC~8: extornal ~ or DC volt~ge, the Remote Indlcator 145 o~ Fig. 2, current l~put ~rom ~ ground current detec-tion trAn3~0rmer 2~, or curr~nt input from the three phaBe current me~surlng tran~or~ers 24.
The rectlfi~d output o~ the ~xternal AC ~ouro~
i8 comp~r~d to the DC voltage ~rom the Remot~ Indlcator and the large~t lnstantan~ou~ value is suppll~d by the auctio~e~r circult 702 to the power 8upply~5 energy ~tor-~g~ capacltor 704 ~or u~e by the DC-to-DC converter 706 and ~h~ trlp coil 22. A voltage sen~ing clrcult 708 monitors the output Or the volt~ge ~uctioneerlng circuit 702. WheneYer th~s voltage l~ greater than 22 ~DC the DC-to-DC converter 706 i8 turned ON. A ~crowb~r~ current ~witch 710 i~ thrown to position ~2) when the voltage exceeds 24 VDC. me converter 706 provides the 5 VIC Rupply (at 100 ~A) ~or the mlcrocomputcr clrcult, a reference Yoltage VREF
(1.64 VDC) and ~ power ON reset control ~lgnal RS, The unlt can al~o be powered by either the rectlfi~d output of th~ ground currant tran8~0~r or the currcnt ~uctloneered, rectified output, oi ~h~ three pha~
curre~t transrorm~rs 24. me two current~ are swmmsd at 712 and ~ed to the ncrowbar" 710 whlch pa88~3 the current either into the energy storage capacitor 704 or a current b~pas~ 714. Currsnt ~lows lnto the capaci-~3 49,049 tor 704 until the c~pacitor voltage reaches about 39 VDC, at which point the "crowbar" 710 -trans~ers -the current to the by-pass circuit 714. Current by-passing con-tinues un-til the voltage on the capacitor 704 ~rops to about 34 VDC
and the switch 710 again causes the current to flow into the capacitor~
2. Circuit Description The power supply 144 is sho~m ln greater detall in Fig. 12, The external ~C input is recti~ied by BR201 ~0 and compared to the external DC input. me result is ~ed through D101 to energy storage capacitors C105 and C112.
The sensed voltage is also fed to the crowbar circuit formed by the power field effect transistor Q101 and gates A and B (connected as inverters) of quad NAND c:ircuit 1C101. The quad NAND circui-t is powered by current flow through R103~ D107~ D10~ and D109, which produc0s a t;empera-ture s-tahilized voltage o~ about 10 VDC for pin 14 o~ IC101D.
The quad NAND ha~ i~put hysteresis which causes the ou~put to go LOW when the lnputs exceed about 70~a Of the ~upply ~oltage ~0 (7 VDC). The output then stay~ low until the inputs drop to 30~ of the supply voltage (3 VDC). Thus the crow~ar ~s turned ON when 7 VDC appears across R105 which corresponds to 24 VDC at the external DC input (7 VIC plus drop across R104, R102, and D1033. It ~ill be noted that the crowbar can also be turned ON if the voltage across the energy storage capacitor 704 exceeds 39 VDC.
I~ external power is available, then the on-off status o~ the converter 706 is controlled by the external power supply voltage, rather than the storage capacitor voltage.
me 24 VDC switching point for the external ~C
input corresponds to the minimum DC voltage required for the trip coil 22 to operate. The 39 VDC limit on the voltage across the energy storage capacitor is a compro mis~ between the 50 ~DC maxlmum limit of the oapacitor ~nd the 30 VDC minlmum input to the converter requirsd to produce 5 VDC out~put at 100 ~A DC with a ~lnimu~n current transformer out~put 32 o~A RMS.
~urrent shunt~ R1~ and R101 are u~ed 1:o ~ense ph~se ~d ground current respectively. It wlll be noted that current îlow through the resi~tors 18 through either Q101 (crowbar ON~ or C105 anà C112 ~crowbar OFF) and ~C~020 ~0 ~e requ$red 15 m~ econd tu~n-ofr delay of t~e ~5 VDC ~pply is achie~ed by mean3 of diode D110, resistor R107, and capacitor C102. ~hen the ~o~tage at plns 8 and 9 of IC101 drops below 3 V~ the out~put pin 10 goe~ higb. A ~5 millisecond delay ex$~ts ~e~ore pin 12 and 13 reaches 7 VDC~ At thi6 tlme pin 15 goes low c:au~-~ng ~he +5 VDC re~erence to go to zero.
m e voltage sensor 708 also provides ~n ONf~FF
control to the DC-t~DCconverter 706. The converter 70~
18 turned ON when the c~pacitor volt~ge reache~ 37 VDC and OFT when lt drops to 33 VDC. A 15 millisecond delay ln the O~F 3ign81 i~ used to lnsure that the mlcrocomputer 154 l~ ~N long enough to d~splay the pre3ent v~ue o~
pha8~ and ground current, eve~ when the output current from transform~rs 24 l~ too 3mall to ~aintain the opera-tiO~ 0~ COnVert~r 706, and tO ensUre the ~ainten~nCe Of a TRIP ~i Ba1 10ng enOUgh tO effeCt generatiOn Of the t:riP
COi1 22. NOte that the tr1P CO~ COntrO11ed bY nVn-1atChi~g FET 192, rather than a 1atChing deV1Ce ~uCh a8 the ScR~B U~ed 1n the PriOr art. Thl8 PrO~ide~ 1m~Un~tY
~rOm nU18anCe triP8 dUe tO e1eCtr~Ca1 tran8i~nt8, and Pr~Vent~ UndUC dra~n on the POWer gupply when OP~rat1ng POW~r i~ supplied by 8 batte~Y.
The ~WitCh1ng PO~nt8 Of the ON/O~F COntrO1 708 and CrOW bar 710 are shOwn in Fig. 13.
The COnVerter 706 ~ a ChOPPer tYPe COnSi8t1ng Of PNP dar11ngtOn S~itCh1ng tran~1~tOr IC102, indUctor L1O1, "free Whee1-i9~35 .' J~ ~ ~
49,049 ing" diode D112, and a voltage feedback reference formed by transistors Q103 and ~104. The voltage at the base of Q103 is ad~usted to be ~5 VDC by means o~ R109. This voltage is approximately 1/2 the temperat~re stabilized +10 VDC produced by D107, D108 and D109~
The circuit operates as follows. I~ the output voltage is below ~5 VDC, QlO3 will be ON and Q104 OFF.
The collector current of Q103 is the base current for the PNP darlington transistor IC102 which i.s then tu~ned ~)N.
~ith approximately +35 VDC applied to I.101 the current will rlse lin~arly~ The current will flow into C106 and the connected load~ When the output voltage exceeds +5 YrC, Q103 will be turned OFF and Q104 will be ~urned ON.
The collector current of Q104 turns on Q102 which clamps the base of IC102 causing it to be turned OFF rapidly. At this time, the current in L101 will switch from IC102 to diode D112~ The output voltage will begin to decrease until Q103 turns ON, Q104 turns OFF, and the process re~
peats itself. Hysteresis in the ON/OFF swi-tching results from natural over and under shoot assoclated with the L101 and C106 resonant network. Pos~tive switchlng ~eedback is provided by C10~ and R110. The switching points of the power supply 144 are shown in Fig. 13.
In addition to the ~5 VDC level, the power supply 144 also pro~ides a reference voltage VREF which is used by the microcomputer 154. In additional signal, a power-on reset signal for the microcomputer is provided by IC103 in combination R114, R115, R116 and C106. When the converter turns ON and ~5 VDC is produced, the RS line remains at circuit ground ~or about 5 milliseconds. This signal is applied to the microprocessor which is then reset. Diode D111 provides an immedia~e power-down reset as soon as the 5 VDC reference gO8S to zero, thereby assuring both a safe power-up and power~down transition.
H. Read-Onl~ Memory The internal microcomputer ROM 155 is supplied with !.3;:''~'~

49,001; ~,002, 49,0~4; 49,006; 49,00g; 49,010; 49,013;
49,048; 49,049; ~9,050 instructi~ns defining a series of eight major functions which are executed every cycle of AC current, that is, r~ every 16.667 ~ . Each function is responsible for retrieving one or more parameter values from outside the microcomputer~ These parameters include values ob-tained from the electrical circuit being protected, such as phase current and ground current J as well as values specified by the front panel potentiometers and switches.
The function then loads the parameter value into a speci-fied location in RAM. In addition, most of the functionsare also responsible for performing one or more limit checks; for example, comparing present phase current to the instantaneous trip pick-up value. Since the entire loop of eight functions is executed every 16.67 onds, each of the limit checks is performed at that rate.
In addition to the scanning and limit check duties, each function is responsible for two operations relating to the front panel numeric displays 80 and 82.
Every four seconds, one function reads a display parameter value from its assigned location in RAM. It then formats this parameter value into four digit values. For example, if the present phase current is equal to 2.14 per unit, the appropriate function would produce four digit values~
a blank, a two, a one, and a four. These digit values would then be placed into assigned locations in RAM, each location corresponding to one digit of the numeric display indicator 80. Generally, each function will so format two parameter values, thus loading a total of eight digit values into corresponding RA*I locations. These digit values remain in RAM for four seconds until the next function performs its digit value loading duty.
At this point, the digit values are residing in RAM; they must now be sent to the appropriate digit of the numeric displays 80 and 82, the second operation performed by the eight main functions. Each function is responsi-ble, at each time it is executed, for retrieving one of the dig~t values ~rom RAM and sendinR t.his dlgit l~alue out ~ port 2 of the microco~ t~r 154 to the numerlc dlspla 80 or 82. q~ dlglt ~lralu2 then appears lighted in lt~
~ppropr~ate lc~catlon in the num~ric dl3plays. Slnce a new 5 i~unctlon ~ executed appr1:?xlmately e~ery 2 ~aillisaconds (160667/8 ~, the dlgit vallle wlll app~sr ~or thi~ gth o~ t~ne on the numerlc dinpldy before :lt i8 extlngulshed end the next digit ~ralue sent to a di~:ferent dîglt loc~-tll~n ~ e numeric displRy. At any glven time, there~ore, nly one d$git on~ o~ etB~t ts l~ghted on th~ nu~ner~c dt~;-plays 80 ~nd 82. ~owev~r, the d1gits :Elash 80 r~pldly that they appear t~ an obser~r to be 8imUl't~leOU8ly lighted.
qh~ ext~ l ROM 151 i~ optiona} and ~ay ~e u~sed to ~tore lnst~qlction3 to implement additional features 15 ~uch as other function~ relat~d to the data I/O system.
A180, the look-~ table for potentiometer settlng~ ~ay be ~torDd ln externsl ROM to ~c~lltate changes in the table lu~s.
me organlzation o~ the main lnstruction loop in ~0 ROM of the mlcrocomputer can be seen ln Flg. 17. q~he elght ~ain ~unctlons are nan~ lNCTx~ where x equals 1 through 8. ma ~ or ~ubroutin~s call~d ~rom the~e nmc-tlo~s ~re the co~on d::lsplay routine CMDIS, ~he an~log to digit~ con~ers~on routine ADCV1, the subroutlne to toggle ~5 bet~reen l~e two d~splay panel ~ultiplexer~ 166 ar~d 168 and perîorm ~he analog to digltal con~erslon T~CV, and ~e subroutl~e to obtain discret~ values irom the potentlo-~et~r ~ettings READ. me D~ unctlons, and the corrQ
~po~dlng ~ubro~tlnQs wlll ~ow be describ~d in greater d2tall.
9: ~e~
Thi8 eu~routine i~ c~ d by each ~Jor ~unct~on ~nd thus l~ executed e~e~y 2 ~llliseconds. It dl~plays one d~gitvalue, as addrs~sed by regi~ter R1' and per~or~s ananalog to dlgital con~ersion on one of the elght lnput l~ne~ of the multiplexer 158, as specified by register R6.

.*J~ S
,. ,~"
~,001; 4~,002; 4~004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,~49; 49,050 s ~/ ,2, CMDIS outputs one pulse of 100 microsecond duration on line 7 of port 1, to energize the data input/output power supply 176. A portion of CMDIS, called TADCV, switches between multiplexer 166 and 168 to read a potentiometer from the other side of the panel. In addition, CMDIS
completes a time delay to ensure that each major function executes in exactly 16.667/8 milliseconds.
Reference may now be made to Fig~ ~6 for a more detailed description of CMDIS. An internal counter is first checked to determine if the 16.667 ms/8 execution time window has expired. If not, the subroutine loops until the window does expire. The counter is then reset.
Next, line 7 of port 1 is activated to perform two functions. The analog-to-digital converter Chip Select terminal is deactivated by this line. This :Line is also connected to transistor 228 of the data input/output power supply. Thus, activation of line 7 of port 1 con-stitutes the leading edge of an approximately 100 micro-second pulse for the data I/O power supply~
Pre-existing alarm conditions are now checked to determine if a pulse should be sent out on the serial output terminal of the optically coupled data input/output circuitry 174. As previously described, the serial output feature provides a pulse coded signal over a 16.667 milli-second time window to inform the remote indicator of possible alarm or trip conditions.
Register 6 is now incremented to obtain the channel address for the next input line of the multiplexer 158 to be accessed. Register 1 is now decremented to obtain the address of the next digit value ~or display.
Using register Rl as an address pointer, one of the eight digit values is now retrieved from RAM and prepared for dispatching to the numeric display indicat-ors. Since the digit value only requires four bits, the upper four bits are used to properly set up the Latch Enable line 5 of port 2 and the inhibit line 7 of port 2 , .

t3S35 :;
49,001; 49,002; 49l004; 49,006; 49,~09; 49~010; 4g,013;
~ 49,0L~8; 49,049; 49,050 . . ~.
212. The LED indicator 84, 86, 88, 90, 92, 94, 96, 98 or 100 corresponding to the parameter now being displayed is controlled by bit 6 of port 2. The corresponding bit in the digit value being displayed is set or reset by the SRACE subroutine in ~UNCTl. This con~rol information and the digit value are then sent out on port 2 to the latch deeoder 194 of the display system 155. /~G or/~
The channel address for the multiplexer ~ as contained in register 6 is now sen~ out on port 2. The lG analog to digital conversion routine ADCV1 is exec~ted, and the digital value of the input to the multiplexer 158 is stored in register 3 and in the accumulator.
FUNCTl ~ ure 18 This function first initializes register Rl with an address one greater than the address of DIGITl, the digit value which will be displayed in the rightmost position of the numeric displays 80 and 82 tWhich will be decremented by CMDIS before used). It also initializes register R6 with the first channel address to be accessed by the multiplexer 158.
Subroutine SRACE is entered next. This subrou-tine increments a four second counter. If this counter overflows from a hex value of FF to zero, this indicates that the four-second display period has elapsed, and it is time~ to command a new pair of values to appear on the numeric indicators 80 and 82. This is done by shifting the register R7. Next, SRACE sets bit 6 in one of the eight digit value RAM locations so that the appropriate LED indicator corresponding to the parameters being dis-3~ played will be lighted.
The common display routine CMDIS is now called.Upon completion, DIGIT1, the rightmost digit of the numer-ic display 82, will be lighted and the present phase current will have been read and processed by the ADC 156. 5 The present phase current value is now stored in RAM.
Index register R7 is now checked to determine if 3S;~S

it i~ time to display the present phase current value on the ~ront p~el Ylumerlc dl~play indicator 80. If ~o, the Yalue o~ present pha8~ current 1~ formatted into ~our ~iglt v~lu~s, ~nd ~ach oî these digit valu~s ~tored in the ~e~osy loclltions DIGIT8, I:I&Iq~7, DIGIT6, AND DIaI$5 in RA~I
corr~pondlng to the leftmo~t di~play digits, that :LB, tho dlgit~ of the numerlc lnd~cator 8C). me present ground current i8 al~o ~o~atted into ~our digit YaluesO l~eso dlgit ~alues are stored ~n the R~M locstions DIGIT4, DIGIT3, DICIT2, ar~d DIGIT1 corres~onding to the v~lues ol ~e righ1;mo~t dlgit~, that ls, the four digit~ of the ~umeric display 82.
Next~ ~eriQ} data I~I operation~ are perfor~d, if call~d Ior, ~nd the ~relue of phase current used ior the ~5 long d~lay ~nct~n l~ read. In order to~telin a ~ilue ha~ing twice the r~30lution o~ the ~dard v~lue o~ pre-~nt phla~e current, t:he rofere~ ce ~oltage suppli~d to thfl ~DC 156 i~ adJusted ~ria lln~ 6 o~ port 1. Th~ ADC ~ now co~and~d tG a~ain oon~rert the v~lue of the peak detector 160 a~ ~upplicd throu~h the multlplexer 158. Followlng the ~on~plotion o~ ~he analog-to-digital conver~ion, the cap~citor o~ phase c~lrrent poak detector 160 is r~set by grounding the output o~ the D~ultlpl~xer 158 thrc~ug~ F13T
186, as con~ndad ~ line 5 o~ port 1. ~he value of long d~lay pha~e current i8 now ~tor~d ~n RAM.
FUNCT1 now send~ a channel addre~ to the ~ultl-plexer 158 ~ port 1 to select the ground current pe~k detector 162. me analog to d~gltal conver~ion rout~ne ADC~I 1 1~ called to read the ground c~ent and convert lt to a dlgital Y lue. The ground current pea~ detector capacitor l now re~et.
~t hig~er l~v~18 OI phase current, l~he grous~d curr~nt trans~or~ner 28 can gen~rate ~ictltlous ~ralu~ o~
ground current when no ~uch v~lue, in f~ct, oxl~t~. IhiA
effect i3 ~ore notlceable a~ pha3e current ~ncreasas.
Therefore, the fictitiou~ ground current i~ accounted for by reducing the value of ground current to be ~tored in 3~
~9,001; 49,002; 49,00~; 49,006; 49,0~9; 49,010; 49,013;
LtS 49,0~8; 49,049; 49,050 R~M by a factor of 1/8 of the phase current whenever the phase current is between 1.5 per unit and 9 per unit. If the present value of phase current is greater than 9 per unit, the ground current is neglected, by zeroing the present ground current, ~-~ appropriate value of ground current is now stored in RAM.
FUNCT2- F~ure .L9 This function determines the average phase cur-rent, performs energy calculationsl and determines the style number of the trip unit 126. First, the multiplexer 158 is supplied an address via port 1, as indexed by register R6 to cause the averaging circuit 164 to supply an analog value to the ADC 156. The common display rou-tine is now called, causing DIGIT2, the second di~it from the right on the numeric display indicator 82, to be lighted, and a digital value for the average phase current to be supplied. The value of average phase current is next multiplied by the product of power factor tim~s line ~voltage3 as specified by the front panel potentiometer :20 110. The result is the Present Kilowatt value, PRKW.
This value is temporarily stored and is also added to the megawatthour tally. A check is next made to determine if PRKW is greater than the peak kilowatt value registered since the last actuation of the Kilowatt Reset pushbutton (P~,A ~ k h~)~
105~ If PR~W is greater, the peak accumulated kilowatt value is set equal to PRKW, and both values stored in RAM.
A check is next made on register R7 to determine if it is time to display the present kilowatt and mega-watthour values on the numeric displays 80 and 82. If so, these quantities are formatted into four digit values apiece and loaded into the digit value storage locations in RAM.
An address is now generated to the multiplexer :158 to select the style number designator 170 to be sup-plied to the ADC 156. An A to D conversion is now made on the style number and this value stored in RAM, to desig-~9,001; 49,002; 49,004; ~9,006; 49,009; 49,010; 49,013;
49,048; 49,0~9; 49,050 ~/~

4~
nate which of several optional features are included in the present trip unit and to select execution of the appropriate instructions farther down in ROM.
FUNCT3_- Figure 20 The first task of this function is to reset the number of pulses to be sent out over the serial output terminal. This information will later be used by the common display program to produce the proper pulse code on serial output. The common display routine is now exe-cuted, to light DIGIT3, the third digit from the right on the numeric displays and return a digital value from the Peak Kilowatt setting potentiometer 108.
Next, a flag is set to prevent an extraneous pulse from being sent on the serial output terminal. The READ routine is then executed to obtain one of eight discrete values for the Peak Kilowatt setting as specified by the corresponding potentiometer 108. This routine will be later described in greater detail.
A check is now made to determine if it is time to display the Peak Kilowatt setting on the numeric indi-cator 80. If so, the value of Peak Kilowatt setting as determined by the REA~ routine is formatted into four digit values and stored in the digit value locations in RAM corresponding to the digits of the numeric display 80.
A running tally of kilowatts is maintained in RAM. This tally is incremented by the present kilowatt value on every execution of FUNCT3, thus integrating the kilowatt values over time, producing a value corresponding to kilowatt hours. A check is now made of this location in RAM to determine if a value corresponding to 10 kilo-watthours has been reached. If so, a megawatthour tally in RAM is incremented and the kilowatthour tally reset retaining the remainder. A check is made to determine if it is time to display the contents of the megawatthour ~5 tally on the display. If so, this quantity is formatted into four digit values and stored in the digit value ~ ", .,i~
~9,00l; ~9,0V2; 49,004; 49,006; 49,009; ~9,010; 49,013;
L/ 7 49,048; ~9,049; 49,050 . ~
locations in RAM corresponding to the numeric display 82.
Line 3 of port 2 is now activated to select multiplexer 166 and deselect multiplexer 168 as an input to multiplexer 158. An analog to digital conversion i5

5 now made on the panel switches 102, 104, and 106, and a digital value unique to each combination of switch set-tings stored in RAM.
FUNCT4 - Figure 21 The first task of FUNCT4 is to call the common display routine to light DIGIT4, the fourth digit from the right on the numeric display indicator 82, and read the PFxLV potentiometer 110 and return a digital value there-from. The READ routine is now called to obtain the look-up table value corresponding to the digital value of the PFxI.V potentiometer 110. If it is time to display the PFxLV value, it is formatted into four digit values and stored in the RAM locations corresponding to numeric display indicator 80.
Line 3 of port 2 now selects multiplexer 166 as 20 input through multiplexer 158 to the A~C 156, and an analog to digital conversion is ordered on the voltage divider network which includes the pushbutton switches 105, 107, 128, and 130. A unique digital value corre-sponding to the pattern of pushbuttons now depressed is stored in RAM. This quantity is also checked to determine if any pushbuttons have indeed been pressed. If none, then FUNCT5 is entered. Otherwise, a check is made to determine if the kilowatt reset pushbutton 105 has been pressed. If so, the value of peak kilowatts in RAM is 3o cleared. Next, a check is made to determine if the system reset pushbutton 107 has been pressed. If so, all trip indicators are cleared, the serial output pulse codes are zeroed, the display sequence is reset, and the interrupt is enabled. If the system reset button is not being pressed, then one of the test pushbuttons 128 and 130 is.
The digital value of the pushbutton read through the ` .

, 49,001; 49~002; 49,00~; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 4/~-multiplexers 166 and 158 is now stored in a test flag.~UNCT5 - Figure 22 The common display routine is called to light DIGIT5, the fifth digit from the right, and to read the instantaneous current pick-up poten~iometer 112. The READ
routine takes the digital value of the potentiometer set-ting supplied by the common display routine and obtains the actual setting from the look-up table in ROM. A check is now made to determine if it is time to display the in-stantaneous current pick-up setting on the numeric indi-cator 80. If so, the instantaneous pick-up value is for-matted into four digit values and stored in RAM locations corresponding to the digits of the numeric indicator 80.
The TEST potentiometer 120 is IIOW read through the multiplexers 168 and 158 and a digital value obtained.
I'he digital value previously obtained from scann:ing the front panel switches is now checked to determine if the switch 106 is in the TRIP position. If so, a fixed value is loaded into the RAM location where the value of the TEST potentiometer 120 would normally be stored. This fixed value is interpreted as either ~ per unit for phase current or 1.5 per unit for ground current, at a later point in the execution of the test. If the switch 106 is in the NO TRIP position, a check is next made to determine if more than one pushbutton is pressed. This is an illegal conditlon, and no test will be performed. If it is determined that only one pushbutton is pressed, a check is made to see which one it is. If the GROUND TEST
pushbutton 130 is pressed, a check is made to determine if the value of the TEST potentiometer 120 as stored in RAM
is greater than or equal to the present value of ground current. If it is not, this means that the actual value of ground current now being detected by the system is greater than the value of ground current simulated by the potentiometer 120. Thus, no test will be performed and the trip unit will execute the standard ground current s~s 49,001; ~9,002; ~9,00~; 49,006; 49,009; 49,010; 49,013;
49,048; 49~0~9; 49,050 / ~

limit checks. If the value of the TEST potentiometer 120 as stored in RAM is greater than the present valuer~of ground current, then indexes are set to turn on the ~ST
LED 100, the value of the TEST potentiometer 120 is for-matted into four digit values and stored in the RAM loca-tions corresponding to the digits of the numeric indicator 82, and the display of the numeric indicator 82 frozen.
If the PHASE TEST pushbutton 128 is pressed, a check is made to determine if the value of the TEST poten-tiometer 120 as stored in RAM is greater than the presentphase current. If it is not, then the actual value of phase current is more critical than the simulated test value, and no test will be performed. Instead, the normal limit checks on the present phase current will be executed by the system. If the simulated test value of phase current i5 greater than the present value of phase cur-rent, then an index is set to turn on the TEST L,ED 100, the value of the TEST potentiometer 120 is formatted into four digit values and stored in RAM locations correspond-ing to the digits of the numeric indicator 80, and anindex set to freeze the numeric indicator 80.
A check is now made to determine if the test flag is equal to the bit pattern produced by scanning the pushbuttons. If it is, this indicates that the TEST push-button is still being depressed. Since a test is not tobe initiated until the button is released, no test will be performed at this time. lf the test fla~ value is differ-ent from the pushbutton value, a check is made to deter-mine if the PHASE TEST pushbutton 128 had been pressed.
3o If so, the value of the TEST potentiometer 120 is stored in the RAM locations corresponding to present pnase cur-rent and long delay phase current. If the GROUND TEST
button had been pressed, then the value of the TEST po-tentiometer 120 is stored in the RAM location correspond-ing to the present ground current value. This completesthe portion of the testing function incorporated in func-49,001; 49, 002; 49,004; 4~,006; 49,009; ~-9,010; 49,013;
~9, 048; 49,049; 49,050 O

tion 5.
Next, the present value of phase current is com-pared to the instantaneous current pick-up as specified by the potentiometer 112. If the present value of phase current is below this value, then function 6 is immediate-ly entered. If the present value of phase current is greater than the instantaneous current pick-up level, an ; index is set to caùse the common display subroutine to put out a pattern of pulses on the serial output terminal to indicate that an instantaneous trip has occurred and the TRIP subroutine is called, as will be explained in a later section.
FUNCT6 - Figure 23 The common display routine is executed to light DIGIT6, and read and convert the long delay pick-up poten-tiometer 114. The digital value of this potentiometer is now acted upon by the READ routine to obtain the table look-up value. If it is time to clisplay the long delay pick-up value on the numeric indicators, the long delay pick up value is formatted into four digit values and stored in the RAM locations corresponding to the digits of the numeric indicator 80. Next, the long delay time potentiometer 122 is scanned and converted to a digital value, and acted on by the READ routine to obtain the table look-up value for the long delay time function.
The long delay limit check is now made, by first comparing the long delay phase current to the long delay pick-up value. If the long delay phase current is not greater than the long delay pick-up, then the long delay tally is reduced by the square of the difference beween the long delay pick-up setting and the long delay phase current. FUNCT7 is then entered.
If the long delay phase current is greater than the long delay pick-up value, then the long delay tally is 3~ incremented by the square of the long delay phase current.
A check is now made to determine if the long delay tally ~9,aOl; 49,00~; 49,004; 4~,006; 49,009; 49,010; 49,013;
~ 9,048; ~9,049; 49,050 is greater than the value of long delay tally specified for a long delay trip. If not, FUNCT7 is then entered.
If the current value of the tally is greater than the trip level, a code is stored in RAM to cause the common display program to generate the proper pulse code over the serial output terminal to indicate a long delay trip. Next, the TRIP subroutine is called, and ~he long delay tally clear-ed. FUNCT7 is then entered.
FUNCT7 - Figure 24 The common display program is called to light DIGIT7 and obtain a digital value for the setting of the short delay pick-up potentiometer 116. The READ routine is then called to obtain the proper table look-up value for short delay pick-up corresponding to the digital value scanned from the potentiometer. A check is made to deter-mine if it is time to displa~ the short delay pick-up function. If so, the short delay pick-up value is for-matted into four digit values and stored in the RAM loca-tions corresponding to the digits of numeric display indicator 80.
Line 3 of port 2 is now activated to select multiplexer 166, scan the short delay time potentiometer 124, and obtain a digital value therefrom. The table look-up value for short delay time is then obtained through the READ routine. If it is now time to display the short delay time value, the short delay time value is formatted into four digit values and stored in the RAM
locations for display as digits 1 through 4 in numeric display 82.
The short delay limit value check is now per-formed, by first comparing the present phase current to the short delay pick-up setting. If the pick-up setting is not exceeded, then the short delay tally is cleared and FUNCT8 entered.
If the present phase current is greater than the short delay pick-up value, the RAM location corresponding .. ..

3~i ~.~, .
49,001; i~9,002; ~9,004; 49,006; ~9,009; ~9,Q10; 49,013;
5~ 49,048; 49,049; 49,050 to the pattern vf switches 102, 104 and 106 is checked to determine if the short delay I2T function is called for, via the switch 102. If so, the square of the present phase current is added to the short delay tally, and the new value of the short delay tally compared to the short delay tally trip level. If the trip level is exceeded, pulse code for serial out and remote indicator is stored and the TRIP subroutine is called. If the tally trip level is not exceeded, then FUNCT8 is entered.
If the I2T function was not specified for the short delay test, then the present phase current value is added to the short delay tally and a comparison made to determine if the new value of the short delay tally now exceeds the short delay tally trip level. If not, FU~CT8 is immediately entered. If the tally trip level :is ex-ceeded, the pulse code for serial out and rernote indicat-ors is stored and TRIP routine is called before entering FUNCT8.
FUNCT8 - ~igure 25 The common display routine is called to light DIGIT8, the leftmost digit in numeric display indicator 80 and to scan and convert the ground fault pick-up potentio-meter 118. The look-up table value for ground fault pick-up corresponding to the digital value of the poten-tiometer 118 is then determined by the REA~ routine and stored in RAM. If it is now time to display the ground fault pick-up value, this quantity is formatted into four digit values and stored in the RAM locations corresponding to the four digits of the numeric indicator 80.
The ground fault time potentiometer 126 is now scanned and a digital value obtained therefor. The READ
routine then determines the look-up table value corre-sponding to the digital value for the potentiometer 126.
If it is time to display the ground fault time value~ this quantity is formatted into four digit values and stored in the RA~I locations corresponding to the four digits of the J. ~ i;3S
__ j,. S, 49,001; 49,~02; 49~04; 49,006; 49,009; 49,010; 49,013;
S ~ 49,048; 49,0~9; 49,050 numeric indicator 82.
A test is now made to determine if the present value of ground fault current is greater than the ground fault pick-up level. If not, an additional test is made to determine if the present value of ground fault current is greater than one-half of the ground fault pick-up level. If so, the ground fault interlock flag is set in RAM. The ground fault tally is then decremented and the loop returns to FUNCT1.
If the present value of ground fault current is ~4~ greater than the ground fault pick-up level, the location in RAM specifying the front panel switch pattern is then checked. If the ground fault I2T switch 104 is set, a quantity equal to 1.5 times the present value of ground fault current is added to the ground fault tally.
If the I T switch 104 is not set, then the ground fault tally is merely incremented.
Next, a check is made to determine if the ground fault tally is greater than the ground fault tîme limit value. If not, the main loop is entered once again at FUNCTl. If the tally is greater than the ground fault time, then a pulse code is stored to allow the proper pulse pattern to be transmitted on the serial output terminal, and the TRIP routine is called prior to return-ing to the top of the main loop at F~NCTl.TRIP - Figure 27 This subroutine is executed whenever electrical conditions on the circuit breaker excee~ the time-current characteristic limit values as entered through the front panel of the trip unit 26. The out-of-limit conditions are detected by the calling functions of the main loop instructions stored in the R0~.
The TRIP subroutine first checks the trip flag to determine if this trip condition was detected on a pre-vious execution of the main loop. If so, the next step isto set register R7 to freeze the numeric display. If this .
49,001; ~9,002; 49,004; 49,006; 49,009; 49l010; 49,013;
49,048; 49,049; 49,050 f is the first time the trip con~ition has been detected, then the trip flag is reset and the present value of phase current is loaded into the digit value locations in RAM
corresponding to the digits of numeric display 80. Next, bit 6 of the appropriate digit value location in RAM is set, to cause the proper LED to be liKhted on the front panel to display that function which caused the trip oper-ation. Note that when bit 6 of a digit value is sent out on port 2, line 6 of port 2 will be actuated when and only when the digit connected to the proper LED is lighted.
This will turn on the transistor 208, lighting the proper LED.
Register R7 is then set to freeze the numeric display and prevent any of the functions of the main loop from attempting to display a different quantity. 'rhe interrupt is now disabled ancl a check is made to determine if this call to the TRIP routine was the result of a test being performed; that is, as a result of the operator having pressed either the P~SE TEST button 128 or the GROUND TEST button 130. If so, a check is next made to determine if the switch 106 is in the NO TRIP position.
If so, the routine resets the test flag and four second timer and returns to the calling location.
If the switch 106 is in the TRIP position, or if the call to the TRIP subroutine was not caused by a test, then line 4 of port 1 is actuated. This sends a signal over the line 190 of Fig. 2 to the transi.,tor 192, actuat-ing the trip coil 22 and causing the contacts 18 to open.
The test flag and four second timer are reset and the 0 subroutine returns to the calling location.
READ - Figure 28 This subroutine performs a table look-up func-tion to allow the limit value setting potentiometers on the front panel of the trip unit 26 to select any of eight discrete values rather than a continuously variable out-put. In addition, the subroutine provides a hysteresis , S~:~5 s ~`J ~ 49,049 effect when adjusting the potentiometers to eliminate the undesirable variation of potentiometer values on ambient temperature and provide greater ease and convenience in adjustment, Upon entry to the RE~D routine, regi~ter RO
contains the address in R~l o~ the location where the parameter value being read will be stored, reglster R2 contains the beginning adclress of the table of eight values which can be selected by the potentiometer, and the aocumulator and register R3 both contain the digltal value o~ the voltage setting produced by the potentiometer, as supplied by the ADC 156.
A check is first made to determine i~ a tripping operation has already occurred. If so, the ~ubroutine is immediately exited~ Otherwise, the eight~blt digi~al value o~ the potentiometer voltage setting has it~ lower five bits stripped of~ and the three most signlficant digits rotated to become the least significant blts. The accumulator thus contains a binary number ha~in~ a decimal ~alue ~rom O to 7. This quantity is then added to the address of the beginning of the table, as stored in regis-ter R2, yielding the address in RAM of the table value selected by this particular adjustment of the potentio-meter. The value thus obtained may or may not be used to update the specif1c parameter being adjusted, depending on the previous value of this potentiometer.
I~ the old setting is equal to ~ero, then a start-up condition exists. The new setting is immediately loaded into the appropriate RAM location and the subroutine READ is exited.
If the new setting as obtained from the lookup table is equal to the old setting, then the old setting is reloaded into RAM at the address specified by register RO.
If the new setting is unequal to the old setting then the hysteresis test is performed~

. ~ r~
.

~ S3S
' q,;
49,049 Essentially, the hysteresis test examines the entire eight-bit output of the AnC 156, as scanned from the potentiometer. If bits 1 and 2 are equal, that is, i~
- they are either 00 or 11, then tha new settlng is ~gnored and the old setting is reloaded into RAM. The purpose of : . ~

49,001; ~,002; ~9,004; 49tO06; 49,009; 49,010; 49,013;
~ 49,04g; 49,049; 49,050 this action can be understood by reference to TABLE I, wherein eight values out of the~28 possible combinations of ADC output are shown. As has already been explained, the most significant bits, that is bits 5, 6 and 7, deter-mine the setpoint of the potentiometer. As can be seen inTABLE I, the potentiometer setting in binary notation will increase from 100 to 101 as the analog-to-digital con-verter output moves from value D to value E. By ignoring a change in potentiometer setting wherein bits 1 and 2 are either 11 or 00, a hysteresis effect is obtained.

TABLE I

Bit Number: 7 6 5 4 3 2 1 0 Value .
0 0 1 1 .~ O O - ~

_ ; 1 0 1 0 0 0 0 0 ~ - E

Remembering that the hysteresis test is only performed if there is a change in the upper three bits of the ADC output, it can be seen that an increase in ADC
output from value B to value C will not result in a new value being stored, since the upper three bits of B and C
are the same. An increase from value B to value G, how-ever, would clearly result in a new value being stored, since bit 5 of the output changed from a zero to a one.
Without the hysteresis test bein~ performed, an increase in ADC output from value C to value F would simi-larly result in a new potentiometer value being slored.

r~ i;3~
49,001; 49,0~2; 49,0Q~; 49,006; 49,009; 49,010; 49,013;
~ 7 49,048; 49,049; 49,050 However, this represents a change in value of about 3/256 of the maximum potentiometer, or less than 1.~%. Such variation can easily occur due to changes in ambient temperature.
Through the use of the hysteresis test, wherein ADC outputs having equal values of bits 1 and 2 are ig-nored, it can be seen that a change in ADC output from value C ~o value E would result in the new potentiometer setting being ignored and the old potentiometer setting being reloaded into RAM, since bits 1 and 2 of value F are both zero. Similarly, if the operator were reducing the value of the potentiometer, causing an ADC output to change from value G to value C the new value would also be ignored and the old value retained, since bits 1 and 2 of value C are both one, and the hysteresis test would reject the new setting. It can therefore be seen that the hys-teresis test insures that the potentiometer setting must be changed by more than 4/256 of its total possible ad-justment before a new setting will be accepted. It can be argued that the hysteresis test just described is not suf-ficiently precise, in that a valid setting change may possibly be ignored. This might occur, for example, if the old potentiometer setting produced an ADC output much larger than value H, for example 10110101, and the new potentiometer setting produced an ADC output equal to value D. It can be seen that this represents a very large excursion in the rotation of the potentiometer, and yet the final position producing a value equal to value D
would be ignored, since bits 1 and 2 are both ONE's. It must be remembered, however, that an interactive operation is being performed, and that the parameter value selected by the READ routine is, from the point of view of a human operator, instantaneously presented on the numeric dis-plays 80 or 82. In the example just cited, the operator would see that a fairly large excursion of the potentiome-ter produced no change in value, and he would naturally r~ $~i3 ~
49,001; 49,002; ~9,0Q4; 49,00~ 9,009; 49,010; 49,013;
49,048; 49,049; 49,050 ~i ~
make an even further adjustment. At some point, his further adjustments would result in a new value being selected by the READ routine and presented under numeric display. If the change produced were larger than desired, the operator would then readjust in the opposite direc-tion, the entire operation taking much less time to per-form than to explain. This represents an extremely cost-effective and convenient method of entering parameter changes for the time current tripping characteristic into a circuit breaker. Adjustment of the potentiometer to the extreme upper and lower limits will cause the most con-servative value to be displayed.
In the event that bit 2 is not equal to bit 3, that is the hysteresis test does not cause the setting to be ignored, a bit pattern is loaded in register R7 to cause display of this setting value on the numeric dis-plays 80 or 82. The four-second timer is then reset and the new setting value is stored in the RAM location corre-sponding to this particular parameter. The subroutine then returns to the calling function.
If an ADC output of all zero's or all one's is obtained, the READ routine interprets this as a poten-tiometer failure. The most conservative parameter value is then selected from the look-up table, displayed on the numeric display 80 or 82, and stored in RAM.
I. Hardware Initialization After Power-On ~L~C~_~
~ J
The microcomputer 154 must be initialized fol-lowing power-up. In the case of the Intel 8048 device this is accomplished by means of a RS pin which if held low causes the program to "jump" to address 0 which by convention is the starting address of the power-on start-up subroutine. The RS pin is held low by the power supply by means of D900 for about 5 ms, after the +5 VDC is applied.
However, the RS pin does not affect the I/O
lines from the microcomputer and thus during the power ON

.9,001; 49,00~; 49,~04; 4g,006; ~9,009; 49,010; 49,013;
49,048; 49,049; 49,050 ' ~3 ~_ transient these may assume either a high or low output state which, in the case of four particular lines of Port 1 and Port 2, can cause excessive power supply drain or even accidental tripping of the c:ircu:it breaker 10 or other interconnected breakers. These :lines are as fol-lows:
1. LED (line 6 of Port 2--should be low to ensure all LED indicators on front panel are O~F).
2. INHIBIT 212 (line 7 of Port 2--should be tristated, that is, held in a high-imped-ance state to ensure that all 8 digits of the 7-segment LED displays 80 ancl 82 are OFF).
3. PULSE 178 (line 7 of Port l--should be tristated to ensure that pulse transformer 501 is OFF).
4. TRIP 190 (line 4 of Port l--should be tristated to ensure that no false trip occurs on power-on).
The desired tristating is achieved by means of hex buffer U900. When RS of the microcomputer 154 is low, the DISABLE (A) of U900 is low (removed) which causes DISABLE (B) to be high (active). In this way the four critical leads from the microcomputer 154 are switched to the high impedance state, except for LED which is held low as desired by the pull-down resistor R905.
A second function of U900 is to reset counter U901 as shown in Fig. 16.
J. Automatic Reset f, ~r~ /~
Once a successful power-up transition is made, the microcomputer 154 continues to execute a logical and sequential series of instructions indefinitely. Under unusual conditions, such as those produced by electrical system transients, it is possible for an instruction to be improperly executed. The only way to restore the micro-r~ 3.~i3S
49,001; ~9,002; ~9,004; 49,006; 4919~ 49,010; 49,013;49, 048; 49, 0~9; 49, 050 computer 154 to is orderly program execution is to per-form another rese~ operation. In unattended applications, this reset must be automatic.
This is accomplished by means of counter U901 which utilizes a 400 kHz clock output (ALE) rom the microcomputer 154 to provide a fixed time delay between the last ~901 RS pulse ~nd a high on Qll (RS for the~C).
If the RS pulse of U901 occurs soon enough, Qll will remain low and the ~C will not be reset.
The U901 RS pulses are derived from the col-lector of transistor 228. Normally these pulses are 100~Us wide and occur approximately every 2 ms. The circuit is designed so that 5.46 ms is required for Q11 to time out (go high) and thus Q.11 is always low.
If improper instruction execution sequence occurs, the following possible conditions would cause an automatic reset of the microcomputer (Qll would time out).

If this condition should exist for more than ; 20 300,~ s, pulse transformer 501 will saturate and U901 RS
~ will remain low.
:~ 228-OFF
If this condition should exist, U901 RS will remain low.
228-Pulse Rate Too Slowly If transistor 228 turn-on pulses occur less than every 5.46 ms, the U901 RS will be low long enough for a ~C reset to occur.
228-Pulsed Too Fast Rapid pulsing of transistor 228 will be filtered by R900 and C900 (39f~s time constant).
-ON/OFF Duty Cycle > 1/10 Transformer T501 is pulsed on for 100 ~ s, to a voltage of 5 volts, by transistor 228. When 228 is turned OFF, the transformer's magnetizing current will flow through diode D901 which will result in a voltage of about ~ 5 ~ .
49,001; ~9,002; 49,004; ~9,()06; 49,009; 49,010; 49,013;
~/ 49,048; 49,0~9; 49,050 -~5 volts being applied to the transformer 501. The average voltage of the transformer must be zero and thus 1000,~,~ s ~ 100 ~5) will be required to "reset" the transformer's magnetizing current to zero. A 1-to-10 or less ON-to-OFF ratio must be maintained for the transformer 501 to function or the transformer's core will ultimately saturate. If trans-former 501 is saturated, the RS pulses will not be applied to U901 and Qll will time out and reset the microcomputer.

~, .

Claims (7)

49,049 What we claim is:

1. Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated circuit and for operating to in-terrupt current flow therethrough on command, sensing means for sensing current flow through said interrupter means;
microcomputer trip means connected to said in-terrupter means and said sensing means for comparing cur-rent flow through said interrupter means to a predetermined time-current trip characteristic and for operating said in-terrupter means whenever current flow therethrough exceeds said time-current trip characteristic, said microcomputer trip means comprising a TRIP output control line connected to said interrupter means, said TRIP output control line being operable by said microcomputer trip means from an inactive to an active state to command said interrupter means to interrupt current flow;
a power supply connected to said microcomputer trip means; and interlock means connected to said power supply and to said TRIP output control line for maintaining said TRIP output control line in a said inactive state following energization of said power supply until such time as operating power to said microcomputer is sufficient to en-able said microcomputer trip means to execute positive con-trol over said TRIP output control line.

2. Apparatus as recited in claim 1 wherein said interlock means comprises delay means for maintaining said TRIP output control line in a said inactive state for a 63 49,049 predetermined time period following energization of said power supply.

3. Apparatus as recited in claim 1 wherein said microcomputer trip means comprises a reset terminal oper-able when actuated to cause said microcomputer trip means to return to a predetermined initialization point in the instruction sequence thereof, and said interlock means are connected to said reset terminal, whereby said TRIP output control line is placed in said inactive state whenever said reset terminal is actuated.

4. Circuit interrupter apparatus, comprising:
circuit interrupter means for conducting current flow through an associated circuit and for operating to in-terrupt current flow therethrough on command;
sensing means for sensing current flow through said interrupter means;
microcomputer trip means connected to said sensing means and said interrupter means for comparing current flow through said interrupter means to a predetermined time-current trip characteristic and for operating said interrupter means whenever current flow therethrough exceeds said time-current trip characteristic; said microcomputer trip means comprising memory means for storing a plurality of instruct-ions, control means for executing said stored instructions in a predetermined sequence, and a reset terminal operable when actuated to cause said control means to return to a predetermined point in said instruction sequence, proper execution of said predetermined instruction sequence caus-ing said output control line to generate a series of pulses having a predetermined duty cycle, duration, and frequency;
and actuating means connected to said reset terminal and to said output control line for actuating said reset terminal upon detection of improper duty cycle, duration, or frequency of said pulses.

5. Apparatus as claimed in claim 4, wherein said 49,049 actuating means comprises a counter and a switch, said counter causing said switch to actuate said reset terminal upon arrival at a predetermined count, said counter being reset by receipt of pulses having said predetermined duty cycle, duration, and frequency.

6. Apparatus as claimed in claim 5, wherein said actuating means comprises filter means connected between said counter and said output control line for filtering said pulse pattern to prevent reset of said counter when said pulse pattern has a frequency greater than a predeter-mined limit.

7. Circuit interrupter apparatus, comprising:
circuit interrupter means for conducting current flow through an associated circuit and for operating to interrupt current flow therethrough on command;
sensing means for sensing current flow through said interrupter means;
microcomputer trip means said connected to said sensing means and said interrupter means for comparing cur-rent Plow through said interrupter means to a predetermined time-current trip characteristic and for operating said in-terrupter means whenever current flow therethrough exceeds said time-current trip characteristic; said microcomputer trip means comprising memory means for storing a plurality of instructions, control means for executing said stored instructions in a predetermined sequence, and a reset terminal operable when actuated to cause said control means to return to a predetermined point in said instruction sequence, proper execution of said predetermined instruction sequence causing said output control line to generate a series of pulses having a predetermined duty cycle, duration, and frequency;
actuating means connected to said reset terminal and to said output control line for actuating said reset terminal upon detection of improper duty cycle, duration, or frequency of said pulses;
said actuating means comprising a counter and a 49,049 switch, said counter causing said switch to actuate said reset terminal upon arrival at a predetermined count, said counter being reset by receipt of pulses having said pre-determined duty cycle, duration, and frequency; and said actuating means further comprising a saturable inductor connected between said output control line and said counter, said inductor saturating if the duration of said pulses is greater than a predetermined limit, whereby said counter reaches said predetermined value to energize said switch and actuate said reset terminal.