CA1154527A - Circuit interrupter with digital trip unit and power supply - Google Patents

Abstract

68 49,010 ABSTRACT OF THE DISCLOSURE
A circuit breaker includes a microprocessor-based trip unit and a power supply for supplying operating power to the trip unit and the trip coil of the circuit breaker from either the internal current transformers of the circuit breaker or a plurality of external sources.
The trip unit includes a numeric display for displaying a sequential series of parameter values under normal condi-tions. Under low-power conditions, the power supply provides pulses of operating power sufficient to enable the trip unit to execute all of its limit check functions and present a flashing display of a single parameter value.

Description

1 49,010 CIRCUIT INTERRUPTER WITH DIGITAL
TRIP UNIT AND POWER SUPPLY
CROSS REFERENCE TO RELATED CAN~DIAN APP~ICATIONS
The present invention i8 related to material disclosed in the following Canadian patent applicatlons, all of which are assigned to the same assignee of the present application.
Canadlan Serlal No. 374,787, "Circuit Interrupter Wlth Solld State Digital Trip Unit" filed April 6, 1981 by J. C. Engel;
Canadian Serial No. 374,755, "Clrcuit Interrupter Wlth Front Pan~l Numerlc Display" filed April 6, 1g81 by J. C. Engel, R. T. E1D8~ and G. F. Saletta;
Canadian Serial No. 374,764, "Circuit Interrupter With Solid State Digltal Trip Unit And Positive Power-Up Feature" fil~d Aprll 6, 1981 by R. T. Elm~, G. F. Saletta, and B. J. Mercier;
Canadian Serial No. 374,776, "Circuit Interrupter Wlth Dlgital Trip Unit And Optically-Coupled Data Input/Output System" filed April 6, 1981 by J. C. Engel, J. A. Wafer, J. T. Wllson, and R. T. Elm8 Canadian Serial No. ~74,716, "Circult Interrupter ; Wlth Energy Management Function~" filed April 6, 1981 by J. T. Wilson, J. A. Wafer, and J. C. EnKel;
! Canadlan S~rlal No. 374,735, "Circult Interrupter With Digltal Trip Unit And Style Designator Circuit" filed April 6, 1981 by J~ J. Matsko, E. W. Lange, J. C. Engel, and B. J. Mercier;
Canadlan Serial No. ~74,742, "Circuit Interrupter W$th ' .

., `

~' 5~ '7

-2 49,010 Overtemperature Trip Device" filed April 6, 1~81 by J J.
Matsko, and J. A. Wafer;
Canadian Serial No. 374,754, "Circuit Interrupter With Digital Trip Unit And Means To Enter Trip Settings"
filed April 6, 19~1 by R. T. Elms, J. C. Engel, B~ J.
Mercier, G. F. Saletta, and J. T~ Wilson;
Canadian Serial No. 374~696, "Clrcuit Interrupter With Multiple Display And Parameter Entry Means" filed ; April 6, 1981 by J~ J. Matsko~ J. A, Wafer, J. C. Engel, and B. J. Mercier;
Canadian Serial No. 374~771, "Circuit Interrupter With Remote Indicator And Power Supply" filed April 6, 1981 by J~ C. Engel, J. A. Wafer, B~ J~ Mercier, and J. J. Matsko;
Canadian Serial No. 374,724, "Circuit Interrupter With Digital Trip Unit And Automatic Reset" filed April 6, 1981 by B. J. Mercier and J. C. Engel; and Canadian Serial No. 374,748, "Circuit Interrupter With ~igital Trip Unit And Potentiometers For Parameter Entry~' filed April 6, 1981 by J. C. Engel, B. J. Mercier, and R. T.
Elms.
~ ACKGROUND OF THE INVENTION
Field of the .Invention:
The invention relates to circuit interrupters having means for electronically analyzing the electrical : 25 condition~ on the circuit being protected and for auto-matically opening to interrupt the current flow whenever electrical condition~ exceed predetermined limit~.
Description o~ the Prior Art:
Circuit breakers are wldely used in industrial ~nd commercial applications for protecting electrical conductors and apparatus connected thereto from damage due to excessive current flow. Although initially used as direct replacements for fuses, circuit breakers were gradually called upon to provide more sophisticated types of protection other than merely interrupting the circuit when the current flow exceeded a certain level. More elaborate time-current trip characteristics were required such that

3 49,010 a clrcu~t breaker would rapidly open upon very high over-load conditions but would delay lnterruption upon detec-tion of lower overload currents, the delay time being roughly inversely proportional to the degree o~ overload.
Addltionally, circuit breaker~ wer~ called upon to inter-rupt upon theddetection o~ ground fault current~. As the complexlty of electrical distributlon circuit~ increased, the control portions of clrcuit breakers were intercon-nected to provide selectivity and coordination. This allowed the designer to specify the order ln which the various circuit breakers would interrupt under specified fault conditlons.
During the late 1960's, solid state electronlc control circuits were developed ~or use in h~gh power low voltage circuit breakers. mese control circuits perform-ed functions such as instantaneous and delayed tripping which were traditionally achieved by magnetic and thermal means. The improved accuracy and flexibility of the solid state electronic controls resulted in their wide-spread acceptance, even though the electronic control circuits were more expensive than their mechanical counterparts.
The earliest electronic control circuit designs utilized discrete components such as transistors, resist-ors~ and capacitors, More recent designs have included integrated clrcuits which have provlded improved product performance at a slightly reduced cost.
As the cost of energy continues its rapid rise, there is increasing interest in effectively controlling the usage of electrical energy through the design of more ~0 sophisticated electrical distribution circuits. There-fore, there is required a circuit breaker providing a more complex analysis o* electrical conditions on the circuit being protected and even greater capability for coordina-tion with other breakers. As always, it is extremely desirable to provide this capability at the same or lower cost.
In providing basic overcurrent protection func-tions9 it would be desirable to provide a circuit inter-

4 49,010 rupter requiring no connections other than line connec-; tion~ to the clrcuit belng protected. Therefore, it ls desirable to provlde a circuit interrupter having a trip unit powered by the circult being protected while at the same providing requlred l~olation~ For additional ~unctions, howe~er, Cuch as dlsplay of the value of current which caused a trip and various energy ~unctionæ, lt i8 ds~irable that the trip unit be powered independently from the circuit belng protected. Accordlngly, it i~ desired to provide a circuit interrupter having the capa~ility of being powered from a variety o~ power ~ources and including means for selecting the most approprlate power source at any given time. In addition, under conditions of lnadequate power availability, it i8 desired that the circuit breaker provide the maximum ~unctions possible for the level of power available.
SUMMARY OF THE INVENTION
In accordance with the principles of the pre~ent invention, there i8 provided circuit interrupter apparatu~
lncluding interrupter means for operating to interrupt current ~low through an a~sociated circuit on eommand, sensing means for sen~ing current flow through the inter-rupter means, and trlp unit means connected to the inter-rupter me~ns and the sensing means for comparing current flow through the lnterrupt0r means to a predetermined time-current trip characteri~tic and for operating the interrupter means whenever current flow therethrough ex-ceeds the tlme-current trip characteristic. The apparatus also includes power supply mean~ connected to the ~ensing means and to a source of external power for supplying operating power to the trip unlt, the power ~upply mean~
selecting the most appropriate power source a~ between the sensing means and the external power source.

/19, ()1 () This page has been lef~ nk inlention~llly.
`:

49,001; 49,002; 49,00~; 49,006; 49,009; ~'3,010; l~9,0l3;
49,048; l~(3,049; 49,0~0 P,Rl~F l)~S(~l~'rl()N OF IH~, I)RAWlN~S
. . .
Figure l is a perspective view of a circuit breaker embodying the principles of the present invention;
Fig. 2 is a functional block diagram of the circui.t breaker of Fig. l;
Fig. 3 is a block diagram of a typical electri-cal distribution system utilizing circuit breakers of the type shown in Fig. l;
Fig. 4 is a graph of the time-current tripping l~ characteristic of the circuit breaker shown in Fig. 1, plotted on a log-log scale, Fig. 5 is a detailed frontal view of the trip unit panel of the circuit breaker of Figs. l and 2;
Fig. 5A is a block diagram of the microcomputer 1'; shown in Fig. 2;
Fig. 6 is a detailed schematic diagram of the panel display system of Fig. 5; and Fig. 7 is a detailed schematic diagram of the parameter input system of Fig. 2;
; 2~ Fig. 8 is a detailed schematic diagram of the ~) C?; q ~
Style Number ~cs1.~hat~L System of Fig. 2;
Fig. 9 is a schematic di~gram of the Kemo~e Indicator and Power Supply of Fig. 2;
Fig. 10 is a diagram of the waveforms present at ~r various locations in the Remote Indicator and Power Supply ` of Fig. 9;
Fig. l1 is ~ block diagram of the System Power Supply shown in Fig.-1~;
; Fig. 12 is a scllematic diagram ot the System , Power Supply shown in Fig. ll;
Fig. 13 i.s a diagram of the switchirlg le~els occurring at various locations in the System Power Supply of Figs. ll and 12;
Fig. 14 is a schematic diagram of the Data Inpu ~, Output System and Power Supply of Fig. 2;
Fig. 15 is a diagram of the waveforms present at 1~5 ~ s,~;~
49, 001; 49, 002; 49, 004; 49, 006; 49, 009; ~,9, 01 0; ~9, 0 1 3;
49 ,04~; l.9 ,0~,'3; /19 ,O jO

various locations in the system of Eig. 14;
F'ig. 1~ is a schematic diagram of a power-on hardware initialization and automatic reset circuit;
Fig. 17 i5 a flowchart of the main instruction loop stored in read-only memory of the microcomputer shown in Fig. 2;
Fig. 18 is a flowchart of the first function of the main instruction loop shown in Fig. 17;
Fig. 19 is a flowchart of the second function of 1'~ the main instruction loop shown in Fig. 17;
Fig. 20 is a flowchart of the third function of the main instruction loop shown in Fig. 17;
, Fig. 21 is a flowchart of the fourth function of the main instruction loop shown in Fig. 17;
Fig. 22 is a flowchart of the fifth function of the main instruction loop shown i.n Fig. 17;
Fig. 23 is a flowchart of the sixth function of the main instruction loop shown in Fig. 17;
. F'ig. 24 is a flowchart of the seventh function of the main instruct.ion loop shown in Fig. 17;
Fig. 25 is a flowchart of the eighth function of the main instruction loop showll in Fig. 17;
~,; Fig. 26 is a flowchart of the conllllon display ,, subroutine of Fig. 17;
Eig. 27 i~ a flowchart of the trip subroutine of' ' Fi.g. l7; anci Fig. 28 is a flowchart of the subrout:ine to ', obtain setti.ng values from the potentiometers of F`ig. 5.
DESCRIPTION OF THE PREFERRED EMBODIMEN'I' _ _ _ _ _ ... _ _ _ .. . . . . _ _ . _ .. ... _ . _ _ . _ . .
3~ I. I TRODUCTION
. A. Use of a_Circuit Breaker-_in an Electricar Power Distri~ution System ___ __ _ .__ __ _ Before explaining the operation of the present invention, it will be helpful to describe in greater 3'~ detail the function of a circuit breaker in an electrical power distribution circuit~ Fig. 3 shows a typical elec-4 ~
9,00l; 49,002; 4'3,0~4: 49,~()6; 4~,009; 49,010: ~19,0l~;
49,048; 49,0~-9; ~9,050 trical distribution system. A pluralit:y of electrical loads 48 are supplied through circui~ breakers 50, 52 and 54 from either of` two sources of electrical energy 56 and

5~. The sources 56 and 58 could be transformers connected r~ to a high v(?ltage electrical feeder line, a diesel-powered emergency generator, or a combination of the two. Power-from the first source 56 is supplied through a first main circuit breaker 50 to a plurality of branch circuit break-ers 60-66. Similarly, power from the second source 58 may be supplied through a second main circuit breaker 52 to a second plurality of branch circuit breakers 68-74. Al-ternatively, power from either source 56 or 58 may be supplied through the tie circuit breaker 54 to the branch circuit breakers on the opposite side. Generally~ the . main and tie circuit breakers 50~ 52 and 54 are coordin-ated so that no branch circuit :is simultaneously supplied by both sources. ~he capacity of the main and tie circuit breakers 50~ 52 and 54 is usually greater than that of any branch circuit breaker.
r~ 20 If a fault (abnormally large current flow) should occur at~ for example, the point. 76, it is clesira-ble that this condition be detected by the branch circuit .. breaker 62 and that this breaker rapid]y trip~ or open, to : isolate the fault from any source of electrical power.
,~r' ~he fault at the point 76 may be a large over-currerlt condition caused, for exatn})le, by a short cir(uit betweell ~ two of Lhe phase conductors of the circuit~ or an o~erloacl : only slightly above the rating Or the breaker cause(1 by a stalled motor. Alternatively, it might be a ground fault 3, caused by a breakdown of insulation on one of the con(~uc-tors~ allowing a relatively small armour1t of cllrrellt floh to an object at ground potential. ln any case, the fault would also be detected by the main or tie breakers 50, 52 or 54 through which the load fed by branch breaker 62 is 3~ supplied at the time of the fault. However, it is desir-able that only the branch circuit breaker 62 operate to s~q 49,001; ~9,002; 4't,004; ~C3,006; 4~,009; 4'~,010; 49,013;
49,0~8; 49.049; ~9,050 isola~e the fault from the source of electrical power rather than the main or tie breakers. The reason for this is that if the main or tie circuit breaker should trip, electrical power would be lost to more than just the load attached in the branch circuit on which the fault oc-. curred. It is therefore desirable that the main and tie circuit 50, 52 and 54 breakers should have a longer dela~
period following detection of a fault before they initiate a tripping operation. The coordination of delay times l~ among the main, tie and branch circuit breakers for vari-ous types of faults is a major reason for the need to provide sophisticated control in a trip unit.
B. Time-Current Tripping Characteristics:
: ln order to achieve the coordination between l~ circuit breakers as described above, the time vs. current tripping characteristics of each circuit breaker must be specified. Circuit breakers have traditionally e~hibited '.; characteristics similar to that shown in Fig. 4, where both axes are plotted on a logarithmic scdle. When CUI--rent below the maximum continuous current rating of the breaker is flowing, the breaker will, of course, remain closed. As current increases, however, it is desirable that at some point, for example the point 300 of Fig. 4, the breaker should trip if this overload current persists for an extended period of timt. Should a current flow ~ equal to the maximum cont.inuous current rating as speci-.~ fied by point 300 persist, it can be seen from Fig. 4 that the breaker wil.l trip in approximately 60 secondx.
At slightly higher values of current, the time required for the breaker to tr:ip will be shorter. For example at 1.6 times maximum continuous current as speci-fied by point 302, the breaker will trip in about 20 seconds. The portion of the curve between the points 300 and 304 is known as the long delay, or thermal, character-3- istic of the breaker, since this characteristic was pro-vided by a bimetal element in traditional breakers. It is 115~
49,Q~1; 49,00~; 49,004; 49,006; 49,009; ~9,010; ~l9,0l~;
49,048; 49,0/~9; 49,050 desirable that both the current level a~ which thc long clelay portion begins ancl the trip time requ:ire~l for any poin~ on that portion be adjustable. These parameters are I;nown as long delay pick-up and long delay t.irne, respec-r` tive]y, and are indicated by the arrows 306 and ~*.3O9, At very high overcurrent levels, for example 12times the nla~imum continuous current and above, it is desirable that the circuit breaker trip as rapidly as .~possible. This point 312 on the curve is knoh7n as the :10 "instantaneous'~ or magnetic, trip level~ since traditional breakers employed an electromagnet in series with the contacts to provide the most rapid response. The instan-taneous pick-up level is usually adjustable, as indicated by the arrow 314.
:~ ].~ To aid in coordinating breakers within a dis-tribution system, modern circuit breakers ha~e added a short delay trip characteristic 316 between the long delay and instantaneous portions. The present invention allows adjustment of both the short delay pick-up level and the 2~ short delay trip time as indicated by the arrows ~18 and 320.
Under certain conditions it is desirable that the trip time over the short delay portion also vary i.nversely with the square of the current. This is kno~n 2':, as an l2t characteristic and is indicated in lig. 4 by the .. broken line 3l0.
HYSICAL_AND OPIRATIONAI Di:S(`R~PrlON
A. Clrc~ult_Bre_ker Reference may now ~e had to the drawings, in ~' which like reference characters r-efer to corresponding components. A perspective view and a ~unctional block diagram o a molded case circuit breaker l0 employing thc principles of the present inven~ion is shown in Figs. I
and 2, respectively. Although the circuit interrupter 10 ~' is a three-pole circuit breaker for use on a three-phase electrical circuit, the invention is, of course, not so 11 49,010 limited and coul~ be used on a single-phase circuit or another type of multlphase circuit. A power ~ource such as a trans~ormer or switchboard bus is connected to input terminals 12 and an electrical load i~ connected to output terminals 14. Internal conductors 16 connected to the terminals 12 and 14 are also connected to interruptlng contacts 18 which serve to selectively open and close an electrical circuit through the circuit breaker. The contacts 18 are mechanically operated by a mechanism 20 which respond~ to manually or automatlcally-lnitiated commands to open or close the contacts 18.
Current trans~ormers 24 surround each of the internal phase conductor~ 16 to detect the level of cur-rent n ow through the conductors 16. me output signal from the current trans~ormers 24 is supplied to a trip unlt 26, along with the output 8ignal from a current transformer 28 which detects the level of ground fault current flowing ~n the circuit. me trip unit 26 con-stantly monltors the level o~ phase and ground fault currents ~lowlng in the circuit to which the breaker 10 ls connected and initiates a command signP~ to a trip coil 22 which actuates the mechanism 20 to open the contacts 18 whenever electrical conditions on the circuit belng pro-tected exceed predetermlned limlts stored in the trlp unit 26. During normal conditions, the mechanism 20 can be commanded to open and close the contacts 18 through man-ually-initiated commands applied through the manual con-trols 32.
Referring to Fig. 1, it can be seen that the clrcult breaker 10 includes a molded insulating hou~ing 34. me termlnals 12 and 14 are on the rear of the hou~-ing 34 and are thus not shown in Fig. 1. A handle 36 is mounted on the right-hand slde of the houslng 34 to allow an operator to manually charge a spring (not shown) in the mechanism 20. The manual controls 32 are positioned ~n ~s~s~
12 49,010 the center o~ the hou~lng 34. Window~ 3B and 40 indicatQ
the state o~ charge of the spring and the position of the contact~ 18~ respectively. A push-button 42 allow~ an operator to cause an internal electrlc motor to mechanic-ally charge the spring ln the same manner as the manualcharging operation which c~n be performed by the handle 36~ A pushbutton 44 allows an operator to cause the spring to operate the mechanism 20 to close the conta~t~
18. Similarly, a pushbutton 46 allow~ an operator to cause the spring and mechanlsm 20 to open the contacts 18.
B. ~E~ hl~
1. Front Panel me panel of the trip unit 26 is po~itioned on the le~t ~ide of the hou~ing 34 as can be seen in Fig. 1.
This panel, shown in more detail in Fig. 5, includes a plurality of indica~or lights, potentiometers, numeric display devices t and swltches, to permit an operator to observe the electrical parameters on the circuit being : protected and the limit values pre~ently stored in the trip unit, and to enter new limit values if so de-3ired.
A rating plug 78 i~ inserted into the front panel of the trip unit 26 to specify the maximum contin-uous current to be allowed in the circuit being protected by the circuit breaker. This may be leqs than the actual capacity of the clrcuit breaker, which is known as the frame q_ , For example, the frame size for the circuit breaker may be 1,600 amperes; however, when the breaker is initially installed the circuit being protected may need to supply only1,000 ampereq o~ electrical current.
Therefore, a rating plug may be ins0rted in the trip unit to en~ure that the maximum continuous current allowed by the circult breaker will be only 1,000 amperes even though the circuit breaker lt~elf is capable of safely carrying 1,600 ampere~.
An auxiliary AC power receptacle 132 is located 49 001; 49 00~.; 49 004; 49 0~ 9 009; ~l9 010; l~9 0l ;
~ o~ 0~9; ~9,or)0 . 1~
: at th~ up~er right of the trip uniL panel, .1S s~erl in l ig.
5. This socket is used to supply auxiliary alternatirlg : current operating power (separate from the electrical ` circuit being protected) to the circuitry of the trip unit. The operation of this auxiliary AC power supply will be described more completely in section III.E.
2. Block Diagram : Referring to Fig. 2 it can be seer- that the trip coil 22 is supplied with power through a conductor 1~ 136 from the power supply 144. The flow of current through the trip coil is controlleci by a non-latching switching device such as a switching field effect tran-sistor 192 actuated by the main trip unit circuitry. The use of a non-latching switch device instead o~ an SC~ or ~ lr other type of latching device as usedIthe prior arL pro-.~ vides greater noise immunity.
In addition the circui.t breaker 10 includes three parallel-connected normally-open thermally activated switches 141 connected in parallel with FET 192. These 2~ swi.tches are physically mounted on the conductors 16 in pro~imity to the contacts 18 with one switch mounted on each phase conductor 1~.
Each s~itch Icomprises cn bimetal elernent which closes the switch contact.s when the temperat:ure of the ~r~ associated conductor rises t:o 150(` and resets whell the conductor temperatur(- fal~s below 130 (`. Although a bimetallic swit.ch is employed in the cli~closed ernbodirllent~
other types of thermally activated swit.ches such as ther-mistors could be mounted on the conductor. Alternatively 3.~ radiation sensors could be used. Infrare(l det:ect.ors coulcl monitor the heat generated on the contact.- or-eondlictors while ultraviolet or RF detectors could sense radiation generated by arcing contacts or terminals.
The switches 141 serve to directly energize the 3C~ trip coil 22 upon high temperature conditions. ln addi-tion the hardh!are interrupt line/o~ the microcomputer is ~5~
14 49,010 connected through the trlp coil 2Z to the high side of the switches 141 to signal the microcomputer 154 that a trip operation has occurred~ This causes execution of appropriate instructions in internal read~only memory (ROM) of the microcomputer 154 to generate output data to a remote indicator 145. Since the mechanism 20 requires somewhat more than 30 ms.
to open the ~ontacts ~ollowing a trip command, power is avail- -able for trip unit 26 to execute 2 complete operation cycles o~ the main loop program even if no external power is supplied.
Alternatively, the switches 141 could be wired solely to the microcomputer 154 to allow it to initiate the trip operation and generate output data in the same manner as an overcurrent trip.
Information concerning electrical parameters on the circuit is provided by the three phase current trans-formers 24, each of which monitors current flow through the individual phase conductors of the circuit. The transformer 28 surrounds the three phase conductors of the circuit and detects currents which flow outward from a source through the phase conductors and then return through unauthorized paths through ground, commonly known as ground fault currents.
The signals from the current transformers 24 are supplied to a rectifier and auctioneering circuit 142 which provides a DC current proportional to the highest instantaneous AC current on any of the three phases. The circuit 142 provides normal operating power for the trip unit through a power supply 144. The transformers 24 and 28 act as current sources and are limited to supply power to the circult 142at approximately 40 volts. This is converted by the power supply 144 to three operating voltages: a 1~67 volt reference voltage labelled VREF, a 5 volt operatlng voltage for the microcomputer and asso-ciated circuitry of the trip unit, and a 40 volt supply which operates the trip coil 22. Information from the rectifier and auctioneering circuit 142 which is propor-tional to the present value o~ phase current is also ~4~7 49,010 supplied to the peak detector 160 of the main trlp circultry a~ indlcated ln Flg. 2 The si~nal from the grou~d tran3former 28 i~
supplied to a rectifier circuit 146 whlch pro~ldes ~n alternate ~vurce of operatin~ power ~or the trip unit through the power ~upply 144, and ~lso supplles lnforma-tion proportlonal to the pre3ent ~alue of ground curr~nt to the peak detector 162 o~ ~he trip unit circuitry. An external DC ~ourc~ 148 of operating power on the order o~
about 40 volts may al80 be supplied to the power ~upply 144, as may be an external AC source 150 of operatlng power supplied through the trip unlt ~ront panel socket 132 to a rectifier 152 and then to the power ~upply 144.
The main tr$p unit circuitry includes an inform-ation processor and sequence controller 154 which may be, ~or example, a type 8048 mlcrocomputer obtainable in commercial quantities ~rom the Intel Corporation. A block diagram of the controller 154 is shown in Fig. 5A; however, a detalled de~cription of the 8048 microcomputer may be obtained from the MCS-48 M~crocomputer User's Manual, published ~y the Intel Corporation.
An analog-to-digital con~erter 156 such as the type ADC3084 obtainable in commerci~l quantities from the National Semiconductor Corporation i5 connected to the . 25 data bus 172 o~ the mlcrocomputer 154. Any o~ eight in-; puts to the analog-to-digltal converter (ADC) 156 are ~e-lected through a multiplexer 158 such as the type CD4051B
according to an address supplied by the microcomputer via - port 1 to the multiplexer 158. These lnputs include peak detectors 160 and 162 for phase and ground current values, . an averaging circuit 164 for average pha~e current, a pair of multiplexers 166 and 168 ~or reading panel ~witches and potentiometer~ addre~sed and selected by the microcomputer via port 2, and four lines from a Style Number Designator circuit 170. The designator circuit 170 a1lows manufac-turing personnel to provide the microcomputer 154 with 11~4~P~
``49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 information cc)nc~rning the optional features and m{)des, such as ground fault detection and serial l/O capability, with which the specific trip unit will be supplied. Use of such a designator circuit allows a single microcomputer configuration to be provided for a plurality of different models of the trip unit 26.
Also connected to the microcomputer data bus 172 is an external read-only memory (ROM) 151 and a data in-,put/output system 174 which allows the trip unit to inter-act with other components and circuit breakers of the electrical distribution system. Power for the data input/
output system is provided by a separate power supply 176 derived from the five-volt bus of the power supply 144.
As will be more completely described in a later section, ].5 the data input/output power supply 176 is a pulse-type , power supply activated by a line 178 connected to port 1 of the microcomputer 154.
~'Input to the microcomputer 154 from the limit value potentiometers and switches of the trip unit panel, ,20 shown in Fig. 2, is supplied through multiplexers 166 and 168 to multiplexer 158. Output information to the panel ~,~ display systemtincluding the LED's 84-100 and numeric dis-play indicators 80 and 82 is supplied from the micropro-cessor 154 through port 2. Port 2 also supplies address 2~ and SELECT information to the multiplexers 166 and 168.
Port 1 of the microcomputer 154 provides a plurality of functions. Control of the ADC l56 is pro-vided by a line 180 from port '1. t,o d s~itching transistor , 182 which varies the reference voltage/to ~hé ADC. Input : 3~ to the ADC 156 from the multiplexer 158 is control1ed through a line 184 from port 1 to a swit,ching transistor 186 to selectively ground the multiplexer output to the ADC 156 under control of the program of the microcomputer 154 as will be described hereinafter. Grounding of the 3~ multiplexer 158 output while either of the peak detectors 160 and 162 are selected causes a reset of the peak detec-i~l545~P~

17 49,010 tors.
Addres~ in~ormation allowlng the multiplexer 158to select from lt~ various input source~ 160, 162, 164, 166, 168 or 170 is provided from port 1 of the micro-computer through address lines 188.
Control of the trip coil 22 is provided ~rom the microcomputer 154 through port 1 and a TRIP line 190.
Thus, when it is determined that a trippirlg operation is called for, the microcomputer 154 ~ends, through port 1, a ~0 signal on the trip line 190 causing the switching tran-sistor 192 to energize the trip coil 22, activate the mechanism 20, and separate the contacts 18.
3. O~erational Modes Mode 1: Low Power mi8 mode is performed under condltions o~ very low current flow through the breaker (less than 25% o$
frame ratlng), when external power is not being supplled to the trip unit. Uhder these conditlons su~ficient operating power cannot be contlnuously ~upplied to the trlp unlt, and some o~ its normal functions cannot be reliably performed. merefore, the power supply generates a pulse of operatlng power to the trip unit c1rcuitry sufficient to execute the normal operating cycle of the trip unit but to display only the pres~nt phase current through the breaker on the numeric display 80. This value is ~lashed by the display at a rate which increa~es as load current increase~. At load current ~alues above 25%
of frame rating, Mode 2 operation i8 performed~ Fractions ; of ratlng values wlll hereinafter be indicated by ~E unit notation; e~g. 25% = .25 PU.
~D~e e: :lon~l Thi~ mode of operation ls performed when load current is greater than .25 PU of ~rame rat~ng but less than 1.0 PU o~ the rating plug value, or when external power i8 b~ing supplied to the trip unit.
As can be seen in Fig. 5, the tr~p unit panel contains a n~mber of ad~ustment potentiometers~ light-emitting diode indicators (LED's), pushbutton sw1tches, 49,001; 49,002; 49,004; ~9,006; 4~,009; 49,010; 49,0:l3;
49,0~8; ~9,~9; 49,050 1~
and two-position switches. The panel also includes a pair of numeric display indicators 80 and 82. The electronic circuitry internal to the trip unit causes the numeric~
display indicators 80 and 82 to sequentially display the present value of electrical conditions on the circuit being protected and the various limit settings defining the time-current trip curve of the breaker as currentl~7 set. The LED's, when lighted, indicate by the legends associated with each indicator, what value is being dis-played at any time by the numeric displays 80 and 82. Ifso desired, the numeric values displayed on the numeric indicators 80 and 82 may also be sent to a remote location .' ~ via the SERIAL OUT terminal of the Data I/O System i~4t~
Beginning at the top of the trip unit panel as c shown in Fig. 5, the LED indicator 84 is labeled PHASE
CURRENT on the left and GROUND CURRENT on the right. When this LED is lighted, it indicates that the present per unit value of current flowing in the three-phase circuit being prot:ected is displayed in the left-hand numeric dis-2(' play indicator 80, and the present per unit value o~ground current on the circuit being protec~ed is indicated in the right-hand digital display indicator 82. In a similar manner, ~he LED 86 is labeled PEAK KW SETTING and PEAK KW SINCE LAST RESET. When this LED is lighted, the value appearing in the left-hand nunleric display 80 is that value of kilowatts clelivered by the circui~ being protecteA which will cause a DEMAND signal to be gellerate(l by the data input/output system. The peak value of ki]o-watts drawn through the bre/aker since the display was last 3~.1 reset (by the pushbutton ~ immediately to the right) is presented on the numeric display indicator 82. The LED's 88 and ~ correspondingly indicate PRESENT KW and MW x HOURS, and power factor multiplied by line voltage as follows:

4~2~

1g 49,010 PRESENT KW 3 presentpha~e ournentx (powerfactorxlin~ voltage~
as entered by operator on front panel actual megawa$t-hours a (MW X HOURS) x ~rame rating In this manner, a user can more readily periorm energy management ~or his ~ystem. Not only is a conti~u-ou~ di~play o~ prese~t dem~nd, peak demand, and total energy usage pro~ided, but in addition, alarming or auto-matic load shedd~ng may be initiated by the outp~t ~ignal proYlded through the dat~ I/O system in response to the PEAK KW monitoring function.
If desired, a potential tran~qformer could be added to the clrcuit break~r 10 to mon~tor line voltage and eliminate the need for manual operator entry of a value o~ line voltage. Furthermore, a high-speed A/D converter could be added to sample line voltage and phase current at a high enough rate to permit direct calculation of power iactor and eliminate the need for an operator to enter the power factor.
Below the ratlng plug in Flg. 5 can be seen a number of LED's labelled INSTANTANEOUS, LONG DELAY, SHORT
DELAY, and GROUND FAULT. To the left of this ~eries of LED's i8 the legend CURRENT PI~K-UP and to the right is the legend TIME IN. When the TFn 92 labelled INSTANTANEOUS is lighted, thls indicates that the value Or current whi¢h wlll result in an in~tantaneous trip is presently being di~played in the le~t-hand digital display indlcator 80. By deflni-tion, the instantaneou~ trlp will occur lmmediately, thus there is no corresponding time to be displayed, and the display 82 i~ blank. When the LED 94 labelled LONG DELAY
is lighted, this indicates that the left-hand numeric dlsplay indicator 80 is presently showing the current value at which a long-delay tripping operation wlll be initiated, while the right-hand numerlc display indicator 82 is showing the time parameter in seconds of a long delay tripping operation. T~e~e time and current values li~'~
4~,001; 49,002; 49,0V4; 49,006; 49~009; 49,010; 49,013;
49,04~; 49,049; 49,050 correspond to the long delay tripping operation discussed above with regard to the time-current tripping curve of the circuit breaker.
When the LED 96 labeled SHORT DELAY is lighted, 5 the left-hand numeric display indicator 80 is showing the . current value which will cause a short delay tripping ; operation to be initiated, while the right-hand numeric display indicator 82 is showing the duration, in cycles, of a short delay tripping operation. Similarly, when the LED 98 labeled GROUND FAULT is lighted, the left-hand ~! numeric display 80 will show the value of ground current which will cause a ground fault tripping operation and the right-hand digital display 82 will show the number of cycles between the detection of the ground fault current ~5 and the command to cause the circuit breaker to trip.
As can be seen in Fig. 5, some of the legends have a solid circular symbol associated therewith, while other legends are associated with a solid square symbol.
The circular symbols indicate that the parameter desig-nated b~ the associated legend will be displayed as a /m~ultip~e of frarne rating. Similarly, those parameters tassociated with a square symbol will be displayed as/mult-iples of ~ ra~ . For example, assume the displays 8() and 82 were presenting values of 0.61 and 0.003, respec-tively, and the LED indicator 84 is lighted. This repre-sents a present phase current of 976 amperes (0.61 .Y frame rating = 0.61 x 1600 amps = 976) anci a present grouncl current of 3.6 amperes (0.003 x plug rat.ing = 0.003 x 1200 amps = 3.6 amps).
3~ A pair of miniature switches 102 and 104 labeled I2T RESPONSE are used to vary the shape of the time-current tripping curve in the short delay and ground fault areas, respectively. When the switches 102 and 104 are in the lower position, this indicates the Ground Fault and Short Delay portions of the curve will not exhibit an I T
slope, but will instead be horizontal. When the switches 21 4~,010 102 and 104 are in the upper pos~tion, the I2T character-istic will be ernployed, and the character~stlc for the Short Delay tripping operation will have the shape as shown in Fig. 4 A potential transformer co~nected to the asso~
ciated circuit could be used to obtain llne voltage data, and rap~d sampling and direct multlplioation of the in-stantaneous values of phase current and line voltage used to calculate real power. However, the disclosed methcd provides a convenient and cost-effective method which avoids isolation problems associated with potential trans-formers.
Summarizing, in normal operation, the following operations will be calculated sequentially, with the entire calculation sequence repeated 60 times per second: peak KW, MW-HR integration, instantaneous trip, long delay trip, short delay trip, and ground fault trip.
In addition the following values will be displayed sequentially in pairs, with each display lasting 4 seconds:
PRESENT PHASE CURRENT - PRESENT GROUND CURRENT, PEAK KW
setting (demand) - PEAK KW SINCE RESET, PRESENT KW - MWHR, POWER FACTOR x LINE VOLTAGE, INSTANTANEOUS PICKUP - TIME, LONG DELAY PICKUP - TIME, SHORT DELAY PICKUP . TIME, AND
GROUND FAULT PICKUP - TIME.
Mode ~: Overcurrent and Trip Mode This mode is performed when either phase current is above the Long Delay Pickup value or ground current ls above the Ground Current Pickup value. Sequencing of dlsplay values and LED indication thereof contlnues as in Mode 2 even through the breaker is overloaded. In addi-tlon, the Long Delay Pickup LED 94 will be lightedO
If the overcurrent or ground fault condition persists, the trip unit will initiate a trippin~ operation according to the time-current trip characteristic loaded therein by the user. When trippln~ occurs, the f~ction which in~tiated the trip (long delay, short delay, inst~n-5~ 7 22 49,010 taneous, or ground fault) wlll be indlcated on the front panel by energiz~tion of the appropriate LED 92, 94, 96, or 98~ The ca~se-of-trlp in~ormation wlll be sent out by th~ data I/0 system to the remote indicator 145. In addi-5 tion, the per unit phase or ground fault current thatcau~ed the trip will be displayed and frozen on the numer-ic display 80.
In additlon to the microcomputer trip capabili-ty, the trip circuit breaker include~ the thermal switcheæ
141 as a back-up system. Should this system initiate a trip operation, the InstantaneouQ LED 92 will be lighted, a value of 15.93 PU current value will be displaysd on the numeric display 80, and an INSTANTANEOUS signal sent by the data I/0 system.
Mode 4: Parameter Ad~ustment As can be seen in Fig. 5, the trip unit panel also includes a plurality of limit value potentiometers associated with the various legends on the trip ~-n~t panel. These potentiometers are provided to allow an operator to adjust the circuitry o~ the trip unit to varY the ~hape of the time-current trip curve and produce the type of tripping characteristics required by the deslgn of the entire electrical distrlbution system. When an operator ad~usts one of the potentiometers, (for example, the INSTANTANEOUS CURRENT PICK-UP potentiometer 112) this ad~ustment is detected by the trip unit circuitry and the sequential dlsplay of values is interrupted. The parameter value being adJusted is immediately displayed in the corresponding numeric display i~dicator, and the correspond-ing LED indicator is lighted. For example, if it i8 desiredto ad~ust the instantaneous current pick-up value, an operator inserts a screwdriver or other tool into the potentiometer 112 and begins to burn it. Immediately, the INSTANTANEOUS LED ind cator 92 lights and the present value of the instantaneous current pick-up is displayed in the numeric display indic~tor 80. This number is ln per unit format, that is, a multiplier ., 49,001; 49,002; 49,00~; 49,006; ~19,009; 49,010; 4~,013;
~9-04~; 49,049; 49,050 times the frame rating, as specified by the solid round symbol. Thus, as the potentiometer 112 is rotated, the ~:; value displayed in the indicator 80 would begin to slowly increase in discrete steps from, for example, 1.00 up to the maximum allowable value as stored internally in the ; trip unit, which is l0Ø When the desired value is ' achieved, adjustment of the potentiometer is ceased and : the trip unit resumes its sequential scan and display of present values and settings. In a similar manner, any of : l~ the potentiometers on the trip unit front panel may be ad-justed to achieve the desired parameter setting.
In the past, adjustment of parameter values using potentiometers in conjunction with digital circuitry ; has presented problems. There was a tendency, for exam-l~ ple, for each minute change in the value of a potentio-meter~to produce a different value which would be immedi-ately displayed. This produced an annoyingly rapid varia-tion of the display which rendered adjustment difficult.
Furthermore, temperature variations and other minor per-turbations in the circuitry would cause variation in the display and value of the potentiometer even when no ad-justment was being made. In addition, failure of the potentiometer in the past would sometimes prevent the designated parameter from being read at all.
~' In order to avoid these problems, the present invention employs the potentiometers to se1ect one of eight predetermined parameter values stored within ROM of the trip unit microcomputer. Thus, the potentiometer acts as a discrete multiposition switch rather than a continu-3~ ously variable adjustment device. In the event of a potentiometer failure, the trip unit selects the most conservative value of the parameter associated with the malfunctioning potentiometer for use in its monitoring functions.
To add further convenience to an adjustment operation, the trip unit includes a hysteresis feature :

.

45~PP
24 49,010 whieh ls described in detail in Section III~C.
Parameter~ may also be entered by an external circuit over the SERIAL IN terminal (Fig. 14) of the data I/O system 174.
~
A TEST mode is also provided in the trlp unit herein disclosed. ~y pressing either of the momentary-~ontact pushbutton ~witches 128 or 130~ an overcurrent condition or ground-~ault condition, respectively, may be simulated.
If the switch 106 is ln the NO TRIP position, the ~ault cur-rent value to be simulated i8 determined by the ad~ustment of the potentiometer 120 while either of the switohes 128 or 130 are depreæsed. W~th the switch 106 in the TRIP posi-tion, fixed values Or fault current are s~mulated. This simulated overcurrent or ground-fault condition w~ll or will not result in actual opening of the contacts 18 of the circuit breaker, as determined by the settlng o~ the TRIP/NO TRIP switch 106. In either case, the test is inltiated upon release of the pushbuttons 128 or 130t causing the TEST MODE LED 100 to be lighted. When the delay period expires, the appropriate LED 92, 94, or 96 will light, thus indicating the successful completion of the test. If the switch 106 has been set to the TRIP
positlon, the contacts of the circuit breaker will actually open.
Through the use Or the TEST moAe with the switch 106 in the NO TRIP position, an operator can check any desired point on the time-current tripping characteristic.
He does this by pressing the desired test button 128 or 130~ and dialing in, on the TEST potentiometer 120, any desired multiple Or the maximum continuous current. He then releaqes the desired pha~e or ground ~ault test button 128 or 130. The trip unit will simulate a fault at that level of the multiple of maximum continuous current ~5 which was entered via TEST potentiometer 120, and will simulate a tripping operation without actually opening the ~;15~sæ7 25 49,010 contacts .
At the completion of the test, LhD 92, g4, 96 or 98 will be li~h~ed to indicate whether the bre~ker tripped under instanta2leous, long delay, short delay, or ground fault modes. l~e display 80 will show the per unlt cur-rent value at which the breaker tripped (which will be the same as the vslue entered via potentiometer 120) and di~play 82 will ~how the ~umber Or seconds or cycles (which is specified by LED'~ 92, 94, 96 or 98) ~ollowing inltiation of the test in whlch the breaker tr~ppedO
During execution of a t~st, a determination is made as to which is larger: actual phase (or ground) current or ~imulated phase (or ground) current, and the larger of the two compared to the various setting ~alues.
Thus, a test can take place with no lo~s of protection.
Furthermore, 1~ simul~ted current is larger than actual current, but both are larger than Long Delay Pick-Up, a trip operatlon will be performed at the end of the test, regardless of the positlon of the TRIP/N0 TRIP ~witch 106.
me operator can then plot the time-currrent value displayed to see if this polnt lie3 on the desired time-current tripping characteristic curve. Any number of points can be so tested, allowing complete ~erlfication of the tripping charact~ristic as entered in the trip unit.
C. Remote Indicator And Power Suppl~
A remote indicatorand power supply 145 may also be connected to the trip unit 26. Thifi device, 8hOWn sohemstically ln Fig. 9, provides the capability of in-dicating at a location remote from the circuit bre~ker 10 when the breaker has tripped and what caused the trip.
In ~dditlon, the de~ice 145 can indicate when peak power demand has exceeded a pre~et limit. These indications are provided by four LED's corresponding to PEAK KW DEMAND
EXCEEDED, OVERCURRENT TRIP (lo~g delay), SHORT CIRCUIT ~RIP
(instantaneous, æhort delay~ or thermal~ and GROUND FAULT
TRIP.
Two relays are also provided in the remote indi-49,001; 49,~02; 49,004; 49,006; 49,009; ~9,010; 49,013;
' 49,048; 49,049; 49,050 ` 26 : cator 145. One relay is act~ated on receipt of a peak KW
demand indication, to provide the capability of automatic load shedding. The other relay is actuated on receipt of any type of trip indication to trigger an alarm bell, light, or other desired function.
The device 145 also includes a power supply energized from the AC line which pro~7ides 32 volts DC.
The output of this power supply is connected to the EXTER-NAL DC terminal 148 of Fig. 2.
l~A detailed description of the circuitry of the remote indicator and power supply is contained in Section III.E.
III. ELECTRICAL DESCRIPTlON
A. Arithmetic, Logic, and Control Processor 15The arithmetic, logic, and control processor 1~4 is a type 804~ microcomputer manufactured by the INTEL
Corporation. As seen in Fig. 5A, the single 40-pin pack-age includes the following functions: an eight-bit arith-~ metic logic unit~, a control unit, a lK x eight-bit ROM
2~! program memory ~J 64 x eight-bit RAM data memory 157, an eight-bit bi-directional data bus 172, and two quasi bi-directional eight-bit ports Port 1 and Port 2. Addi-tional control lines are also provided. A more detailed description may be obtained from the previously referenced 2- MCS-4~ Microcomputer Users Manual. Referring to the figures, and especially Figure 2, the interconnections to the microcomputer 154 will now be described.
The eight-line data bus 172 is connected to the eight output terminals of the ADC 156. The eight-bit 3~~ digital values supplied by the ADC are thus read by the microcomputer 154 by the following sequence: a pulse is sent out on the WR line of the microcomputer 154 to the ADC 156, commanding the ADC to convert the analog quantity appearing at its input terminals into an eight-bit digital 3- quantity. Upon completion of the conversion process, the ADC 156 generates a pulse over the line connected to the 27 49,010 T1 test terminal of the microcomputer~ The microcomputer then generates a pulse on the RD line, which transfers the bit pattern produced by the ~DC to the accumulaSor of the microGompul;er 154.
The data bus 172 is also connected to the data input/output system 174, to allow the trip unit 26 to communicate with other circuit breakers and with the remote indicator/power supply 145. me data input/output system will be more completely described in Section IIIG.
Port 1 and port 2 of the mlcrocomputer provide the capability to communicate and control the other compo-nents of the trlp unit 26. The speci~ic connections will now be described~ Line numbers correspond to the notation used in the MCS-48 Microcomputer Users Manual.
Port 1 Llne 0, line 1, line 2- mese lines provide the channel address information from the microcomputer 154 to the multiplexer 158, as indicated at 188 on Figure 2.
Line ~--This llne, indicated at 180 in Figure 2, actuates the FET 182 to change the reference voltage de-livered to the ADC 156, thereby increasing the resolution for the Long Delay phase current measurement.
Line 4-- mis line activates the transistor 192 to energize the trip coil 22 and cause the mechanism 20 to open the contacts 18 to the breaker. Line 4 is indicated at 190 in Figure 2.
Llne 5--This llne actuates the FET 186 to ground the output of the multiplexer 158, which also grounds the individual input to the multiplexer 158 which happens to be selected at that time. Thus, activating line 5, (indicated at 184 in Figure 2) csn reset the peak detectors 160 ~d 162, when these are selected by the multiplexer 158.
Line 6--This llne activates the Chip Select terminal on the external ROM when performing a read oper-28 49,010 input/ou~put sy~tem 174.
Port 2:
___ L~ne 0, Line 1, Line 2, Line ~-- mese lines car ry the data sent from the microcomputer 154 to the panel dlsplay system 155. As can be ffeen ln Figure 6, the digit ~alues are supplied o~er these lines to the latch decoder 194 for di~play on ~he numeric ind~cator~ 80 and 82~ Line 0, line 1, and line 2 (indicated as 207 in Figure 6 and Figure 7) also supply channel address information to multiplexers 206, 166 and 168. Line 3 (indicated as 216 in Fi~ure 7) is connected to ~he INHIBIT terminals o~ the mNltiplexers 166 and 168 and serves to toggle or selec-tively acti~ate the multiplexers 166 and 168.
Line 4, identified as 200 in Fig. 6,--Thi~ l~ne actuates the transistor 198 to light the decimal point on the numeric indicator~ 80 and 82.
Llne 5--Thi~ line is connected to the Latch En-able terminal of the latch decoder 194 and serves to latch the data values appearing on lines O through 3 in the latch de~oder 194.
Line 6-- mis line energizes the transistor 208 which, in conJunction with the output lines of the latch decoder 194 serves to energize the LED indicators 84 through 98.
Line 7--This line is connected to the INHIBIT
terminal of multiplexer 206 and i~ indicated at 212 ln Figure 6.
The Interrupt terminal INT of the microcomputer is connected to the high voltage slde of the thermal switches 141. Activation of the~e switches thu~ causes the Interrupt terminal 143 to go LO and initlate the Interrupt instructions in ROM 155 which proce~ses the thermal trip operation, and lndicates an instantaneou~ display trip.
B. ~
A detailed schematic diagram of the panel dis-49,001; ~9,002; 49,004; 49,006; 49,009; 49,010; 49,01~;
49,048; 49,04~; 49,050 play systenl o Fig. 2 is shown i.n Fi~. 6. As can be seen, a seven-segment latch decoder circuit 194 such as a type CD4511B is provided. A four-bit input signal is provided by lines 0-3 of port 2 of the microcomputer 154. The de coder circuit 194 provi.des a seven-line output si.gnal through a load resistor array 1.96 to the pair of four digit seven-segrnent LED digital display indicators 80 and 82. An eighth line for act.ivating the decimal point of the digital display indicators 80 and 82 is also provided through a transistor 198 which is actuated by a line 200 also connected to port 2 of the microcomputer 154. A
driver circuit 202 and transistor 204 are provided under control of a multiplexer circuit 206, which may be for example, a type CD4051B. A three-bit SELECT signal, also driven by three lines 207 from port 2 of the microproces-sor is supplied as input to the multiplexer circuit 206.
The LED indicators 84, 86, 88, 90, 92, 94, 96, 98 and 100 are actuated through the transistor 208 by a line from port 2 of the microcomputer 154 in conjunction with the 2'J digital display indicators 80 and 82. The TESl` LED 10() is also driven by the transistor ~ and an additional t.ran-sistor 210 in conjunction with an INHIBIT line 212 also supplied to the multiplexer 206 from port 2 of the micro-computer.
2' C. Param_.er Input Limit values for the trip unit 26 are pro~ided by the potentiometers 108-120, as shown in Figs. 2, 5, and 7. Each of the potentiometers has one end of its resis-tance element connected to the VREF supply, and the other 3~ end of the resistance element grounded. The wiper of each potentiometer is connected to an input terminal of one of the multiplexers 166 and 168 which may be, for example, a type CD4051B. Thus, each of the potentiometers provides an analog voltage signal to its appropriate multiplexer 3- input terminal. These input terminals are selected by a three-bit address line ~ plus an INHIBIT line 216 con-.

49,001; 49,002; 49,004; 49,006; 49,009; ~.9,010; 49,013;
~9,048; 49,0~,9; ~,9,05 nected t~ port 2 of the microprocessor.
The two-position switches 102, ~04 and ].06 correspond respectively to I2T IN/O~T switches for phase current and ground current, and a TRIP/~O TRIP function for the test mode. As can be seen, these switches serve to construct a variable voltage divider between VREF and ground which provides any of six analog voltage values to a terminal of the multiplexer 168. In a similar manner, the pushbutton switches 107~ 105, 128 and 130 correspond-1~ ing respectively to DISPLAY RESET, DEMAND RESET, PHASETEST, and GROUND TEST, serve to place any of eight analog voltage signals on another terminal of the multiplexer 168.
D. Style_N_mber Designator Figure 8 shows in detail the style number desig-nator circuit 170 shown in Fig. 8. Each four-digit deci-1 l b co~cspond5 to a particular option combination. As can be seen in Fig. 8, the style desig-nator circuit provides input to four terminals of multi-plexer 158. Each of these terminals represents one digit of the decimal style number and may be connected to any of four positions on a voltage divider formed by the resist-ors 218, 220, and 222 connected between ground and VREF.
These connections are selected and made b~ jumper connec-. tions wired at the factory to provide each o~ the termin-als of multiplexer 15~ with any of four possible analog voltage signal value~. The mu:ltil)lexer 158, orl command, then supplies these ~alues to the Al)(` Ir~6 which con~ertC.
them to thè 8-bit digit.al code which is read by the micro-3 computer and interpreted as the style numb~l, a11owing t.h~
microcomputer to determine whic~h of the many option com-binations for the trip unit 26 are actually present in that particular trip unit.
E. Rem~t~ i~di~ d Power upply 3 The data input/output system 174 supplies pulse coded output signals, over a single optically coupled pair i~S~S~7 31 49,010 of wires, to the Remote Indicator 145 shown in Eig. 9 pro-viding a remote indication $hat the load being supplied through the circuit breaker has exceeded a predetermined power llmit. In addition, cause-of-trip ind~cations of overcurrent, short clrcult, or ground fault are provided.
The circuit to be de~cribed decode~ the corresponding four input signals to pro~ide both LED indications and relay closures.
In addition, the cirouit provide~ a remote souroe o~ power, from both the AC line and from batteries, to the power supply 144. mi s capability i~ needed in those applications which require continuous retentlon of data such as cause-of-trip indicators and energy functions including megawatt-hours and peak demand power.
As can be seen in Figure 9, input power i5 SUp-plied through a transformer 602, rectifier c~rcuit 604J
and filter capacitor 606 at a level of approximately 32 volts. A current limiting resistor 608 i5 provided to protect against accidental shorting of the output terminal 610. Terminal 610 is connected to the EXTERNAL DC INPUT
148 (Figure 2) and terminal 612 is connected to the digi-tal ground terminal of the trip unit 26. If a jumper is co~lected between terminal 610 and terminal 614, the three internal 8-volt nickel-cadmium batteries 616 can be acti-vated to support the output voltage at 24 volts, should the AC input voltage be interrupted. A 10 K "trickle charge" resistor 618 i~ provided for battery charging.
An 8.2 volt power supply is provided by resistor 620, Zener diode 622, and capacitor 624 for the decoding ; and alarm circuit.
me data I/0 output terminal 508 of Figure 14 labelled ~emote Indicator Out is connected to termlnal 626 of Figure 9, and the I/O COMMON terminal 500 of Figure 14 i8 connected to terminal 628 of Figure 9. m e 100 micro-~econd, 4 volt output pulses applied to ter~inals 626 and 628 produce an 8 milliampere current flow through the optical coupler 630. mis current turns on the coupler 49,001; 49,00~; 49,004; 4'~,006; 49,009; 49,010; ~9,013;
49,048; 49,0~9; l~9,050 transistor which produces an 8 volt pulse across resistor 632.
The microcomputer 154 can produce one 100 micro-second pulse every two milliseconds, or a maximLIm of eight pulses per cycle of AC power. A coding technique is used, with one pulse out of eight denoting a D~MAND alarm. If a trip has occurred, two consecutive pulses out of eight denote a ground fault trip, three consecutive pulses out of eight denote overcurrent (long delay) trip, and five consecutive pulses out of eight denote a short circuit (either instantaneous or short delay) trip condition. The pulse coding scheme is shown/in Figure ~.A
The input pulses provide trigger inputs for a retriggerable 3 millisecond monostable flip-flop output Q1 f integrated circuit 634 which may be for example an RCA CD4098 device. The retriggerable feature means that any pulse which occurs during the 3 millisecond timing interval will cause a new 3 millisecond interval to start.
Waveforms B of Figure 10 show the resulting ~1 output for one, two, three, and four consecutive input pulses, corre-sponding to a DEMAND ALARM, a ground fault trip, a long delay trip, and a short circuit trip, respectively. The amplitude of the Ql pulses is equal to the supply voltage supplied to the integrated circuit 634. When the Ql 25 output is averaged by resistor 636 and capacitors 638, a DC voltage C is produced whose value is the following fraction of the supply voltage:either 3/16 volts, 5/16 volts, 7/16 volts, or 11/16 volts, respectively. This value is fed to the inverting input terminals of quad comparator 640 which compare the filtered value C to fixed fractions of the supply voltage of 1/8 volts, 1/4 volts, ; 3/8 volts, and 9/16 volts, which are developed by the divider network including resistors 642, 644, 646, 648, and 650. The comparator then provides outputs which !' 3~ indicate which of four possible pulse patterns were ap-plied at input terminals 626 and 628. If, for example, a s~
Lj 9,001; 49,002; 49,004; 49,036, 49,009; 49,010; 49,013;
l~9,048; ~9,049; 49,050 Dl.MAND condition exist:s, producing a pulst pattern of one out of eight pulses, the DC voltage at the inverLing terminal. of comparator A of 640 will be 3/16 of the supply : volts, which is greater than 1/8 of the supply volts but smaller than l./4 of the supply volts. As a result, the output terminal of comparator A will be LO while other inputs will/HIGH. l`ransistor 652 and relay 654 will be turned on by current flow through resistor 656 which also lights the demand LED 658.
An overcurrent trip condition will cause three consecuti.ve pulses to appear at the input terminals 626 and 628, and an averaged value of 7/16 of the supply ~lt~
will appear at the inverting terminals of the comparators of 640. This value is greater than 3/8 of the supply volts but less than 5/8 of the supply volts. In this ` case, the output terminals of comparators A, B, and C will : be LO. Transistor 660 and relay 662 will be on, because of current flow through the overcurrent LED 664 and re-sistor 666. Transistor 652 and the DEMAND LED will be off because of the shorting effect of transistor 668. The GROUND LED 670 is also off because of the shorting effect of the OVERCURRENT LED 664. In this way, the highest level comparison always dominates. A function of inte-grated circuit 672(which may be, for example, an RCA type CD040)and Ql is to provide a 1/2 second ON delay for the comparators, which is required t:o allow the vol~age on capacitor 638 to stabilize. ~I'he Ql pulses occur every 1/60 seconds. Ihese are countecl by counter 67~ until thirty-two pulses occur and output Q6 goes HIGH. At this 3~ time, output Q1 is turned on, and additional pulse inputs are inhi.bited b~ diode 674.
Approximately 30 milliseconds after the last pulse is received by optical isolator 630, the Q2 terminal of the retriggerable monostab~e flip-Llop 634 will go 3~, HIGH. This resets the output Q6 of 672 and turns Ql off.
The function of counter 672 and Ql is to provide positive .

:1~15~S~
3~ t+g,o10 on~o~ operation of the LED indicators and the ALARM/LOCK-OUT and DEMAND RELAYS 662 and 654.
F.
As hereinbe~ore explained, it is contemplated that a circuit breaker employing the principles of the pre~ent invention will be employed in an electrical dis-tribution system in coordinatlon with a number o~ other clrcuit brea~er~. It is sometimes ~esired that vario~s com~ands and in~ormation be sent from this oircuit bre~cer and that various parameters sent by other associated breakers be sensed by this breaker. mis info~mation is used to construct the desired interlocking scheme as specified by the system architect or designer.
The Data I/O System, shown in detail in Fig. 14, include~ four output lines: Short Delay Interlock Out 502, Ground Interlock Out 504, Serial Out 506, and Remote Indicator Out 508.
Three input terminals are also provided: Short Delay Interlock In 510, Ground Interlock in 512, and Serial In 514. The Serial Out and Serial In term~nals are used to communicate digital data between the microcomputer 154 and a remote digital circuit. The Remote Indicator Out terminal provides a one-of-four coded pulse output for cause-of-trip indication (overcurrent, short circuit, or ground), and peak demand alarm indication to the Remote Indicator, as described in Section IIIF. m e input and oùtput interlock terminals allow direct interlock connec-tlons between breakers without any additional components.
If typical optical coupling circultry were used, 400 milliwatts of power would be requlred (12 milliamperes at 5 VDC for each of seven lines). The power which the current trans~ormers 24 are capable o~ supplying is only ; about 500 milliwatts (100 milliamperes at 5 VDC), most of which is required by the microcomputer 154. Conventional optical coupling circuitry thus cannot be used.
e power supply for the data input/output sys-tem 174 includes a pulse trans~ormer 501 connected through a transistor 228 to line 7 of port 1, indicated as 178 in .~ ~

35 49,010 Figures 2 and 14. The microcomputer provide~ a 100 microsecond pulse every 2000 micro~econds, as commanded in the eommon display subroutine, thereby reducing the power supply require-ment of the data input/output ~y~tem 174 by a factor of nearly 20 to 1, or about 20 milllwatt~ (4 milliamperes average at 5 VDC). Thi~ is small enough to be ea~ily ~upplied from the power BUpply 144~
The waveforms appearing in the power supply 176 are shown in Figure 15. Waveform A is that generated on line 7 of port 1 by the microcomputer 154~ For approxi-mately 100 microseconds out oY about every 2000 microsec-onds (actually 1/8 x 1/60 seconds) line 7 of port 1 is held low at mlcrocomputer circuit ground. Thl5 turn~ on tran~istor 228, thereby applying ~5 volts to the input of tran~former 501, as seen in waveform B of Figure 15. A
corresponding waveform i~ produced on the output terminal of transformer 501 relative to the system common terminal of the data input/output system 174.
If an output is desired from, ~or example, the Remote Indicator Out terminal 508, the corresponding microcomputer output line, line 3 of the data bus 172 is held at circuit ground, as shown in waveform C in Figure 15. Led 516 is turned on by current flow through transis-tor 228. me phototranslstor 517 then turns tran~istor 518 on, producing output voltage waveform D. If line 3 of data bus 172 (wave~orm C) i8 HIGH, then the corresponding output from transistor 518 i8 zero~ a~ shown by waveform D.
The input circuitry i5 designed to work wlth both a dlrectly coupled DC slgnal from an older circult breaker, or a pulse input such as that previou~ly described in this section. An input signal at, for example, the SeriP1 Input terminal 514 a~ shown ln waveform E, will also appear at the gate of FET 236, a~-3hown in waveform F.
When the pulse voltage appears at the output of pul~e transformer 501 current will ~low in LED 238, and then through FET 236 which has been turned on by the input ~ 5~
49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
~9,048; 49,049; ~9,050 signal at the Serial Input terminal 514. The FET 236 has a turn-on gate voltage of 2.5 volts and internal gate-to-source 15 volt ~ener diode protection. This range is required to meet the 4 volt pulse input provided by a microcomputer type circuit and a 12 volt DC signal pro-vided by the older type of solid state trip unit.
FET 236 provides two f~nctions. First, it pro-vides a memory element when the input signal is a pulse.
It does this in connection with the capacitor 232 which is 10charged through resistor 230 by the 100 microsecond input pulse. The values of capacitor 232 and resistor 230 are chosen so as to give a 15 microsecond time constant.
Capacitor 232 discharges through resistor 234, sized to give a 10 millisecond time constant. The capacitor 232 cannot discharge through 230, since the input signal is provided by the emitter of an NPN transistor. Thus, the gate of transistor 236 is held high as long as input pulses occur every two milliseconds. Appro~imately 10 milliseconds after the input pulses disappear, transistor 2~ 236 will be turned off.
The second purpose of transistor 236 is current gain. The optical coupler 226 requires nearly 10 milli-amperes to turn the associated phototransistor on. This current is provided by transistor 236. The high DC input .. 25 impedance at the input terminal is required, since the ~: older trip unit control circuits can provide only a small DC input currenL. O~ ~ ~ 1 s~
f~Ihe presence or lack of an inpu~ signal~is read by the microcomputer at line 0 of the data bus, waveform G, which is high during the 100 microsecond pulse period if, and only if, an input signa~1 is present at the termi-nal 514. A pull-down resistor .3~ is provided to maintain the data bus lines connected to the data input terminals -: at circuit ground when no input signal is present at the terminal 514. In this marner, a signal from a circuit breaker, emergency power generator, or other associated :

37 49,010 component o~ the electr~cal power distri~ution 5y5tem can be sensed by the microcomputer 154 and the circuit bre~ker 10 can be commanded to perform appropriate action~ Fur-thermore~ parameter values can also be supplled~ through the SERIAL IN terminal 514, from a remote locatio~. ~p-propriate instruotions in ROM then decode the incoming information and ~tore it in RAM for use by the li~lt checking functions.
G. ~tem Pow~r-~E~ay 1. Block Diagram Descriptlo~
The power ~upply 144 of Figr 2 is shown in block diagram fo~m in Flg. 11. It can be powered by one of four sources: external AC or DC voltage, the Remote Indicator 145 of Fig. 2, current input from a ground current detec-tion transformer 28, or current lnput from the three phase current measuring transformer~ 24.
The rectified output of the external AC source is compared to the ~C voltage from the Remote Indicator and the largest instantaneou~ value is supplied by the auctioneer circult 702 to the power supply's energy stor-age capacitor 704 ~or use by the DC-to-DC converter 706 and the trlp coil 22. A voltage sen~lng c~rcuit 708 monitors the output of the ~oltage auctioneering circuit 702. Whenever this voltage is ~reater than 22 VDC the DC-to-DC converter 706 i8 turned ON. A "crowbar" current switch 710 1~ thrown to position (2) when the voltage exceeds 24 VDC. The converter 706 provldes the 5 VDC supply (at 100 ; mA) for the microcomputer clrcult, a reference ~oltage VREF
(1.64 VDC) and a power ON reset control slgnal RS.
The unit can also be powered by either the rectifi~d output of the ground current transformer or the current auctioneered, recti~ed output, of the three pha~e : current trans~ormers 24. me two currents are summed at 712 and fed to the ncrowbar" 710 which passes the current either into the energy storage capacitor 704 or a current bypass 714. Current flows into the capaci-3~ 49,010 tor 704 until the capacltor voltage reaches about 39 VDC, at whlch point the "crowbar" 710 trans~ers the current to the by-pass circuit 714~ Current by-passing continues until the voltage on the c~pac~tor 704 drops to about 34 YDC and the switch 710 again causes the current to flow into the capacitor~
2, Circuit Description The power supply 144 is shown in greater detail~
in Fig. 12. The external AC input is recti~ied by BR201 and compared to the external DC i~put. The resul~ i5 ~ed through D101 to energy storage capacitors C105 and C112 The sensed voltage is also fed to the crowbar circuit formed by the power field effect transistor Q101 and gates A and B (connected as inverters) of quad NAND circuit IC101. The quad NAND circuit is powered by current flow through R103, D107, D108 and D109, which produces a tempera-` ture stabilized voltage of about 10 VDC for pin 14 of IC101D.
The quad NAND has input hysteresis which causes the output to go LOW when the inputs exceed about 70% of the ~upply voltage (7 VDC~. The output then stays low until the inputs drop to 30% of the ~upply voltage (3 VDC). Thus the crowbar is turned ON when 7 VDC appears across R105 which corresponds to 24 VDC at the external DC input (7 VDC plus drop across i R104, R102, and D103~ It will be noted that the crowbar - 25 can also be turned ON if the voltage across the energy storage capacitor 704 exceeds 39 VDC.
If external power i8 available, then the on-off status of the converter 706 is controlled by the external power supply voltage, rather than the storage capac~tor voltage.
me 24 VDC ~witching point for the external DC
input corresponds to the minimum DC voltage required for the trip coil 22 to operate. The 39 VDC limit on the voltage acro~s the energy storage capacitor is a compro-S~
39 49 ,010 mise between the 50 VDC maximum limit of the capaoitor and the 30 VDC minimum input to the conv~rter requir~d to produce 5 VDC output at 100 mA DC with a mlnimum current tra~sformer output 32 mA RMS.
Current shunts R100 and R101 are used to sen~e phase and ground current respectively. It will be not~d that current flow through the re~lstors i8 through either Q101 (crowbar ON) or C105 and C112 (crowbar OFF) and IC102.
me required 15 millisecond turn-o~f delay of the +5 VDC ~upply is achieved by means of diode D110, resistor R107, and capacitor C102. When the voltage at pins 8 and 9 of IC101 drops below 3 VDC the output pin 10 goes high. A 15 millisecond delay exists before pin 12 and 13 reaches 7 VDC. At thi~ tlme pin 15 goes low caus-ing the +5 VDC reference to go to zero.
The voltage sensor 708 also provides an ON/OFF
control to the DC-t~DCconverter 706. The converter 706 i~ turned ON when the capacitor voltage reaches 37 VDC and OFF when it drops to ~3 VDC. A 15 millisecond delay in the OFF 5ignal iS used to insure that the microcomputer 154 is ON long enough to display the present value of phase and ground current, even when the output current from transformers 24 i8 too small to malntain the opera-tion of converter 706, and to en~ure the maintenance of a TRIP slgnal long enough to effect generation of th~ trip coil 22. Note that the trip ooil ls controlled by non-latching FET 192, rather than a l~tching devic~ such as the SCR's used in the prlor art. This provides immunity rrom nuisance trip~ due to electrical translents, and prevents undue drain on the power supply when operatlng power is supplied by a battery.
The ~witchlng points of the ON/OFF control 708 and crow bar 710 ~re shown in Fig. 13.
The converter 706 i~ a chopper type consisting of PNP darlington switching transistor IC102, inductor L101, "free wheel-` 40 49,010 ing" diocle D112, and a voltage feedback re~erence formed by transistors Q103 and Q104. The voltage at the base o~
Q103 is adju~ted to be ~5 VDC by means of R109~ This voltage ls approximately 1/2 the temperature stabilized +10 VDC produced by D107D D10B and D109.
`~ me circuit operates as ~ollows. If the output ~oltage is below +5 VDC, Q103 will be ON and Q104 OFF.
The collector current o~ Q103 is the base current for the PNP darlington transistor IC102 which is then turn~d ON
With approximately +35 VDC applied to L101 the current will rise linearly. me current wlll flow into C106 and the connected load. When the loutpu~ voltage excseds +5 VDC, Q103, Q103 will be turned OFF and Q104 will be turned ON.
The collector current of Q104 turns on Q102 whlch clamps the base of IC102 causing it to be turned OFF rapidly. At this time, the current in L101 will switch ~rom IC102 to diode D112. The output voltage will beginbD decrease until Q103 turns ON, Q104 turns OFF, and the process re-peats itself. Hysteresis in the ON/OFF switching results from natural over and under shoot associated with the L101 and C106 resonant network. Positive switching feedback is provided by C103 and R110. The switching points of the power supply 144 are shown in Fig. 13.
In addition to the +5 VDC level, the power supply 144 also provides a reference voltage VREF wh~ch is used by the microcomputer 154. An additional ~ignal, a power-on reset ~ignal for the microcomputer is provided by IC103 in combination R114, R115, R116 and C106. When the converter turn5 ON and +5 VDC is produced, the ~ line remains at circuit ground for about 5 milliseconds. This slgnal i8 applied to the microprocessor wh$ch is then reset. Diode D111 provides an immediate power-down reset as soon a~ the 5 VDC reference goes to zero, thereby assuring both a safe power-up and power-down transition.
H. Read-Onlv MemorY
The internal microcomputer ROM 155 ls supplied with ~; 4~,001; 49,002; 49,00~i, 49,006; 49,009; 49,010; ~9,013;
4~,048; 49,~49; 49,050 instructions deEining ;I series of eight ll~ajor l~unctiolls ~: which are executed every cycle of AC current, that is, every 16.667 m~ cc~. Each function is responsible for retrieving one or more parameter values from outside the microcomputer. These parameters include values ob-tained from the electrical circuit being protected, such as phase current and ground current, as well as values specified by the front panel potentiometers and switches.
The function then loads the parameter value into a speci-n fied location in RAM. In addition, most of the functionsare also responsible for performing one or more limit checks; for example, comparing present phase current to the instantaneous trip pick-up value. Since the entire loop of eight functions is executed every 16.67 ~ ~cc.
onds, each of the limit checks is performed at that rate.
In addition to the scanning and limit check duties, each function is responsible for two operations relating to the front panel numeric displays 80 and 82.
Every four seconds, one function reads a display parameter 2'~ value from its assigned location in RAM. lt then formats this parameter value into four digit values. For example, if the present phase current is equal to 2.14 per unit, the appropriate function would produce four digit valuesl a blank, a two, a one, and a four. These digit values would then be placed into assigned locations in RAM, each location corresponding to one digi~- of the numeric display i.ndicator 80. Generally, each function will so format two parameter values, thus loading a total of eight digi L
. values into corresponding RAM locations. These digit values remain in RAM for four seconds until the next function performs its digit value loading duty.
At this point, the digit values are residing in RAM; they must now be sent to the appropriate digit of the numeric displays 80 and 82, the second operation performed by the eight main functions. Each function is responsi-ble, at each time it is executed, for retrieving one of l~Lr.;~.r~217 42 49,01Q
the digit value~ from RAM and ~ending this digit value out on port 2 o~ the microcomputer 154 to the numeric displays 80 or 82. The d~git value then appears lighted in it~
appropriate location in the ~umerlc displays . Slnce a new function is ~xecuted approximately every 2 m~ econds (16.667/~ ms), the digit value will appear for thls length of time on the numeric di~play be~ore it is extlnguished and the next digit va1 ue sent to a different digit loca-tion on the numeric d$splay. At any given time, thereiore, only one d~git one oi eight is lighted on the ~umeric dis-plays 80 and 82. However, the digits flash so rapidly that they appear to an observer to be simultaneously lighted.
The external ROM 151 is option~l and may be used to store instructions to implement additional features such as other functions related to the data I/O system.
Also, the look-up table for potent1ometer settlngs may be stored in external ROM to facilltate changes in the table ~alues.
me organization of the main instruct~on loop in ROM of the mlcrocomputer can be ~een in Flg. 17. The eight main functions are named FUNCTx, where x equals 1 through 8. me ma~or subroutin~s called from the~e ~unc-tion~ are the common display routine CMDIS, the analog to digltal conversion routine ADCV1, the subroutine to toggle between the two display panel multiplexers 166 and 168 and perform the analog to digital conversion TADCV, and the ~ubroutine to obtain dlscrete values from the potentio-meter settings READ. The main functions, and the corre-sponding subroutines will now be described in greater ~0 detail.
CMDIS - Fi~re 26 mis subroutine is called by each major function and thu~ is executed every 2 mllliseconds. It displays one dtgitvalue, as addressed by register R1' and performs ananalog to dlgital conversion on one of the eight input lines of the multiplexer 158, as specified by register R6.

li~J~s,~
49,0~1; 49,002; 49,004; 49,006; 49,009; 49,010; ~9,013;
49,048; 49,049; ~9,050 CMDIS outputs one pulse of 100 microsecond duration on line 7 of port 1, to energize the data input/output power supply 176. A portion of CMDIS, called IADCV, switches between multiplexer 166 and 168 to read a potentiometer from the other side of the panel. In addition, C~DIS
completes a time delay to ensure that each major function executes in exactly 16.667/8 milliseconds.
Reference may now be made to Fig. 26 for a more detailed description of CMDIS. An internal counter is first checked to determine if the 16.667 ms/8 execution time window has expired. If not, the subroutine loops until the window does expire. The counter is then reset.
Next, line 7 of port 1 is activated to perform two functions. The analog-to-digital converter Chip 1~ Select terminal is deactivated by this line. This line is also connected to transistor 228 of the data input/output power supply. Thus, activation of line 7 of port 1 con-stitutes the leading edge of an approximately 100 micro-second pulse for the data l/O power supply.
Pre-existing alarm conditions are now checked to determine if a pulse should be sent out on the serial output terminal of the optically coupled data input/output circuitry 174. As previously described, the serial output feature provides a pulse coded signal over a 16.667 milli-second time window to inform the remote indicator of possible alarm or trip condition~.
Register 6 is now i.ncremented to obtain the channel address for the next input line of the multiplexer 158 to be accessed. Register 1 is now decremented to 3(! obtain the address of the next digit value for display.
Using register Rl as an address pointer, one of the eight digit values is now retrieved from RAM ancl prepared for dispatching to the numeric display indicat-ors. Since the digit value only requires four bits, the 35 upper four bits are used to properly set up the Latch Enable line 5 of port 2 and the inhibit line 7 of port 2 49,001; '~3,()~2; 4~7~04, 4'~,006; ~9,00~; 49,010; 49,013;
~9,048; 49,0~9; 4~,050 212. The l,ED indicator 84, 86, 88, 90, 92, 94, 96, 98 or lO0 corresponding to the parameter now being displayed is controlled by bit 6 of port 2. The corresponding bit in the digit value being displayed is set or reset by the SRACE subroutine in FUNCTl. This control information and the digit value are then sent out on port 2 to the latch decoder 194 of the display system 155. I~Go~J~
A The channel address for the multiplexer ~ as contained in register 6 is now sent out on port 2. The ln analog to digital conversion routine ADCV1 is executed, and the digital value of the input to the multiplexer 158 is stored in register 3 and in the accumulator.
FUNCTl - F~ e 18 __ This function first initializes register R1 with an address one greater than the address of DIGITl, the digit value which will be displayed in the rightmost position of the numeric displays 80 and 82 (which will be decremented by CMDIS before used). It also initializes register R6 with the first channel address to be accessed 2' by the multiplexer 158.
Subroutine SRACE is entered next. This subrou-tine increments a four second counter. If this counter overflows from a hex value of FF to zero, this indicates that the four-second display period has elapsed, and it is time~ to command a new pair of values to appear on the numeric indicators 80 and 82. This is done by shifting the register R7. Next, ~RACE sets bi L 6 in one of the eight digit value RAM locations so that the appropriate L.ED indicator corresponding to the parameters being dis-3~ played will be lighted.
The common display routine CMDlS is now called.Upon completion, DIGITl, the rightmost digit of the numer-ic display 82, will be lighted and the present phase current will have been read and processed by the ADC 156.
3C~ The present phase current value is now stored in RAM.
Index regis~er R7 is now checked to determine if ~4S2~7 49,010 it is time to display the present phase current value on : the ~ront panel numeric display indlcator 80. I~ ~o~ the ~alue of present phase current i5 formatted into four dig~t values, and each of these diglt values stored in the memory locations DIGIT8, DIGIT7, DIGIT67 AND DIGIT5 in RAM
corresponding to the le~tmost display digits, that i~, the digits of the numeric indicator 80. T~e present ground current is also formatted into ~our digit values~ These digit values are stored in the RAM locatlons DIGIT4, DIGIT3, DIGIT2, and DIGIT1 corresponding to the values of the rightmost digits, that is, the four d~gits of the numeric display 82.
Next, ~erial data I/I operations are performed, if called ~or, and the value o~ phase current used for the long delay function is read. In order todbtain a ~alue having twice the resolution of the standard value o~ pre-sent pha~e current, the reference voltage supplied to the ADC 156 is ad~usted via line 6 of port 1~ me ADC is now commanded to again convert the value of the peak detector 160 as supplied through the multiplexer 158. Following the completlon of the analog-to-dlgital conversion, the capacitor of the phase current peak detector 160 ls reset by grounding the output of the multiplexer 158 through FET
186, as commanded by line 5 of port 1. The value o long delay phase current is now stored in RAM.
FUNCT1 now sends a channel address to the multi-plexer 158 via port 1 to select the ground current peak detector 162. The analog to digital conversion routine ADC~ called to read the ground current and convert it to a digital value~ The ground current peak detector capacitor is now reset.
At higher levels of phase current, the ground current transformer 28 ca~ generate fictitious values of ground current when no such ~alue, in fact, exist~. mis effect is more notic~able as phase current increases.
Therefore, the fictitious gro~nd current i5 accounted for by reducing the value o~ ground current to be stored in '~iZ7 49,001; 49,002; 49,004; 49,006; 49,009; ~9,010; 49,013;
~9,0~8; 49,049; ~9,050 , 46 RAM by a factor of l./8 of the phase current whenever the phase current is between 1.5 per unit and 9 per unit. I~
the present value of phase current is greater than 9 per ' unit, the ground current is neglected, by zeroing the present ground current. ~hæ appropriate value of ground current is now stored in RAM.
FUNCT2- _igure 19 This function determines the average phase cur-rent, performs energy calculations, and determines the style number of the trip unit 126. First, the multiplexer 158 is supplied an address via port 1, as indexed by register R6 to cause the averaging circuit 164 to supply an analog value to the ADC 156. The common display rou-tine is now called, causing DIGIT2, the second digit from 1~ the right on the numeric display indicator 82, to be ' lighted, and a digital value for the average phase current to be supplied. The value of average phase current is next multiplied by the product of power factor times line voltage, as specified by the front panel potentiometer 2~) 110. The result is the Present Kilowatt value, PRKW.
This value is ternporarily stored and is also added to the megawatthour tally. A check is next made to determine if PRKW is greater than the peak kilowatt value registered since the last actuation of the Kilowatt Reset pushbutton 105~ R~W is greater, the peak accumulated kilowatt, value is set equal to PRKW, and ~oth values stored in RAM.
A check is next made on register R7 to deterrnine if it is time to display the present kilowatt and mega-watthour values on the numeric displays 80 and 82. If so, these quantities are formatted into four digit values apiece and loaded into the digit value storage locations in RAM.
An address is now generated to the multiple~er 158 to select the style number designator 170 to be sup-plied to the ADC 156. An A to D conversion is now made onthe style number and this value stored in RA~i, to desig-: .

, : .

~ 4~7 49,001; 4~,~02; k~,004; 4~,006; 49,009; 49,010; 49,0]3;
49,048; 49,049; 49,050 nate which of several optional features are included in the present trip unit and to select execution of the appropriate instructions farther down in ROM.
FUNCT3 - Fi.gure 20 5The first task of this function is to reset the number of pulses to be sent out over the serial output terminal. This information will later be used by the common display program to produce the proper pulse code on serial output. The common display routine is now exe-cuted, to light DIGIT3, the third digit from the right on the numeric displays and return a digital value from the Peak Kilowatt setting potentiometer 108.
Next, a flag is set to prevent an extraneous pulse from being sent on the serial output terminal. The READ routine is then executed to obtain one of eight discrete values for the Peak Kilowatt setting as specified by the corresponding potentiometer 108. This routine wil]
be later described in greater detail.
check is now made to determine if it i5 time to display the Peak Kilowatt setting on the numeric indi-cator 80. lf so, the value of Peak Kilowatt setting as determined by the READ routine is formatted into four digi.t values and stored in the digit value locations in RAM corresponding to the digits of the numeric display ~30.
25A running tally of kilowatts is maintained in RAM. This tally is incremented by the present kilowatt.
value on every execution of FUNCT3, thus integrating the kilowatt values over time, producing a value corresponding ` to kilowatt hours. A check is now made of this location 3C in RAM to determine if a value corresponding to 10 kilo-watthours has been reached. If so, a megawatthour tally in RAM is incremented and the kilowatthour tally reset retaining the remainder. A check is made to determine if it i~ time to display the contents of the megawatthour 35 tally on the display. If so, this quantity is formatted : into four digit values and stored in the digit value 49,001; 49,002; ~9,004; ~9,006; 49,009; 49,010; 4g,(~13;
49,048; 49,049; 49,050 locations in RAM corresponding to the numeric display 8~.
Line 3 of port 2 is now activated to selecL
multiplexer 166 and deselect multiple~er 168 as an input to multiple~er 158. An analog to digital conversion is now made on the panel switches 102, 104, and 106, and a digital value unique to each combination of switch set-tings stored in RAM.
FUNCT4 - F`igure 21 ; The first task of ~NCT4 is to call the common display routine to light DIGIT4, the fourth digit from the right on the numeric display indicator 82, and read the PFxLV potentiometer 110 and return a digital value there-from. The READ routine is now called to obtain the look-up table value corresponding to the digital value of the PFxLV potentiometer 110. If it is time to display the PFxLV value, it is formatted into four digit values and stored in the RAM locations corresponding to numeric display indicator 80.
Line 3 of port 2 now selects multiplexer 166 as ~G input through multiplexer 158 to the ADC 156, and an analog to digital conversion is ordered on the voltage divider network which includes the pushbutton switches 105, 107, 128, and 130. A unique digital value corre-sponding to the pattern of pushbuttons now depressed is stored in RAM. This quantity is also checked to determine if any pushbuttons have indeed been pressed. I r none, then FUNCT5 is entered. Otherwise, a check is made to determine if the kilowatt reset pushbutton 105 has been pressed. If so, the value of peak kilowatts in RAM is 3~1 cleared. Next, a check is made to determine if the sysLem reset pushbutton 107 has been pressed. If so, all trip indicators are cleared, the serial output pulse codes are zeroed, the display sequence is reset, and the interrupt is enabled. If the system reset button is not being pressed, then one of the test pushbuttons 128 and 130 is.
The dititsl value of the pushbutton read throu~h the .

1~ r.r~S~
49,001; /J9~002; 49,004; 4~00f~; 49,009; 49,010; 49,013;
49,04~ 9,04g; 49,050 multiplexers 166 and 158 is llOW stored in a test tlag.
FUNCI'5 - Figure 22 The common display routine is called to light ~IGIT5, the fifth digit from the right, and to read the instantaneous current pick-up potentiometer 112. The READ
routine takes the digital value of the potentiometer set-ting supplied by the common display routine and obtains the actual setting from the look-up table in ROM. A check is now made to determine if it is time to display the in-stantaneous current pick-up setting on the numeric indi-. cator 80. If so, the instantaneous pick-up value is for-matted into four digit values and stored in RAM locations corresponding to the digits of the numeric indicator 80.
The TEST potentiometer 120 is now read through the multiplexers 168 and 158 and a digital value obtained.
The digital value previously obtained from scanning the front panel switches is now checked to determine if the switch 106 is in the TRIP position. If so, a fixed value is loaded into the RAM location where the value of the TEST potentiometer 120 would normally bce~ stored. This fixed value is interpreted as either ~ per unit for phase current or 1.5 per unit for ground current, at a later point in the execution of the test. If the switch 106 is in the NO TRIP position, a check is next made to determine if more than one pushbutton is pressed. This is an illegal condition, and no test will be performed. If , it. is det:ermined that only one pushbutton is pressed, a check is made to see which one it is. If the GROUND TEST
,` pushbutton 130 is pressed, a check is made to determine if the value of the TEST potentiometer 120 as stored in RAM
: is greater than or equal to the present value of ground current. If it is not, this means that the actual value of ground current now being detected by the system is :` greater than the value of ground current simulated by the , 3~ potentiometer 120. Thus, no test will be performed and the trip unit will execute the standard ground curren-' ~

.

5~7 ~9,001; 49,002; ~9,004; 49,006; 49,009; 49,010; 49,013;
49,048; 49,049; ~9,050 limit checks. If the value of the TEST potentiometer 120 as stored in KAM is greater than the present value of A ground current, then indexes are set to turn on the -LED 100, the value of the TEST potentiometer 120 is for-:5 matted into four digit values and stored in the RAM loca-tions corresponding to the digits of the numeric indicator 82, and the display of the numeric indicator 82 frozen.
If the P~ASE TEST pushbutton 128 is pressed, a check is made to determine if the value of the TEST poten-tiometer 120 as stored in RAM is greater than the presentphase current. If it is not, then the actual value of phase current is more critical than the simulated test value, and no test will be performed. Instead, the normal limit checks on the present phase current will be executecl c~ by the system. lf the simulated test value of phase .current is greater than the present value of phase cur-rent, then an index is set to turn on the TEST LED 100, the value of the TEST potentiometer 120 is formatted into four digit values and stored in RAM locations correspond-~o ing to the digits of the numeric indicator 80, and anindex set to freeze the numeric indicator 80.
A check is now made to determine if the t.est flag is equal to the bit pattern produced by scanning the pushbuttons. If it is, this indicates that the TEST p-lsh-.25 button is still being depressed. Since a test: is not to be initiated until the butt.on is released, no test will be performed at this time. If the test flag value is differ-ent from the pushbutton value, a check is made to deter-mine if the PHASE TEST pushbutton 128 had been presscd.
If so, the value of the TEST potentiometer 120 i.s stored in the R~M locations corresponding to present phase cur-rent and long delay phase current. Ii the GROUND TEST
button had been pressed, then the value of the TEST po-tentiometer 120 is stored in the RAM location correspond-ing to the present ground current value. This completes .the portion of the testing function incorporated in func-`' .
' S~
49,001; 49,002; 49,004; 49,006; 49,009; 49,010; 49,013;
49,04~; 49jO49; 49,050 tion 5.
Next, the present value of phase current is com-pared to the instantaneous current pick-up as specified by the potentiometer 112. If the present value of phase current is below this value, then function 6 is irrlmediate-ly entered. If the present value of phase current is greater than the instantaneous current pick-up level, an index is set to cause the common display subroutine to put out a pattern of pulses on the serial output terminal to indicate that an instantaneous trip has occurred and the TRIP subroutine is called, as will be explained in a later section.
FUNCT6 - Figure 23 The common display routine is executed to light '15 DIGIT6, and read and convert the long delay pick-up poten-tiometer 114. The digital value of this potentiometer is now acted upon by the READ routine to obtain the table look-up value. lf it is time to display the long delay pick-up value on the numeric indicators, the long delay pick up value is formatted into four digit values and stored in the RAM locations corresponding to the digits of the numeric indicator 80. Next, the long delay time :~,potentiometer 122 is scanned and converted to a digital value, and acted on by the READ routine to obtain the tabl.e look-up value for the long delay time function.
.;The long delay ]imit check is now made, by first comparing the long delay phase c~lrrent to the long delay pick-up value. If the long delay phase current is not greater than the long delay pick-up, then the long delay 3~ tally is reduced by the square of the difference beween `the long delay pick-up setting and the long delay phase current. FUNCT7 is then entered.
If the long delay phase current is greater than the long delay pick-up value, then the long delay tally is incrernented by the square of the long delay phase current.
A check is now made to determine if the long delay tally ~ 52~
49,001; 49,002; 49,004; ~9,006; 49,009; 49,010; ~9,013;
49,048; 49,0~9; 49,050 is greater than the value of long delay tally specified for a long delay trip. If not, FUNCT7 is then entered.
If the current value of the tally is greater than the trip level, a code is stored in RA~I to cause the comrnon display program to generate the proper pulse code over the serial output terminal to indicate a long delay trip. Ne~t, the TRIP subroutine is called, and the long delay tally clear-ed. FUNCT7 is then entered.
_UNCT7 - Figure 24 The common display program is called to light DIGIT7 and obtain a digital value for the setting of the short delay pick-up potentiometer 116. The READ routine is then called to obtain the proper table look-up value for short delay pick-up corresponding to the digital value scanned from the potentiometer. A check is made to deter-mine if it is time to display the short delay pick-up function. If so, the short delay pick-up value is for-matted into four digit values and stored in the RAM loca-tions corresponding to the digits of numeric display indicator 80.
Line 3 of port 2 is now activated to select multiplexer 166, scan the short delay time potentiometer . 124, and obtain a digital value therefrom. The table look-up value for short delay time is then obtained through the READ routine. If it is now tirne to display : the short delay time value, the short delay time value is formatted into four digi.t values and stored in the RA~
locations for display as digits 1 through 4 in numeric display 82.
~C The short delay limit value check is no~ per-formed, by first comparing the presen~ phase currerlt to the short delay pick-up setting. If the pick-up sett:ing is not exceeded, then the short delay tally is cleared and FUNCT8 entered.
If the present phase current is greater than the short delay pick-up value, the RAM location corresponding -49,001; 49,002; ~9,004; 49,006; 4~,009; 49,010; 49,013;
49,048; 49,0~19; 49,~50 to the pattern of swit:ches 1.0~, 104 and lO~) is checked to . determine if the short delay I2T function is called for, via the switch 102. If so, the square of the present phase current is added to the short delay tally, and the : 5 new value of the short delay tally compared to the short delay tally trip level. If the trip level is exceeded, . pulse code for serial out and remote indicator is stored : and the TRIP subroutine is called. If the tally trip . level is not exceeded, then FUNCT8 is entered.
- lOIf the I T function was not specified for the short delay test, then the present phase current value is added to the short delay tally and a comparison made to : determine if the new value of the short delay tally now exceeds the short delay tally trip level. If not, FUNCT8 i,; 15 is immediately entered. If the tally trip level is ex-ceeded, the pulse code for serial out and remote indicat-`! ors is stored and TRIP routine is called before entering FUNCT8.
: FUNCT8 - Fi~ure 25 : 2~)The common display routine is called to light DIGIT8, the leftmost digit in numeric display indicator 80 and to scan and convert the ground fault pick-up potentio-meter 118. The look-up table value for ground fault pick-up corresponding to the digital value of the poten-2~ tiometer 118 is then determined by the READ routine and stored in RAM. If it is now ~:ime to ciisplay the ground fault. pick-up value, this quantity is formatted into four digit values and stored in the RAM locations corresponding to the four digits of the numeric indicator 80.
-~-,The ground fault time potentiometer 126 is now scanned and a digital value obtained t.herefor. The READ
routine then determines the look-up table value corre-sponding to the digital value for the potentiometer 126.
If it is time to display the ground fault time value, this quantity is formatted into four digit values and stored in the RAM locations corresponding to the four digits of the S2~
49, ool; 49, 002; 49, 004; 49, 006, 49, oog; 49, ol 0; ~1~, 0~ 3;
49, 0~8; 49, o~,g; 49, 050 numeric indicator ~2.
A test is now made to determine if the present value of ground fault current is greater than the ground fault pick~up level. If not, an additional test is rnade to determine if the present value of ground fault current ` is greater than one-half of the ground fault pick-up level. If so, the ground fault interlock flag is set in RAM. The ground fault tally is then decremented and the loop returns to FUNCTl.
1~If the present value of ground fault current is ~e~ greater than the ground fault pick-up level, the location in RAM specifying the front panel switch pattern is then checked. If the ground fault I2T switch 104 is set, a quantity equal to 1.5 times the present value of ground fault current is added to the ground fault tally.
If the I2T switch 104 is not set, then the ground fault tally is merely incremented.
~ ext, a check is made to determine if the ground fault tally is greater than the ground fault time limit : 20 value. If not, the main loop is entered once again at FUNCTl. If the tally is greater than the ground fault time, then a pulse code is stored to allow the proper pulse pattern to be transmitted on the serial output terminal, ancl the TRIP routine is called prior to return-ing to the top of the main loop at FUNCT1.
TRIP_- F_~re 27 This subroutine is executed whenever electrical conditions on the circuit breaker e~ceed the time-current characteristic limit values as entered through the front panel of the trip unit 26. The out-of-limit conditions are detected by the calling functions of the main loop instructions stored in the ROM.
The TRIP subroutine first checks the trip flag to determine if this trip condition was detected on a pre-vious execution of the main loop. If so, the next step isto set register R7 to freeze the numeric display. Ii this ll'~ 7 49,~0l; 49,()02; 49,00~; 49,006; ~9,009; 49,010; 49,0l3;
' ~9,0~8; 49,049; 49,050 is the first time the Lrip condition has been letecte(l, then the trip flag is reset and the present value of phase , current is loaded into ~he digit value locations in RAM
corresponding to the digits of numeric display 80, Next, ' 5 bit 6 of the appropriate digit value location in RAM is ,~ set, to cause the proper LED to be lighted on the front '. panel to display that function which caused the trip oper-ation. Note that when bit 6 of a digit value is sent out on port 2, line 6 of port 2 will be actuated when and only ' l0 when the digit connected to the proper LED is lighted.
~:~ This will turn on the transistor 208, lighting the proper LED, Register R7 is then set to freeze the numeric display and prevent any of the functions of the main loop ' 15 from attempting to display a different quantity. The '. interrupt is now disabled and a check is made to determine , if this call to the TRIP routine was the result of a test ,~, : being performed; that is, as a result of the operator having pressed either the P}~SE TEST button 128 or the GROUND TEST button 130. If so, a check is next made to determine if the switch 106 is in the NO TRIP position.
If so, the routine reset.s the t:est flag and four second ti.mer and returns to the calling location.
If the switch 106 is in the TRIP position, or i~' the call to the TRIP subrouti.ne was not caused by a test, then line 4 of port l is actuated. This sends a signal over the line 190 of Eig. 2 to the transistor l92, actuat,-i.ng Lhe trip coil 22 and causing the contac~s 18 to open.
The test flag and four second timer are reset and the subroutine returns to the calling location.
READ - Figure 28 This subroutine performs a table look-up func-tion to allow the limit value setting potentiometers on the front panel of the trip unit 26 to select any of eight discrete values rather than a continuously variable out-put. In addition, the subroutine provides a hysteresis llS~S2~t 56 49,010 effect when adjusting the potentlometers to eliminate the unde~irable variation of potentlometer values on ~mbient termperature and provide greater ea~e and convenience ln adjustment.
Upon entry to the READ routine, register RO
contains the address in RAM of the locatlon where the parameter value being read wlll be $tored, register ~2 contains the beginning addre~ o~ the table of eight value~ which can be seleoted by the potentiometer, and the accumulator and register R3 both contain the digital value o~ the voltage setting produced by the potentiometer, as supplied by the ADC 156.
A check is f$r~t made to determine if a tripping operation has already occurred. If so, the subroutine is immediately axited. Otherwise, the eight-bit digital value of the potentiometer voltage ~etting has its lower five bits ~tripped off and the three most significant digits rotated to become the least signi~icant bits~ me accumulator thus conta~ns a binary number having a decimal value from O to 7. This quantity i5 then added to the address of the beginning of the table, as stored in regis-ter R2, yieldlng the address in R~M o~ the table value ~elected by this particular ad~ustment of the potentio-meter. The value thus obtained m~y or may not be used to update the specific parameter being ad~usted, depending on the previous ~alue of this potentiometer.
If the old setting is equal to zero, then a start-up condition exlsts. The new setting is immediately loaded into the appropriate RAM location ~nd the subroutine READ
is exited.
If the new setting as obtained from the lookup table is equal to the old setting, then the old setting i8 reloaded into RAM at the address specified by register RO.
If the new setting i8 unequal to the old setting then the ., 56a 49,010 Essentially, the hysteresls test ex~mine~ the entire ei~ht-bit output o~ the ADC 156, as ~canned ~rom the potentiometer. If bits 1 and 2 are equal, that 1~
they are elther 00 or 11, then the new ~etting i8 l~nored and the old ~ettlng is reloeded lnto RAN. ffle purpose o~

' ., ~5452~
49,001; 49,0~2; 49,004; 49,006; 49,009; 49,010; 49,013;
49,048; ~9,049; ~9,050 this action can be understood by reference to TABIE 1, wherein eight values out of the128 possible combinations of ADC output are shown. As has already been explained, the most significant bits, that is bits 5, 6 and 7, deter-5 mine the setpoint of the potentiometer. As can be seen inTAB~E 1, the potentiometer setting in binary notation will increase from 100 to lO1 as the analog-to-digital con-verter output moves from value D to value E. By ignoring a change in potentiometer setting wherein bits 1 and 2 are l~ either ll or 00, a hysteresis ef~ect is obtained.

TABLE l Bit Number: 7 6 5 4 3 2 1 0 Value ~5 ; 1 0 0 1 l 1 0 0 - - - - - - A

. 1 0 0 1 1 1 1 0 - - - - - - C
l 0 0 1 1 1 l 1 - - - - - - D
l 0 1 0 0 0 0 0 - - - - - - E

l 0 l 0 0 0 1 0 - ~ - G
0 1. 0 0 0 1 1 - - - - - - ~1 i '5 Remembering that the hysteresis test is onl~
performed if there is a change in the upper three bits of the ADC output, it can be seen that an increase in ADC
output from value B to value C will not result in a new value being stored, since the upper three bits of B and C
are the same. An increase from value B to value G, how-ever, would clearly result in a new value being stored, since bit 5 of the output changed from a zero to a one.
Without the hysteresis test being performed, an increase in ~DC output from value C to value F would simi-larly result in a new potentiometer value being stored.

æ~
49,001; 49,002; 49,00~: 49,006; ~19,009; l~9,010; ~9,013;
49,048; ~9 ,0~!~; 49,050 however, this represents a change in value of about ~/256 of the maximum potentiometer, or less than l.2%. Such variation can easily occur due to changes in ambient temperature.
Through the use of the hysteresis test, wherein ADC outputs having equal values of bits l and 2 are ig-nored, it can be seen that a change in ADC output from value C to value F would result in the new potentiometer setting being ignored and the old potentiometer setting being reloaded into RAM, since bits l and 2 of value F are both zero. Similarly, if the operator were reducing the value of the potentiometer, causing an ADC output to change from value G to value C the new value would also be ignored and the old value retained, si.nce bits l and 2 of value C are both one, and the hysteresis test would rejeet : the new setting. It can therefore be seen that the hys-teresis test insures that the potentiometer setting rnust be changed by more than 4/256 of its total possible ad-justment before a new setting will be accepted. It can be 23 argued that the hysteresis test just described is not suf-ficiently precise, in that a valid setting change may possibly be ignored. This might occur, for example, if the old potentiometer setting produced an ADC output much larger than value H, for example l0ll010l, and the new 2~, potentiometer setting produced an ADC output equal to value D. It can be seen that this represc-nts a very large excursion in the rotation of the potentiometer, and yet the final position produci.ng a vaLue e~ual to va1ue D
would be ignored, since bits l and 2 are both ONE's. It 3~ must be remembered, however, tha~ an int.eractive operation is bei.ng performed, and that the paraoeter value selected by the READ routine is, from the point of view of a human operator, instantaneously presented on the numeric dis-plays 80 or 82. In the example just cited, the operator would see that a fairly large excursion of the potentiome-ter produced no change in value, and he would natural1y 49, 001; 49, 002; 49, 004; 49, 006; 49, 009; ~Iq, ()1 0; / 9, 01 3;
(~9 , 048; 49 , ()~ I 9 , 050 v~ f~rtl~ Ju~tm~nl~ At so~ ()int, lli~
further adjustments would result in a new value being selected by the READ routine and presented under numeric display. If the change produced were larger than desired, the operator would then readjust in the opposite direc-tion, the entire operation taking much less time to per-form than to explain. This represents an extremely cost-effective and convenient method of entering parameter changes for the time current tripping characteristic into a circuit breaker. Adjustment of the potentiometer to the extreme upper and lower limits will cause the most con-servative value to be displayed.
In the event that bit 2 is not equal to bit 3, that is the hysteresis test does not cause the setting to be ignored, a bit pattern is loaded in register R7 to cause display of this setting value on the numeric dis-plays 80 or 82. The four-second timer is then reset and the new setting va:lue is stored in the RAM location corre-sponding to this particular parameter. The subroutine 2Q then returns to the calling function.
If an ADC output of all zero's or all one's is obcained, the READ routine interprets this as a poten-tiometer fail.ure. The most conservative parameter value is then selected from the look-up t.a~le, displayed on the numeric display 80 or 82, and stored in RAM.
I. Hardware_lnitlallzation_After Power-On -f~'a~r~ IG
The microcomputer 154 must be i.nitialized fo~-lowing power-up. In the case of the Intel 8048 devicc this is accomplished by means of a RS pin which if held ~-~ ]ow auses the program to " jump" to address () which i~y convention is the starting address of the power-on start-up subroutine. The RS pin is held low by the power supply by means of D900 for about 5 ms, after the +5 VDC is applied.
3r~ ~owever, the RS pin does not affect the I/O
lines from the microcomputer and thus during the power ON

.~

49 00l; 49,00~; L~9 O()l~; 49,0()~ 9,009; ~9,010; 49,013;
49,04~ (3l0~9; 49,050 transient these may assume either a high or low output state which, in the case of four particular lines of Port l and Port 2, can cause excessive power supply drain or even accidental tripping of the circuit breaker 10 or other interconnected breakers. These lines are as fol-lows:
1. LE~ (line 6 of Port 2--should be low to ensure all LED indicators on front panel are OFF).
1~ 2. INHIBIT 212 (line 7 of Port 2--should be tristated, that is, held in a high-imped-ance state to ensure that all 8 digits of the 7-segment LED displays 80 and 82 are OFF).
3. PULSE 178 (line 7 of Port 1--should be tristated to ensure that pulse transformer 501 is OFF).
4. TRIP 190 (line 4 of Port l--should be tristated to ensure that no false trip occurs on power-on).
The desired tristating is achieved by means of hex buffer U900. When RS of the microcomputer 154 is low, : the DISABLE (A) of U900 is low (removed) which causes DISABLE (B) to be high (active). In this way the four , 2~) critical leads from the microcomputer 154 are switched to the high impedance state, excep~. for LEI) which is held low s as desired by the pull-down resistor R905.
A second function of U900 is to reset counter U901 as shown in Fig. 16.
J. Automatic Reset ~ ~ r~ I ~
Once a successful power-up transition is made, the microcomputer 154 continues to execute a logical and ~, sequential series of instructions indefinitely. Under unusual conditions, such as those produced by electrical 35 system transients, it is possible for an instruction to be improperly executed. The only way to restore the micro-.

2~

49,001; 49,002; 49,0~4; 4g,~06; 49,009; 49,010; 49,013;
49,048; 49,049; 49,050 computer 154 to its orderly program execution is to per-form another reset operation. In unattended applications, this reset must be automatic.
This is accomplished by means of counter U90l which utilizes a 400 kHz clock output (ALE) from the microcomputer 154 to provide a fixed time delay betweer, the last U901 RS pulse and a high on Q11 (RS for the~ C).
If the RS pulse of U901 occurs soon enough, Qll will remain low and the ~C will not be reset.
The U901 RS pulses are derived from the col-lector of transistor 228. Normally these pulses are 100 ~ s wide and occur approximately every 2 ms. The circuit is designed so that 5.46 ms is required for O~11 to time out (go high) and thus Qll is always low.
If improper instruction execution sequence occurs, the following possible conditions would cause an j automatic reset of the microcomputer (Q11 would time out).
~ 228-ON
.
If this condition should exist for more than 300,~¢s, pulse transformer 501 will saturate and U901 RS
will remain low.

__ If this condition should exist, U901 RS will . remain low.
2~ 228-Pulse Rate Too Slowly If transistor 228 turn-on pulses occur less than every 5.46 ms, the U901 RS will be low long enough for a,~C reset to occur.
228-Pulsed Too Fast 3~ Rapid pulsing of transistor 228 will be filtered b~ R900 and C900 (39~<s time constant).
-ON/OFF Duty Cycle > 1/10 Transformer T501 is pulsed on for 100 ~ s, to a voltage of 5 volts, by transistor 228. When 228 is turned 3~ OFF, the transformer's magnetizing current will flow ; through diode D901 which will result in a voltage of about 5~
49,001; 49,0~2; ~9,004; 49,006; 49,009; ~19,010; ~9,013;
49,048; ~9,~49; ~9,05 -.5 volts being applied to the tranx~ormer 501. rhe average voltage of the transformer must be zero and thus 1000,~< s (~ x 100 ,~s) .5 will be required to "reset" the transformer's magnetizing . current to zero. A l-to-10 or less ON-to-OFF ratio must be maintained for the transformer 501 to function or the transformer's core will ultimately saturate. If trans-former 501 is saturated, the RS pulses will not be applied to U901 and Qll will time out and re~et the mlcrocomputer.

. . .

Claims (14)

63 49,010 What we claim is:

1. Circuit interrupter apparatus comprising:
interrupter means for conducting current flow through an associated circuit and for operating to in-terrupt current flow therethrough upon command;
a phase current transformer coupled to the associated circuit;
trip unit means connected to said phase current transformer for comparing the output of said phase current transformer to a predetermined time-current trip character-istic and for operating said interrupter means whenever said output exceeds limits defined by said time-current trip characteristic;and power supply means connected to said phase current transformer and to a source of external power for supplying operating power to said trip unit, said power supply means selecting the most appropriate power source as between said phase current transformer and said. external power source.

2. Apparatus as claimed in claim 1 comprising a ground current transformer coupled to the associated circuit and connected to said power supply, and said power supply means comprises means for selecting either said phase current transformer output or said ground current transformer output for comparison against an external power source, according to which of said current transformers has the highest output current.

3. Apparatus as recited in claim 1 comprising means adapted for connection to a plurality of external 64 49,010 power sources, and means for selecting the one of said external power sources having the highest current output.

4. Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated circuit and for operating to inter-rupt current flow therethrough on command;
sensing means for sensing current flow through said interrupter means;
trip unit means connected to said interrupter means and said sensing means for operating said inter-rupter means whenever current flow therethrough exceeds a predetermined. time-current trip characteristic, said trip unit means comprising electronic circuit means for provid-ing a plurality of functions; and power supply means connected to said sensing means for supplying operating power to said trip unit means, said trip unit means comprising low-power condition sensing means for causing said electronic circuit means to execute a subset of said plurality of functions upon detection of low-power conditions at the input of said power supply means.

5. Apparatus as recited in claim 4 wherein said power supply means produces pulses of operating power to said trip unit means upon detection of low-current condi-tions.

6. Apparatus as claimed in claim 5 wherein said trip unit means comprises a numeric display device and microcomputer means for causing said display device to display a plurality of sequential numeric values under normal conditions and for executing a plurality of pro-tection functions during a predetermined time period less than the duration of said power pulses, said microcomputer means comprising means for altering said normal display sequence, for executing all of said protection functions, and for displaying a predetermined one of said normal display values during such low-power conditions as would cause generation of said operating power pulses.

49,010

7. A circuit breaker, comprising:
interrupter means comprising a spring-powered mechanism for conducting current flow through an associated circuit and for operating upon energization for a prede-termined time period to interrupt the current flow therethrough on command;
sensing means for sensing current flow through said interrupter means;
trip unit means connected between said interrupter means and said sensing means for comparing current flow through said interrupter means to a predetermined time-current trip characteristic and for operating said interrupter means whenever current flow therethrough exceeds said time-current trip characteristic;
power supply means for supplying all electrical operating power to said trip unit means and to said inter-rupter means; and a non-latching switching device for energizing said interrupter means from said power supply means upon actuation by said trip unit means;
said trip unit means actuating said non-latching switching device for said predetermined time period, where by said interrupter means operates to interrupt current flow on the associated circuit whenever current flow therethrough exceeds a time-current trip characteristic, but does not so operate when said non-latching switching device is actuated by noise pulses less than said predetermined time period.

8. Apparatus as claimed in claim 7 wherein said power supply means comprises an energy storage device.

9. Apparatus as claimed in claim 8 wherein said energy storage device comprises a battery.

10. Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated curcuit and for operating to inter-rupt current flow therethrough on command;
sensing means for sensing current flow through said interrupter means;

66 49,010 trip unit means connected to said interrupter means and said sensing means for comparing current flow through said interrupter means to a predetermined time-current trip characteristic and for operating said inter-rupter means whenever current flow therethrough exceeds said time-current trip characteristic; and power supply means connected to said sensing means for supplying operating power at a first voltage to said trip unit means and operating power at a second voltage to said interrupter means;
said trip unit means comprising means for de-tecting impending failure of said power supply means to supply adequate operating power to said trip unit means and to said interrupter means and for executing a prede-termined power-down protection sequence to prevent nuis-ance tripping upon failure of said operating power.

11. Apparatus as recited in claim 10 wherein said power supply means comprises energy storage means for storing an amount of energy sufficient to maintain operat-ing power to said trip unit means and said interrupter means for a predetermined time, and said power supply means comprises time delay means for maintaining operating power to said trip unit means from said energy storage means for a predetermined time sufficient to execute a power-down sequence and prevent nuisance tripping upon failure of operating power to said trip unit means.

12. Apparatus as recited in claim 11 wherein said power supply means comprises means adapted for draw-ing supply power from a plurality of power sources, and said power supply means comprises a like number of criter-ia for determining failure of said power sources.

13. Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated circuit and for operating to inter-rupt current flow therethrough on command;
sensing and empowering means for sensing current flow through said interrupter and for supplying operating power to said interrupter means and to associated elec-67 49,010 tronic circuitry;
trip unit means connected to said interrupter means and to said sensing and empowering means for compar-ing current flow through said interrupter means to a pre-determined time-current trip characteristic and for operat-ing said interrupter means when current flow therethrough exceeds time-current trip characteristics; and power supply means connected to said sensing and.
empowering means, to said trip unit means, and to said interrupter means for supplying operating power from said sensing and empowering means to said trip unit means and to said interrupter means, said power supply means com-prising energy storage means and shorting means for di-verting the output of said sensing and empowering means from said energy storage means and for supplying a short circuit across the output of said sensing and empowering means when said sensing and empowering means output rises above a predetermined level.

14. Circuit interrupter apparatus, comprising:
interrupter means for conducting current flow through an associated circuit and for operating to interrupt current flow therethrough on command;
a current transformer for providing the dual func-tion of sensing current flow through said interrupter means and deriving power from the associated circuit trip unit means connected to said interrupter means and said current transformer for operating said interrupter means whenever current flow therethrough exceeds a prede-termined time-current trip characteristic; and power supply means connected to said current transformer for supplying operating power to said trip unit means, said trip unit means comprising means for sensing low-power conditions at the input of said power supply means; said power supply means comprising means producing pulses of operating power to said trip unit means upon detection of low-current conditions.