CA1168749A - Filter and system incorporating the filter for processing discrete samples of composit signals - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A system for processing discrete digitized samples representing composite signals utilizing a filter which eliminates a periodic signal component from the composite signal. The filter receives and stores consecutive digital sample representations of the composite signal and, for each received sample representation, provides a digital average representation of the value of a selected number of the received digital sample represen-tations which define a zero average value of the periodic signal component. In one embodiment of the signal processing system, the filter is arranged in circuit with digital delays and digital signal combining and differencing circuits to form a digital color television signal dropout compensator, which is adaptable for use in NTSC, PAL, PAL-M, or other television standard systems. In a dropout compensator adapted for NTSC
color television signals, the filter receives the digital composite television signal and eliminates the chrominance component therefrom, leaving only the luminance component at its output. A following digital subtractor is coupled to subtract the luminance component provided by the filter from the received digital composite television signal and provide the chrominance component at its output. The separated chrominance component is phase adjusted on consecutive television lines and recombined with the separated luminance component provided by the filter for substitution in the tele-vision signal in place of the dropout affected portion thereof. The dropout compensator also includes a digital delay of one horizontal line period through which the television signal components are passed to provide the delay necessary for substituting television signal information from a prior horizontal line.

Description

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This is a d:ivisional application of Canadian Application 362,754 filed October 20, 1980.
BACKGROUND OF THE INVENTION
The present invention relates to a filter for processing composite signals and a dropout compensator utilizing the filter and, more particularly, to a filter for processing digital representations of composite signals and a digital dropout compensator utilizing the filter for separating components of a composite signal.

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~ 4 ID-2635 In systems for processing composite signals~
it i~ often desirable to separate various signal compo nents into different signal paths for individual process-ing and then recombine the processed components into a composite signal form for ~urther use. Known devices for separating composite signals composed of di~ferent fre~uency components are comb fil~ers~ Generally, comb filters are known as multiple bandpass fi~ters desig~ed to pass signals of selected frequency bands and to reject signals outside the selected frequency bands, For example, in processing color television si~nals, comb filters are widely utilized fOÆ
separating the luminance and chrominance componentsO One such comb fil~er produces the . desired separation by processing discr~te digitized samples reprecenting the analog color television signal and pro~iding a weighted avera~e of three samples taken ~rom three consecutive horizontal lines o~ the same field a~ ver~ically aligned picture elements of the lines~ The averag ng is repeated for aLl picture elements.
While this method is applicable to analog signalsg it is 20 par~icularly suitable for di~italïy encoded signals, since these typically ~epres n~ samples of discre~e signal values .~ occurring at a known sampling frequency~ ~owever, to obtain samples from the vertically aligned picture elements often : requires selec~ion of ~pecial sampling rates or special ~ 25 sampling phases and the addi on of further sample processiny ; circuits, thus complicating the apparatus~

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For example, in some standard color television , signal systems, ~he color subcarrier signal component differs in phase on adjacent lines of the television field raster. In NT5C systems, the phase di~erence is 5 180 degrees; and, in PAL and P~L-~ systems, it is 90 degrees. Some digital signal processin~ systems for such television signals utilize a sampllng signal f~equency ~hat is an odd multiple of the subcarrier signal ~requencyO To obtain samples of such television 10 signals corresponding to locations of vertically aligned picture elements, the aforementioned further circuits are necessary to provid~ line-to-line phase adjustment of the sampling o the television signal. If samples :~/ corresponding to locations of vertically misaligned 15 picture elemen~s are comb filtered, picture distortion results. ~s an example, a circui~ for ~enerating samples corresponding to vertically aligned picture element locations within a television field raster is described in U. S. Patent NoO 4~075~656O The above 20 patent reveals that such circuit contributes to the : complexi~y of the overall system for processing digi-$ized color television signalsO A prior art digital comb filter circuit suitable for NTSC systems is - described in TJ. SO Patent No. 4,143,396~ While this 25 type o comb :Eiltering is suitable for NTSC systems, the specific embodiments described in the 4,143,396 patent mus~ be provided with further processing : circuitry for other color television systems; such as :~ ~ PAL~ PAL-Mt etc., where the different chrominance I~^2635 component line-to-line phase characteristics create additional problems in obtaining samples orresponding : to locations of vertically aligned picture elements of consecutive linesO
Color television signal dropout compensators are examples of television signal processing devices in which ~he a~ove problems are encountered. Dropout compensators are widely utilized in sys~ems for process-ing color television signals, such as for magnetic recording and re~roduction, to replace a deficient or missing por~ion of the color television signal informa-tion, commonly called a ~dropout", due to unpredictable . instan.taneous mal~unction of the system or to diminutive defects o~ the recording medium. When such dropouts lS occur in the television signal, ~hey produce visible disturbances in the displayed picture. Dropout compensa~
tors reduc the disturbing effect of dropouts seen by the viewer.

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Most prior art analog dropout compen~ators employ an R. F. envelope le~el detector which monitors the amplitude level of tha modulated television sign~l carrier waveformO A switch normally applies ~he incomihg ; continuous television signal to an ou~pu~ terminal of the compensator. A delay line is arranged .in the television s;ignal path, for example, between an input terminal of the compensator and an input terminal of th~
switch or be~ween ~he ou~p~t ter~inal of ~he co~pensator and the input terminal of the switch. When ~ drop in the R. ~ envelope level is detected, the switch is controlled .. . . .

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to apply the delayed signal to the output terminal, instead of the incomin~ televi.sion signal. The delayed signal thus replaces the deficien~, information. When the ~. F. en~elope level returns to normal, the switoh is controlled to switch its input from the dela~ed signal back ~o the incoming television signal, which i~
then applied to the output terminal~ As an example, a prior art analog dropou~ compensator of the above ~ype is described in the U. S. Patent NoO 2~996,576~
10There are known analog dropout compensators utilized in color television systems which separate the continuous color television signal.into the luminance and chrominance components, delay the components by one or ~wo television line periods and inver~ the chrominance 15 component on consecutive lines to assur~ i~s p~oper phase ~hen ~ubs~ituted for a dropout in the color television signal, E~owever, in color television ~ystems in which th~ signal is in ~he form of di~itized samplesr utilization of digital comb fil~ers for separat.ing the 20 components often requires use of the aforementioned additional complex signal processing eircuits to obtain samples corresponding to vertically aligned picture element locations throughout each field of the television : signal.
25 An example of another prior art digital dropout compensator is described in the manual "AVR-2 Video Tape Recorder, Theory of Operation" t Catalog No~
18009179-01, published by Ampe~ Corporation, November, ~: -6-`r~e~ ID~ 63 5 1977, pages 9-10, ~-14, 9-20 and 9~77 to 9~92. This particul~r dropout compensator replaces individual digital samples of data or an entire line of data with the corresponding data from an earlier o~curring line of the 5 same field. The dropout signal to be substituted ~or the deficient information is stored alternately on a line-by-line basis in one of two 256-bit shi~ r~gis~ers forming a two-line delay circuit. While the data for one horizon~al line is being writ~en in~o one o~ the shift registers, the data from ~wo lines earlier is being read out from the same shift regis~era In this latter applica~ion, ~he chrominance and luminance signals are not separated for processing. However, the color television signal information replacing ~he 15 dropou~ signal is delayed by two lines of the same field. The interlacin~ property of typical television : signals results in the delayed signal appearing in ~he .
:: display of the television signal at a location four . .
. horizontal line positions away rom its real time positionO
20 In some cases~ the display of the dropout compensated signal is quite disturbing to the eye, especially if sharp vextically oriented patterns are represented on i the screenO Such vertically-oriented patterns will bè
horizontally displaced in the dropout compensation lines ~, .
~5 relative to t:he adjacent undelayed lines.

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In accordance with the present invention there is provided a digital filte.r circuit for processing a digitally encoded composite signal having a periodic signal component of a known frequency and symmetrical with respect to a signal crossing axis, the encoded composite signal comprising consecutive digital representations corresponding to discrete amplitude values thereof provided at a frequency equal to a rational number multiple of the periodic signal frequency and in a frequency and phase-locked relationship to the periodic signal, the rational number multiple frequency being greater than t~ice the frequency of the highest frequency component of the composite signal, comprising in combination: a firs-t means coupled to receive and store the consecutive digital representations of the composite signal;
and a second means coupled to the first means for arithmetically combining a given number of consecutive digital representations defining a zero average value of the periodic signal component, to provide an average value output signal representative of the digitally encoded composite signal from whlch the periodic signal component is eliminated.

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In accordance with a second aspect of the present invention there is provided a method for processing a composite signal comprisi.ng a periodic signal component of a known frequency and symmetrical with respect to a signal crossing axis, the composite signal being encoded in the form of consecutive digital representations by sampling at a frequency equal to a rational number multiple ~requency of the known periodic signal, the rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, comprising the steps of: receiving and storing consecutive digital representations of the composite signal; and arithmetically combining a given number of consecutive digital representations which define a zero average value of the periodic signal component to provide an average value output signal representative of the digital composite signal from which the periodic signal component is eliminated.
BRIEF DESCRIPTION OF THE DRAWINGS
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. 20 Fig. 1 is a block diagram of a preferred embodiment of the filter circuit of the invention.
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~ 2635 Fig. 2 is a block diagram o~ a preferred embodiment of the filter circuit of the invention.
Figs~ 3a and 3b are graphical representations of the generation of digitized samples processed by the S embodiment of the filter circuit of the invention illus~rated by Fig. 2.
Fig. 4 . is an examp:Le o~ a frequency character-istic of the embodiment of the filter circuit of the invention illustrated by Fig. 2.
Fi~. 5 is a graphi~al representation of ~he generation of digitized samples processed by an alterna tive embodiment of the ~ilter circuit illustrated by .
Fi~. 2.
Fig~ ~ is a block diagram of an alternative embodiment o~ the filter circu.it of the invention.
Fig.. 7 is a graphical represen~a ion of the generation of digitiæed samples processed by the embodi men~ of the filter circuit of the invention illu~tra~ed by Fig. 6.
~; 20 Figs. 8 to 12 are block diagrams of ;rarious p~eferred embodimen~s of ~he dropout compensator of the `
- invention utilizing the filter circuit of the invention.
~i~s. 13a ~o 13~ are consecutive par~s of a detailed circuit diagram of the fil~er circuit embodiment illustrated .in the block diagram of Fig~ 80 Figs. 14 and 15 are block diagxams of embodi-: ments of the dropout compensator of ~he nvention - utilizing the filter circuit of the invention and , :

~ 7~ XD-2635 arranged for compensating PAI. and PAL-M color television signals.
Figs. 16a and 16b`are consecutive parts of a detailed circuit dia~ram of an alternativ~ memory address generator embodiment for use in the dropout compensator illustrated in ~igs~3a to 13h to adapt the compensator for PAL col~r television signal applications.
DESCRIPTION OF THE PREFERRED AND ALTERNATIVE EMBODIMENTS
Preferred embodiments of the fil-ter of the ~lesent invention will be described, followed by the description of examples o~ the utilization o~ the filter in systems for processing digital composite signals. .
The f~lter of the present invention is a type of digital comb fil~er constructed to process a digital type composite information signal including two or more . frequency components. By the filter of the present invention, one or more selected components of the composite information signal are eliminated by filtering~
For simplicity of description, the composite information signal is referred to herein as the composite signal The ~ digital type signal to be processed may be obtained~ for : example, by sampling a composite analog signal utilizing `~ a sampling clock signal which is frequency and phase-locked to the selected frequency component or components, to be ,~, 25 filtered, as will be described hereinbelowO Digital representations of the samples are generated by a quantiæer that receives each sample represen~ing a discrete amplitude value of the composite analoy signal : and converts or encodes it into a suitable digital c~de, i__2635 ~ 3 such as an NRZ code. These digital representations of the samples are combined in the filter of the present invention in such a manner that one or more selected periodic symmelrical signal components, each having a known nominal frequency, are eliminated from the composite signal. More specifically, the filter of the presen~, inven~ion receives and stores Eor a selected interval consecutive samples representing the composite signal from which one or more periodic signal components are to be removed by the fil~er. The filter continuously combines a selected number of the received samples to provide a digital average representation of the values of ~he combined samples which define a zero average value of the gelected periodic signal component or 15 Components.
The filter comprises a combination of digital storage devices, such as delaysy and arithmetic circuitry arranged and operated ~o provide a~ ~he filter's output for each digitized sample received at the filter's ~ input a digital average representation of the values of a selected number of received samples. The number of samples averaged is selected to define a time interval which provides a zero average value of the portion of the averaged digital sample representations correspond~
ing to the signal component to be eliminated from ~he :: composite signal by the filter. The operation of the combination of digital storage and arithmetic means for processing the received digitized samples to obtain a ' , I~-2~35 7~L~

running digital average representation of the values thereof is controlled by a cl.ock signal that has a frequency which is synchroniz:ed and e~ual to the f~e~uency at which the samples are received by the filter. As will become more apparent ~rom the follo~ing des~rip~ion, an important feature of the ~)resent invent.iQn i.s ~he capability of the filter to .~ilter out or eli~inate selected signal components from digitized samples of a composite signal transmitted to the filter at an unpre-dickable and randomly varying ra~eO In such applications ; o the present invention, the fre~uency of the filter's clock signal must vary synchronously with the varyin~
~ rate o~ receipt of the digitized samples by the filter, `~ Of course, a stable frequency clock signal is provided to the filter in those applications where the digitizedsamples are received by ~he fil~er at a sta~le ra~e.
Fig~ 1 illustra~es an embodiment of ~he filter of ~he inven~ion arranged to filter a selecte~ 3~58 MHz chrominance signal component rom a composite analog 20 NTSC color television signal. Typically~ the composite ; colo~ television signal is an analog signal~ often : containing randomly varying time base error~. In ;;
accordance with the present invention, the analog signal ; first is converted ~o a binary coded digital signal and 25 then is passed through the signal delays and ari~hmetic circuitry to remove the selected frequency co~nponent.

~ore specifically, the analog composite color television :signal received at an input terminal 80 IS coupled to an inpu~ of a video signal processor 81. The signal processor 81 is a conventional arrangement o~ circuitry found in color television signal processing CJ~;tem.s, such as time base corr ctors, that amplifies the ~eceived signal, provides D. C. resto:ration and separates the vertical .~ield and horizonta:l line syn~hronizing compo-nents (vertical and horizontal sync) as well as the color burst synchroni2ing component, respectively, from the composite signalO The above-indicated respective synchronizing components are then furthe~ utilized in the following signal processing for synchronization purposes. The analog composite signal obtained at the output of t~e signal processor Bl i5 coupled to an input of an analog-to-digital (A/D) converte~ 82 which encodes or converts the analog signal to a binary coded signalO
~; In one pre~erred embodiment~ an ~/D convelter 82 i.~
employed in which the composite analog NTSC television signal is sampled at a rate of three times the subcarri~r si~nal fre~uency, that is, 3 x 3.58 MHz or appro~imately 20 10~7 MHz. Each sample is digitally yuantized into a~
NRZ digital word composed of 8 parallel bits. In accor-dance wi~-h the present invention, a 10.7 M~z sampling clock signal tha~ is substan~ially coherent with ~he 3.$8 M~z chrominance si~nal component to be filtered rom the composite television signal is employed to clock the A/:D conuerter 82 to effect the sampling and quantizing of the composite analog telev;sion signal.
The 10 ~ 7 M~z clock signal is generated by a sampling --lg--clock signal generator 83 from the color burstO horizon-tal line and vertical field synchronizing components ob~ained from a television synchronizing signal separatox included in ~he signal processor 81. While ~mall phase variations may be present in the horizontal line of video inrormation following the color burst interval due to velocity errors and the like, particularl~, when such signals are ob~ained from video recorder television signal sources, such varia~ions are ~o small that they can be disregarded and the 10.7 M~z clock signal can be considered coheren~ with the 3.58 M~æ chrominance signal component for purposes of the invention described herein, Some television signals contain a continuously available pilot signal~ In those cases, the pilo sign~l may be lS used to generate a 10.7 MHz clock signal that is truly coherent wi~h the 3.58 MHz chrominance signal componenk.
The A/D converter 82 responds to the 10.7 M~z , clock signal provided at its clock input terminal by the clock signal generator 83 and a clamp control si~nal provided at its clamp con~rol input terminal by ~he signal processor 81 to provide at the output of A/D
converter 82 the NRZ digi~cal words representative of the input analog television signal. The 8-bit NR~ digital words provided by the A/D converter 82 are applied over 25 eight parallel lines 84 to the filter circuit 2,>
The circuit details of the si~nal processor 81, A/D converter 82 and clock signal generator 83 are : not shown or described herein as they are ident;cal in I~2635 7~"3 their design and operation as those incorporated in the Ampex Corporation TBC-l digital time base corrector, More specirically, the schematic diagrams of those circuits are shown in ~he catalog number 18092-/4-02 5 published by Ampex Corporation in November, 1~77. The specific circuitry for the signal processor 81 is shown in schematic drawing No. 1406103A appearing on page 29/30; the ~/D converter 82 is shown in schematic drawing Nos. 1402409B and 1401312, respectively, appearing on pages 37J3~ and 43/44, respectively; and the clock signal generator 83 is shown in schematic : drawing No. 1402337 appearing on pages 49/S0 and 51j52~
I the digitized television signal is coupled directly from the A/D con~er~er 82 ~o the input of the filter 2 withou~ further altera~ion of the data rate, as in ~he embodiment illustrated by ~igs. 1, 2 or 5, ~he 10.7 MHz clock signal generated by the clock signal generator 83 is also coupled to the filter 2 to clock the filter ' s circuit elements or means utilized in the 20 processing of tha composite digitized television signal to remove the selected periodic signal component.
. ~ , Howeverf if a recloc~ing or buffer circui~ means (not : shown~ is p}aced in the signal path be~ween the A/D

converter 82 and the filter 2 to alter the data rate o~

: 25 the diyitized television signal before coupling it to , th filter, for example, as would be necessary to synchronize an unstable digitized signal to a frequency stable reference, a corresponding frequency stable :

~ -2635 reference clock signal would be employed to clock the ~ilter's circuit elements. Of course~ the frequency stable reference clork signa:L would be generated to have the same frequency and synchronous relationship relative to the reclocked selected periodic signal component as described hereinabove.
The 8-bit digital word output signal from the analog-to-digital converter 82 is applied to an input of the ~ilter circuit 2 of the invention via connectin~
line 85. Generally, the filter circuit 2 o~ the invention comprises a cooperative combination of circuit element~, which in the preferred embodiment of Fig. 1 are shown as delay means 84, signal combiner means 86 and signal divid~r means 87. ~s i~ will be described in more detail hereinbelow, the filter circui~ 2 receives consecutive digital sample~ from the above~indicated A/D
converter and delays and combines them to provide a digi~al average representa~ion o~ the values of the combined samples by processing a selected number of

2~ samples rep~esenting the analog color television signal received at the input terminal 80. The number of digital samples combined to provide the digital aYerage represen~ation is selected ~ith respect ~o the relation-ship between the ~lock signal frequency and frequency of ~S the selected signal component to be eliminated by the filter in such a manner that the digital average repre-se~tation at the outpu~ of the filter represents an average signal value of the com~osite signal and t at the ~ 7 ~

same time, a zero averaye va:Lue of the selected frequency componentO
Now, the operation o:E the filter circuit 2 of Fig~ 1 w~ll b~ described in general, followed by the description of the specific preferred embodiments shown in ~igs. 2 ~nd 5, respectively.
The delay means 85 rece~ves the consecutive digitized samples from ~he A/D converter ~2, and it delay~ or stores each sampl~ for a predetermined number of ~ample intervals so th~t a selected number of : received samples are simultaneously accessable for arithmetic combinatlon~ In the preferred embodiments of the Pil~er circuik 2, the delay means includes a plurality of parallel sign~l transmission paths having siynal delay elements that provide different transmission times between the input and output o~
the delay means for each received sample so that he selected number of di~feren~ received samples are simul~aneously provided to ~he signal combiner 20 means 86. The selec~ed num~er of delayed samples transmitted ~hrouyh ~he delay ~eans 85 are applied via respective conn~cting lines 89 to associated inputs of the si~nal combiner means 86. The signal cnmbiner means arithmetically combines selected 25 samples and provides at its output a digital xepresentation of the value of the combined samples~
The digital representation is applied to an input : of the signal divider means 87 via connectiny .
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1~-2635 line 90. The signal divider means 87 divides the combined sample value to provide at its outpuk 91 a digital average representation of the values af the combined samples. The number of samples combined, 5 the arithmetic combinational factor and the divisor are selected so that the signal p~ov~ded at ~he output 91 of the filter circuit 2 ~s a digital average representation of ~he values of the combi~ed samples that defines a zero average value of the 10 selec~ed frequency component. In this manner, t.he selected freque~cy component ~s el~minated from the composi~e signal by the filter circui~ 20 Now, preferred embodiments of the filter circuit 2 shown .
in Figs. 2 and 5 will be described.
;~ ~5 The filter circuit of ~ig. 2 provi~es a ; digital average representation o~ the values of three consecutive dig~tal sample represen~ations, Sl, S2, S3~ received in succes~ion fromg for example, an ~/D
converter ~, su~h as shown in Fig . 1~. The fil~er circui~
20 of Fig. 2 u~ilizes a cascade combination of digital devices, ~ ncluding registers~ b nary adders and a divider, arranged to form three parallel transmission paths of different transmission times for each of the received samples~. Each consecutive sample gener ated by 25 the A/D conY~erter 82 shown in Fig. 1 is coupled by ~he eight parallel connecting lines 84 to a~ înput o~ a clocked regi~ster 49, which serves as a ~iming buEfer between the A/D converter 82 and the fil~er circui~ 2 --19-- , 1~-2635 ~ 7 ~3 The propag~ion of the 8-bit digital word samples through the register 49, as well as through other clocked devices o~ the ~ilter ~ircuit 2, is controlled by the 10.7 M~z clock signal generated by the clock signal generator 83 ~Flg. 1) and provided over connecting l~ne 8~. The ou~pu~ of the register ~ .is coupled by lines I ~o an inpu~ of a clocked regis~er 50 and a first input of an adder 51~ Register 50 is clocked by the 10.7 M~z clock signal to receive the consecu~ive samples ~1~ S2, S3, etc~, coupled to its input by the clocked register 49 and delays each received sample by one clock cycle rela~ive ~o the ~ime the sample ~ppears on lines I coupling ~he output of the register ~9 to the inpu~ of register 50. The outpu~ of regis~er 50 is 15 coupled by connecting lines II to a second input of the aader 510 ~dder 51 is an ar~thme~ic device of the type ~hat provides at i~s ou~put coupled to connecting lines III the sum of its inputs received over lines I and IIo There~ore, adder 51 adds each one clock cycle delayed 20 sample received ~rom the regis~er 50 to ~he next consecu-tive sample received ~rom regis~er 49 to provide a running sum of ~wo consecutive samples output by the ~/D
converter ~2. Another clocked zegister 52 has i~s inpu~
coupled ~o the output of the adder 51 by the connecting 25 lines IXI and is clocked by the 10.7 M~z clock signal present on line 88 to receive the sum of two consecutive ~ samples provided by th~ adder 51~ Like regis~ers 49 and - 50, the regi~ter 52 provides a delay of one clo~k cycle r~ ~

for each sample sum received from the adder 51. The output of the register 52 is coupled by connecting lines IV to a second input of an aclder 53, which adder has its first input coupled by lines I to receive the consecutive samples from register 49. Aclder 53 provides on connect-ing lines V coupled to i~s output the sum of its inputs received over connec~ing lines I and IV. Therefore, a running sum of three consecutive samples provided by the A/D converter 82 through register 49 is present at the . 10 lines V coupled to the ou~put of the adder 53~ A
clocked divider 57 has its input cbupled to the outpu~ V
of adder 43 via a pre~eding register 54 and it provides a division by ~hree of the received sum of th~ee consecu-: tive samples. The register 54 immediately preceding the divider 57 (or register 56 in the filter circuit embodi-ment arranged to average four consecu~ive samples) is utilized to reclock the bits forming each averag~d 8-bit digital word and~ ~hereby, remove any bit skewing or transients that may be present in the averaged 8-bi~
digîtal word~ Bit skewing ;s caused by small differences in the propagation delays experienced by the individual bits of each 8 bit digital word as they are processed in parallel through the filter circuit. Transients are generated by active circult elements that immediately transmit to their outputs without clocking the results of signal s~ate changes a~ ~heir inputs~ The adders employed in the preferred embodiment of the fil~er circuit 2 are examples of such circuit elements in that ' I~-2635 7~

they are the kind in which changes in the logic level of the signals at their inputs are immediately transmitted to their outputO The registers 49, 50 and S2 also per~orm a reclocking function~ Should the bit skewing 5 and transients be tolerable or absent, the reclockin~
register immediately preceding khe divider 57 can be eliminated from the ilter circuik 2.
Each of the registers and the divider of the fil~er circuit delays the data received at its input by one clock cycle~ This delay resul~s ~rom the clocking of the registers and dividers because the digital sample represen~a~ions present at their inputs do not ~ppear at the.ir outputs until af~er ~he devices have been clocked by the 10.7 MHz clock signal. As a result of such 15 clocking, each sample proceeds along the seri~s circuit : ~ paths defined by ~he register and divider devices only in steps of one device per clock cycle.
In the filter circuit 2, th~ connec~ing lines ~:: I at its input branch into ~chree different signal ~ transmission paths to the output 91 of the filter circuitO The signal transmission times through the three paths dif er by integral multiples o~ the p~riod of ~he 10~7 M~z clock signal, with the transmis5ion time : through the :Longest signal transmission path being two 25 clock signal periods longer than ~he transmission ~ime through the shortest signal transmission path and the transmission time through the signal transmission path of intermediate length being one clock signal period i ~635 ~ 3 longer than the transmission time through the shortest signal transmi~sion path. The shortest signal trans-mission path between the connecting lines I and the output 91 of the filter circuit 2 includes the binary adder 53 followed by the register 54 and the divider 57. The register 54 and the divider 57, respectively, introduce a propagation delay of one clock signal cycle each in the signal transmi~sion pathD Conse~Iuentlyr the shortest signal transmission path has an overall signal transmission delay of two clGck signal cycles~ A~der 53, register 54 and divider 57 are common to the three signal transmission paths. Therefore, the aforementi~ned dL~ferences in ~he transmission times through the three paths must be established before~he adder 53O
The portion o~ the signal transmission path of intermediate leng~h ketween connecting ~ines X and the adder 53 includes another binary adder 51 followed by ~ the register 52. As described hereinabover the regist~r :~ : 52 introduces a propagation delay of one clock signal : 20 cycle in the signaL transmission pa~hO Consequen~ly, ; the signal transmission path of intermediate length provides a signal transmission delay between lines I and ~` ~
the connecting lines IV coupled to the second input of ~ the adder 53 of one clock signal cycle, which is one 25 c~cle longer than 'che delay throu~h the portion o$ the shortest slgnal transmission path between thP lines I
and the input to the adder 53. Thus, alt ~he same time that registe~' 52 provides data at khe second input o~

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the adder 53~ a sample that was yenerated one sample interval or clock period earlier by the A/D converter 82 of Fig. l is provided at the ~irst inpuk of the adder 53 over connecting lines I.
. 5 The longest signal transmission pa~h is formed in part by ~he signal transmission path of intermediate length, i.e., the path from adder 51 to divider 57 and in part by register 50. Since the register 50 introduces a propa~ation delay of one clock signal cycle in the transmission path, the signal transmission delay between the lines I and the connecting lines II coupled to the second inpu~ of the adder 51 is one clock signal cycle, which is one cycle longer than the signal transmission : delay through the transmission path of intermediate ; 15 length. Thus t at the same time that a sample is coupled ~; by lines I to the ~irst inpu~ of the ad~er 51, a sample generated one sample interval or oloc~ signal period~
earlier by the A/D conver~er 82 of Fi~ 1 is provided a~
the second input of the adder by the register 50O
Therefore, the longest signal transmission path provides a ~ignal transmission delay between lines I and the output of the filter circu.it 2 that is two cl~ck signal cycles longer than that provided by the shortest signal :~ transmission pa h~
The filter circuit illustrated by Fig. 2 provides an average of three consecutive samplesO If it is desired to provide ~ for example, an average of four consecutive samples, an additional addex 55 and clocked register 56 : - -2~-'~

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are added to the ~ilter circuit 2, coupled in cascade between register 5~ and divider 57, as shown by dashed lines. In this modified filter circuit, the divider 57 is a divide-by-four divider. For each additional sample averaged, an additional adder and register are coupled in the filter circuit of Fig. 2, preceding the divider 57 in the above-described m nner~ and the divider is implemented according1y. All the above digital devices are commercially available conventional devices, as will be apprecia~ed upon con~ideration o ~he detailed circuit diagram o~ Figs. 13a to 13h. The operation of the filter circuit of Fig. 2 will be described now with respect to particular circult locations indicated I, IIr IIX, etc., and as indicated in TAB. 1 below.
TAB. 1 Location Cl-ock Time I II III XV V VI VII
1 Sl _~ ~ .
2 52 Sl Sl+S2

3 s3 52 B2~S3 Sl~S~ 1 S2 S3

4 S4 S3 S3+~4 S2+S3 S2~S3+S4 Sl~S~S3 S 55 B4 B4+55 53+54 3 4 55 2 53 54 3 ( 1 2 3 ~ .

' :
~ .

~'`; ' . :
.

l~ 2635 7~

As shown in TAB. 1, each consecutive sample clocked to the output of the register 49 is recelved simultaneously oYer lines I at respective inpuks o~
registe~ 50; first adder 51 and second adder 53, as well as any further adder, such a~; 55, present .in the circuit~
At a first clock time l, regtster ~9 is clocked to plac~
sample Sl at its output, which is coupled by lines I
to the input of the register 50 and ~irst input o~ each o~ ~he adders 51, 53. Because of the clocking of 10 regis~er 49, sample 51 does not appear at its ou~put on lines I, henceD at the inpu~s of the adders 51-, 53 ~ and register S0, unt~l after the clocking of the regis~ers ;l and divldersO Consequently, sample Sl is not clocked at this ~ime ~hrough regi~ter 50 to the connecting lines 15 II ex~ending to the second input of ~he adder 51~ Each adder 51, S3, however, immediately responds to the receipt of a new digital sample representation at i~s input, ~uch as the appearance of sample Sl on lines I~
to couple to its output the sum of the new digital 20 sample represen ations at its inputs. While the sample ~.
~:~ Sl is present in the summed outputs of adders 51 and 53, such presence occurs after the clockYng of the followiny registers 52 and:S4; and, ~herefore, the sample ; Sl is not clocked~throu~h the registers 52 and 54 25 during clock time~l.
At the next clock time 2, sample S2-is ~ present a tXe input of register 49. Each of the :: registers 49, 50, ~2, 54 and d~v~der 57 is clocked to ~26- .

:
' ' 1~-2635 eEfect the transmission to their respective outputs o~
the data then present at theLr respective inputs, which occurs an interval after the onset of the clock.in~ A5 a result of the clocking, sarnple S2 appears at the S output of register 49, hence, on lines I extending to the inpu~s of th~ adders 51, 53 and register 50; reglster 50 tran~mits the previous sample Sl ~rom i'cs lnput to it~ output, hence, connecting line5 II extending to the second input o~ the adder 51; the summed samples appear-10 ing on connecting lines III coupled to the input ofregister 52 are ~ransmitted t~ the output o~ the register and placed on connectiny lines IV extending to a second input of ~he adder 53; the summed samples appearing on corsnecting lines V coupled to the input of register 54 are transmitted o the output of ~he regis~er and placed on connecting lines VI extending ~o the input of the divider 577 and ~h~ summed samples appearing on connect-ing lines VI coupled to the input o~ the divider 57 are divided by three and the divided output is transmi~ted to the divider's output and placed on connecting lirses VII. Following the aforedescribed clocking of the registers and divider, both adders 51 and 53 provide the new sample sum on lines III and V respectively coupled . ~ ~ to the outputs o~ adders.
At the next clock time 3, sample S3 is pr~sent at the input of the register 43 and the registers and divider are clocked to transmit the sample sum ~hen presen~ at t~seir respective inputs., As a result, adder 51 I~~263 ~ 7~ ~ .

receives sample S2 from khe clocked register 50 and sample S3 over lines I from the clocked ~egister ~9 and responsively provides the sample sum S2 ~ 53 on lines III connected to its output. Adder 53 receives the sample sum Sl ~ S2 over lines IV Erom the locked register 52 and the sample S3 over lines X
from the clocked register 49 and responsively provides the sample sum Sl + S~ + S3 on lines V connect~d to its output~ Clocked register 54 ~ransmi s the sample 10 sum previously provided at the output of the adder 53 ~o lines VI connected to î~s output and the clocked divider transmits the divided sample sum ~o lines VII connected ~' to its output.
At ~he next clock ~ime 4, sample S4 is 15 present at the input of the register 49 and the registers and divider are again clocked to transmit the sample sum theA present at ~heir respective inputsO As a result of this clocking, adder 51 rece~ves sample S3 over lines I~ from khe clocked register 50 and sample 5~ over 20 lines I frcm the clocked register 49 and responsively provides the sample sum S3~ S,~ on 1 ines III connected t:Q its outpUt. Adder 53 receives 'che ~ample sum 52 ~ S3 over lines IV from the clocked register 52 and the sample S4 over lines I from ~he clocked regis~er 49 25 and responsively provides the sample sum S2 + S3 + S~
on lines V connected to its output. Clocked register 49 transmits the sample sum Sl + S2 + S3 on lines VI
connected ~o its output and the clocked divide~ transmits the divided sample sum previously provided by the register 54 to lines VIX connected to its output.
At the next clock time 5, sample S5 is present at the input of the register 49 and the registers and divider are a~ain clocked to transmit ~he sample sum then present at their respect:ive inputs. In the manner described hereinbefore with respect to previously received samples, adder Sl places the sample sum S~ ~ S~
on the lines III coupled to its output, adder 53 places the sample sum S3 ~ S4 ~ S5 on lines V
coupled ~o its ou~pu~, register 54 transmits the sample sum S~ ~ S3 ~ S4 to the lines VI coupled to its outpu~ and divider 57 transmits the divided sample sum 3(Sl ~ S2 + S3) to the lines VII coupled to : 15 itC~ output, the di~ital representation of the average : ~alues of three consecutive samples~ For each subsequent 8-bit dlgital word sample received o~er lines 84 from ; ~h~ A/D converter 82, the adders, registers and divider cooperate to provide on lines VII t connected to the ou put o~ the divider 57, the digital average representa-tion of the values of each next three consecutive samples, whereby a running digit~l average representa-tion of the values of three consecutive samples of the signal received at the input of filter circuit 2 is provided at t:he ou~put 91 of the filter circui~
To illustrate the manner in which the foregoing operation of the filter circuit shown in Fig~ 2 eliminates a selected periodic fre~uency component of the composite :' 7~

analog signal, reference is directed to Fig. 3a. The periodic frequency component to be eliminated, represented as sine wave of amplitude v at frequency ~, is sampled at a frequency 3f by a clo~k signal that is in phase with the periodic signal component. According to the well-known Nyquist sampling theorem~ the .sampling frequency should be higher than twice the highest frequency of the sampled composite signal bandwidth. The sampling points on wave v are designated V1, ~2~ V3, V4, etc~, and are 120 degrees apar t . Each sampl ing po in t Vn represents a particular amplitude value of the sine wave,, In this example, a running average voltage value Ln .is obtained for each consecutiYe sample received by the filtPr by averaging the comb;ned amplitudes of three ~:15 consecu~ive ~amples. For filter embod~ments that are constructed and operate ~o provide an average value output for each received sample by averaging each samp:La with a given number of its immediately preceding and succeeding samples, the average value, L, of each sample, 20 y, 1 s ~iven by the equation:

T'n ~ ~ ~ Vl+V2 . . . +V ) ( 1 ) ;~where n is a known integral number of the samples averaged. Speci~ically~ when averaging three corlsecutive sampl es .

L3 = 3 (Vl~V2+V3 ) (2 , ~30-ti~

Because of the symmetrical properties of sine wave signals with respect tlo a signal crossing D~ Ca axis, any average value Ln obtained by averaging n consecutive sampl~s which dlefine an integral number of

5 signal oycles as described above with respect to equation (1) will be zero. This is true for an~ integral number of averaged sa~pl~s, greater than two per sine wave period and regardless of the phase points at which the sine wave is sampled, s.e., phase relationship between 10 the sine wave and sampling clock signal.
Furthermore, because the sampling signal or clock signal employed to control the arithmetic operations performed by the filter is, at ~he ~nput to the fil~er, frequ~ncy a~d phase-locked ~o the periodic si~nal 15 component to be separated or eliminated by the filter o~
the presen~ inven~iony the filter may be u~ilized, ~or example, to separate or el~minate signal components ~rom a composite signal having time base errors, such as resulting from a magnetic recording and reproducing 20 process.
An example of ~ampIlng a slne wave w of fre~uency utilizing a sampling clock signal having an arbitrary phase relationship thereto~ is shown in Fig.
: 3b. Equispaced sampling po~nts 1, 2, 3 and 4 of fre~uency 25 3f are shown displaced by 3 = 120 degrees with respect to the sine wave period T - 360 degrees~. There is an arbit:rary phase difference between the-wave, w, ~6~ 74~ ID-2 635 and the samp1ing clock signa1, represented by sampled points 1, 2, 3, 4, etcO The sine wave w may be generally de~ined as:
w~t) = A sin (B - C) ~) 5 where C is the arbitrary phase cliffere;lce be~ween the sine wave w and the sampling si~nal, and A is the amplitude.
Equation (3) may be further def ined as:
A sin (B - C) - Alcos B ~ A2 sin B (4) A1 = - sin C ( S ) A2 = cos C (6 ) When substituting particular amplitude and :~ phase angle va1ues for Al, A2? and cos C and sin C, respectively, into the above equations (3) to (6), the 15 sum of any three consecutive samp1es equals zero, and, :: thus, any averaye sample val,ue Ln as indicated in (1) also will be zero. The zero average values are plotted as L1, L2, L3, etc., in Fig. 3a and as 1', 2~, 3', : etc., in Fig. 3b. It i5 seen from both Figs. 3a and 3b 20 tha~ a full cycle of the selected signal component of the kind defined by equations (2) and (3) has equal and identical portions extending above and below a signal crossing Do C. axisO Consequently, the average D. CO value of that signal component is zero. An integral number, n, 25 of samples which define a time interva1 equal to an integral number, N, of one or more cycles of the selected periodic signal component to be eliminated by the filter circuit 2 comprise an equal number of ~positive~ and I~-2635 ~negativet' value samples whose average value, Lnt equals zero, that is, ~he summation of the values of sample~ from above the D. C. axis is cancelled by the summation of the values of the samples from below the D. C.
5 axis. In other words, an integral number of samples defining one or more integral cycles of the selected signal component have complemenl:ary ampl.itude levels above and below a signal crossing axis, which yield a zero average valuen This is true regardless of the phase 10 points at which the signal component waveform is sampled, as it follows from the foregoing description.
The filter of the present invention is a type of comb filter which eliminates signals h~ving frequencies coinciding with the notch frequencies defined by the 15 filter's response characteristi~, such as illustrated in Fig. 4. The filter can be constructed and operated to remove any one or more harmonically related signal components included in ~he digiti~ed composite signal coupled to its input, with the number of harmonically 20 related signal components removed depending upon the ~: frequency of digitized samples at the input of the : filter and the number of samples averaged by the fllter to generate the running average value output. The lowest order signal component removed by the filter of 25 the present invention is defined as Xaving a frequency fmin - sa_ ~ ID-2635 where fs~mpl i5 the sampling clock frequency defined in equation (l); and n is the number of samples taken ~or averaging as defined in equation (1). The diagram shown in Fig. 4 depicts the frequency components eliminated by the filter oE the present i:nVentiQn~ As it i~ seen, the fil~er of the invention has a first notch at a frequency fm~n defined by equation (7) and it has further notches a~ higher in~egral multiple frequencies of fmin. Conse~uently, the highest order signal component removed by the filter is one having fre~uency equal to an in~egral multiple of the lowest removed component fmin and which is contained within the frequency band of the ~ ered composite signal. However, in applica--tions where it ~s desirable to remove only a specific selected frequency component from a wideband composit~
signal, the sampling frequency f5ampl (or filter's clock signal frequency) is selected such that the frequency of any other component included in the compQsite signal does not coincide with the notch frequencies of ~ 20 ~le ~ilter.
: : In the embodiment o the ~il er circuit 2 illustrated in F~g~ 2, the sampling clock frequency and filter's clock frequency have been chosen as an integral multiple of the selected frequency component to be removed~ ~owever, the filter circuit 2 can be modified to process digital sample representation5 provided at a sampling frequency which is a rational fractional multiple of ~he selected frequency component to be eliminàted ~ 7~

from the composite signal; a sampliny frequency equal to 2.5 times the selected signal component frequency being selected as an illustration o~ this embodimentv With such a samp~ing frequency, two and one-half samples are obtained for each cycle of the selected periodic s~gnal component and five samples are obtained over two full siynal component cycles, as shown in Fiy~ 5. To obtaln an average sample value defining a zero value for the selected periodic signal compon~nt, a running average sample representation is generated of the values of n-5 consecutir~e samples.
To provide a running dig~tal average represen ta~ion of the values o~ five consecutive samples generat-ed at a ra~e of 2.5 times the selected frequency ~ompo-nent to be eliminated from the composite signal, thefilter circui~ 2 o~ Fig. ~ is modified ko include ~wo additional parallel signal transmission paths between the con~ecting lines I and the input of the diY~der 57O
The firs~ of the additional paths includes the connecting lines I, the adde 55 and the clocked regis~er 56 illus~ra~d by dotted lines in Fig. 2~ The second of the additional paths is ormed by an additional parallel path extension of the connecting lines I and another cascaded combination of an adder and clocked register (none of which are shown in FigO 2). The additional adder has one input coupled to receive the ~ummed samples from the register 56 and a second input coupled to receive consecutive samples from the parallel exten-~ 9 sion of the connecting lines I. The additional register is coupled between the output o the addit.ional adder and the input of the divider 57 and performs the above descri~ed reclocking function. With the two additional parallel signal transmission paths, the modified filter circuit 2 has five parallel signal transmission paths be~ween ~he connectin~ line I and the ~nput of the divider 5.7, respectively providing signal transmission times di~fering by 1 through 5 clock signal period~
whereby five consecutive samples can be arithmetically combined for averaging.
Besides adding the two additional parallel signal transmission paths to the filter circuit, t~e divider 57 is modified to divide the combined samples by a factor of five. Also, all clocked reyisters and diYiders are adapted to be clocked by a clock signal coupled by line 88 to their respective clock inputs haviny a frequency of 2.5 times the selected frequency componen~ to be eliminated from the component signal.
Summing five consecutive samples and dividin~
the ob~ained value by 5 provides an average representa-tion of the values of the five consecutive samples which defines a zero value of the selected periodic signal componen~ ~owever, ~n his modified embodimen~ of ~he filter circuit 2, a frequency component equal to one half of the frequency component of the composite signal also will be eliminated. For example, for a selected signal component of frequency fsi~ = 3.58 M~z, such as the ~3 6--standard chrominance subcarrier signal component included in the NTSC color television signal, and for the samplin~ frequency fs mpl equal to two and one-half times ~he subcarrier signal frequency, i.e~, 5 fs~mpl = 2.5 x 3.58 = 8.95 ~IHz. The lowest frequency component removed by the mocIified Eilter circui~, a.s 8.95 ~Hz given by equation ~7) is fmin = 5 - 1.79 MHz~
If it is undesirable to remove the 1~79 MHz component in addition to the 3.58 M~z chrominance component from the color television signal, a different sampliny fre~uency should be selected, such as the previously desc~;bed fs mpl = 3 f5ig~ Removal of the 1.79 ~q~z component of a color television s~gnal may undesirably degrade the signal~ In the previously described unmodified embodîmen~
1~ of the filter circuit 2 illus~ra~ed by Fig. ~ fmin equals 3~58 MHz, which is the lowest frequency component -removed by the filter. As it has been explained above~
and illustrated in Fig~ 4, lntegral multiples of the lowest frequency componen~ removed by ~he filter corres-20 ponding to higher order harmonics also will be remo~edby the filter.
The filter of the invention can b~ construc ed and operated to average either an even number or an odd number of input samples to generate at its output ~he 25 digital average representation for each recei~ed input sampleO ~owever, averaging an odd number o inpu~ samples facilitate~ the avoidance of the lntroduction of !

.

~ 74 ~ ID-2635 undesirable phase shifts to the digital average represen-~ation provided by the filter. Averaging an odd number of the input samples permits substituting in place of each input sample value a representation in the fo~m of a digital representation of the average of the value of the input sample plus the values of equ~l numbers of input samples occurring before and after the input sample. Averaginq an even number o~ input samples to genera~e the digital average represen~a~ion does not permit generating the representation from equal numbers of input samples occurring before and after the input sample to be substituted by the representation. As a result, some phase displacement occur~ when averaging an even number of input samplesO The phase displacement can 15 be limited to one-half of the interval between consecutive samples, ar sampl ng periodp ~f the digital average epresentation generated from a sequence of an even number of inpu~ samples is substi~uted ~or an ~nput sample ~ccurring nearest the middle of the se~uence. Since 20 such phase displacement is constant for all su~stituted sample values, no objectionable phase distortion results~
~owever, in some signal processing applica~ions, such a~
color television signal dropout compensators, such fractional pha~e displacements are undesirable because 25 they complicate the processing of the signal for use in alleviating dropouts that often occur in television signals reproduced from a magnetic recording.

, .

t;~

When utiliziny the filter of the above-descrihed invention as a low-pass filter, it is preferable to have a relatively low integral number of samples per cycle of the selected periodic signal to avoid high sampling 5 signal frequencies while maintaining the shortest possible signal period for averaging. A sampling rate of three tlmes the frequency of the selected periodic signal to be eliminated by the filter satlsfies these preferred conditionsO. Such sampling rate has the further advantage of facilitating the avoidance of the introduct.ion of the aforementione~ undesirable phaso shift~ because an odd number of input samples can be conveniently averàged to generate the digital average represen~ation for each input sample.
A ~ er constructed in accordan~e wi~h the embodiment ~llustrated in Fi~. 2 and operated to pro~ide a running average sample value representakion o~ a composita signal sampled at a frequency equal to an even number multiple o~ the signal component to be eliminated 20 by the filter will introduce ~he aforedescribed phase displacement. ~owever, the embodimen~ of the present invention shown ~n Fig. 6 avoids introducing a phase displacement in the running average sample value represen-tation of a composite signal sampled at such even number 25 multiple ~requency~ Generally, the filte~ embodiment of Fig. 6 avo~ds the introduction of a phase displacement by generatin~ an average sample value representation of each sample f rom selected ones of a sequence of inpu~

: -39-.

::~ :' ~ 4~ ID-2635 samples which are weighted for averaging. That filter embodiment and the manner in which it operate to generate the desired average sample value representation are described in detail hereinbelo~7 To obtain a zero average value o~ a selected periodic signal, a weighted aver~ge value signal may be provided, for example~ by assigning selected respective weighting coefficients to respective inputs of the various circuit elements utilized in the filter of the present invention. The foregoing may be implemented by coupling digital multipliers 70 to 75, indicated by dashed lines in Fig. 2, to the respective inputs of adders 51, 53, 55O For example, digital multipllers TDC
10085 manufac~ured by T.R~WJ Corporation may be utilized~
Alternatively, if the samples being summed are weighted by coefficients of powers of 2, i.e.~ 1/4, 1/2, 1, 2, 4, etc., to obtain the~averaged sample value representation, the weighting of the samples can be accomplished conven-iently by bit shifting the 8-bit digital word sample a the inputs of the adders the appropriate number of bit positions and in the appropriate direction corresponding to the weighting coefficientO Such bit shifting is effected in the well known manner of coupling the input bit lines to lower or higher order binary bit position ; ~ 25 inputs of the adders. For example, to multiply ~he sample by 4, each input bit line is coupled to a bit position input oX the adder which is two bit position orders higher than the bit position order of the input ' ~ r~4 ~ ID-2635 bit line. To multiply the sample by 1/4 (or divide by 4)~ each input bit line is coupled to a bit position input of the adder which is two bit position orders lower than tne bit position order of the input bit line.
The foregoing will be explained with reference to Figs. 6 and 7 respectively depicting the block diagram of an alternative embodlment of the dig~tal filter of the present invention and the operation thereof.
Fig~ 7 shows a sine wave of amplitude Z at frequency f 10 sampled at a frequency 4f. The sampling points on waveform Z are designated Zl~ Z2~ Z3r etc., and are 90 degrees apart~ An average sample value of the sine wave Z is obtained by generating a weighted average sample value of five consecutive samples in ac~ordance 15 with the following equation:

~n ~ 2 Zn + 4 (~n-2 + Zn~2) + (Zn-l ~ Zn+l~~ (8) For example, an average sample value M4 substi~uted for sample Z4 is: ' M4 = 2 Z~ ~ 4 (Z2 ~ Z6~ + (Z3 ~ Z5) = (9) To generate the weighted average value of ~he five consecutive samples in accordance with equation (8), digital weighti~g means are arranged in circuit with digital time delay and digital arithmetic devices to weight the five consecutive samples by weighting 25 coefficien~s as follows: Zn is weighted by Rl/2~;

both Zn 2 and Zn+2 are weighted by Wl/4~; and both - Zn 1 and ~n+l are weighted by "3~. As illustrated by Fig. 7 and the above equations 8 and 9, appropriately selected weighting of consecu~ive samples enahles a selected periodic signal component Z to be eliminated from a composite signal sampled at a frequency equal to an even number mult~ple o~ t:he ~requency of the ~selected 5 periodic signal without introducing a phase displacement to the resulting composite ~;ignal. Introduct~on of a phase displacement is avoide!d because each generated averaye sample value is subs~ituted for a sample that occurs in the middle of the se~uence of consecutive samples that are averaged.
~ block diagram in Fig. 6 shows an embodiment of the filter circuit 2' of the presen~ inven~ion as arranged to gener~te and substitut~ an average sample value for each ~nput sample in accordance wi~h equation ~8). To facilitate the description, the operatlon of the circuit of Fig. 6 is indica~ed in ~AB. 2 below, depic~ing ~he propaga~on of cons~cutlvely ~ecelv~d samp1e~.
Zl' Z2' Z3~ etc., a~ clock signal times 1, 2, 3, etc., wi~h respec~ to particular locations At B, C, e~c., in the block diagram of Fig. 6O

.

;i'4~ ID~2 6 3 5 TAB~ 2 ~. .. _ _ _ _... ___ ... .. . . .. . _ _.. ..... .. . . . .. .. .. . . . .. . _ Location Clock . A B C D E F G H

~ ~ r ~-. .. __ z~ .~ . . _~ , 3 Z3 Z2 ZlZ3~ 1 -~ ,~ _ Z:2 Zl- ~
~ 4 z4 z3 Z;2Z4+ 2 Z3~2 .
.~ _ Z Z Z Z--' Z-' .
~ ~ 5 ZS z4 ~3 Z5+~ z4~22 Z3~2l. ~Z3+2l . _ ~ .. ___ _~

6 Z6 25 z4 Z.6~ 4 Z5+~3 Z f~ ~Z~+22 2L (~Z3+2li ~: 7 Z~ Z6 Z~ Z7+~ Z6+24 Z5+23 27+Zs+23 l(~$z4+~) 8 Z8 Z7 Z6 Z8+26 Z7+~ Z6+~ ~Z6+24 ~ _ :~

: : ' ' :

~ - . . :. . ....... . ".. . . .. . . . .... .

`:` ::
:: : :
:

: ,

7~6~

The filter circuit 2' illustrated .in FigO 6 comprises a combination of commercially available binary addersr registers and dividers of the kind described hereinabove as being employed in the filter circuit embodimen of FigO 2. Each 8~bit digital word sample generated by the A/D converter 82 of Fig. 1 is coupled b~
the connecting lines 84 to the input of the tlming bufer regi~ter 49~ Upon the occurrence of each clook signal of the 10~7 M~z sampling signal a~ the clock input 88 of the re~ister 490 an 8-bit digital word sample is transmitted from the input o~ the reg~ster 49 ~o its output coupled to the eigh~ parallel connecting lines A. The connecting lines A branch into three differen~ signal transmission paths to the output 91 of the filter circuit ~'. The transmission paths ~nclude signal delay elements or means that provide different.
transmission ~mes for each sample through the diferen signal ~ransmission paths. In the embodimen~ of the filter circuit 2g illustrated by Fig. 6, the transmission times differ by even multiples of the period of the 14.32 M~z sampling signal, with the ~ransmission time ~hrough the longest signal transmission path bèing four samplin~ ignal periods longer than ~he transmission time through the shor est s gnal transmission path and 25 the t.ransmission time through the signal transmlssion path of intermediate length bein~ two sampling signal periods longer than the transmission time through the sho~test signal transmission path. As will become more -~ ID-2635 apparent upon considera~ion of the more detailed descrip~
tion of the filter circuit 2' hereinbelow, the even mul~iple sampling signal period relationship of the transmission times of the three transmission paths creates the "~' weighting coefficients specified in equation (8) because only e~ery other sample o~ ~ach sequence of .ive consecu~ive samples are combined to form the weighted ave~age sample value represantation at the output 91 o~ the fil~er circuit 2'.
The shortest signal kransmisslon path between connecting lines A and the output 91 of the ~ilter circuit 2~ includes a binary adder 65-coupled at its first input to the lines A extendin~ from the buffer register 49 and followed by a binary divider 66. The lS divider is responsive to the 10.7 ~z samplîng signal coupled by, llnes 88 to its clock inpu~ to divide ~he binary slgnal at its input by a fac~or o two. As described hereinhefore with reference to the embodiment of the filter circui~ illustrated ln Fig~ 2, such dividers introduce a propagation delay of one sampling signal cycle in the signal trans~isslon pathO Conse-quentlyt the shortest signal ~ran~mission path has an overall signal transmiss~on delay of one sampl~ng signal . cycle, with the delay loca~ed ~n the ransmission pa~h so that a sample appearing on th~ connecting lines A
coupled to OUtpll~ of the register 49 appears at the first input o~ the adde~ 65 without delay and a sample sum appearing on connecting lines G coupling the output , .

, ~: :

~';iJ ~ ~33 ID - 2 6 3 s of the adder 65 to the input of the divider 66 is dela~ed one sampling signal time before it appears on the connec~ing lines H extending to the output 91 of the filter circuit 2'. The shortest s.ignal transmis,sion path yenerates the weighted averaye value 1/4 Zn~2 specified .in equation (8). The divider 66 provides a weighting coefficient of 1/2. The ~emaining 1/2 of the weighting o~ the average value is accomplished at the firs~ .~nput of the adder 65 b~ coupling each o~ ~he input bi~ lines A to a bit position input o~ the adder which is one bi~ position order lower than the bi~ posi~ion order o~ ~he input bit line.
~ Adde~ 65 and divider 66 are common ~o the ; ~hree signal kransmission pa~hsO Therefore, the ~ore-1~ mentioned differences in the transm~ssion times through ~he three paths mus~ be eskablished before th~ adder 6 Th~ pos.ition of the sign~l transmlssion p~th : ~ of intermediate length between connect~ng lines A and a second inpu~ of the adder 65 includes another binary adder 62 followed by two cascaded binary registers 63 and 64. As described hereinbefore with reference to the embodiment o:E the filter circuit illustrated in ~ig., 2, each of the registers transmits data from its inpu~
to its output ~n response to the sampling signal coupled to its clock input by line 88 and i.ntroduces a propagation delay o~ one sampling signal cycle in the signal trans-mission~path. Consequently, the signal transmission path of intermediate length provides a slgnal transmission delay between lines A and the connecting lines F co~pled ~I~L~7~9 to a second inpu~ of the adder 65 of two sampling signalcycles, which is two cycles longer than the delay through the corresponding shortest signal transmission path. ~herefore, a sample appearing on 1.ines A coupled 5 to the firs~ input of adder 6~ essentially will appear simultaneously on connecting lines D coupling the outpu~
of the adder to ~he input of the register 63. Upon the occurrence o~ the ~ext sampling signal, ~he sample will be transmitted by the regis~er 63 to the connecting lines 10 E coupling the output of the register 63 to the input o~ the following register 64. Upon the occurrence o~ the second following sampling signal, the sample wlll be ~ransmitted by the regis~er 6~ to ~he connecting lines F
coupling the ou~pu~ of the register 64 to the second 15 input of the adder 65. Thus, at the same time that register ~9 provides a sample a~ ~he f~rs~ input of the ~dder 65, a sample that was generated two sample perlods earlier by ~he A/D conver~er 82 of Fig~ 1 and transmi~ted through the trarlsmission path of intermediate length is 20 provided a~ the second input of the adder 65 by the : regis~er 64r The signal transmission path of in~ermediate ' length ~s completed through adder 65 and divider 66 to ;: generate the weighted average value 1j2 Zn specified in equation (8).
~5 . The longest signal transmission pa~h ~s formed in par~ by the signal transm7ssion path of intermediate length, i.e., the path from adder 62 to div;der 66 and in part by registers 60 and 61 preceding the adder 62 ~ 7~ ID-2635 Each of the registers 60 and 61 introduces a p~opagation delay of one sampling signal cycle in the signal trans-mission path ~hereby the signal transmission delay between lines A and the connectin~ lines C coupled to a second input of the adder 62 is two sampling signal cyclesO The value of each samp.le received a~ the second input of the adder 62 is wei~hted by a factor of l/2 by coupling each of the ~npu~ lines C ~o ~ bit position inpu~ o~ the adder which is one bit position order lower than the bit position order of ~he input bit line. A~
~he same time that ~he register 61 provides a sa~ple at the second input of the adder 62, a sample that is ~enerated two sample periods later by the A/D conver~er 82 of Figd 1 ls provided at the other ~irst input of the adder 6~ by the register 49. There~ore, ~he longes~
signal tran~mission path provides a signal transmission delay between lines A and the oukput 91 of the fil~er ~; circuit 2 ' ~ha~ is four sampling signal cycle longer than that provided by the shor~es~ signal 'cransmisson path and generates the weighted average value l/4 Zn specified in equatloR (8~.
; The operation o~ the filter circui~ embodiment of Fig. 6 wi~l be described now wlth reference to T~B. 2 tha~ dep1cts the propagation and p~ocessing of collsecutive samples through the filter circuit 2'. Consecutive samples Zl~ Z2~ æ~ etc., are received in succession at the input of the re~ister 49 from the A/D conver~er 82 via connecting lines 84 at a rate of four times the ~6~ 74~ ID-2635 frequency of the selected component to be eliminated from the composite signal sampled by the A/D converter.
At each clock ~ime, the register and divider devices included in the fIlter circuit 2' are clocked by the sampllng signal applied to their respective clock inputs by line 88 to initiate p~ocessing of the digi~al signals present at their respec~ive data inputs. For example, at the first clock ~ime 1, regis~er 49 is clocked to trans~er sample Zl present on l~nes 84 to i~s outpu~, which is coupled to lines A that extend to the inputs o~
reglster 60, adder 62 and adder 65. Immedia~ely upon khe occurrence of ~he sample Zl on lines A extending to the firs~ input of the adder 6~, the adder responds by transferring to its ou~put the sum o~ the samples received at its two inputs. This sample sum, which includes sample 81, is coupled by lines D to the input of the register 63. In addi~ion, the adder 65 responds by ~ transferring to its output the sum of the samples : received a~ its ~wo inpu~s, which includes the sample 21 present on lines A as weighted by a factor of 1/2 a~ ~he ~ir~t inpu~ of the adder 65. This sample sum i5 :~ coupled by lines G to the input of th~ divider 66~
Upon the occurrence of the next clock ~ime 2, :~ sample Z~ is placed on lines A and D and the weighted ; 25 sample I~2 Z2 is placed on lines G at the output of the adder 65 in the manner desc~bed hereinabove wi~h respect to samp:Le Zl at the clock ~ime 1. In addi~ion, : registers 60, 61, 63 and 64 and di~ider 66 are clocked ;~ -49-.

.~
'~ ' ~ 7~ ~ ID-2635 to process and transfer to their respective outputs the sample values present at their respective inputs. As a result, samp~e Zl is placed on lines B extending from the output of register 60 to th~ input of register 61, S and on lines ~ extending from the output of reyister 63 to t~e input of register 64~ Also, divider 66 weights the value of.the sample sum then presen~ on lines G by 1/2 and places the weighted sample sum on lines H extending to the output lines ~1. Thi~ weighted sample sum includes ~.he weighte~ sample 1/4 Zl~
Durlng ~he next clock time 3, sample Z3 is placed on llnes A and D, sample Z2 is placed on llnes B and E and the weigh~ed sample 1/2-Z3 i5 placed on lines ~ in the manner described hereinabove with respect to samples Zl and Z2 at clock times l and 2~ In addition register 64 and di~ider 66 are c~ocked to process and transfer to their respec~ive outpu~s the sample values then presen~ a~ their respec~ive inpu~s.
Thi~ places sample Zl on lines F coupling the ou~put of register 64 to the second input o~ the ad~er 65.
:~ Conse~uently, th adder 65 places a sample sum on lines . G that includes sample 2l plus the weighted sample l/2 Z3. Register 61 places the sample Zl on lines C
extending to the second input of the adder 62, at which 25~ point it is wei.ghted by a fac~or of 1~2 and placed on the lines D. Eience, before clock time 4, the combined sample value 1/2 Zl ~ Z3 is transferred to the outpu~ of the adder 62 and is placed on lines D ex~end-~50-' 7~

ing to the input of register 63. Divider 66 weights the sample sum presen~ on lines G by a factor of 1/2 and places ~he weighted sample ~um on lines H extending to the output 91 o~ ~he fil~er circui~ 2'. This weighted S sample sum includes the weighted sample 1/4 Z2~
During the nex~ three cloc:k ~imes 4, 5 and 6, samples Z4 I Z5 and Z6 ~re successively plac~d on lines A by the timing ~u~er register 49 and are proc~ss-ed in the manner described hereinabove with r~spec~ to 9amples Zl~ Z2~ and Z3 a~ previous clock times 1, 2, and 3. A more d ta1led unders~anding of ~he proces~
; ing and propaga~ion o~ samples 24, 2~ and Z6 .through the filter circui~ 2' in response ~o sampliny signals at cloc~ ~imes 4, 5 and 6 can be had by reference ~ 15 to TAB. 2, above. Clocking the register and divider : devices of ~he filter circuit 2' during th~ clock t~es 4 and S cau~es reg~sters 63 and 64 to t~an~fer the com~ined sample valu~ 1~2 Zl + Z3 from ~he input of the regisker 63 to lines F extend1ng rom: ~he output of the 20 register 64 to the second input of the adder ~5 and causes the register 49 ~o place the ~ample value Z5 on ~; ~ lines A extending to the firs~. weigh~ing input o the adder 65~ ~ence, at ~he end of the clock ~ime 5, adder 65 proYides a combined sample valu~ l/2 Zl ~ Z2 ~
25 l/2 Z5 on its ou~put coupled to lines G extending to the input of divider 6~.
Upon the occurrence of ~he clock time 6, ~he combined sample value 1~2 Zl + Z3 + 1/2 Z5 pzesent -51~

- .

7~9 at the input of the divider 66 is weighted by a factor of 1/2 and transferred to its output coupled to lines extending to the filter circuit's output 91. The weighted output of the filter circuit, i.e., 1/4 Z
1/2 Z3 ~ 1/4 Z5 and following weighted sample value representations is in accordancle with equation ~8) and has the selected component whose ~requency corresponds to one-fourth the frequency of the clocking signal elimina1-ed because the weighted sample value representat~on of the sel~ected component is zero, as can be seen upon consider~
aton of equation (8~ and Fig. 7~
It will be understood ~rom the foregoing description that other combinations and arrangements of registers and arithme~ic devices could be provided in a similar manner to obtain for a given number of averaged samples a zero weigh~ed average sample value of a selected periodic sign21~
To simplify thé description, the frequ~ncy and phase of the sampling signal is selected so tha~ ~he ~ sampled points Zl to Z7 shown in Pig. 7 coincide - with zero and maximum values of sine wave Z. It will become apparent wi~h re~pect to ~he ~oregong description that the embodiment of Fig~ 6 also will provide a desired zero average value o~ sine wave Z i~ there is a constant 25 phase difference be~ween the sampling signal and ~he sine wave or selected signal component to be filtered~
The filter circuit embodiment of the present invention illustrated in Fig~ 6 is particularly ad-vanta- :
.

~ 749 ID-263s geous for f~lter ci~cuits utilized in applications where the sampling signal frequency is an even number multiple of the ~requency of ~he periodic signal component to ~e eliminated from a composite signalO The embodiment o~
5 Fig. 6 provides a desired zero weighted average value o~
the period signal componen~ from a given odd number of samples. Consequen ly, ~he aforementioned potentially - undesirable phase shift of one-half of the sampling signal period which would result from averaging an even 10 number of samples ts avoided by the circuit o~ Fig. 6~
W~th reference to ~he foregolng description, it is to be unders~ood tha~ the filter of ~he presen~
invention is not limited to the above-described embodi-mPnts illus~rated ~y Figs. 2 and 6t ~t will become 15 apparent to those skilled in the art that the filter may comprise various arrangemen~s of digital signal process~
ing means that cooperate ~o provide a zero average value or a weigh~ed 2ero average value o the signal component to be eliminated from a composite signal in accordance : 20 with ~he described method of the invention~ For example, the filter circuit m~y utilize circuit elements for dividing or partlally dividing the samples followed by circuit elements for adding the divided samples instead of bit shif~ing the samples at the 1nputs of the adders 5:as described above with reference to the embod~ment of FigO 6. Furthermore, the filter o the invention can be arranged ~o operate with various rela~ionships of sampling signal frequency and frequency of signal component to be eliminated or flltered from a composite signal. As described hereinbefore, the sampling signal fr,equency can be an odd or even integral multiple of the selected periodic component frequency to be eliminated.
S Also, the sampling frequency can be a non-integral rational multiple of the selected periodic signal frequency. With respect to ~he embodiment illustrat~d by Fig. 6, an average o~ three weighted samples is obtained by weighting the first and last sample of five consecutive 1~ samples by one~half and not weighting the third of the five consecu~ive samples and dividing the sum of the three samples by a factor of two, i.e~, ~eighting the sum by a factor o~ 1/2. ~owever, if the three samples are weighted ~y lower ~actor, such as one-eighth for the first and last sample of the five consecutive samples and one~fourth for the third sample, the weighted sum would havle to be multipl;ed by a factor of two, i~e., weighted by a factor of 2, to obtain the deslred average sample representa~ion.
The filt~r of the present invention provide~
special advan~ages as a luminance-chrominance separator in color television signal processors, such aSr for ~ example, aropout compensators. Fig~ 8 illustrates one ; ~ embodiment of the dropout compensator of the present invention in which a digital color television signal is received at an input terminal 10 coupled to a firs~
input 11 of a two-way switch 1. A control signal indicating preslence o~ a dropout is received by a control terminal 12, for example, from a conventional ~ 7~ ID-2635 dropout detector (not shown), such as included in commercially available video tape recorders. A suitable dropou~ detector may be of a conventional carrier monitor type which pro~ides a control signal when the X. F.
S envelope of the modula~ed television signal drops below a predetermined level 7 such as used, for exampl~, in the Amepx Corporation manufactured VPR-l Video Production Recorder, and shown in the manual for that recorder, Catalog No. 1809~76-02, publishe~d by Ampex ~0 Corporation in December; 1977, schematic drawing 137863.3C~
payes 8-~1/42 and 8-43~44. The control terminal 12 i~

: ' . i .

, ~ , ;

; ~
, .

: -54a-.

~ 3 ID-263S

coupled to a control input 13 o~ switch lo Ou~put 14 of s~i~ch 1 is coupled to an outpu~ terminal 15 of the dropout compensator. The output: 14 of s~itch 1 is also coupled to an input 18 of a dig~al filter 2 cor~espond-ing to the filter 4f the present invention, such as ~heabove-described embodiments illus~rated by Fi~. 2 or Fig.
6, respectively. The output 14 of switch 1 is further coupled to first input 1~ of a cligltal dif~erencing circuit 3 v~a a digi~al delay circuit 7. A second input 17 of ~he differenciny circuit 3 is coupled to an output 19 of ~he digital fil~er 2. An output 20 of the d~f~er;
encing circuit 3 i~ coupled to a first input 21 of a digital add~ng circuit 5 via a fixed digital delay line The second inpu~ 2~ o adding c~rcuit 5 is coupled 15 to ~he outpu~ lg of ~he digital filter 2~ A~ ou~put 23 of the adding circui~ S is coupled to a second inpu~ 24 of switch 1 v~a ano~her fixe~ digi~al delay line 6D The ; delay circuit 7, coupled between the output 14 o switch 1 and inpu~ 16 of differencing ircuit 3 is utilized to 20 compensate for circuit delays in filter 2, as 1~ will ---follow from the further description~ The dropout compensator is controlled to process the digital ~ele-vision signal by a clock ~ignal provided at inpu~
terminal ~6. The provided cloc~ signal is ~he signal 25 related clock signal previously described as being generated for use by the fiJ.ter clrcuit of the presen~
invention and is determined by the particular filter embodiment used in the dropout compensator~ If the _5~j_ .
.

ID--~! 635 t7~ ~3 filte~ circuit illustrated in Fig. 2 ~s used in the dropout compensatorl the clock signal ~.s obtained from the signal clock generator 83 of Fig. lo Now the operation of one preferred embodiment of the dropout compensator of t.he present inYention will be described with reference to ~Fig. 8. A digital MT5C
color television signal in the form of discrete B~bit digital data word~ representing samples o~ the ~elevision signal, such as provided by the A/D conver ter 82 of Fig.
- 10 1, is received at input terminal 10 and ~ed ~o firs~
- input 11 of switch 1~ When the television signal system is in normal ope~at~on, that is, no dropouts in the incoming signal are detected by the dropout detector, switch 1 is ~n i~s first position re~ei~Ting the input 15 siqnal at input lI and applying it to ou pu~ 14 . When a dropout is detected ~n the color television ~ignal, for exa~ple, by the aforemen~.ion~?d conven~ional dropou~
detec~o~ ~he con~rol ~ignal received a~ ~erminal 12 is applied to control input 13 of the two-way switc~ 1., 20 The control signal received by ~he two-way switch 1 causes it to disconnect the first input 11 froM the ou~put 14 and to ~onnect i s second inpu~ 24 to the output. Consequently; the signa~ representing a delayed portion o~ the digital color television signal receiYed ~5 at second input 24 is now applled to output terminal 15.
. That delayed signal represents a dropout compensation signal u~ilized to replace the dropout poxtion o~ the television: information signa:l, thus preventing any ~ 7~3 disturbances in the displayed television picture which would be caused ~y the presence of a dropout. The above-indicated dropout compensation may be provided for one or more television line periods or any f~action thereofO
The portion 25 oE the dropou~ compensator circuit circumscribed by dashed lines, which provides the desired signal delay for dropou~ compensa~ion, w~ll be described now in accordance wl~h the preferred embodiment of the invention shown in ~ig. 80 Filter 2, whlch is designedy Eor example, as shown in Fig. 2, receives the digital composite color television s.ignal from ou~put 14 of switch 1 in the form of consecutive samples at a selected clock signal frequency, for example, equal to three times the nominal ~requency o~
the NT5C chrominance subcarrier componen~, ~hat i5, fsampl ~3 x 3.58 MHz ~ 10074 M~z. The sampling sl.~n~.l is phase locked to ~he chrominan~e subcarrier signalf as it is well known in the ar~, for example by phase-locking ~0 to the color burst component, as descr~bed in the p~eviously mentioned AVR-2 Video Tape Recorder Ca~alog, pages 9-2~ to 9-39. It ollows from the foregoing description of the operat~on of the filter with respect to Fig. 1 that t~ree samples define a time interval equal to one cycle of the chrominance subcarrier component.
It also follows from the foregoi~g descr~ption that the lowest frequency component which is removed by filter 2 from the composite signal is 3.58 M~z. Th~ nex~ n.igher .

~ 2635 frequency component also removed by the filter is 2 x3.58 MHz - 7.16 MHz~ This la~ter frequenc~, however, is outside the frequency band of an NTSC signal whose total bandwidth is 4. 2 M~z~ Generally, in other conventional color television signal systems, such as PAL, PAL-M, etc ~, the total bandwid~h is also below twice the color subcarrier signal frequency and, consequently, no signal degradation resultsO
As described hereinbefore with reference to Fig. 2, filter 2 prov~des an average of ~he amplî~ude ~alues of three con~ecu~ive samples received at i~s input 18~ ~, follows from equation (2) that each such average value o~ the chrominance subcarrier signal componen~ is equal ~o zero~ Consequen~ly, ~he 15 signal ak the output 19 of filter 2 represents the composite color ~elevision signal from which the chromi-nance subcarrier component haYing a nominal frequency of 3~58 M~z is eliminated. Thus, th~ resulting signal at he output 19 of filter 2 is a ~hrominance-less color 20 television signal, which will be considered further as representing the lum~nance component~ It follows rom :~ the foregoing descrip ion, tha~ the resulting signal at the output 19 of the filter 2 is represented by average sample values obtained by successively averaging th~ee 25 consecutive samples~ Each obtained average sample value is substi~uted for the sample in the middle of each three consecutive samples taken for averagingO It is noted that the obtained averaged samples do not exhibit -sa-~ 7f.l9 ID-2635 a phase-shift wi~h respect to the originally received samples, since an odd number of consecutive samples is being averayed.
With further reference to Fig. 8, the signal from output 19 of dig~tal filter 2 representlng the separated luminance component i~; applied to the second input 17 of differencing circuit 3O The color television signal V from ou~put 14 of switch 1 is applied via delay circui~ 7 to the ~irst input 16 of circuit 3~ Differenc-ing circuit 3 provides a~ its output 20 a differencesignal of the two signals received at its first and : second inputs. The resulting difference si~nal repre~ents the separate~ chrominance component of the color tele~
vision signal. It is seen ~rom the foregoirlg description that by utili~ing the digi~al fil~er 2 o~ the presen~
inven~ion in combination with the diferencing circuit 3, as above disclosed, separation of the luminance and : chrominance components o~ the color television signal is : provided. The separa~ed chrominance componen~ at outpu~
20 is delayed in the first delay line 4 by a time ; subs~antially corresponding ~o one horizontal line period of the television signal. The separated and : delayed chrom~na~ce component and separated luminance .~ , component are respect~vely fed to inputs 21 and 22 of ` 25 adding circuit S. These l~cwo signa1 components are recombined in c t rcuit 5 to form a composite color television signal at output 23 thereofO The latter signal is fed from output 23 of circuit 5 to input 24 of :

,~ .
.
~: ~ . . . .. .
: ;

~ 74 ~ ID-2635 switch 1 th.rough a second deiay line 6, and it is delayed thereby by a ~ime substantially corresponding to one horizontal line period o the television signal.
The delayed signal represents the dropout compensat~on S signal by which one or more consecu~ive lines~ or fractions of lines, o~ missing television informatlon may be replaced by the dropout compensator when a control signal at term~nal 12 is applied, as it has been described previously~ If i~ is necessary ~o replace more than one ~elevision line by the dropout compensator, the ou~put signal from circuit 25~ representing the : dropout compensation signal, will circulate from output .
14 of switch 1 ko its second input ~4 via circuit 25 and out through output terminal 15 until the control signal at 12 is removed.
It is to be realized that the above-d~scribed preferred embodimen~ of F~g. 8 represen~s a di~i~al dropout compensator in accordance with the presen~
inv~ntion in which high speed digital data is processed.
Consequently~ the var~ous elements shown in the simpli-fied block diagram of Figr ~ may be designed as eonven~
tional digltal circuit~ in which the high speed da~a is precisely clocked at three times the color subcarrier :~ signal frequency, that is, at app~oximately 10.74 M~z, 25 while the clock signal is frequency and phase-locked to the chrominance subcarrier component of the sampled : color teievisiorl signal 9 as descri~ed before. For : simplicity o~ representation, the clo~k signal path is ' '~ . ' ' ' - ' ' . '.

~ 7~ ~

not shown in the block diagram, however, it i5 sho~n in a detailed circuit diagram o~ Figs. 13a to 13h correspond-ing to the block diagram of Fig., 8, which circuit will be described later.
Delay circuit 7, shown in Fig. 8 as coupled between input 18 of digital filter ~. and input 16 o diffeEencing circuit 3 ln the composite color television signal path, serves to provide additional fixed delay to compensate ~or the propagation delay of the .signal ~hrough the digital fil~er circuit 2G For proper operation o the digi~al dropout compensator, i i5 important to separate and combine corresponding data by the subtraction circuit 3 and addition circuit 5, respec~ively, in a precisely sy~cbronized manner to ~ 15 prevent undesirable phase shifts between the separated :; chrominance and luminance component~ Such phase shift~
would introduce unacceptable time base error~ and distort the resulting television picture. Therefore, t is necessa~y to determine ~he exac~ amount o~ fixed delay provlded by ~he respective delay l~nes 4, 6 and 7 in such a way that the total delay of the chrominance si~naI component from outpu~ 14 of ~witch 1 ~o ~ts input 24, that is, when passing through circuit branch 25, is : exac~ly e~ual to ~wo horizontal line periods 9~ the color televislon signal received at terminal 12, whereas the total delay of the l~inance signal component . efXected by its passage thraugh the circuit branch 25 i5 exactly equal to one hori ontal line period~ For ; ~ ~61-:~ .
.

"
.

~ ID-263$

determinlng the exact amoun~ of delay to be provided by each of the fixed delay lines 4, 6 and 7, respectively, the to~al amount o~ delay provicled by the respective circuit elements ln the luminanc:e and chrominance signal S paths should be considered. The actual amount of delay provided by delay lines 4, 6 and 7 should be adjusted accordingly. Consequently, in t:he preferred embodiment o Fig. 8, the delay provided by d~lay line 4 is equal to one horizontal line period less khe delay provided by dif~erencing circui~ 3. Similarly~ the ac~ual amount of delay provided by de].ay line 6 is equal to one horizontal line period less the combined delays provided by filter .
2 and adding circuit 5, respectively.
With respect to the well known relationship ; 15 of the color subcarrier component freque~cy and horizontal line freque.~cy of NTSC signals fSC-227~5~, in this pa~ticular embodimen~ o~ the invent~on a non-integral number of samples equal to 3 x 227.5=682,5 clock cycles ~: is obtained within one horizontal line period. To ~; 20 compensate for the non-integral relationship, delay line 6 may be designed to provide an alternative delay of, for example, 682 and 683 clock cycles on alternative ; consacutive lines, corresponding to the closes~ highar and lower integral numbar of clock cycles~ Thus, the 25~ a~erage delay provided by delay line 6 over any ~wo ; consecutive lines will be 682.5 clock cycles. To compensate for the a~ove deviation of one clock cycle on consecutive lines~ delay line 4 may be designed to -.
.

' ~ 4~ ID-2635 provide complementary delays in the chrominance si~nal path of, for example, 683 and 682 clock cycles, respec-tively, on alternative consecutive lines~ Thus, a desired two line delay of exactly 2 x 682O5 cycles 5 i5 provided ~y combined delay lines 4 and 6 in ~he chrominanc~ signal path~ However, it is noted with respect to the previous dl~closure that, the actual delays provided by delay lines 6 and 4 will be reduced by the above mentioned respective circuit delays in the lum~nance and chrominance signal path~.
It will become ~vident that if an integral ; number of clock signal~ is provided wi~hin one horizontal line period, such as by selecting a sampling frequency . equal to an even number multiple of ~he color subcarrier 15 frequency, for example four times the color subcar~ier frequency, ~he delay provided by delay line 4 does not have ~o be changed on al~ernate lines.
Wi~h respec~ to the above-described operation : of the d~gi~al dropout compensator of Fig. 8~ providlng : 20 a one-line delay of ~he 3uminance component and a two-line delay of ~he c~rominance ~omponen~ offers several advan~ages- First of all~ the one-line delay of the wideband luminance component is an improvement over known digital dropout compensators~ which provide a . 25 two-line delay of the~ luminance component. Secondly, the circuit of the present invention is an ~mpro~ement over the prior art analog dropout compensators which provide one-line delay o~ both the luminance and chromi-: ~ -63-.: , ' ,: ' ,, ' :

~ 7~3 ID-2635 nance componen~ and require line to-lin~ inversion of the chro~inance component to obtain a proper phase relationship thereo~. As it has been pointed out above, these latter dropout compensators are not directly S applicable for digital P~L or P,~L-M sys~ems~ Similarly, they are not directly applicable for digltal NTSC
systems utilizing a sampling signal frequency equal ~o an odd integral multiple or ra~ional number multlple of the ~TSC subcarrier frequency~ In case ~he above 10 indicaked typ~ of analog dropout compensator would be adapted for di~ital color television sys~ems utiliz~ng known comb filter ~ircuits, i~ would be necessary to provide ver~ical alignment of samples. An advantage of the digital dropout compensator of the invent~on is that it does not require ve~t~cal alignment of samples ~hus elimina~ing the need or line-to-line adjus~ment of ' ~ samplesO
It ls to be noted that in the digital dropout ; compensator of the presen~ invention the separat~d chrominance component notched out by the filter has a ::
bandwidth res~rlcted ~o a single nominal freq-lencyr such as 3.S8 ~q~z for NTSC, or 4043 MEIz fo~ PP~I,. This r~st~ict-ed bandwidth is very narrow in comparlson to the lumi-~: nance componen~. bandwidth, which is, for example, D. C. to 25 4.2 M~z in NTSC systems. Consequen~ly~ the two linedelayed chrominance component combined with ~he one line delayed luminance component does not represent objection-able distortion of the displayed television signal.

: -6~-~ ID-2635 When comparing the above-described dropout compensator of ~he invention to prior art analog compensators utilizing, for example, band pa.ss ~ilters for separation of the chrominance and luminance components, a dropout compensation signal comprising a luminance component delayed one line an~ a chrominance componant delayed ~wo lines would in~oduce a visible luminance to chrominance interference in the television picture. This is largely due to a relatively wide nominal bandw~dth o~ the separated analog chrominance component resul~ing from the well known frequency characteristics of analog filters. Furthermore~ when recombining the separately processed componen~s in~o a composite signal b~ the dropout compensator of the present invent~on, the full original frequency bandwidth of the television signal is restored, ~hus p~actically no frequency losses occur.
As opposed there~o, losses in the composi~e signal bandwidth are e~fected when analog filters are utilized ~or signal processing~
There is a further advantage o~ the dropout - compensator o~ the present invention when comparing to known analog compensa~ors. In the dropout compensator of the present invention, no relative delay be~ween the luminance and chrominan e component oth~r than the desired one hor:~zontal line delay occurs in the composite signal processecl by the compensator, since these signal components are maintained synchronous throughout the processing by precisely clocking the digital s~gnals, ~ 7~ ID-2635 and the respective delays prov ded by various circuit elemen~s are known and compensated for by fixed delay lines.
Since the flltering process of the pr~sent invention is restricted to averaging a few cons~cutive samples within the same television lis-~e, any unwanted short time disturbances, such as noise spikes introduced into the television signal, are limited in ~ime to the occurrence of the particular samples and to ~he rela~ive-ly short ~ime in which they are averagedO As opposed~hereto~ known diyi~al comb fil~ers providing sample values taken from samples of different ~elev7 sion lines or, analog filters whose time response effects visible transients in form of s~reaks in the displayed television signal caused by noise splkes, prov~de a more extensive signal distortion. ' Stlll, there is a further advan age of ~he digi~al dropou~ compensatio~ circui~ o the present ` invention in tha~ all slgnal process~ng is provided in real time utilizing standard TTL ( transistor-to-transistor logic) circui~ry, as 1~ will be seen from a detailed cir'cuit diagram o~ a preferred embodiment of the present invention shown in Figs~ 13a to 13h, ~he description of which follows. The circui~ of the above-indicated ~5 ~igures is suitable for dropout compensation i~ a color television signaI recording and reproducing system where ~ -an NTSC, PAL, PAL-M, etc~ r color television signal is encoded in digital form by sampling at a frequency . .

~ 749 ~D 2635 equal to three times the color subcarrier frequency of the television signalO First~ an embodiment suitable for use in NTSC systems will be described/ in which the sampling signal frequency fsampl ~ 3 x 3.58 M~z - 10.74 M~z~
The sampling signal is phase locked to the color burs~
component o~ the subcarrier signal as well known ~n ~he artO The sampling frequency i5 equal to ~he clock frequency as previously mentioned with respec~ to the description of Fig~ 8; consequently, in ~he further description we will refer interchangeably ~o the sampllng frequency and clock frequency.
Generally, for operation of th~ dropout compensator of the invention, the sampling frequency utilized to encode ~e composite analog signal, for 15 example~ ~he bolor tel~vision signal, does not have to be the same as the clock signal ~requency utilized to synchronize ~he Yarious elements of the dropou~ compen~a-tion circuit. In ~he lat~er case ~he samples may be received and stored ln a buffer circuit, for example, at 20 the sampling frequency, and subsequently recov~red at a :~ different: clock equency, while the làtter frequency is utilized for synchroniza~lon of ~h circuitO
` ~Alternative dropout compensa~or embo~iments are shown in Fiqs~ 9 ~o 11 and will be described brieflyO
; 25 To facilitate comparison wi~h the previously described embodiment of F:ig . 8, similar circuit elemen~s in the following alternative embodiments are designated by like reference numerals. The circuit of Fig. 9 i5 ., ' .
. , ~ '7~

similar to tha~ of Fig. 8 with the exception that the input of the circuit branch 25, that isr input 18 o~
filter 2 and input 27 of delay circuit 7, respectively, are coupled to input 11 of switch 1, instead of to its 5 output 14, as it is in Fig. 8. This par~icular circuit arrangement is useful when only one line of the television ; information is to be replaced by a dropout compensation signal since no means is provided for recirculating ~he delayed informa~ion from the output of the swltch back 10 to its input as in the circuit o~ Fig. 8. If it is necessary to compensate for rnore than one televislon line, additional memory means, such as a known circulat-ing memoryt could be utilized at the ~utput of switch 1.
~igs. 10 and 11 depict fu~ther alternative lS embodimen~s of ~he dropout compensator of ~he presen~
invention~ These latte~ embodiments dif~er from the pre~iously described embodi.ments of F~ gs . ~ and 9 hy ~he implementation of the circuit branch 25, as followsO In the embodimen~ of Fig. 10, ~he delay line 6 of the 20 embodiment of Fig. 8 is replaced by delay line 30 : coupled in the composite television signal path between the output 14 of switch 1 and input 18 of filter 2.
Delay line 30 provides delay for both the chrominance and ~, luminance component of a period of one horizontal line 25 less the combined delays in filter 2 and adder 5. It is : seen that the resulting respective delays of the chromi-: nance and luminance component are the same as in the :~
:

~ 7~ ID-2635 ~ !

previously descri~ed circuit of ~igc 80 In the clrcuit branch 25 of the embodiment o~
Fi~. 11, the delay line 6 in thle co~re~pondin~ circuit branch 2S of the embodiment of Fi~ 8 .is replaced by S a delay line 31 coupled .in the separated luminance signal pa~h bet~een the output :L9 o~ filter ~ and input 22 of summing circuit S, by an ~ldditional delay line ~n the separated chrominance signal path, as it is explained below~ ~ilter 31 provides a one horizontal line delay 10 less the comb~ned delays provided by filter 2 and adder ~: : 5~ Dela~ line 4 of Fig~ B is repl~ced in the embodiment of Fig. 11 by a delay line 32 coupled in the separa~ed chrominance signal path between ~he ou~put 20 of the differencing circult 3 and ~nput 21 of adder 5. Delay 15 line 3~ provides a ~wo horizontal line delay less ~he ~ combined delays in circuits 7~ 3r and 5. Consequently, ; ~ ~ the desired one line delay o~ the luminance component and two line delay of the chrominance component are provided each in the respective separated signal paths 20 of these components ln the circuit of Fig. 11.
: I~ will become apparent from ~he above descrip~
.;
: tion that the dropout compensator of the present inYention .~ may be implemented by a variety of comb~nations of delay means coupled in th~composite signal pa~h as well as in 25 ~he separated cllrominanGe and lum~nance signal paths to achieve:the decired one-line luminance and two-line chrominance com~onen~ delay, espectlvely~ ~ will :become fur~her apparent that~various alternat ve embodl-'. ~ .

~ 74R~ ID-26~5 ments of circuit branch 25 of the dropout compensator may recei.ve an input si~nal directly, as shown in Fig. 9 or via switch, as shown in ~igs. 8, 10 and 11. It will also become apparent that in the embodiments of Figs. 8 to 11 filter 2 may be implemented to provide an averaye value output signal or a weighted average value ignal in accordance with ~he oregoin~ disclosure with respect to Figs. 2 and 5.
An example of a preferred embodiment of the 10 dropout compensator of the present invention arranged to process a digital NTSC color televislon signal formed by sampling the signal at a sampling fre~uency that is an even number mult~ple of the color subc~rrier signal frequency is illustrated in Fig. 12. In that embodiment, 15 a sampling frequency of four. times h color subcarrie~
frequency is used. ~s is well known in the art, sampling ; an NTSC color television signal at a frequenGy equal to an even numbe~ multiple of the color subcarrier signal : frequency results in obtaining samples corresponding to 20 locations of vertically aligned picture elements.
: Howeve~, an NTSC color subcarrier signal has an opposite phase on consecuti~e horizontal lines and an identical phase on every other line~ Conse~uently, to achieve a properly phàsed dropout compensa~ion signal, a separa~ed 25 NTSC chrominanca component may be simply inverted on consecu~ive lines, as i~ is known in the art. To facilitate a comparison with the previously described em~odiments of FigsO 8 to 11, corresponding circuit _7~_ ~ 74~ ID-2635 elements in the embodiment of Fig. 12 are designated by corresponding xeference numeralsO To avoid undue repeti~ion, only those portions of Fig~ 12 will be described which are dif~erent from the previously S described circuits of FigsO 8 to 11~ As mentiond above, the embodiment of ~ig. 12 uses al sampl~ng frequency fsampl that is an even multiple of the subcarrier frequency f5ubc~ a clock signal frequency equal to 4 x 3058 M~z = 14.32 M~z. In the embodiment o~ YigO 12, filter 2 may be designed in accordance with the embodi~
ments of ~igs. 2 o~ 5~ as previously described.
In the embodiment of Fig. 12, an NTSC color television signal is separated into its luminance and chrominance componen~ a~ the output of filter ~ such as previously described with respect ~o Fig. 8. When compar~ng the circui~ of FigO 12 to the circuit of Fig.

8, it is seen that delay line 4 in the separated c~romi-nance component path is replaced by phase inverter 400 : To compensate for ~he circuit delay of the invertert an 2~ additional delay circuit 41 is coupled in ~he separated ~ luminanse signal path. Delay circuit 41 provides a ; delay equal to that provided by inverter 40. Thus, the same amount of delay in both the separated luminance and . - .
: chrominance signal pat~s is provided in preparation ~or subsequent comblnation of the separated signals in :~ adding circuit 5. Consequently, the one-line delay 6 provides a delay equal to one horizontal line interval less the combine~ circuit delays of filter 2, delay . .

~ 7~ ID-2635 circuit 41, and adding circuit 5. It follows from the foregoing description that both the luminance and chrominance components of the dropout compensator in Fig~ 12 are delayed by one horizontal line interval.
One preferred embodiment of speci~ic circuitry ~or implementing the dropout compensator embodiment of the present invention shown in ~ig. 8 is illustrated in consecu~ive Figs. 13a to 13h. To facilitate comparison between Figs~ B and 13, individual circuits in the 10 specific clrcuitry of Figs. 13 corresponding to elements of the block diagram of FigO 8 are circumscxibed by dashed lines and designated by like reference numerals~
~Similarly, connecting lines between the individual circuits of the specific circui~ry are designated by 15 reference numerals corresponding to input/outpu~ designa-tions of corresponding blocks of Fi~. 8. ~or ~he purpose of complete disclosure, the in~egrated circui~
` ~ components shown in Figs. 13a to 13h are des~gnated by respec~ive part numbers commonly used by manufacturers~
In Fig. 13a, consecutive 8 bit parallel digltal word samples Sl, S2, S3, etcO~ of thedigital color telev~sion signai are recei~ed at inpu~ 10 ~f the dropou~ compensator by ~wo data selector/multl plexers U42 and USl o~ switch 1. These multiplexers 25 also receive data at input 24 from delay line 6, shown in Figs. 13g and 13h. A control signal is received at nput 12 by the mult~plexers from a conventlonal R. F~
envelope level dropout de~ector circu~t ~not shown), as ~72--, ~ .

ID~2635 mentioned beore, In normal operation, the multiplexers apply the inpuk data from 10 to output 14. When the control signal at 12 is received, the multiplexers switch from input 10 to input 24. The data from 14 i5 fed to output 15 of the dropou~ compensator, and it is also supplied to the inpu~s 18 of the three transmission paths through the filter circuit 2 loca~ed in Figs. 13a, 13b and 13c~ A filte~ circuit embodiment of the kind shown in Fig. 2 is utilized. The data from 14 is applied ~o ~he ~irst register 50 of the filter circuit formed of flip-flops U66 and U9~ which delays the ~irs~ sample Sl by one clock signal period to assure its proper ~iming for addi~ion with ~he second sample 52 received one clock signal later~ Samples Sl and S2 are coupled for add~ng in adder 51 formed of two 4-bit binary adders U75 and U83 shown in Figs 13b and the ~um Sl~S2 is coupled to regiser 52 formed by flip-flops - U57 and U50, which provides the one clock signal delay in preparat:ion for addition with the subsequently.
. 20 received sample S3~ The latter summation ~s performed by ~he addeY 53 formed by ~wo 4-bit ~inary adders IJ58, U67" and an outpu~c ~ignal herefrom represellts the sum S=Sl+S2~S3. The summed signal S is coupled to register 54 formed by ~lip-flops U49~ U50 to assure 25 proper timing for fur~her p~ocessing~ In t~is particular ; ~ embodiment of the invention an average sample value is o~tained by dividing signal S by 3. The division by 3 : is performed wit:h a 0.13% accuracy by an approximation , : . ' algori~hm:
3 = S4 + Sl6 ~ 64 ~ 256 ( 10 ) For the particular application of averaging the samples in the presently described preerred 5 embodimen~, the approxima~ion algorithm of e~uation ~ lO ) is implemented in two s~eps as follows:
PS = S4 + l~; (11) 3 = PS ~ -Pls6 ( 12 ) Steps ( 11 ) and ( 12 ) are performed by the divider 57 of filter 2 shown in Fig. 13c as described below.
4-bi~ binary adders U39~ U48 of Fig~ 13c receive the signal S a~ ~wo sets of inputs. At one o~
the inputs, the lines are coupled to the adder ~n a conven~ional manner ~o bi~ shift ~he signal S two blt 15 positions to become 4. The adder provides a sum of ~S + S4~ o At the output o~ the adder, the summed signal is shifted conventionally another bit postion to obtain an ou~put signal correspondîng to (S + )/2.
The latt~r oul~put signal represents twic~
the partial sum PS defined in equation ~ll). The signal 2PS is applled to flip-~lops ~40, U14, which are clocked to supply signal ZPS to two sets of inputs of the 4-bit ~ -binary adders U32 and U33. At on~ of the inputs, th~
lines are coupled conventionally to the adders ~o bit shift the signal 2PS four bit positions to obtain : 2P6S. At the output of ~he adders, the summe~
: signal is conventionally shifted another bit position to provide an output signal corresponding to .

~ ID;-2635 (2PS ~ 2P6S ~/2. Th~s outpu~ signal represents S3 of the approximation algorithm indicated by equa~ioll (12). The ob~ained signal S3 corresponds ~o ~he prevlously described average value output signal 5 of the filter of Fig~ 2 at the output VII of divider 57~
For be~er comparison with Fig. 2, corre~ponding registers and adders in-FigsO 13a and 13b and lthe divlder in Fig. 13c of the filter circuit 2 are respecti~ely designaked by like reference numerals. The ou~pu~ signal of the 10 divider 57 in ~g. 13c thus represen~s the chrominance-less color television signal~ that is~ the separated luminance componen~, as has been described above with reference ~o Fig~ 8. Signal 3 ~s applied to ~lip-flops U31 and U22 which prov~de both an output 15 signal 3 applied to input 22 o~ adder 5 shown in Fig~ 13f and an invexted output signal -3 applied to ~.nput 17 of di~fer~ncing circuit 3 ~hown in Fig~ 13do The differencing circuit 3 includes 4-bit 20 binary adders U30 r U21 that receive the signal _S3 at one set of inputs 17~ As it is shown în Fig. 13a, the color ~elevision data received by switch 1 is ~ applied to the delay line 7 comprising flip-flops : des gna~ed U8, U65~-U~6 and U47, which are clocked by the clock signal on line 26 to provide a fixed predeter-mined delay of the received signal to oompensate for a : known amoun~ o~ delay provided by the filter circuit 2 illustxated in ,Figs~ 13a through 13c. ~he output data, ~ 7~3 ID-2635 indicated V, of delay line 7 .i~ applied to a second set of inputs 16 of adders U30, U21, of the differencing circuit 3 shown in Fig. 13d. The above adders provide an output signal (V ~ -3 which represent~
the separated chrominance component of the color tele-vision signai t as de~cribed above with reference to the embodiment of Fig~ 8. The obtained chrominance component is fed via clocked fl~p-flops ~29, U3 and output 20 of circu~ 3 to the delay line 4 shown in Fig. 13e.
Delay line 4 comprises eight identical 4 x 256 bi~ rarldom acce~s memo~es of which six memories designat ed U26~ ~17, Ul, U27, Ul~ and U2 are shownO ~wo ~roups of four memories each are utilized for receiving higher and lower order bits, respect~vely~, ~he delay line 4 provides a fixed amount of delay of the separated chrominance component:, equal to one horizontal line peri~d of the color television signal less ~he delay in differencing circuit 3 coupled in the chrominance signal path. The WEiting of da~a into and readin~ of data from 2~ the memories of the delay line 4 is controlled by control signals ~ through ~ These signals are obtained from the memory address genera~or 9 shown in FigO 13d, which will be described in further de'cail hereinbelow. Cascaded clocked ~lip-flops Ull, U3 and ~5 1:ll2~ U3, and multil?lexers IJ20, U4 are utili~e~l ~o assure proper timing o~ ou~put data at output 28 from delay llne 4 to achieve the foregoing del2y.
~7~-~,.. !", ,~ , r ~ -~ '7~

To effect the aforedescrihed alteratlon of the delay provided by the delay line 4 so that the overall delay in ~he chrominance slgnal path is changed between 68~ and ~83 clock cycles, a control signàl, WAO, 15 5 applied to the multlplexers U20, U4 to switch the ou~put of the mul~iplexers between its two inputs respectlvely supplied by the flip-flop~ Ull, U3 and U12, U30 The control signal, WAO" is a siynal ~ha~ alternates be~weer a high and low logic level at a freque~cy equal to 10 one-half the horizon~al line rate and is generated ko be synchronous wi~h the 10~7 ~S~z clock signal and ~he horizontal synchroni~ing signal of the vldeo signal ; being processed by ~he dropout compensa~or. During each cycle of ~he con~rol s~gnal, WAO r i~ is a~ one o~ ~ts : 15 logic levels for an ~nterval equal to 68~ clock cycle and a~ the other fo~ an ln~erval of 6B3 clock cycles.
: Swltch~ng ~he ou~put of ~he ï3~ plexers between ~he inputs supplied by ~he two clocked cascaded flip-flops : : has the e~fect of inserting (or removing~ one clock cycle of delay into th~ delay 4 9 With the output of the multiplexers coupled ~o ~he input supplied by the flip-flop U12, U3, the delay provided by delay dev~ce 4 is one clock cycle longer than when the multiplexer'~
outpu~ ~s coupled ~o receivP data supplied by ~he flip-flop Ull~ U3~ This additional one clock cycle of ~elay is the ti.me required to transfer data from the output o~ flip-flop Ull, U3 ~o the ou~pu~ of flip-~lop U12, U3~

~ 74~ ID 2635 The delayed chrominance component provided at the ou~put 28 of delay 4 is app:lied to inpu~ 21 of adder 5 shown in Fig. 13f. As shown .in Fig. 13f, the da~a from input 21 is applied to a f.irst set of inputs o 4-bit binary adders U37, Ul3. The data S3 fxom input 22, representing the separa~ed luminance component, is applied to a second set of the inputs of the adders via clocked 1ip-~lop~ U38, U14 to assure proper timing for additionc The output data ~rom the latter adder~
represen~s a composi~e color television signal in which the chrominance component is delayed about one horizontal line period of th~ television signal while the luminance ; component is essentially undelayed0 with the exception of ~he respective circui~ delays as indicated before.
To preven~ foldback in the output signa~ from adders U37, U13, an overflow and underflow ind~ca~ing circuit is u~ilized in the circuit of Fig. 13f as ., ~ follows. The mos~ slgnif3.can~ bi~ Cl a~ ~he input of :~ , adder U37 is applied via inver~er Il to ~he inpuk of 20 AND ga~e Al. The other input:of Al i~ formed by the "carryn output at p~n 9 o adder U37. The output of .
Al is applied to one input of OR gat~s l to 8' resp~ctively. The other inputs of ~he O~ ga~es receive the ou~put signal from adders U37,: Ul3. The output signal from the OR gates l t~ 8 is applied to : multiplexers U:39, U46. Whenever an overflow occurs, ~he :: AND gate al activates the OR gates to force the : multiplexers U39, U46 to place a hlgh loyic level s~gnal , . . .
~ ~7~-~, .. .
.

~ 7~ ID 2635 on all its output lines 23 when clocked by the clock signal, For underflows, ~he "carry" output of pin 9 of adder U37 is also applied via inverter I2 to one input of NAND gate N1, which also receives at its other input the most significan~ bit Cl applied at the input o~ adder U37. The output of Nl is applied ~o a control input of the multiplexers U39/ U46. Whenever an underflow condi~ion occurs, wh~ch is represented by a simultanei~y of conditions a~ pins 9 and 11 of the adder U37, the outpu~ of the N~ND gate Nl goes to a low logic level and forces the multiplexer U39, U46 ~o place a low logic level signal on all of its output l-nes 23., .
As it is ~nown in the ar~, the NTSC chrominance : subcarrie~ component has an opposite phase a~ the beginning of each consecu ive television line, and consequently, it has the same phase at the beginning of every other line. It is also known in ~he art tha~ for obtainin.g a dropout compensation signal it is necessary to delay bo~h the luminance and chrom~nance component by 2~ one horizontal line period. ~owever, o ach~eve a proper line-to line phasP relationship of the chrominance componen~ in ~he e:mbod1ment of Figs. 13a to 13h, the lat~er component is delayed ~y two horlzontal line : periods as will become apparent from ~he following 25~ descriptionO
The signal at ~he output 23 of multiplexe~s U39 J U46 in F.ig. 13f represents an NTSC color television signal ha~ing the chrominance component delayed substan-~ 7~ ID-2635 tially by one horizontal line pexiod and having the luminance component substantially undelayed~ The combined composi~e television signal from the ou~put 23 is applied to the second delay line 6 shown in Figs. 13g s and 13h. Delay line 6 comprises eight identical 4 x 256 - bit xandom access memox~es of ~hich six memories designat-ed U79, U70, U52, U80, U71 and U53 are shown. Two groups o~ fou~ memories each are utilized to recelve - higher and lowe~ order bits, respec~ively. The delay 10 line 6 delays ~he composite color televis~on signal for an interval ~hat ls adjusted on alternate ho~izon~al lines by one clock signal cycle so that a delay of 682 or 683 clock signal cycles less the respec ive circui~ delays in the luminance slgnal path prov~dëd by ~he fil~er 2 lS and adder 5 is providedO
;: Altexa~ion of ~he length of the delay prov~ded by delay line 6 is effected by the multiplexers U82, U73 and clocked flip-flops U817 U74 shown in Fig. 13h~
, These multiplexers and ~lip-flops coopera~e in the same 20 manner as the coxresponding devices described hereinbefore ~: with refexence to the delay line 4 illustxated in Fig~
13f ~o alternately insert and remove ~he flip-flops from ~he signal path oX the delay line 60 As in the case of thP delay line 4t the outpu~ of the multiplexers U82, 25 U73 is alternately switched between its inputs by the previously described control signal WAOo Delay lines 4 and 6 are synchronously clocked so ~hat each provides ~: the same length o~ delay at ~he same time~ Conse~uently, .
.

.

~ 74~.~ ID-2635 the separated chrominance component will pass ~hrough the delay line 4 while the delay lines 4 and 6 each provide a firs~ delay tha~ corxesponds ~o an cverall delay of, for example, 68~ clock signal cycles. However, 5 the same chrominance component (now combined with the - luminance componen~) passes ~hrough the.~ollowing delay line 6 after ~he multiplexers o the delay lines have been swi~ched so that a delay corresponding to an overall delay of 683 clock signal cycles is provided 10 Thus~ the chrominance component experlences a ~wo line overall delay and an average delay of 682.5 clock signal cycles relative to the luminance component. The luminance component experiences essen~ially a one line overall delayc The altera~ion o~ the delay provided by delay 15 line 6 by one clock cycle of the 10.7 MHz clock signal does not introduce signi~icant lumlnance dls~urbances in the displayed picture con~aining a subs~i~u~ed, dropout ` compensating portion.
As i is seen from ~he above descrip~ion, 20 the com~ined delays provided respec~ively by fil~er 2, adder 5 and delay line 6 effect a luminan~e signal delay corresponding to about one horizontal line period.
Similarly, the com~ined delays provided respec ively by delay line 7, differencing cixcuit 3, delay llnes 4 and 25 6 and adder 5 e:E~ect a chrominance signal delay correspond~
ing to two horizon~al line perlods. As shown in Fig~
13h, the output data from d~lay line 6 is applied to input 24 of switch 1 shown in Fig~ 13aO As i~ has been .

described previously in the specification with respect to Fig. 8, ~he la~er data represents a color television dropout compensa~ion signal in which ~he luminance component is delayed by a period of one horizontal line 5 and the chrominance componen~ by two horiæontal line periods.
Figs. 13f and 13d show respec~ive circuit diag~ams of memory address gener^ators 8 and 9 providing address signals on memory address lines Ao to ~7 and A~o to A'7, respectively, and write and read enable control signals on memory ~rite/read lines OEl ~o OE4 and WEl ~o WE4, which are coupled ~o control the data flow ~hrough ~he respec~ive delay lines 6 and 4~ In Fig~ 13d, coun~ers Ul9, U28 and U36 are coupled to count clock cycles corxesponding ~o ~he ac~ual delay provided by the delay line 4 coupled in ~he chrominance si~nal path, as previously desc~ibed wi~:~ respect ~o Figs. 8 and 13a to 13h. The binary outpu of counter ~: U36 is coupled to a two bit binary decoder U44 ~ which 20 decodes~he ~wo bit binary inpu~ signal into a cor~espond-ing four line ou~put signal. The four bit signal is applied ~o a D~type flip flop U35 which, in ~urn!
~ provides a ~our bi~ con~rol signal on lines OEl to ;~ OE~. Each bit of the lat~er signal ~s utilized as a 25 memory write and memoxy read signal ~o control the ~espective read and write cycles of the previously mentioned xandom access memories U26, U17, Ul, U~7, ~18 and U2 o~ ~he delay line 4 in Fig~ 13e.

~`
~ -82-`

The memory write control signals axe coupled to pin 20 and memoxy read signals to pin 18 of each memory.
In Fig~ 13f the counters U72, U63 and U54 axe coupled to count clock cycles cor~esponding to ~he actual delay provided by delay line 6 coupled in the combined dropout compensa~ion signal path, as previously described with reference ~o the above indica~ed igur~s.
The circuit design o~ ~he memory address genera~or 8 of Fig. 13~ is slmilar to that of memory address genera~or

9 of Fig. 13d. Consequently, ~he four bit memoxy write and read con-~rol sign~l on lines ~ WE4 a~ the ou~put o~ D~ype flip-~lop U43 in Fig. 13f is analogous ~o the above-described control signal OEl ~ ~2 f Fig. 13d and i~ is utilized to con~rol the wri~e and read cycles o~ random access memories U79, U70, U52, U80, U71 utilized in delay line 6 of Fig. 13g~ The di~grams of Figs. 13f and 13d reveal the memory addxes~
generators 8 and 9 in sufficient detail; consequently, no further disclosure ~hereo~ ~i s nece~sary~
As it will become apparent to those skilled in ~he art, alternative embodiments similar ~o the disclosed detailed cixcui~ diagrams of Fi~so 13a ~o 13h, as well as altexnative c~rcuit elements ~n these embodiments, may be u~ilized ~o obtain the disclosed opera~ion of ~he 25 dropout compensa~or in accordance with the method of the present inventionO Thus, the differencing circuit 3 may be implemented as a subtracting circuit to which respec-tive signals of the same polari~y are applied, as it ls .

known in the art. Similarly" known alte~native circui~
elements in ~;he summing circuit 5 may be utilized to obtain the combination o~ the chrominance and luminance components., As an alterna~ive, differen'c mean~ of obtaining the delay ~n the delay lines 4 and 6 may be utilized, such as shift registers, instead of the random access memories. Likewl se, to obtain division by 3 of ~he samples in ~ e~. circuit 2, read only memories may be utilized instead of the disclosed circuit elemen~s implementing the approxima~ion algori~hm of equa~ion (lO) o ~ ereinbefore, examples of preferred embodimen~s of dropout compensa~ors have been described or compensat-ing NTSC color ~elevision signals. ~s it will become 15 appaxent to those skilled in ~he art, ~he various embodimen~s could be adapt~d or dropou~ compensa~ion o~
other color ~eIevision systems, such as PAL, PAL-M~ e~c.

:
For example, ~be de~ailed circuit diagram as shown in ~igs. 13a to 13h may be utilized for PAL systems w~h 20 the excep~ion of the respective memory address genera~or circuits 9 and 8 for con~rolling ~he respective delay lines 4 and 6. The la~tex difference in the circuit diagrams is necessi~ated because of the difference in the relationship o~ the ch~ominance subcarxier signal ~ .
25 frequency to the horizon~al line frequency in NTSC and PAL systems. For PAL color television signalsf a Jchree times chrominance subcarrier clock signal frequency o ; .
13 ., 29 M~z is required in contrast to 10 0 7 M~3~ for NTSC

~ ' . . .

~ 7~ ~

signals. Since the horizontal line frequency of PAL and NTSC signals diffex by less ~han 1 pexcent, the higher sampling frequency in PAL results in a higher nu~ber of clock cycles per one horizon~al line period. Consequent-ly, for PAL signals, the above-mentioned circuits 4, 6, 8 and 9 o~ Figs. 13a to 13h have ~o be adap~ed to process ~he hiyher number of clock cycles per line to provide substantially ~he same amount o~ fixed delay as provided for NTSC signals. Furth~rmore, the cloc~
signals indicated 10~7 MHz and 10.7 M~z ln Figs. 13a to 13h will be replaced by 13.3 MHz and 13.3 MHz, ~espective ly. Similar changes would have to be made in circuit elements of ~he respective embodiments of Figs. 9 to 12 if they are ~o be arranged to process PAL or o her television signals. In addition~ a sampling frequency that is an ev~n multiple of the PAL (or other television si~nal) color subcarrier f~equency may be employed.
Figs. 14 and 15 illustra~e block diagrams of a PAL
~ropout compensator in which the PAL television signal is sampled at a }requency equal to four times the PAL
color subcarrler }~equency, i~e., 17.72 M~z, and a fil~er ci~cui~ 2 is used that is adapted ~o process such samples, such as a filter circui~ of the type shown in `~ Fig. 6. Since the embodtments of-Figs. 14 and 15 ~e simila~ to those illustrated in Pigs. 8 to 12, correspond-ing circuit elements in ~he various embodiments are identi}ied by corresponding reference numerals and only ~those por~ions o} Figs~ 14 an~ 15 will be described ; ~85-which are differen~ from ~che previously described embod imen ts .
The embodiment of Fig . 14 is useful for compen sating bot:h PAL and PAL-M color televi.sion signalsr The 5 separated chrominance component is delayed on consecutive lines by a one-line delay cixcui.t 4 an~ inver~ed by phase inverter 40, both latter elements being coupled in the separated chrom~nance signal. path~ The delay provided by delay l~ne 4 is equal to one horizontal line

10 period less the combined circuit delays in differenclng circui~ 3 and phase inverter 40. The one-line delay means 6 provides a delay equal to one horizontal line : period less the combined circuit delays provided by fil~er 2 and addtng circui~ 5. Thus, in the embodimen~
15 of Fig. 14, the luminance component is delayed by essentially one horizontal line period and the chromi-nance component by two horizon~al line periodsO
In the embodlmen~ o~ Fig~ 15 t a dropout .compensator circuit in accordance with the presen~
~ invention is shown, suitable for PAL and PAL-M system applications. The separated chrominance component at the ou~put of the differencing circuit 3 is color decoded by decoder 42 into its u and v color components as it is known in the art. For example, if the sampling of the color televlsion si~nal is done precisely along the color subcaxrier component axis, alternative consecu-tive samples wi:Ll represent the respective u and v components. The latter follows from the well known : ~ --86--7~

feature o~ PAL and PAL-M signals, that the u and v components are ~uadrature-modula~:ed onto the subcarrier thus having a phase difference oi exac~ly 90 a~ all times~ Consequen~ly, when the sampling frequency is 5 equal to four times the color subcarrier signal frequency and the sampling signal is in phase with ~.e color subcarrier signal, the decoder 42 may be implemented by a simple ga~e for separating alternative consecutive samples pertaining ~o the u and v components, respectively~
10 The above-indicated decoding ~echn~que i5 well known in the PAL or PAL-M systems. The separated v component i5 - then inverted by a phase inve~ter 44. The separated u component and inverted v component are combined in adder 45, for example, by ~imply adding the ~wo components u 15 and (-v~. To compensa~e for the cixcuit delay of inverter 44l a delay circui~ 43 is utilized in the separated u signal path, coupled between the output of decoder 42 and adder 45, to obtain ~he same amount of d~lay of the u and v component= in prepara~on for ~he 20 subsequene addit~on in adder 45~ Similarlyr delay circuit 41 coupled in the sepaxa~ed luminance signal path between the output of filter 2 and inpu~ of adder S has a delay equal to the:combined circuit delays of elements 3, 42, 43 and 45, in ~e separa~ed chrominance 25 signal path to provide exactly the same amount of delay :~ in the separated chrom~nance and luminance signal paths, respectively, ill preparation for subsequent addition of these components in adder 5.

ID-~635 It follows from the foregoing descrip~ion that both the chromillance and luminance slgnal components are delayed iJI the circuit of Fig. 15 by one horizontal line period.
The line-by-line one quarter cycle offse~
resulting from the ~0 degree phase sh~t occuring in ~he PAL subcarrier component during consecut~ve television lines is selectively adjusted i:n ~he PAL~type dropout com~ensators of the pre~ent invenkion when a previous 10 line of the television signal is substituted for a subsequen~ defective line of the television signal.
This is achieved by applying an approp~iate number of clock signAls to the respectiv~ delay lines 4 and 6 o the various embodiments, and shiftlng ~he beginning 15 of each consecutive line accordingly ~o compensate for ~ the o~fset~
; TG illus~rate this, Fig~. 16a and 16b reveal detailed circui~ diagrams o respective memory address generators for utilization in the dropout compensator ~20 circuit of Figs. 13a to 13h as adapted for PAL color television signals. More par~icularly, the PAL memory address generator circuit 109 shown in Fig. 16a replaces the NTSC memory address generator 9 of Fig. 13d, and the PAL circuit 108 shown ~n F~g. 16b replaces ~he ~TSC
. ~
: : 2$ address generator B of Fig~
In Fig. 16a, a first signal Cl of fre~uency ~/4, that is, one-quarter o the 15.625 k~ PAL
horizontal sync frequency, ~s received by a flip-flop , il ~ :
~ , ~ ID-2635 U2~1. A second signal C2 of ~requency fH/2, that is, one-half of the PAL horizontal sync frequency, is received by flip-flop U223. Both signals Cl and C2 are ~requency and phase locked to the standaxd PAL our horizontal line sequence television signal received at terminal 10 in Fig. 13a and they may be obtained from a conventional PAL sync processing circuit (not shown).
These signals are clocked by ~he ~lip flops U221 and U223 for noise immunity. The fH/4 output s~gnal from flip-flop U221 is fed ~ia inverter U222 to both flip-flops U224 and U2250 The latter flip-flops each receive an f~/4 signal fxom ~lip-~lop U223, which in turn, is clocked by a 13~3 M~z clock slgnal. The frequency of ~he clock signal corresponds to ~hree times ~he PAL color subcarrier signal ~requency 4.43 M~20 ~lip-flops TJ2~4 and U225 both divide the fxequency o~ the~signals at their respective input signals by two. Thus, the xespective outpu~ signals of flip-flops U~24 and U225 : have a frequancy fH/4 and are phase locked ~o each : ~: 20 other by the above-described operation of c~rcuit : elements~
An ~-rate write pulse, fH, is received by a one-sho~ multivibra~or U226 which opera~es as a pulse stretcher. The wrlte pulse is modulated by ~he well-known ~2~ PAL ~/4 hori~ontal line sequence and is genexated by :: the aforementioned conventional PAL sync processor circuit to be frequency and phase locked to signals C
and C~. The stretched write pulse is ID-~635 ~ ~ 7~3 received by a coun~er U227, which also receives the f~/4 signal rom flip~flop U2~4 and the 13~3 M~z clock signal. The stretched write pulse indicated "counter reset~ is utilized to reset the counter U227 at the beg.inning of each horizontal lineO
Memory address coun~er;s U229, U230, U231 and U235 are coupled to count 0 to 768 clock cycles a~ the 13.3 M~z clock signal rate in a well Icnown manner ~o effect the generation of memory address signals A~o to 10 A'7 and write and read enable signals ~1 to OE4 fox ; use in ~he control of random access memories of the delay line 4 shown in Fig~ 13e. A ~wo-by-~our decoder U236 and following clocked la~ches U237, U238 xespond to the coun~ers to provide the address signals and wri~e 15 and read enable signals in the manner described hereinbe-fore for the compara~le devices included in the memory : address gellerator 9 illustrated in ~igO 13d. The : aforementioned Qne-quar~r subcarrier cycle line-by-line : ad~ustment is effec~ed by counter U227. The output signal of counter U227 is coupled via inverter U228 to counters U229. U230 and U231 and via an additional flip-flop U233 ~o counter U235. The output signal of coun~er U227 i5 utiliz d to s ar~ the memory address counters at the beginning of each horizon~al lineO
25 Mo~ulation of ~he output signal of coun~er U2~7 by the fH/4 signal from flip-flop U224~ effecta shifting of the beginning of each consecutive horizontal line to obtain the desired offse~ by one-quarter of the subcarrier >~

cycle on consecutive horizontal lines. The above-mPntioned 768 clock cycles correspond to the one-line delay provided by the delay line 4 in the chrominance s.ignal path as it has b0en described in detail with 5 respect to the block diagram of Fig. B and detailed diagram of Figs. 13a to 13h.
As it is revealed by the drawings, the memory address generator circuit 108 of Fig~ 16b is similar to ~he above-desCribed circuit. 109 of Fig. 16a. Bo~h 10 pulses, the fH/4 output pulse from flip~flop U225 and the counter reset pulse from U226, are applied to ~ counter U227a o circu~t 1080 As it will become apparent `; from comparing the circuits of Figs. 16a and 16br the operation of counter U227a of Fig. 16b is similar to the lS previously described operation of counter U227 of Fig.
16a. Consequently, circuit 108 opera~es in a similar manner as the previously described c~rcuit 109. ~owever, the actual count provided by the memory address counters of Fig. 16b transferred via memory address lines ~0 to : 20 A7 to random access memories of delay line 6 shown in iy~ 13g, is different from the count provided ky circuit lO9o The latter difference is effec'ced with respect to the di~ferent length of the one-line ~elay 6 in the recombined luminance and chrominance ~ignal path~
25 as i~ ha5 been previously disclosed with respect to Figs. 8 and 13a to 13h. Thus,:the minor differences ;between the respective circuit diagrams of Figs. 16a and 16b reflect the above-indicated variation~
~: -91- ' , .

A PAL or PA~-M chrominance subcarrier signal has an incLemental 90 degree phase shift on consecutive lines and has an opposite phase on every other line.
Conse~uen~ly, a PAL or PAL-M signal has an identical phase on every fourth line. To achieve a proper phase of the dropou~ compensa~ion signal fo~ PAL or PAL-M
signals, the separated chrominance component may be delayed by one horizontal line period and inverted on consecu~ive lines or, instead, the separated chrominance component may be decoded into u and v components and the v componen~ subsequen~ly inverted on consecutive lines ~o achieve vertical alignmen~ of samples of the dropou~
compansation signal.
With respect to variations of the various ~ 15 embodiments o~ the presen~ invention, it should be apparent tha~ .instead of coupling the input of the dropou~ compensator circuit 25 to outpu~ 14 of swltch 1, :~ ~ as shown in Figs. 12, 14 and lS it may be coupled ~o input 11, of switch 1~ similarly as shown in Fig~ 9.
-: 20 Fur~hermore, in ~he embodimen~s of he invention shown :
:: in Flgs. 12, 14 and 15 a sampling frequency equal to .~ four times the aolox subcarrier frequency is used.
Therefore, it ls advantageous o u~ilize the embodimen~
: of fiI~er 2 shown in FigO 2. This advan~age follows ~5 from~ ~he fact that the filter of ~ig. 2 provides a weighted average~ sample value of the color television signal taken from an odd number o~ samples hus eliminating phase displacemen~ of the average samples by one-half '7~L~
sampling period with respect to the origi.nally receivedsamples, as it has been disclosed previously in detail.
However, the emhodiment of filter 2 shown in Fig. 6, providing an average sample value taken fron an even number of consecutive samples could be used as well.
Certain embodiments disclosed in this application are disclosed and claimed in paxent application 362,75~.
While the invention has been shown and described with particular reference to preferred and alternative embodiments thereof, it will be understood that variations and modifications in :Eor~ and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

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Claims (25)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A digital filter circuit for processing a digitally encoded composite signal having a periodic signal component of a known frequency and symmetrical with respect to a signal crossing axis, the encoded composite signal comprising consecutive digital representations corresponding to discrete amplitude values thereof provided at a frequency equal to a rational number multiple of said periodic signal frequency and in a frequency and phase-locked relationship to said periodic signal, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, comprising in combination:
a first means coupled to receive and store said consecutive digital representations of said composite signal; and a second means coupled to said first means for arithmetically combining a given number of consecutive digital representations defining a zero average value of said periodic signal component, to provide an average value output signal representative of said digitally encoded composite signal from which the periodic signal component is eliminated.

2. The circuit of Claim 1 wherein said second means is coupled to arithmetically combine an integral number of consecutive digital representations defining a time interval equal to an integral number of cycles of said periodic signal component.

3. The circuit of Claim 1 wherein said second means is coupled to arithmetically combine an odd integral number of consecutive digital representations and wherein each average value output signal provided by said second means corresponds to a digital representation occurring in the middle of each given number of consecutive digital representations taken for averaging.

4. The circuit of Claim 1 wherein said second means comprises means for weighting said consecutive digital representations in accordance with selected weighting coefficients and means for providing a weighted average value output signal by arithmetically combining a given number of said weighted consecutive digital representations defining said zero average value.

5. The circuit of Claim 4 wherein said discrete amplitude values of said composite signal are provided at a frequency equal to an even integral number multiple of said periodic signal frequency and said means for providing said weighted average value output signal is coupled to arithmetically combine a given odd integral number of selected ones of said weighted consecutive digital representations defining said zero average value, each said weighted average value output signal provided by said second means corresponding to a digital representation occurring in the middle of each said number of consecutive digital representations taken for averaging.

6. A digital filter circuit for eliminating a chrominance subcarrier signal component from a composite color television signal, said color television signal being encoded into consecutive digital representations by sampling at a frequency equal to a rational number multiple of said subcarrier signal frequency, utilizing a sampling signal which is frequency and phase-locked to the subcarrier signal, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, comprising:
a first means coupled to receive and store said consecutive signal representations; and a second means coupled to said first means for providing an average value output signal by arithmetically combining a given number of consecutive digital representations which define a zero average value of said subcarrier signal component.

7. The filter circuit of Claim 1 or 6, wherein said first means comprises register means for receiving and storing said consecutive digital representations in synchronization with a known clock signal and wherein said second means comprises adding and dividing means for arithmetically combining said given number of consecutive digital representations in synchronization with said clock signal.

8. The filter circuit of Claim 6 wherein the sampling signal frequency is equal to an integral multiple of the subcarrier signal frequency and said second means is coupled to provide said average value by arithmetically combining an integral number of consecutive digital representations defining a time interval equal to an integral number of subcarrier signal cycles.

9. The filter circuit of Claim 6 wherein said second means is coupled to provide said average value by arithmetically combining a given odd integral number of consecutive digital representation and wherein each average value output signal provided by said second means corresponds to a digital representation occurring in the middle of each said given number of consecutive representations taken for averaging.

10. A digital comb filter circuit for eliminating selected periodic signal components from a digitally encoded composite signal, said selected components representing a basic periodic signal of a known frequency and higher and lower order frequency components thereof, said selected signal components being symmetrical with respect to a signal crossing axis, said encoded composite signal comprising consecutive digital representations corresponding to discrete amplitude values thereof provided at a frequency equal to a rational number multiple of said basic periodic signal frequency and in a frequency and phase-locked relationship to said basic periodic signal, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, comprising in combination:
a first means coupled to receive and store said consecutive digital representations of the composite signal; and a second means coupled to said first means to successively provide an average value output signal by arithmetically combining a given integral number of consecutive digital representations defining a zero average value of said basic periodic signal component in a time interval equal to an integral number of cycles of said basic periodic signal, a lowest order periodic signal component being eliminated by said comb filter having a frequency equal to the frequency of said discrete amplitude values divided by the number of consecutive digital representations taken for averaging.

11. In a system for processing a digitally encoded composite signal having a periodic signal component of a known frequency and symmetrical with respect to a signal crossing axis, said composite signal comprising consecutive digital representations corresponding to discrete amplitude values thereof provided at a frequency equal to a rational number multiple of said periodic signal frequency and in a frequency and phase-locked relationship thereto, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, a combination comprising:
a first means coupled to receive and store consecutive digital representations of said composite signal;
a second means coupled to said first means to successively provide an average value output signal by arithmetically combining a given number of consecutive digital representations defining a zero average value of said periodic signal component, said average value output signal of said second means representing said digitally encoded composite signal from which said periodic signal component is eliminated; and a third means having a first input coupled to receive said output signal of said second means and a second input coupled to receive said consecutive digital representations of said composite signal to provide a difference signal representative of said periodic signal component.

12. The circuit of Claim 11 wherein the sampling frequency is equal to four times the subcarrier signal frequency, and wherein:
said second means is coupled to provide said weighted average data value by arithmetically combining continuously three alternate ones of five consecutive data with the first and fifth data weighted by a factor of one-half and the third data unweighted.

13. A digital filter circuit for eliminating a chrominance subcarrier signal component from a digitally encoded composite color television signal comprising consecutive data obtained by sampling at a frequency equal to an even integral multiple of the frequency of said subcarrier signal component, said even integral multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, said sampling signal being frequency and phase-locked to said subcarrier signal, comprising:
a first means coupled to receive and store said consecutive data; and a second means coupled to said first means for weighting said consecutive data in accordance with selected weighting coefficients and for providing a weighted average data value output signal by arithmetically combining a given odd integral number of weighted consecutive data defining a zero weighted average value of said subcarrier signal component, each weighted average data value output signal corresponding to a data occurring in the middle of each said odd integral number of weighted consecutive data taken for averaging.

14. In a system as defined in Claim 13 for separating a luminance and a chrominance signal component of a digitally encoded composite color television signal, said periodic signal component corresponding to a color subcarrier signal, said color television signal being encoded into consecutive digital data by sampling at a clock signal frequency equal to a rational number multiple of said color subcarrier signal frequency, utilizing a sampling signal which is frequency and phase-locked to the subcarrier signal, wherein:
said first means comprises register means for receiving and storing said consecutive data at a said clock signal frequency;
said second means comprises adding and dividing means for arithmetically combining said given number of consecutive data defining a zero average value of said color subcarrier signal in synchronization with said clock signal, said average value output signal of said second means representing said separated luminance component; and said third means is coupled to provide said difference signal in synchronization with said clock signal, said difference signal representing said separated chrominance component.

15. The apparatus of Claim 14 wherein said second means provides a circuit delay equal to a known fixed number of clock cycles, said apparatus further comprising a fixed delay means coupled between an input of said second means and said second input of said third means to compensate for said delay provided by said second means.

16. A method for processing a composite signal comprising a periodic signal component of a known frequency and symmetrical with respect to a signal crossing axis, said composite signal being encoded in the form of consecutive digital representations by sampling at a frequency equal to a rational number multiple frequency of said known periodic signal, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, comprising the steps of:
receiving and storing consecutive digital representations of said composite signal; and arithmetically combining a given number of consecutive digital representations which define a zero average value of the periodic signal component to provide an average value output signal representative of the digital composite signal from which the periodic signal component is eliminated.

17. The method of Claim 16 wherein the step of arithmetically combining includes combining a given integral number of consecutive digital representations which define a time interval equal to an integral number of cycles of the periodic signal component.

18. The method of Claim 16 wherein the step of arithmetically combining further comprises weighting said consecutive digital representations in accordance with selected weighting coefficients and combining a given number of weighted consecutive digital representations defining said zero average value.

19. The method of Claim 18 wherein the sampling frequency is an even integral multiple of the periodic signal frequency and wherein the step of arithmetically combining includes combining a given odd integral number of selected ones of said weighted consecutive digital representations defining said zero average value, each weighted average value output signal corresponding to a digital representation occurring in the middle of each said odd number of consecutive digital representations taken for averaging.

20. A method of digitally separating the chrominance and luminance component of a digital composite color television signal represented by consecutive data obtained by sampling at a frequency equal to a rational multiple frequency of the color subcarrier component, utilizing a sampling signal frequency and phase-locked to the subcarrier signal, said rational number multiple frequency being greater than twice the frequency of the highest frequency component of the composite signal, comprising the steps of:
receiving and storing the consecutive data in preparation for subsequent arithmetical combination thereof;
arithmetically combining successively a given number of consecutive data which define a zero average value of the color subcarrier component to provide an average data value output signal representing the separated luminance component; and subtracting the obtained average data value output signal from said digital composite color television signal to obtain a difference signal representing the separated chrominance component.

21. The method of Claim 20 wherein the consecutive data is obtained by sampling at a frequency equal to three times the color subcarrier signal frequency, and wherein the step of arithmetically combining includes successively combining three consecutive data to provide said average data value output signal, each obtained average data corresponds to that data which occurs in the middle of the three consecutive data.

22. The method of Claim 20 wherein the consecutive data is obtained by sampling at a frequency equal to four times the color subcarrier signal frequency, and wherein the step of arithmetically combining includes:
successively combining three alternate ones of five consecutive data, with the first and fifth data weighted by one-half and the third data unweighted, to provide a weighted average data value output signal, each obtained average data corresponding to a data occurring in the middle of said five consecutive data.

23. A digital filter circuit for processing a digital signal representing a composite signal having a signal component of a known frequency, the digital signal comprising consecutive digital value representations at a frequency equal to a rational number multiple of said known frequency and in a frequency and phase locked relationship to said signal component, said rational number multiple frequency being greater than two times said known frequency, comprising:
first means responsive to a clock signal in synchronism with said rational number multiple frequency for receiving and storing each of said consecutive digital value representations for a duration corresponding to an interval defined by at least three consecutive digital value representations received by the first means; and second means coupled to said first means for arithmetically combining each received digital value representation with a selected number of other selected ones of said received digital value representations to generate in place of said each received digital value representation a further digital value representation of the average of the values of said arithmetically combined digital value representations that is productive of a zero average of a portion of said arithmetically combined digital value representations corresponding to said signal component of a known frequency.

24. The digitial filer circuit according to Claim 23 wherein the digital signal represents an analog composite signal and further comprising an analog-to-digital converter means coupled to receive the analog composite signal and responsive to a clock signal for converting the received composite signal to the consecutive digital value representations at a frequency of the clock signal, and a clock signal generator means responsive to the signal component of known frequency contained in the composite signal for generating the clock signal at a frequency which is said rational number multiple of the frequency of said signal component.

25. A method of processing a digital signal representing a composite signal having a plurality of signal components one of which is of a known frequency, the digital signal comprising consecutive digital value representations at a frequency equal to a rational number multiple of said known frequency and in a frequency and phase locked relationship to said one signal component of a known frequency, said rational number multiple frequency being greater than two times said known frequency, the steps comprising:
transmitting consecutive digital value representations through a digital signal transmission path at a rate corresponding to and synchronous with said rational number multiple frequency, said transmission path of a length equal to an interval defined by at least three consecutive digital value representations;
combining each digital value representation transmitted through the digital signal transmission path with a selected number of other selected ones of said digital value representations being transmitted through said digital signal transmission path to generate in place of said each digital value representation a further digital value representation of the summation of the values of said combined digital value representations that is productive of a zero summed value of a portion of said combined digital value representations corresponding to said signal component of a known frequency; and weighting each further digital value representation to obtain an output digital value representation of the average of the values represented by the combined digital value representations.