CA1165880A - Peak dynamic stress calculator - Google Patents
Peak dynamic stress calculatorInfo
- Publication number
- CA1165880A CA1165880A CA000397147A CA397147A CA1165880A CA 1165880 A CA1165880 A CA 1165880A CA 000397147 A CA000397147 A CA 000397147A CA 397147 A CA397147 A CA 397147A CA 1165880 A CA1165880 A CA 1165880A
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- Prior art keywords
- signal
- stress
- maximum
- output
- peak
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
- G01L1/22—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
- G01L1/225—Measuring circuits therefor
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
This invention relates to an apparatus for automatically determining various stresses measured by a rectangular strain gauge rosette. The invention receives signals from the rosette and provides signals representative of the maximum principal stress, the minimum principal stress and the maximum shear stress, the peak maximum principal stress, the minimum principal stress at the instant when the maximum principal stress is peaking, and the peak value of the shear stress. A first analog signal processor provides stress signals representative of the maximum principal stress, minimum principal stress and maximum shear stress for each instantaneous input signal amplitude from each arm of the strain gauge rosette, and a second signal processor receives the stress signals and provides output signals representative of the peak maximum principal stress, minimum principal stress at the instant of peak maximum principal stress, and peak maximum shear stress. Using the invention a designer of a vehicle or other apparatus normally subject to stress can observe the aforenoted stresses immediately during a test and either repeat the test or very slightly alter it to affirm the data or to detect subtle differences, knowledge of which would otherwise be lost using prior art techniques.
This invention relates to an apparatus for automatically determining various stresses measured by a rectangular strain gauge rosette. The invention receives signals from the rosette and provides signals representative of the maximum principal stress, the minimum principal stress and the maximum shear stress, the peak maximum principal stress, the minimum principal stress at the instant when the maximum principal stress is peaking, and the peak value of the shear stress. A first analog signal processor provides stress signals representative of the maximum principal stress, minimum principal stress and maximum shear stress for each instantaneous input signal amplitude from each arm of the strain gauge rosette, and a second signal processor receives the stress signals and provides output signals representative of the peak maximum principal stress, minimum principal stress at the instant of peak maximum principal stress, and peak maximum shear stress. Using the invention a designer of a vehicle or other apparatus normally subject to stress can observe the aforenoted stresses immediately during a test and either repeat the test or very slightly alter it to affirm the data or to detect subtle differences, knowledge of which would otherwise be lost using prior art techniques.
Description
I 65~0 02 This invention rela-tes to apparatus for au-tomatically 03 determining the principal stresses and maximurn shear stress 04 ~rom one or a plurality of rectangular strain gauge rosettes 05 during real time.
06 The design o~ equipment such as vehicles which undergo 07 various degrees of stress depends to a great extent on stress 08 testing. This is usually undertaken using measurements ~rom 09 strain gauges placed at various stress points on the vehicle or apparatus undergoing test.
11 It is often desirable to determine the maximum 12 principal stress, the minimum principal stress and the maximum 13 shear stress, as well t~e peak maximum principal stress, the 14 ~ninimum principal stress at the instant when the maximum ~5 principal stress is peaking, and the peak value of the maximum l6 shear stress. When little is known about a stress ~ield or its 17 direction at a particular test point, it is necessary to employ 18 a three element strain gauge rosette to enable determination of 19 the previously mentioned values. The de-termination of these values ~rom the outputs of the strain gauges is complex, and 21 heretofore could not be measured directly to ob-tain real time 22 observation of the relative stresses.
23 Real tirne observation of the aforenoted stresses is 24 important, since, for example, when a vehicle is being tested, a certain mode of operation which causes a particular peak
06 The design o~ equipment such as vehicles which undergo 07 various degrees of stress depends to a great extent on stress 08 testing. This is usually undertaken using measurements ~rom 09 strain gauges placed at various stress points on the vehicle or apparatus undergoing test.
11 It is often desirable to determine the maximum 12 principal stress, the minimum principal stress and the maximum 13 shear stress, as well t~e peak maximum principal stress, the 14 ~ninimum principal stress at the instant when the maximum ~5 principal stress is peaking, and the peak value of the maximum l6 shear stress. When little is known about a stress ~ield or its 17 direction at a particular test point, it is necessary to employ 18 a three element strain gauge rosette to enable determination of 19 the previously mentioned values. The de-termination of these values ~rom the outputs of the strain gauges is complex, and 21 heretofore could not be measured directly to ob-tain real time 22 observation of the relative stresses.
23 Real tirne observation of the aforenoted stresses is 24 important, since, for example, when a vehicle is being tested, a certain mode of operation which causes a particular peak
2~ stress to be observed can be immedia-tely repeated or varied 27 slightly and the results observed. Previously, the 28 determination of peak maximum principal stress, minimum 29 principal stress at the instant when the maximum principal stress is peaking, and the value o~ the peaX maximum shear 31 stress was obtained either by recording the output signals from 32 the strain gau~es, and then either hand calculating the 33 stresses, or by applying the recorded strain gauge rosette 34 output data to digital computers. In both cases there is a 3S significant tirne lag during which the exact physical external 36 actors which are to be repeated can be, and often are lost.
37 The present invention is a circuit which provides, on a 38 real time basis, signals representing the maximum principal -`` 1 3 fi ~ O
01 stress, the minimum principal stress, the maximum shear stress,~2 the peak value of the maximum principal stress, the value of 03 minimum principal stress at the instant w~en the maximum 04 principal stress is peaXing, and the peak value of the maximum 05 shear stress. These signals can be displayed on an 06 alphanumeric display, which allows the operator of the 07 apparatus which is under test to repeat certain tests with 08 similar external factors immediately upon observation o* their 09 effect, or to make note of the external factors giving rise to the stress which would otherwise be missed with the prior art 11 methods of hand and computer calculation a long time after the 12 transient factors have passed.
13 In general, the present invention is apparatus or 14 the determination of stress in a structural member comprising means for receiving input signals from the arms of a 16 rectangular strain gauge rosette attached to the member, a 17 first analog signal processor for providing stress signals 18 representative of the maximum principal stress, minimum 19 principal stress, and maximum shear stress for each instantaneous input signal amplitude continuously upon receipt 21 of the input signals, and a second signal processor for 22 receiving the stress signals and for providing output signals 23 representative of maximum peak principal stress, minimum 24 principal stress at the instant of peak maximum principal stress, and peak maximum shear stress.
26 A number of such circuits can be connec~ed in parallel27 to a channel selector to provide a plurality of input 28 channels. A group of digital panel meters can be switched to 29 receive signals from any of the channels as desired. Of course a printer can also be used to record the output signals o* each 31 of the channels continuously.
32 A better understanding of the invention will be 33 obtained by reference to the detailed description below, in 34 conjunction with the following figures, in which:
`35 Figure 1 is a basic block schematic of the invention, 36 Figure 2 is a detailed block diagram of the invention,37 Figure 3 is a schematic diag~am illustrative oE a 38 first signal processor portion of the invention, and ~ `
5~0 01 Figure 4 is a basic schematic dlagram of the preferred 02 form of the second signal processor por-tion of the invention.
03 Turning to Figure 1, strain gauges disposed in the 04 usual form at 45 to the other, forming a three elemen-t 05 rectangular strain gauge roset-te 1 are connected -to 06 corresponding strain gauge conditioners 2. The strain gauge 07 conditioners are of conventional construction, and provide 08 output signals ~A~ ~BI and ~C which signals are dir ctly 09 related to the amount of strain each corresponding arm of the rosette undergoes. In use the strain gauge rosette i5 a-ttached 11 to a structural member of an apparatus under test.
12 The aforenoted output signals from the strain gauge 13 conditioners are applied to a first analog signal processor 3.
14 This processor contains circuitry which provide output signals ~1 representative of the instantaneous maximum principal 16 stress, ~2 representative of the minimum principal stress, 17 and max~ the maximum shear stress. The analog signal 18 processor translates the output signals from the strain gauge 19 conditioners by circuitry which has the following transfer functions:
22 ~ ~ ~ 2(~_V~ ~ 2(l~V~ J(~ ~2~ (2~g~ 2 ~ C~) 24 ~2- E[ 2-~l-V) ~ ~ V) J~ c) ~ (2 ~8~ c)2 J
227 E - ~ __ )A ( 3 29 where ~ is approximately 0.3 for steel, E is approximately 3x107 for steel, and 31 ~A~ ~B and ~C are the conditioned output 32 signals of -t~e 0, 45 and 90 oriented arms of the strain 33 gauge rosette. The values ~ and E given above are also a 34 fairly good approximation for most metals.
Equation (1) can be expressed as follows:
36 'S~ - E (,714(~ ~c)~ JL,38S (~ c)~ 5(2~ C)72) 38 and equation (2) can be similarly expres~ed, but with -the 1 .1 6~3gO
01 second "+" sign replaced by a "-" sign.
02 Analog signal processor 3 thus produces three output 03 signals, respectfully corresponding ~o the maximum principal 04 stress, the minimum principal stress and the maximum shear 05 stress, on an instantaneous real time basis. These signals can 06 be recorded (chart recorder or magnetic tape recorder) or applied 07 to readout devices such as panel meters or the like for use by 08 the operator.
09 The signals are applied to a second signal processor 4. lhis processor has a transfer function which provides 11 output signals determinative of the peak principal stress 12 values, and detects, captures and holds signals represen-ting 13 ~he peak value of the maximum principal stress, the value of the 14 minimum principal stress at the instant o:E the pea~ maximum principal stress, and the peak value of the maximum shear 16 stress. The aforenoted peak value signals are stored, but the 17 second signal processor 4 can be reset to zero whenever desired.
1~ The peak value signals noted above can then be routed 19 to panel meters or, if desired, can be routed via bus 5 to a channel selector 6, with similar buses 5a-5n from other signal 21 processing equipment connected to other strain gauge rosettes.
22 In one useful configuration, for instance, there could be six 23 strain gauge rosettes resulting in six buses connected to 24 channel selector 6. Three digital panel meters 7 can be switched to any one channel to read the three peak value 26 signals described above. The signals ~l,o~2 and ~max 27 could also be connected through a channel selector to a group 28 of panel meters, or, if desired, each could have its own 29 readout display. Further, each bus 5a-5n can be connected to a data logger which records permanently the peak value signals 31 which have been obtained.
32 In Figure 2, showing more detail of the invention, a `33 strain gauge rosette 1 is connected to conditioners 2, as in 34 Figure 1. The outputs o the conditioners are ~ A~ ~B and ~C respectively. Signals ~A and ~C are applied to a 36 circuit which adds them together and multiples the sum by a 37 factor .714, to produce a signal A. Similarly the ~ignals ~A
38 and~ C are applied to a circuit which subtrac-ts the signal ~C
, ~
~ ~ 3 ~ 3gO
01 from ~A and multiplies the difference by a factor .3~5, to 02 produce a signal ~. All three signals ~A~ ~B and ~C are 03 connected to a third circuit 9 which rnultiples the signal ~B
04 by 2 and subtracts the signals ~A and ~C therefrom, 05 multiplying the result by .385, to produce the signal C.
06 The signals B and C are applied individually to full 07 wave rectifiers 10 and 11, to produce the signals lB¦ and tc3 08 respectively. These signals are applied to a circuit 12 which 09 squares each of signals lB~ and lc~, adds the squares together, and takes the square root of the sum, to produce the signal D.
11 The signals A and D are applied to an adding circui-t 12 13, which adds the two signals together to produce the signal 13 ~1~ which is representative of the maximum principal stress.
14 The signals A and D are also applied to a su~tracting circuit 14 which substracts the signal D from the signal A, and 16 produces the resulting signal ~2~ which is representative of 17 the minimum principal stress. The signal D is passed through a 18 buffer 15, which provides at its output a signal ~max which 19 is representative of the maximum shear stress encountered by the strain gauge rosette.
21 The three stress signals thus obtained provide a real 22 time determination of the instantaneous maximum principal 23 stress, minimum principal stress, and maximum shear stressl and 24 can he displayed directly on appropriately calibrated analog or digital panel meters or recorded using a chart recorder or 26 magnetic tape recorder.
27 The signals are also applied to a peak determination 28 and holding circuit as will be described below.
29 The maximum principal stress signal ~1 is applied to an analog peak detector 16. The output of this detector 31 circuit is applied to a digital peak store (memory) 17, which 32 provides an output signal on lead 18 which is representative of 33 the peak principal stress.
34 Similarly, the maximum shear stress signal rmax is applied to an analog peak detector 19, which has its output 36 connected to a digita]. peak store (memory) 20, the ou-tput 37 signal of which, on lead 21, is representative o -the peak 38 value of the maximum shear stress.
:..
f.~ ~3 0 01 The remaining circuitry provides a siynal indica-tive 02 of the minimum principal stress at the instant w~en -the maximum 03 principal stress is peaking.
04 Both the peak maximum principal stress signal on lead 05 18 and the maximum principal stress signal are applied to a 06 logic circui~ 22, with two signals to be described later from 07 the interior and -the output of the analog peak aetector 16.
08 The output of logic circuit 22 is a control signal which is 09 high (or "on") when both the instantaneous maximurn principal stress is greater than the digi~ally stored peak maximum 11 principal stress, and a new analog peak is being detected~
12 The control signal is applied to sample and hold circuit 23 13 with the maximum shear stress signal, the output of which is 14 applied to digital peak store [memory~ 24. The output of logic circuit 22 is also applied to the reset input of digi~.al peak l6 store 24.
~7 The output of digital peak store 24 is connected to 18 the input of a subtrac-ting circuit 25 with the output of 19 digital peak store 17. This circuit multiplies the output of digital peak store 24 by a ~actor of 2, and subtracts the 21 product from the signal at the output of digital peak store 17, ~22 to provide an output signal on lead 26 which is representative 23 of the minimum principal stress at the instant when the maximum -24 principal stress is at its peak.
In operation, it will be noted that the maximum 26 principal stress and maximum shear stress signals are applied 27 to analog pea~ detectors 16 and 19 respectively, which retain 28 signals representative of the peak voltage detected and apply 29 these signals to digital peak stores 17 and 20. The output signals, on leads 18 and 21 respectively, are representative o~
31 the peak value of the maximum principal stress and the peak 32 value of the maximum shear stress undergone ~y the strain gauge 33 rosette.
34 Logic circuit 22 provides an output signal which has either of two states, high or low. When the in~tantaneous 36 maximum principal stress signal is less than its previous peaX, 37 the output o~ logic circuit 22 is low or "oE~. However, when 38 the input si.gnal is of greater amplitude than its previous .~
~ J ~i5~.~30 01 peak, the output goes high, or "on", the signal sampled in 02 sample and hold circuit 23, and digital peak store 24, w~ich is 03 reset to zero. Immediately after the new input sign~l peak has 04 passed, the output of logic circuit 22 goes low, the signal at 05 sample and hold circuit 23 is held, and digital peak store 24 06 digi-tally stores the new signal value. The ou-tput o~ digital 07 peak store 24 is applied to subtractor 25, where the minimum 08 principal stress is derived. The resulting output signal is 09 representative of the minimum principal stress at the instant of peak maximum principal stress.
11 Turning now to Figure 3, the ~irst signal processor 12 portion is shown. The outpu~ signals ~rom the signal 13 conditioners connected to each section o e -the strain gauge 14 rosette, that is, signals~ A~ ~C and ~B are applied to the inputs of operational amplifiers 30, 31 and 32. Signal 16 A is applied to the non-inverting inputs Oe amplifiers 30 17 and 31 through resistors 33 and 34 respectively, and to the 18 inverting input of ampli~ier 32 through resistor 35. Signal 19 C is applied to the non-inverting input of operational amplifier 30 through resistor 3~, to the inverting input Oe 21 amplifier 31 through resistor 37, and to the inverting input of 22 amplifier 32 through resistor 38. Signal input B is applied 23 to the non-inverting input of amplieier 32 through resistor 39, 24 that input also being connected to ground through resistor 40.
The non-inverting input of amplifier 31 is connected to ground 26 through resistor 41, and the inverting input of ampli~ier 30 is 27 connected to ground through resistor 42. A feedback resistor 28 43 connects the output of ampli~ier 30 to its non-inverting 29 input, a resistor 44 connects ~he output of amplifier 31 to its non-inverting input, and the output of amplifier 32 is 31 connected to its non-inverting input through resistor 45.
32 The ou~puts of amplifiers 31 and 32 are connected to 33 similar circuits. The circuit connected to the output of 34 amplifier 31 is comprised of a pair of operational arnplifiers 46 and 47 having their outputs connected together through 36 diodes 48 and 49, the anodes of -the diodes being connec-ted 37 respectively to the outputs of the ampliEiers 46 and 47. Their 38 inverting inpu-ts are connected to their outputs through 39 corresponding diodes 50 and 51, and also to -the junction of the ._ ~ .
;, .5 ~ ~ 0 01 cathodes of diodes 48 and 49 through reslstors 52 and 53. The 02 inverting input of amplifier ~6 is connec-ted to the output of 03 amplifier 31 through resistor 54, and the non inverting inpu-t 04 of amplifier 47 is connected to the output of amplifier 31.
05 The circuit connec-ted to the output of ampli~ier 32 is 06 similar ~o that described above, having similar components 07 labelled with similar numerals suffixed with the letter "A".
08 The cathodes of diodes 48 and 49 are connected to the 09 input of a multifunction converter 55, which has its output terminal connected through resistor 56 to the non-inverting 11 input of operational amplifier 57. Operational amplifier 57 12 has its output connected to its inverting input through 13 resistor 58, the inverting input also being connec-ted to ground 14 through resistor 59. The output of amplifier 57 is connected lS to the non-inverting input of amplifier 60 through resistor 61, 16 which input is also connected to the non-inverting input of 17 amplifier 57 through a pair of resistors 62 and 63. The 18 cathodes of diodes 48A and 49A are connected to the junction of 19 resistors 62 and 63, and the output of amplifier 60 is ~0 connected to the its non-inverting input through resistor 64.
21 The output of amplifier 57 is connected to the 22 non-inverting inputs of operational amplifier 65 and 66 through 23 resistors 67 and 68, and to the inverting input of operational 24 amplifier 69 through resistor 70. The output of operational amplifier 30 is connected to the non-inverting inputs of 26 amplifiers 65 and 69 through resistors 71 and 72 respectively.
27 The inverting inputs of amplifiers 65, 69 and 66 are connected 28 to their respective outputs through resistors 73, 74 and 75.
29 ~nplifier 65 has its inverting input connected to ground through resistor 76.
31 The ratio of the resistors connected to operational 32 amplifier 30 is adjusted so as to provide an amplification of 33 0.714. Since the input signals to amplifier 30 are ~A and
37 The present invention is a circuit which provides, on a 38 real time basis, signals representing the maximum principal -`` 1 3 fi ~ O
01 stress, the minimum principal stress, the maximum shear stress,~2 the peak value of the maximum principal stress, the value of 03 minimum principal stress at the instant w~en the maximum 04 principal stress is peaXing, and the peak value of the maximum 05 shear stress. These signals can be displayed on an 06 alphanumeric display, which allows the operator of the 07 apparatus which is under test to repeat certain tests with 08 similar external factors immediately upon observation o* their 09 effect, or to make note of the external factors giving rise to the stress which would otherwise be missed with the prior art 11 methods of hand and computer calculation a long time after the 12 transient factors have passed.
13 In general, the present invention is apparatus or 14 the determination of stress in a structural member comprising means for receiving input signals from the arms of a 16 rectangular strain gauge rosette attached to the member, a 17 first analog signal processor for providing stress signals 18 representative of the maximum principal stress, minimum 19 principal stress, and maximum shear stress for each instantaneous input signal amplitude continuously upon receipt 21 of the input signals, and a second signal processor for 22 receiving the stress signals and for providing output signals 23 representative of maximum peak principal stress, minimum 24 principal stress at the instant of peak maximum principal stress, and peak maximum shear stress.
26 A number of such circuits can be connec~ed in parallel27 to a channel selector to provide a plurality of input 28 channels. A group of digital panel meters can be switched to 29 receive signals from any of the channels as desired. Of course a printer can also be used to record the output signals o* each 31 of the channels continuously.
32 A better understanding of the invention will be 33 obtained by reference to the detailed description below, in 34 conjunction with the following figures, in which:
`35 Figure 1 is a basic block schematic of the invention, 36 Figure 2 is a detailed block diagram of the invention,37 Figure 3 is a schematic diag~am illustrative oE a 38 first signal processor portion of the invention, and ~ `
5~0 01 Figure 4 is a basic schematic dlagram of the preferred 02 form of the second signal processor por-tion of the invention.
03 Turning to Figure 1, strain gauges disposed in the 04 usual form at 45 to the other, forming a three elemen-t 05 rectangular strain gauge roset-te 1 are connected -to 06 corresponding strain gauge conditioners 2. The strain gauge 07 conditioners are of conventional construction, and provide 08 output signals ~A~ ~BI and ~C which signals are dir ctly 09 related to the amount of strain each corresponding arm of the rosette undergoes. In use the strain gauge rosette i5 a-ttached 11 to a structural member of an apparatus under test.
12 The aforenoted output signals from the strain gauge 13 conditioners are applied to a first analog signal processor 3.
14 This processor contains circuitry which provide output signals ~1 representative of the instantaneous maximum principal 16 stress, ~2 representative of the minimum principal stress, 17 and max~ the maximum shear stress. The analog signal 18 processor translates the output signals from the strain gauge 19 conditioners by circuitry which has the following transfer functions:
22 ~ ~ ~ 2(~_V~ ~ 2(l~V~ J(~ ~2~ (2~g~ 2 ~ C~) 24 ~2- E[ 2-~l-V) ~ ~ V) J~ c) ~ (2 ~8~ c)2 J
227 E - ~ __ )A ( 3 29 where ~ is approximately 0.3 for steel, E is approximately 3x107 for steel, and 31 ~A~ ~B and ~C are the conditioned output 32 signals of -t~e 0, 45 and 90 oriented arms of the strain 33 gauge rosette. The values ~ and E given above are also a 34 fairly good approximation for most metals.
Equation (1) can be expressed as follows:
36 'S~ - E (,714(~ ~c)~ JL,38S (~ c)~ 5(2~ C)72) 38 and equation (2) can be similarly expres~ed, but with -the 1 .1 6~3gO
01 second "+" sign replaced by a "-" sign.
02 Analog signal processor 3 thus produces three output 03 signals, respectfully corresponding ~o the maximum principal 04 stress, the minimum principal stress and the maximum shear 05 stress, on an instantaneous real time basis. These signals can 06 be recorded (chart recorder or magnetic tape recorder) or applied 07 to readout devices such as panel meters or the like for use by 08 the operator.
09 The signals are applied to a second signal processor 4. lhis processor has a transfer function which provides 11 output signals determinative of the peak principal stress 12 values, and detects, captures and holds signals represen-ting 13 ~he peak value of the maximum principal stress, the value of the 14 minimum principal stress at the instant o:E the pea~ maximum principal stress, and the peak value of the maximum shear 16 stress. The aforenoted peak value signals are stored, but the 17 second signal processor 4 can be reset to zero whenever desired.
1~ The peak value signals noted above can then be routed 19 to panel meters or, if desired, can be routed via bus 5 to a channel selector 6, with similar buses 5a-5n from other signal 21 processing equipment connected to other strain gauge rosettes.
22 In one useful configuration, for instance, there could be six 23 strain gauge rosettes resulting in six buses connected to 24 channel selector 6. Three digital panel meters 7 can be switched to any one channel to read the three peak value 26 signals described above. The signals ~l,o~2 and ~max 27 could also be connected through a channel selector to a group 28 of panel meters, or, if desired, each could have its own 29 readout display. Further, each bus 5a-5n can be connected to a data logger which records permanently the peak value signals 31 which have been obtained.
32 In Figure 2, showing more detail of the invention, a `33 strain gauge rosette 1 is connected to conditioners 2, as in 34 Figure 1. The outputs o the conditioners are ~ A~ ~B and ~C respectively. Signals ~A and ~C are applied to a 36 circuit which adds them together and multiples the sum by a 37 factor .714, to produce a signal A. Similarly the ~ignals ~A
38 and~ C are applied to a circuit which subtrac-ts the signal ~C
, ~
~ ~ 3 ~ 3gO
01 from ~A and multiplies the difference by a factor .3~5, to 02 produce a signal ~. All three signals ~A~ ~B and ~C are 03 connected to a third circuit 9 which rnultiples the signal ~B
04 by 2 and subtracts the signals ~A and ~C therefrom, 05 multiplying the result by .385, to produce the signal C.
06 The signals B and C are applied individually to full 07 wave rectifiers 10 and 11, to produce the signals lB¦ and tc3 08 respectively. These signals are applied to a circuit 12 which 09 squares each of signals lB~ and lc~, adds the squares together, and takes the square root of the sum, to produce the signal D.
11 The signals A and D are applied to an adding circui-t 12 13, which adds the two signals together to produce the signal 13 ~1~ which is representative of the maximum principal stress.
14 The signals A and D are also applied to a su~tracting circuit 14 which substracts the signal D from the signal A, and 16 produces the resulting signal ~2~ which is representative of 17 the minimum principal stress. The signal D is passed through a 18 buffer 15, which provides at its output a signal ~max which 19 is representative of the maximum shear stress encountered by the strain gauge rosette.
21 The three stress signals thus obtained provide a real 22 time determination of the instantaneous maximum principal 23 stress, minimum principal stress, and maximum shear stressl and 24 can he displayed directly on appropriately calibrated analog or digital panel meters or recorded using a chart recorder or 26 magnetic tape recorder.
27 The signals are also applied to a peak determination 28 and holding circuit as will be described below.
29 The maximum principal stress signal ~1 is applied to an analog peak detector 16. The output of this detector 31 circuit is applied to a digital peak store (memory) 17, which 32 provides an output signal on lead 18 which is representative of 33 the peak principal stress.
34 Similarly, the maximum shear stress signal rmax is applied to an analog peak detector 19, which has its output 36 connected to a digita]. peak store (memory) 20, the ou-tput 37 signal of which, on lead 21, is representative o -the peak 38 value of the maximum shear stress.
:..
f.~ ~3 0 01 The remaining circuitry provides a siynal indica-tive 02 of the minimum principal stress at the instant w~en -the maximum 03 principal stress is peaking.
04 Both the peak maximum principal stress signal on lead 05 18 and the maximum principal stress signal are applied to a 06 logic circui~ 22, with two signals to be described later from 07 the interior and -the output of the analog peak aetector 16.
08 The output of logic circuit 22 is a control signal which is 09 high (or "on") when both the instantaneous maximurn principal stress is greater than the digi~ally stored peak maximum 11 principal stress, and a new analog peak is being detected~
12 The control signal is applied to sample and hold circuit 23 13 with the maximum shear stress signal, the output of which is 14 applied to digital peak store [memory~ 24. The output of logic circuit 22 is also applied to the reset input of digi~.al peak l6 store 24.
~7 The output of digital peak store 24 is connected to 18 the input of a subtrac-ting circuit 25 with the output of 19 digital peak store 17. This circuit multiplies the output of digital peak store 24 by a ~actor of 2, and subtracts the 21 product from the signal at the output of digital peak store 17, ~22 to provide an output signal on lead 26 which is representative 23 of the minimum principal stress at the instant when the maximum -24 principal stress is at its peak.
In operation, it will be noted that the maximum 26 principal stress and maximum shear stress signals are applied 27 to analog pea~ detectors 16 and 19 respectively, which retain 28 signals representative of the peak voltage detected and apply 29 these signals to digital peak stores 17 and 20. The output signals, on leads 18 and 21 respectively, are representative o~
31 the peak value of the maximum principal stress and the peak 32 value of the maximum shear stress undergone ~y the strain gauge 33 rosette.
34 Logic circuit 22 provides an output signal which has either of two states, high or low. When the in~tantaneous 36 maximum principal stress signal is less than its previous peaX, 37 the output o~ logic circuit 22 is low or "oE~. However, when 38 the input si.gnal is of greater amplitude than its previous .~
~ J ~i5~.~30 01 peak, the output goes high, or "on", the signal sampled in 02 sample and hold circuit 23, and digital peak store 24, w~ich is 03 reset to zero. Immediately after the new input sign~l peak has 04 passed, the output of logic circuit 22 goes low, the signal at 05 sample and hold circuit 23 is held, and digital peak store 24 06 digi-tally stores the new signal value. The ou-tput o~ digital 07 peak store 24 is applied to subtractor 25, where the minimum 08 principal stress is derived. The resulting output signal is 09 representative of the minimum principal stress at the instant of peak maximum principal stress.
11 Turning now to Figure 3, the ~irst signal processor 12 portion is shown. The outpu~ signals ~rom the signal 13 conditioners connected to each section o e -the strain gauge 14 rosette, that is, signals~ A~ ~C and ~B are applied to the inputs of operational amplifiers 30, 31 and 32. Signal 16 A is applied to the non-inverting inputs Oe amplifiers 30 17 and 31 through resistors 33 and 34 respectively, and to the 18 inverting input of ampli~ier 32 through resistor 35. Signal 19 C is applied to the non-inverting input of operational amplifier 30 through resistor 3~, to the inverting input Oe 21 amplifier 31 through resistor 37, and to the inverting input of 22 amplifier 32 through resistor 38. Signal input B is applied 23 to the non-inverting input of amplieier 32 through resistor 39, 24 that input also being connected to ground through resistor 40.
The non-inverting input of amplifier 31 is connected to ground 26 through resistor 41, and the inverting input of ampli~ier 30 is 27 connected to ground through resistor 42. A feedback resistor 28 43 connects the output of ampli~ier 30 to its non-inverting 29 input, a resistor 44 connects ~he output of amplifier 31 to its non-inverting input, and the output of amplifier 32 is 31 connected to its non-inverting input through resistor 45.
32 The ou~puts of amplifiers 31 and 32 are connected to 33 similar circuits. The circuit connected to the output of 34 amplifier 31 is comprised of a pair of operational arnplifiers 46 and 47 having their outputs connected together through 36 diodes 48 and 49, the anodes of -the diodes being connec-ted 37 respectively to the outputs of the ampliEiers 46 and 47. Their 38 inverting inpu-ts are connected to their outputs through 39 corresponding diodes 50 and 51, and also to -the junction of the ._ ~ .
;, .5 ~ ~ 0 01 cathodes of diodes 48 and 49 through reslstors 52 and 53. The 02 inverting input of amplifier ~6 is connec-ted to the output of 03 amplifier 31 through resistor 54, and the non inverting inpu-t 04 of amplifier 47 is connected to the output of amplifier 31.
05 The circuit connec-ted to the output of ampli~ier 32 is 06 similar ~o that described above, having similar components 07 labelled with similar numerals suffixed with the letter "A".
08 The cathodes of diodes 48 and 49 are connected to the 09 input of a multifunction converter 55, which has its output terminal connected through resistor 56 to the non-inverting 11 input of operational amplifier 57. Operational amplifier 57 12 has its output connected to its inverting input through 13 resistor 58, the inverting input also being connec-ted to ground 14 through resistor 59. The output of amplifier 57 is connected lS to the non-inverting input of amplifier 60 through resistor 61, 16 which input is also connected to the non-inverting input of 17 amplifier 57 through a pair of resistors 62 and 63. The 18 cathodes of diodes 48A and 49A are connected to the junction of 19 resistors 62 and 63, and the output of amplifier 60 is ~0 connected to the its non-inverting input through resistor 64.
21 The output of amplifier 57 is connected to the 22 non-inverting inputs of operational amplifier 65 and 66 through 23 resistors 67 and 68, and to the inverting input of operational 24 amplifier 69 through resistor 70. The output of operational amplifier 30 is connected to the non-inverting inputs of 26 amplifiers 65 and 69 through resistors 71 and 72 respectively.
27 The inverting inputs of amplifiers 65, 69 and 66 are connected 28 to their respective outputs through resistors 73, 74 and 75.
29 ~nplifier 65 has its inverting input connected to ground through resistor 76.
31 The ratio of the resistors connected to operational 32 amplifier 30 is adjusted so as to provide an amplification of 33 0.714. Since the input signals to amplifier 30 are ~A and
3~ ~C~ the output signal therefrorn equals 0.71~x(~A~c).
3S T~is ou~put signal, referenced as signal A is applied to the 36 input of operational amplifier 65.
37 The resistors connected to operational amplifier 31 ' ~:
~ .~ &~3~0 01 are adjusted so as -to provide an amplification of 0.385.
02 Signal ~C is applied to the inverting input of operational 03 amplifier 31, and signal ~A is applied to its non-inverting 04 input. Consequen-tly the output signal, reference B, of 05 operational amplifier 31 is equal to .385x(~A-~c).
06 Both signals ~A and ~C are applied to the 07 inverting input of operational amplifier 32, while signal C B
08 is applied to its non-inverting input. 'Fhe resis-tors connected 09 to amplifier 32 should be adjusted so as to provide an amplification of 0.385, but -to provide gain of twice the amount 11 for signal ~B as for signals ~A and ~C For example, if 12 all of the signal-carrying resis-tors 34, 37, 35, 38 and 39 are 13 lOk ohms, a~d resistors 44 and 45 are 3.85k ohms, resistor 41 14 can be 3.85k and resistor 40 can be 7.69k ohms. As a result, the output signal of amplifier 32, reference C, is equal to 16 385X(2~g-~A-~c)-17 The circuits connected to the outputs of amplifiers 31 1~ and 32 to the junctions of diodes ~8 and 49 (and 48A and ~9A) 19 form full wave rectifiers, the output signals being referenced (B) and (C) respectively.
21 As mentioned earlier, circuit 55 is a multifunction 22 converter, typically type LH0094, available from National 23 Semiconductor. That circuit in conjunction with operational 24 amplifiers 57 and 60 with their associated resistors (each of which can be lOk ohms) provides a transfer function as follows:
27 ~ lBI 2.~ ICI 2 28 The output signal of the circuit which provides the aforenoted 29 transfer function is referenced D.
It may be seen that the signal D is applied with 31 signal A so as to add in operational amplifier 65, and in a 32 direction so as to be subtrac-ted frorn signal A in amplifier 33 69. Signal D is also applied to amplifier 66 so as merely to 34 be buffered therethrough.
The output signal of amplifier 65 is ~
36 representative of the maximum principal stress; the output 37 signal of amplifier 69 is ~2 representative oE the minimum 38 _ 9 _ .
';, ' .
13~ 3~
01 principal stress, while the outpu-t signal of buffer ampli~ier 02 66, ~max is representative of the maximum shear stress.
03 These signals can be applied to a display system whereby the 04 maximum and minimum principal stresses and maximum shear stress 05 can be read as they are incurred.
06 The maximum principal stress signal and the maximum 07 shear stress signal are applied to the circuit shown in Figure 08 4~ The maximum principal stress signal is applied -to the 09 non-inverting input of operational amplifier 80 through resistor 81. The output of amplifier 80 is connected to 11 capacitor 82 through diode 83, the junction of diod~ 83 and 12 capacitor 82 being connected back to the inverting input of 13 operational amplifier 80. This junction is also connected to 14 the non-inverting input of amplifier 84, which has its output lS connected to its inverting input. Its non-inverting input is 16 connected to ground, with capacitor 82, through the series 17 circuit of resistor 85 and reset switch 86~
1i~3 The output of amplifier 80 is connected to the lg non-inverting input of comparator 87, through resistor 88, the output of amplifier 84 being connected to its inverting input 21 through resistor 88A. The maximum principal stress signal ~1 22 is also applied to the non-inverting input of comparator 89 23 through resistor 90, its inverting input being connected to a 24 source of the derived peak maximum principal stress signal ~lPK which will be described below. The outputs of 26 comparators 87 and 89 are connected to a source of positive 27 potential V+ through resistors 91 and 92, and to separate 28 inputs of AND gate 93. The output of A~D gate 93 is connected ~9 to one input of OR gate 94, which has its other input connected to an external reset terminal RST. The ou-tput of OR gate 94 is 31 connected to the control input of a sample and hold circuit 95, 32 to which memory capacitor 96 is connected. Sample and hold 33 circuit 95 can he type 398, while comparators 87 and 89 an be 34 type 339.
The maximum shear stress signal % max is applied to 36 the non-inverting input o~ operational amplifier 97 throu~h 37 resistor 98, and to the other si~nal oE sample ancl hold ,~
:
'I ~ S ~ O
01 circuit 95 through resisto~ 99. The output of operational 02 amplifier 97 is connected -through diode 100 to capacitor 101, 03 the junction of diode 100 and capacitor 101 being connected 04 back to the non-inverting input of ampliEier 97. This junction 05 is also connected through the series circuit of resistor 102 06 and reset switch 103 to ground, with capacitor 101. The 07 junction is also connected to the non-inverting input of 08 operational amplifier 104, which has its output connected to 0~ its non-inverting input.
Circuits are connected to the outputs of amplifiers 11 ~4, 95 and 104, which are all of similar construction. Only 12 one will ~e described in detail, connected to amplifier 84, -the 13 circuit reference connected to operational amplifiers 95 and 14 10~ having suffixes "A" and "B" respectively, denoting similar components.
16 The output of ampliier 84 is connected to the 17 non-inverting input of comparator 105, through resistor 106.
18 The output of amplifier 105 is connected through resistor 107 19 to the source of positive potential V+, and also to one input of AND gate 108. The other input of A~D gate 108 is connected 21 to a terminal to which an oscillator signal is to be applied, 22 preferably about 100 kilohertz in frequency.
23 The output of AND gate 108 is connected to the input 24 of a binary counter 109, e.g. type 4040. The parallel outputs of binary counter 109 are connec-ted to digital-to-analog 26 converter 110, e.g. type 1020. The reference voltaye input of 27 digital-to-analog converter 110 was connected in a successful 28 prototype to a voltage source of -10.24 volts, in order that 29 the resolution of the digital peak store should be 10 millivolts. The reset input of binary counter 109 is connected 31 to an external reset terminal.
32 The output signal terminals of digital-to-analog 33 converter 110 are connected to the inputs of an operational 3~ amplifier 111, which has its non-inverting input connected to ground, the output of amplifier 111 being connected to its 36 inverting input through a small capacitor 112.
37 The output of amplifier 111 is a:Lso connected to the 3 ~3 0 01 inverting input of cornparator 105 through resis-tor 113.
02 The output of OR gate 94 is connected to the reset 03 input of binary coun-ter 109A. The outputs of operational 0~ amplifiers 111 and lllA are connected through corresponding 05 resistors 114 and 115 to the non-inver-ting and inverting inputs 06 respectively of operational amplifier 116, the non-inverting 07 input being bypassed to ground through resistor 117, and the 08 inverting input being connected to the output throuyh resistor 09 118. Resistors 114 and 118 can be 20k ohms each, and resistors 115 and 117 can be 10k ohms each. The output of amplifier 111 11 is connected -to the ~lPK input of comparator ~9 through 12 resistor 90A.
13 In operation, the ma~imum principal stress signal is 14 applied on lead 1 to operational amplifier 80, and the peak value is stored as charge in capacitor 82, the peak voltage 16 accumulated being representative of the peak maximum principal 17 stress encountered. Capacitor 82 can be discharged by 18 operating switch 86, which discharges the capacitor through 19 resistor 85. Switch 86 can be an analog switch such as CD4066, 2Q having an exkernal reset, from a main external reset terminal.
21 The peak maximum shear stress signal is also stored in 22 capacitor 101 in a similar manner, which capacitor can be 23 discharged through switch 103.
24 The peak maximum principal stress voltage stored by capacitor 82 is buffered by operational ampliier 84 and is 26 applied through comparator 105 to one input of AND gate 108, a 27 signal received from an oscillator being applied to the second 28 input of AND gate 108.
29 Assuming there has been no prior signal stored on capacitor 82, as capacitor 82 charges, storing a signal which 31 is applied to one input o~ comparator 105~ If the value 32 stored by the binary counter is less than the capacitor signal, 33 the output o comparator 105 will go high and ef~ectively turn 34 on AND gate 108. Consequently with each positive pulse from the oscillator, the value stored by binary counter 109 will be 36 incremented. The output signal is converted to analog in 37 digital-to-analog converter 110 ana appears at the output of 1 1 6 ~ 0 01 amplifier 111. ~his signal can be applied to a digital 02 readout, a data logger, or the like, and is represen-tative of a 03 continuous readout of the peak maximum principal stress so far 04 encountered.
05 However -the peak maximum principal stress signal is 06 also applied ~ack to the inver-ting input of comparator 105.
07 Consequently if the signal applied to its non-inver-ting input 08 is no greater than the digita1ly stored peak maximum principal 09 stress signal applied to its inverting input, the output signal from comparator 105 will stay low. Consequently, the 11 oscillator signal applied to AND gate 108 will be blocked 12 resulting in no increment of binary counter 109.
13 However, as soon as there is a signal applied to the 14 non-inverting input of comparator 105 which is greater -than the previously digitally stored peak maximum principal stress 1~ signal, it exceeds the signal applied to the inverting input, 17 and a high (logical "true") signal is applied to ~D gate 108.
18 Consequently the oscillator pulses pass through ~ND gate 108, 19 the number of puLses being counted in digital peak store 109.
The digital count is converted to analog in digital-to-analog 21 converter 110, and the resulting higher output signal is 22 applied to the inverting input of comparator 105. As soon as ~3 this signal matches or is slightly greater than the signal 24 applied to its non-inverting input, the output pulses from ~D
gate 108 cease, and the increasing count in binary counter 109 26 ceases. Clearly binary counter 109 is usefully embodied as a 27 digital peak store.
28 The circuitry involving amplifiers 97, 104, 105B, AND
29 gate 108B, binary counter lO9B and digital-to-analog converter llOB operate similarly to that noted above. The output signal 31 of amplifier lllB is representative of the peak maximum shear 32 stress.
33 The minimum principal stress at the time of the peak 34 maximum principal stress i5 derived as follows. The peak maximum principal stress signal at the output of operational 36 amplifier 111 is applied to the inverting input of 37 comparator 89. The maximum principal stress signal ~-1 is ~ 3 ~ 380 01 applied to i-ts non inverting input. Consequently only when the 02 maximum principal stress signal exceeds the digitally stored 03 peak maximum stress signal is there a high output from 04 comparator 8g. This output is applied to one input of A~D gate 05 93.
06 Similarly, the output of buffer 84 is connected to the 07 inverting input of comparator 87 and the output of operational 08 amplifier 80 is connected to the non-inverting input of 09 comparator 87. When the maximum principal stress signal at any particular instant exceeds the value as stored in capacitor 82, 11 a positive-going output signal from comparator 87 appears, 12 which is applied to the second input of A~D gate 93. The 13 output of ~ND gate 93 passes through OR gate 94, instructs 14 sample and hold circuit 95 ~o sample the current value of ~max and store it in capacitor 96 and resets binary counter 16 109A.
17 The output signal from sample and hold circuit 95 is 18 applied to comparator 105A in a manner similar to the signal 19 applied to comparator 105. Thus digital peak store 109A is reset at the time that there is a new peak maximum stress 21 signal, and at that instant the amplitude of the maximum 22 principal stress signal which exceeds the preceding peak 23 maximum principal stress signal causes the current ma~imum 24 shear stress signal to be stored by sample and hold circuit 2S 95. Since binary counter 109A has previously been reset, the 26 output of operational ampliier lllA goes to zero, and the 27 output level from sample and hold circuit 95 causes comparator 28 10SA output to go high and allow AND gate 108A to pass a series 29 of pulses generated by the oscillator. As binary counter 109A
counts the pulses, the output of digital -to analog converter 31 110A rises, causing an output signal from operational amplifier 32 lllA to increase the ~oltage appl.ied to the inverting input of 33 comparator 105A. When this voltage rises to equal to that 3~ which is applied to the non-inverting input of diEferential amplii~r 105A, its output signal goes to zero inhibiting the 36 passage of oscillator pulses through AND gate 10~A. ~hus no 37 further pulses may be counted by binary counter 109A.
.
~ 1 ~5~0 01 The output signal frorn operational ampli-fier lllA is 02 multiplied by two and subtracted from -the signal at the ou~put 03 of operational amplifier 111 in operational amplifier 116, to 04 provide at its output a signal which is -the minimum principal 05 stress signal at the instant of the peak maximum principal 06 stress. This signal, as well as -the other two derived siynals, 07 the peak maximum stress signal at the output of amplifier 111 08 and the peak maximum shear stress signal at the output of 09 amplifier lllB can be applied to separate digital panel meters, recorded by a data logger, etc.
11 While the above has described a single channel, a 12 plurality of parallel channels may be used, the outputs from 13 the last-noted amplifiers being selectable and connectable to 14 individual digital panel meters by switches.
In a multichannel system, a sine wave oscillator clock lG connected to the AND gates is preferred, in order to reduce 17 spurious noise in the analog circuitry. However in a single 18 channel system a CMOS square wave oscillator ~e.g. type CD4047) 19 is preferred.
The above-described invention has been found to be an 21 extremely useful tool for the structural analyst, since real 22 time determination of the stress actors has not been 23 previously available to him. As a result, significant 24 increase in accuracy of design and saving of time with attendant cost reduction in the design of such structures as 26 military vehicles can now be realized.
27 A person skilled in the art understanding this 28 invention may now conceive o variations or other 29 embodiments thereof. All are considsred to be within the sphere and scope of the present invention as defined in the 31 claims appended hereto.
3S T~is ou~put signal, referenced as signal A is applied to the 36 input of operational amplifier 65.
37 The resistors connected to operational amplifier 31 ' ~:
~ .~ &~3~0 01 are adjusted so as -to provide an amplification of 0.385.
02 Signal ~C is applied to the inverting input of operational 03 amplifier 31, and signal ~A is applied to its non-inverting 04 input. Consequen-tly the output signal, reference B, of 05 operational amplifier 31 is equal to .385x(~A-~c).
06 Both signals ~A and ~C are applied to the 07 inverting input of operational amplifier 32, while signal C B
08 is applied to its non-inverting input. 'Fhe resis-tors connected 09 to amplifier 32 should be adjusted so as to provide an amplification of 0.385, but -to provide gain of twice the amount 11 for signal ~B as for signals ~A and ~C For example, if 12 all of the signal-carrying resis-tors 34, 37, 35, 38 and 39 are 13 lOk ohms, a~d resistors 44 and 45 are 3.85k ohms, resistor 41 14 can be 3.85k and resistor 40 can be 7.69k ohms. As a result, the output signal of amplifier 32, reference C, is equal to 16 385X(2~g-~A-~c)-17 The circuits connected to the outputs of amplifiers 31 1~ and 32 to the junctions of diodes ~8 and 49 (and 48A and ~9A) 19 form full wave rectifiers, the output signals being referenced (B) and (C) respectively.
21 As mentioned earlier, circuit 55 is a multifunction 22 converter, typically type LH0094, available from National 23 Semiconductor. That circuit in conjunction with operational 24 amplifiers 57 and 60 with their associated resistors (each of which can be lOk ohms) provides a transfer function as follows:
27 ~ lBI 2.~ ICI 2 28 The output signal of the circuit which provides the aforenoted 29 transfer function is referenced D.
It may be seen that the signal D is applied with 31 signal A so as to add in operational amplifier 65, and in a 32 direction so as to be subtrac-ted frorn signal A in amplifier 33 69. Signal D is also applied to amplifier 66 so as merely to 34 be buffered therethrough.
The output signal of amplifier 65 is ~
36 representative of the maximum principal stress; the output 37 signal of amplifier 69 is ~2 representative oE the minimum 38 _ 9 _ .
';, ' .
13~ 3~
01 principal stress, while the outpu-t signal of buffer ampli~ier 02 66, ~max is representative of the maximum shear stress.
03 These signals can be applied to a display system whereby the 04 maximum and minimum principal stresses and maximum shear stress 05 can be read as they are incurred.
06 The maximum principal stress signal and the maximum 07 shear stress signal are applied to the circuit shown in Figure 08 4~ The maximum principal stress signal is applied -to the 09 non-inverting input of operational amplifier 80 through resistor 81. The output of amplifier 80 is connected to 11 capacitor 82 through diode 83, the junction of diod~ 83 and 12 capacitor 82 being connected back to the inverting input of 13 operational amplifier 80. This junction is also connected to 14 the non-inverting input of amplifier 84, which has its output lS connected to its inverting input. Its non-inverting input is 16 connected to ground, with capacitor 82, through the series 17 circuit of resistor 85 and reset switch 86~
1i~3 The output of amplifier 80 is connected to the lg non-inverting input of comparator 87, through resistor 88, the output of amplifier 84 being connected to its inverting input 21 through resistor 88A. The maximum principal stress signal ~1 22 is also applied to the non-inverting input of comparator 89 23 through resistor 90, its inverting input being connected to a 24 source of the derived peak maximum principal stress signal ~lPK which will be described below. The outputs of 26 comparators 87 and 89 are connected to a source of positive 27 potential V+ through resistors 91 and 92, and to separate 28 inputs of AND gate 93. The output of A~D gate 93 is connected ~9 to one input of OR gate 94, which has its other input connected to an external reset terminal RST. The ou-tput of OR gate 94 is 31 connected to the control input of a sample and hold circuit 95, 32 to which memory capacitor 96 is connected. Sample and hold 33 circuit 95 can he type 398, while comparators 87 and 89 an be 34 type 339.
The maximum shear stress signal % max is applied to 36 the non-inverting input o~ operational amplifier 97 throu~h 37 resistor 98, and to the other si~nal oE sample ancl hold ,~
:
'I ~ S ~ O
01 circuit 95 through resisto~ 99. The output of operational 02 amplifier 97 is connected -through diode 100 to capacitor 101, 03 the junction of diode 100 and capacitor 101 being connected 04 back to the non-inverting input of ampliEier 97. This junction 05 is also connected through the series circuit of resistor 102 06 and reset switch 103 to ground, with capacitor 101. The 07 junction is also connected to the non-inverting input of 08 operational amplifier 104, which has its output connected to 0~ its non-inverting input.
Circuits are connected to the outputs of amplifiers 11 ~4, 95 and 104, which are all of similar construction. Only 12 one will ~e described in detail, connected to amplifier 84, -the 13 circuit reference connected to operational amplifiers 95 and 14 10~ having suffixes "A" and "B" respectively, denoting similar components.
16 The output of ampliier 84 is connected to the 17 non-inverting input of comparator 105, through resistor 106.
18 The output of amplifier 105 is connected through resistor 107 19 to the source of positive potential V+, and also to one input of AND gate 108. The other input of A~D gate 108 is connected 21 to a terminal to which an oscillator signal is to be applied, 22 preferably about 100 kilohertz in frequency.
23 The output of AND gate 108 is connected to the input 24 of a binary counter 109, e.g. type 4040. The parallel outputs of binary counter 109 are connec-ted to digital-to-analog 26 converter 110, e.g. type 1020. The reference voltaye input of 27 digital-to-analog converter 110 was connected in a successful 28 prototype to a voltage source of -10.24 volts, in order that 29 the resolution of the digital peak store should be 10 millivolts. The reset input of binary counter 109 is connected 31 to an external reset terminal.
32 The output signal terminals of digital-to-analog 33 converter 110 are connected to the inputs of an operational 3~ amplifier 111, which has its non-inverting input connected to ground, the output of amplifier 111 being connected to its 36 inverting input through a small capacitor 112.
37 The output of amplifier 111 is a:Lso connected to the 3 ~3 0 01 inverting input of cornparator 105 through resis-tor 113.
02 The output of OR gate 94 is connected to the reset 03 input of binary coun-ter 109A. The outputs of operational 0~ amplifiers 111 and lllA are connected through corresponding 05 resistors 114 and 115 to the non-inver-ting and inverting inputs 06 respectively of operational amplifier 116, the non-inverting 07 input being bypassed to ground through resistor 117, and the 08 inverting input being connected to the output throuyh resistor 09 118. Resistors 114 and 118 can be 20k ohms each, and resistors 115 and 117 can be 10k ohms each. The output of amplifier 111 11 is connected -to the ~lPK input of comparator ~9 through 12 resistor 90A.
13 In operation, the ma~imum principal stress signal is 14 applied on lead 1 to operational amplifier 80, and the peak value is stored as charge in capacitor 82, the peak voltage 16 accumulated being representative of the peak maximum principal 17 stress encountered. Capacitor 82 can be discharged by 18 operating switch 86, which discharges the capacitor through 19 resistor 85. Switch 86 can be an analog switch such as CD4066, 2Q having an exkernal reset, from a main external reset terminal.
21 The peak maximum shear stress signal is also stored in 22 capacitor 101 in a similar manner, which capacitor can be 23 discharged through switch 103.
24 The peak maximum principal stress voltage stored by capacitor 82 is buffered by operational ampliier 84 and is 26 applied through comparator 105 to one input of AND gate 108, a 27 signal received from an oscillator being applied to the second 28 input of AND gate 108.
29 Assuming there has been no prior signal stored on capacitor 82, as capacitor 82 charges, storing a signal which 31 is applied to one input o~ comparator 105~ If the value 32 stored by the binary counter is less than the capacitor signal, 33 the output o comparator 105 will go high and ef~ectively turn 34 on AND gate 108. Consequently with each positive pulse from the oscillator, the value stored by binary counter 109 will be 36 incremented. The output signal is converted to analog in 37 digital-to-analog converter 110 ana appears at the output of 1 1 6 ~ 0 01 amplifier 111. ~his signal can be applied to a digital 02 readout, a data logger, or the like, and is represen-tative of a 03 continuous readout of the peak maximum principal stress so far 04 encountered.
05 However -the peak maximum principal stress signal is 06 also applied ~ack to the inver-ting input of comparator 105.
07 Consequently if the signal applied to its non-inver-ting input 08 is no greater than the digita1ly stored peak maximum principal 09 stress signal applied to its inverting input, the output signal from comparator 105 will stay low. Consequently, the 11 oscillator signal applied to AND gate 108 will be blocked 12 resulting in no increment of binary counter 109.
13 However, as soon as there is a signal applied to the 14 non-inverting input of comparator 105 which is greater -than the previously digitally stored peak maximum principal stress 1~ signal, it exceeds the signal applied to the inverting input, 17 and a high (logical "true") signal is applied to ~D gate 108.
18 Consequently the oscillator pulses pass through ~ND gate 108, 19 the number of puLses being counted in digital peak store 109.
The digital count is converted to analog in digital-to-analog 21 converter 110, and the resulting higher output signal is 22 applied to the inverting input of comparator 105. As soon as ~3 this signal matches or is slightly greater than the signal 24 applied to its non-inverting input, the output pulses from ~D
gate 108 cease, and the increasing count in binary counter 109 26 ceases. Clearly binary counter 109 is usefully embodied as a 27 digital peak store.
28 The circuitry involving amplifiers 97, 104, 105B, AND
29 gate 108B, binary counter lO9B and digital-to-analog converter llOB operate similarly to that noted above. The output signal 31 of amplifier lllB is representative of the peak maximum shear 32 stress.
33 The minimum principal stress at the time of the peak 34 maximum principal stress i5 derived as follows. The peak maximum principal stress signal at the output of operational 36 amplifier 111 is applied to the inverting input of 37 comparator 89. The maximum principal stress signal ~-1 is ~ 3 ~ 380 01 applied to i-ts non inverting input. Consequently only when the 02 maximum principal stress signal exceeds the digitally stored 03 peak maximum stress signal is there a high output from 04 comparator 8g. This output is applied to one input of A~D gate 05 93.
06 Similarly, the output of buffer 84 is connected to the 07 inverting input of comparator 87 and the output of operational 08 amplifier 80 is connected to the non-inverting input of 09 comparator 87. When the maximum principal stress signal at any particular instant exceeds the value as stored in capacitor 82, 11 a positive-going output signal from comparator 87 appears, 12 which is applied to the second input of A~D gate 93. The 13 output of ~ND gate 93 passes through OR gate 94, instructs 14 sample and hold circuit 95 ~o sample the current value of ~max and store it in capacitor 96 and resets binary counter 16 109A.
17 The output signal from sample and hold circuit 95 is 18 applied to comparator 105A in a manner similar to the signal 19 applied to comparator 105. Thus digital peak store 109A is reset at the time that there is a new peak maximum stress 21 signal, and at that instant the amplitude of the maximum 22 principal stress signal which exceeds the preceding peak 23 maximum principal stress signal causes the current ma~imum 24 shear stress signal to be stored by sample and hold circuit 2S 95. Since binary counter 109A has previously been reset, the 26 output of operational ampliier lllA goes to zero, and the 27 output level from sample and hold circuit 95 causes comparator 28 10SA output to go high and allow AND gate 108A to pass a series 29 of pulses generated by the oscillator. As binary counter 109A
counts the pulses, the output of digital -to analog converter 31 110A rises, causing an output signal from operational amplifier 32 lllA to increase the ~oltage appl.ied to the inverting input of 33 comparator 105A. When this voltage rises to equal to that 3~ which is applied to the non-inverting input of diEferential amplii~r 105A, its output signal goes to zero inhibiting the 36 passage of oscillator pulses through AND gate 10~A. ~hus no 37 further pulses may be counted by binary counter 109A.
.
~ 1 ~5~0 01 The output signal frorn operational ampli-fier lllA is 02 multiplied by two and subtracted from -the signal at the ou~put 03 of operational amplifier 111 in operational amplifier 116, to 04 provide at its output a signal which is -the minimum principal 05 stress signal at the instant of the peak maximum principal 06 stress. This signal, as well as -the other two derived siynals, 07 the peak maximum stress signal at the output of amplifier 111 08 and the peak maximum shear stress signal at the output of 09 amplifier lllB can be applied to separate digital panel meters, recorded by a data logger, etc.
11 While the above has described a single channel, a 12 plurality of parallel channels may be used, the outputs from 13 the last-noted amplifiers being selectable and connectable to 14 individual digital panel meters by switches.
In a multichannel system, a sine wave oscillator clock lG connected to the AND gates is preferred, in order to reduce 17 spurious noise in the analog circuitry. However in a single 18 channel system a CMOS square wave oscillator ~e.g. type CD4047) 19 is preferred.
The above-described invention has been found to be an 21 extremely useful tool for the structural analyst, since real 22 time determination of the stress actors has not been 23 previously available to him. As a result, significant 24 increase in accuracy of design and saving of time with attendant cost reduction in the design of such structures as 26 military vehicles can now be realized.
27 A person skilled in the art understanding this 28 invention may now conceive o variations or other 29 embodiments thereof. All are considsred to be within the sphere and scope of the present invention as defined in the 31 claims appended hereto.
Claims (6)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. Apparatus for the determination of stress in a structural member comprising:
(a) means for receiving continuous input signals from the arms of a rectangular strain gauge rosette attached to said member, (b) first analog signal processor means for continuously providing stress signals representative of the maximum principal stress, minimum principal stress and maximum shear stress for each instantaneous input signal upon receipt of said input signals, (c) second signal processor means for receiving said stress signals and for providing and storing output signals representative of the peak detected level of maximum principal stress, minimum principal stress at the instant of peak maximum principal stress, and the peak detected level of maximum shear stress.
(a) means for receiving continuous input signals from the arms of a rectangular strain gauge rosette attached to said member, (b) first analog signal processor means for continuously providing stress signals representative of the maximum principal stress, minimum principal stress and maximum shear stress for each instantaneous input signal upon receipt of said input signals, (c) second signal processor means for receiving said stress signals and for providing and storing output signals representative of the peak detected level of maximum principal stress, minimum principal stress at the instant of peak maximum principal stress, and the peak detected level of maximum shear stress.
2. Apparatus as defined in claim 1, in which the second processor means is comprised of first and second peak detectors for receiving said maximum principal stress and maximum shear stress signals respectively, and for providing an output signal representative of peak maximum principal stress and an output signal representative of peak maximum shear stress, respectively, a first memory for receiving and storing said peak maximum principal stress output signal, a second memory for receiving and storing said peak maximum shear stress output signal, a logic circuit for receiving said maximum principal stress and peak maximum principal stress signals and for providing an output control signal for controlling the acquisition of the maximum shear stress signal at the time of occurrence of a new peak maximum principal stress, a sample and hold circuit for receiving and storing said maximum shear stress signal and said control signal, third memory means for receiving an output signal from the logic circuit at a reset input and for storing an output signal from the sample and hold circuit following resetting thereof, and subtracting means for receiving the output signal of the first and third memory and for subtracting a multiple of the output signal of the third memory to provide a signal representative of the minimum principal stress at the instant that the maximum principal stress is peaking.
3. Apparatus as defined in claim 1, in which said input signals include one from each of three arms of said rosette located at successive 45° angles relative to a given principal axis, and in which the first analog signal processor means includes circuit means having three simultaneous analog transfer functions:
?1= (1) ?2= (2) ?MAX= (3) where .epsilon.A is an input signal from a first strain gauge rosette arm located along the principal axis of an apparatus to be measured, .epsilon.B is an input signal from a second strain gauge rosette arm located at a 45° angle to the first arm, .epsilon.C is an input signal from a third strain gauge rosette arm located at a 90° angle to the first arm, ?1 is one output signal from the apparatus representative of maximum principal stress detected by the rosette, ?2 is a second output signal from the apparatus representative of minimum principal stress detected by the rosette, ?max is a third output signal from the apparatus representative of maximum shear stress, ? is a constant, approximately 0.3, and E is a constant, approximately 3x107.
?1= (1) ?2= (2) ?MAX= (3) where .epsilon.A is an input signal from a first strain gauge rosette arm located along the principal axis of an apparatus to be measured, .epsilon.B is an input signal from a second strain gauge rosette arm located at a 45° angle to the first arm, .epsilon.C is an input signal from a third strain gauge rosette arm located at a 90° angle to the first arm, ?1 is one output signal from the apparatus representative of maximum principal stress detected by the rosette, ?2 is a second output signal from the apparatus representative of minimum principal stress detected by the rosette, ?max is a third output signal from the apparatus representative of maximum shear stress, ? is a constant, approximately 0.3, and E is a constant, approximately 3x107.
4. Apparatus as defined in claim 3, in which the second processor means is comprised of:
(a) first means for storing the peak voltage amplitude of a maximum stress signal, (b) a comparator for receiving the peak voltage amplitude at one of its inputs, (c) an AND gate for receiving the output signal of comparator at one of its inputs, and for receiving a clock signal at a second one of its inputs, (d) a counter having its input connected to the output of the AND gate, (e) a digital-to-analog converter connected to-the outputs of the counter, for providing a first continuous output signal representative of said peak stress detected by the rosette, and (f) means for applying said first output signal to the second input of the comparator whereby clock pulses are passed through the AND gate which are counted by the counter when the peak voltage amplitude signal applied to the comparator exceeds the first output signal also applied thereto.
(a) first means for storing the peak voltage amplitude of a maximum stress signal, (b) a comparator for receiving the peak voltage amplitude at one of its inputs, (c) an AND gate for receiving the output signal of comparator at one of its inputs, and for receiving a clock signal at a second one of its inputs, (d) a counter having its input connected to the output of the AND gate, (e) a digital-to-analog converter connected to-the outputs of the counter, for providing a first continuous output signal representative of said peak stress detected by the rosette, and (f) means for applying said first output signal to the second input of the comparator whereby clock pulses are passed through the AND gate which are counted by the counter when the peak voltage amplitude signal applied to the comparator exceeds the first output signal also applied thereto.
5. Apparatus as defined in claim 4 further including a second comparator, means for providing a signal representative of the difference between the peak voltage amplitude and the maximum stress signal to the second comparator with polarity such as to cause a predetermined polarity output signal to be generated when the maximum stress signal exceeds the previous stored peak maximum stress signal, a third comparator, means for applying the maximum stress signal to one of its inputs and the first output signal to the second of its inputs, means for applying the output of the third comparator with similar signal polarity as the second comparator to corresponding inputs of a second AND gate, means for applying the output of the second AND gate and the maximum shear stress signal to a sample and hold circuit, means for applying the output of the sample and hold circuit to one input of a fourth comparator, means for applying an output signal of the fourth comparator to one input of a third AND gate, means for applying said clock pulses to the second input of the third AND gate, a second counter having its input connected to the output of the second AND gate, a second digital to analog converter connected to the output of the second counter, for providing a counter output signal, means for applying the counter output signal to the second input of the fourth comparator, and means for doubling and subtracting the doubled second counter output signal from the first counter output signal to provide a second continuous output signal representative of the minimum principal stress at the instant of peak maximum principal stress.
6. Apparatus as defined in claim 3, 4 or 5 in which the first processor includes first operational amplifier means for receiving and for adding the signals .epsilon.A and .epsilon.C to provide an output signal A, second operational amplifier means for receiving and subtracting the signal .epsilon.C from the signal .epsilon.A to provide an output signal B, third operational amplifier means for receiving the signal .epsilon.B, for multiplying signal .epsilon.B by 2, and for receiving the signals .epsilon.A and .epsilon.C and for subtracting them from the multiplied signal .epsilon.B to provide a signal C, means for full wave rectifying the signals B and C to provide signals [B]
and [C[ respectively, converter means for receiving the signals [B] and [C] and for generating a voltage D formed of the square root of the sum of the squares of the signals [B] and [C], fourth operational amplifier means for adding the signals A and D to provide said signal ?1 representative of the maximum principal stress, fifth operational amplifier means for subtracting the signal D from the signal A to provide said signal ?2 representative of the minimum principal stress, and means for providing signal D as signal ?max representative of the maximum shear stress.
and [C[ respectively, converter means for receiving the signals [B] and [C] and for generating a voltage D formed of the square root of the sum of the squares of the signals [B] and [C], fourth operational amplifier means for adding the signals A and D to provide said signal ?1 representative of the maximum principal stress, fifth operational amplifier means for subtracting the signal D from the signal A to provide said signal ?2 representative of the minimum principal stress, and means for providing signal D as signal ?max representative of the maximum shear stress.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000397147A CA1165880A (en) | 1982-02-26 | 1982-02-26 | Peak dynamic stress calculator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000397147A CA1165880A (en) | 1982-02-26 | 1982-02-26 | Peak dynamic stress calculator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1165880A true CA1165880A (en) | 1984-04-17 |
Family
ID=4122173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000397147A Expired CA1165880A (en) | 1982-02-26 | 1982-02-26 | Peak dynamic stress calculator |
Country Status (1)
| Country | Link |
|---|---|
| CA (1) | CA1165880A (en) |
-
1982
- 1982-02-26 CA CA000397147A patent/CA1165880A/en not_active Expired
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