CA1164968A - Multi-source/receiver data processing system comprising a communication bus - Google Patents

Abstract

PHN. 9736 49 ABSTRACT:
A multi-source/receiver data processing system comprising a communication bus which consists of at least one transfer medium. Clock signal generators have diffe-rent tolerances with respect to each other. In order to prevent sources and/or receivers having a slow clock sig-nal generator from being excluded as rightful participants from an action concerning a communication, there are pro-vided means whereby it can be determined whether said bus is "ready" for executing said action. The means comprise first and second detecting means whereby it can be deter-mined that the communication bus is "ready" during a first and a second period of time, respectively. When an active participant determines that this second period of time has expired, the bus is indeed ready for this active partici-pant and all further active participant which have mean-while determined during their first period of time that the bus is ready, so the bus can be occupied by this action.
A data source and/or data receiver may be a programmed digital signal processor.

Description

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PI~ 9736 1 17.3.81 Multi-source/receiver clata processing system comprising a communication bus.

The invention relates to a multi-source/re-ceiver system in which the data source (sources)and data receiver (receivers) are connected to a communication bus which consists o~ at least one transfer medium which i5 suitable for the transport of at least logic level (O or 1~.
Systems of this kind are known, notably systems in which the data qources and receivers consi~t at least partly o~ signal pro¢essor units such as microprocessors etc. Due to the increasing availability of` micro-electro-nics in the ~orm of increasingly ~urther integrated elec-tronic functions on so-called chips9 the time has come f`or the application o~ micro-electronics in ~ields where costs have to be minimized; ~or example~ in consumer pro-ducts such as video equipment, audio equipment 9 etc. When co-operation between different apparatus in a network (~or example, video or audio network o~ equipment) is desirable or required, communication between the various parts will be necossary. Given apparatus or parts there-oP will then act as a data source or a data receiver or 2D may even combine both ~unctions. In a system cornprising a number o~ data sources and receivers it is known to use aso-called communication bus ~or the mutual communication;
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~or example, see the article by Casaglia in Euromicro Newsletter5 October 1976~ Volume 2, No. ~, page 5 and f~r-t~er. Thus f`ar~ these communication buses had ample capa-:
;~ ~city, whIch means that they included a number o~ lines which pro~ide smooth execution o~ the communication. Sys-bems comprising 4-line and 8-line buses etc. are univer-sally known. The most direct approach to the problem of`
an asynchronous communication between sources and recei-vers requires f`our lines: at least one data line and three handsha~e lines~ ~ccordin~ to this solution (f`or ~ .
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s ~ a PHN 9736 2 17.3.81 example, see Fall Joint Comp. Conf~ 1972, pages 719 _ 740) communication is possible between the modules without it being necessary for the modules to kno ~ each other's processing speed. However, a communication bus of this kind is too complex and often too expensive for use as a bus in the fields where the costs have to be minimi~ed.
Solutions have been pursued where the communication bus and hence the communication to be executed thereby is as simple and inexpensive as possible. Notably a bus com-prising a minimum number of transfer lines wo~lld q~alify in this respect. Minimum means at least one transfer me-dium which is suitable for the transport of at least one logic level (O or 1), In practice this may be a coaxial cable, a twisted core pair or also a wireless connection, or an optical fibre connection. In the latter examples, for example, there may be a connection by way of a car-rier wave modulated with at least the logic level O or 1, or an infrared beam or light beam. A known example of a m~ti-source/receiver data processing system of the described ~ind is published in the conference papers known as EUROMICRO 1976: ~O Sommer, "Cobus, a firmware controlled data transmission system", pages 299 - 3O3.
'tCobus stands for coaxial bus and communication is realiz ed thereby be-tween a number of stations comprising micro-processors, However, this system does no-t satisfy the re-quirements as regards low cost: the requirements as re-gards timing in the various processors are rather severe.
For smooth execution o~ the communication, the partici-pating processors must know the bit periods of the other processors, This means that each processor must comprise an expensive crystal oscillator 9 or that the system must comprise a central clock means7 or that a timing network has to be trimmed after assembly, which is also expensive and notabl~ unreliable.
Such an inexpensive and reliable solu-tion also implies a simple solution, because once a system of this kind is in operation (for example, at a consumer), spe-::

P~ 9736 ~ 17.3.81 cial trimming and other adaptatlon steps may no longer be necessary. This is even more applicable when the addition of new da-ta sources and/or data receivers at a later stage is a feature of -the system. The invention has for i-ts object to provide a solution which satisfies -the described requirements as regards low cost, reliability, simplicity and possibili-ty of future extension. To this end, the multi-source/receiver data processing system of the described type is characterized in that:
- the system comprises a plurali-ty of clock signal genera-tors having different tolerances, and - in the source (sources) and/or the receiver (receivers) there are provided means whereby it can be determined for all sources and/or receivers which actively participate in an action concerning a communication (active partici-pants) whether said bus is ready for execu-ting said ac-tion, said means comprising - first and second detecting means whereby it can be de-termined that during a first and a second period of time, respectively, (for example, TAi and TBi), the communica-tion bus is ready for the relevant action, the first period of time being smaller than the second period of time (for example~ TAi ~ TBi)7 the first period of time being determined by a preparation time factor (for exam-ple9 a~i) of the relevant active participant, the secondperiod of time being related to the largest product (R.V) of the set of products (Ri.Vi) of all potential active participants, the products (Ri.Vi) being formed per ac~
tive participant by a tolerance ~actor (Ri) of the oloc~
signal generator for the active participant and a response time factor (Vi) of this active participant, - when an active participant detects that the second period of time (TBi) as expired9 the bus is (indeed) rea-dy for executing the relevant action and can thus be occu-pied by this action for this active participant and allfurther active participants which have meanwhile detected, at least during their relevant first period of time, that ~, .

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P~ 9736 4 17.3.81 the bus is ready.
The invention allows ample tolerance differe~-ces of the clock signal generators present in the system.
These tolerances are taken into account- as the toleran-ces are larger, the second period of time will be longerdue to the dependency of the tolerance factor (R). This means a reduced communication speedD but it does not af-fect the requirements imposed. It is to be noted that in these systems9 such as notably a consumer system9 the fac-tor speed is not so important as in more professional systems in which the use of communication buses compris-ing a number of lines (for example, 4 or 8, etc.) is not prohibitive per definition.
In a multi-source/receiver data processing sys-tem two kinds of sources and/or receivers may in princi-ple be included: active and passive units; this means:- aotive units whi.ch can independently participate active-ly in an action concerning a communicationO Hereinafter9 uni-ts of this category are also referred to as "modules'!.
~ source or receiver can thus hecome the master of the ; system. In addition, these active sources and or recei-vers may remain passive by choice or may ~ave to remain passive due to a higher priority of another active source or receiver. In the latter cases these sourc~sand/or re-ceivers may act as slaves in the system.
~; - passive units which cannot independently take an ini-tiative in order to obtain a communication connection. A
source and~or receiver of this kind~ therefore7 can only act as a slave in the system.
When (like in the foregoing and hereinafter) ; reference is made to "activo participants~ the active data source ~sources) and/or receiver (receivers) are meant which indeed participate in an action concerning a communication at a given instant~ (So this need not be the total number of active data sources and receivers present~ because there is not always a situation where the total number wishes to participate)~ It is to be noted , , .

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Pl~ 9736 5 17.3.81 again tha-t, obviously, a data source may also be a data receiver and vice versa. The invention is based on the re-cognition of the fact tha-t all active par-ticipants must have the opportunity of actually participa-ting in an ac-tion concerning a communication. The differant clock to-lerances may not be the cause that active participants having a clock which is -too slow cannot participate (be-cause they do not react quickly enough to participate in such an action). In order to achieve this object9 a so-called "induc-tion mechanism" is introduced by the intro-duction of said first and second period of time (for exarn-ple, TAi and TBi) which ensures that all activ~ partici-pants can indeed participate. This can ~e illustrated as ~ollows: assume that several modules wish to use the bus.
To this end, they must wait until the bus has been "ready"
for a suf~iciently long period of time. ~lso assume that the local clock signal generator of a ~irst module is fas-ter than that of a second module. The first module can -thus know that the bus is free, which means ready for use, sooner (after TBi) than the second module. The ~irst mo-dule then starts using the bus ("occupies" the bus)~ The induction mechanism ensures that the second module (which has meanwhile detected the instant TA2), a~ter having de-tected that another module (the ~irst module) has started using the bus, also starts to use the bus in reactionthereto.
The ter~ response time of a data source and da-ta receiver relates to the time required by such a modula in order to react to a data bit~ Normally speaking, the 3~ response time is a product of a factor Vi ~- 1 and the cloc~ signal period duration for such a module (Mi)o The term "action concerning a communication"
has already been used several -times in the ~oregoingOi ~
communication consists of a number o~ actions to be e~e-Cuted-- t~e issuing o~ ra~uests ("start") by several active participants ~or establishing a communication connection ~ ~ .

a P~ 973~ 6 17.3.81 - the execu-tion of a selection procedure from several active participants requesting a communication connection (master selection) on the basis of priority and/or address data - establishment by the master of the connec-tion with the source or receiver which serves as a slave in this commu-nication (so-called "open-slave" phase).
- the data transfer itself.
The described induction mechanism in accordance with the invention is important notably for the first two ac$ionso it should be possible for more than one active participants to participate in spite of the clock tole-rances. For the las-t two actions, this is no longer ur-gent 7 because the direct connection is concerned between a master and a slave which is addressed and which enters into a data transfer with the master. Because the master knows which unit is the slave, it is feasible that the master also knows the response time of the slave and takes into account this time for the data transfer. In practice it will be possible to adapt the data transfer speed to the relevant situation between master and slave: higher speeds can then be realized. It is not necessary to take into account data sources and or receivers which react more slowly.
In order to enable the "induction" notably for the first action9 the multi-source/receiver data proces-sing system in accordance with the invention is charac-terized in that said means are adapted to de-termine that the communication bus is ready for executing an ac-tion concerning the issuing of requests (start) by several ac-tive participants for realizing a communica-tion connec-tion. In order to enable the induction notably for said second aotion, the multi-source/receiver data processing system is characterized in that said means are adapted to determine that the communication bus is "ready" for e~ecuting an action concerning the execution, on the ba-sts of prlority and/or identity data, of a selection pro-' :.

9 ~ ~3 Pl~ 9736 7 17.3.81 cedure from several data sourc~ and/or receivers (activeparticipants) re~uesting a communication connection.
In order to obtain ~ast and unambiguous deci-sions on the communication bus when several active parti-cipants present -their data to the bus, a ~ur-ther embodi-ment o~ the multi-source/receiver data processing system is characterized in that the communication bus consisting o~ at least one trans~er medium comprises a wired logic gate ~unction ("wired AND" or "Wired OR") per connec-tion o~ an active participant.
Especially important are solutions where the communication bus consists notably o~ only one or two -trans~er media. For the action concerning the issuing o~ requests (start) by several active participants, the system comprising only one trans~`er medium has a minium second period o~ time TBi which satisfies the expression TBi = aB Tci = (R .V) oTci per acti~e participant (Mi)~ in which Tci is the period duration of the clock signal gene-rator ~or this active participant (Mi). Furthermore, in this case the system comprising t~o trans~er media has a minimum second period of time TBi = (R3~V) .Tci.
For the action concerning the selection proce-dure, the sys-tem comprising a single trans~er medium has a minimum seeond period o~ time TFi = aFTci = (R .V)~ Tci.
Furthermore, in the latter case the system comprising two trans~er media has a minimum second period o~ time TFi =
(RrV) .Tci.
A suitable construction o~ a data source and/or a receiver which is adapted ~or aetive par-ticipation in an action concerning a communication in the present system ~; is characterized in that the data source and/or receiver eomprises at least one control input and one control out-~ put, the said means in the source and/or the receiver:
-~ - switching over a logic level "ready"-on the communica-;~ 35 tion bus to a logic level "busy" via the control output, a~ter detection in the second detecting means that said second period o~ time (~or example, TBi) has expired, ' ~

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P~ 9736 ~ 6~ 17.3.81 - supplying, via the control output, also the logic level "busy" when via the control input the logic level "busy"
produced on the bus by another active participant is re-ceived and, moreover, the source and/or receiver itsel~
has meanwhile determined, by way o~ the ~irst detecting means, that at least the ~irst period o~ time (~or exam-ple, TAi) has expired, so that the source and/or receiver can be activated to participate in the execution of a relevant action.
It will occur in practice that said data source and/or receiver is a digital slgnal processor which com-prises programmed ~unction means which include said means and an input o~ which acts as said control input whilst an output thereo~ acts as said control output.
When use is made o~ the digital signal proces-sors in the described manner as a data source and/or data receiver, an improvement can be achieved by providing a logic level "ready/busy" transition detector ~or the source and/or receiver whereby a "ready/busy" transition on the communication bus results in a reduced response time ~or the lssuing of the logic level "busy" on the con-trol output by the data source and/or receiver itsel~
moreover, it has meanwhile determined that at least the ~irst period o~ time has expired. The response time of the source and/or the receiver is thus reduced, so that the communication speed is increased.
In the cases where it is applicable or econo-mically justi~ied on the basis o~ the type of data source and/or data receiver~ an attractive solution as regards response time can be realized. To this end, the data source and/or data receiver is characterized-in that it comprises a first section and a second section, said ~irst section embodying mainly the source and/or receiver ~unction and being connected, via at least one request output and one acknowledge input, to the second section which comprises a request input and an acknowledge out-put and ~urthermore said means ~or determining whether ,.

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Pl~ 9736 17.3.81 the communication bus is ready f`or executing an action concerning a communication7 for which purpose the second sec-tion can be co~nected to the bus by way of` said con-trol input and control.output. Moreover9 said second sec-tion may also comprise iden-tity comparison means whereby the ide~tity of` the data source and/or receiver can be compared with an identity presen-ted via the communication bus.
A special version of the above solution is fur ther characterized in that the said means in the second section comprise a read-only memory, an address counter and a logic AND-f`unction element, the ready-only memory being addressable by the address counter; the address counter counts clock signals which are supplied by the ~irst section, via a clock signal generator input, after first a request signal has been received via the request input; when the counter position is reached which repre-sents the ~irst period o~ time (TAi), the addressed read-only memory produces an output bit whereby the logic AND-f'unction element is prepared; when the counter position is reached ~hich represents the second period of' time (TBi), or sooner when via the control inpu-t the bus "ready" signal changes over to the bus "busy" signal so that the counter is forced to the coun-ter position of the second period of` time (TBi), the location o~ the read~only memory then addressed supplies the logic level "busy" to the control output.
Finally, it is to be noted that the ready-only memory whi~h is addressed via the address counter can also be adapted ~or the execution of` the identity check in co~
operation with the identity comparison means.
The communication bus consists o~ at least one transf`er medium. This is the most advantageous solution, be it that the communication speed is not very high be-cause the clock signal generator tolerances have a strongef`f`ec-t.
Solutions involving more transf'er media are also P~ 9736 10 17.3.81 possible by using the induction principle in accordance with the invention. Notably a multi-source/receiver data system is characterized in -that the communication bus consists o~ two transfer media, one o~ which serves as the control trans~er medium whilst the other serves as the data trans~er medium, ~t le~ast each active partici-pant comprisin~ a contro ~ medium write terminal and a read terminal and a data transfer medium write terminal and a read terminal. A ~urther embodiment is characteriz-ed in that the communication bus consists o~ three trans-fer media, two o~ which serve as eontrol trans~er mediumwhilst the third serves as a data trans~er medium, at least each active participant comprising control trans~er medium write terminals and read terminals and a data trans~er medium write terminal and a read terminal. A ~r-ther special embodiment comprising a multiple trans~ermedium is characterized in that the communication bus con-sists o~ three trans~er media, one o~ which serves as a control transfer medium whilst the other two serve as data trans~er media, at least each active participant compris-ing a control trans~er medium write terminal and a readterminal and data trans~er medium write terminals and read terminals.
The invention will be deseribed in detail here~
ina~ter with re~erence to the Figures~ It is to be noted that only examples are deseribed whereto the invention is by no means restrieted.
Fig~re1diagrammatically shows a number o~ ac~
tions constituting the communication via a communication bus.
Figure 2 shows a multi-source/receiver data pro-cessing system comprising a trans~er medium in the ~orm o~ a single line.
Figure 3 shows a time diagram associated with the system shown in Figure 2.
Figure 4 shows a multi-source/receiver data processing system comprising a trans~er medium in the `

P~ 9736 11 17.3.81 form of two lines.
Figure 5 shows a time diagram associated with the system shown in Figure 4.
Figure 6 shows a system comprising a transfer medium in the form of three lines.
Figure 7 shows a slightly modified embodiment of the system comprising a -transfer medium in -the form of three lines.
Figures 8a and 8b show embodiments of modules which are constructed as a digital signal processor.
Figure 9 shows a flow chart for the execution of interrupts.
Figure 10 shows a flow chart of a main programS
Figure 11 shows a flow char-t of an interrupt procedure.
Figure 12 shows a flow chart of a detailed in-terrupt procedure.
; Figure 13 shows a flow chart of the bus "ready?"
testO
Figure 14 shows a block diagram of a data source and/or data receiver, consisting of a first section and a second section.
Figure 15 shows a detailed diagram of the block diagram shown in Figure 14.
Figure 16 shows a time bit diagram for the dia-gram of Figure 15.
Figure 17 shows the diagram of a "ready/busy transition" detector.
Figure 1 diagrammatically shows the actions which may form part of a communication via a bus:
Wait until the bus is ready for an action concerning a communication (~lock 20). The bus is considered to be ~'ready" when it does not exhibit any action for a sufM -ciently long period of time. It is important that ail ac-tive participants known this situation "bus ready", sothat they can all participate in -the next action.
rbitration (block 22) is the next action which concerns :~ ` .

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P~ 9736 12 17.3.81 the execution o~ a selection procedure on the basis o~
priority and/or identity data. It is thus determined which module becomes the master o~ the system~
- Slave selection (block 2l~): the master issues a disti-nation address. All modules compare this address withtheir own identity. The source or receiver which detects correspondence considers itsel~ to be the slave. This is so so-called "open-slave" phase.
- This source or receiver will usually make its own iden-l tity known to the master, so that the master can checkwhether the correct slave has been selected (block 26)o - Data trans~er (block 28). The data to be trans~erred is transported via the bus. The slave considers the trans~er to be terminated ~hen it detects that the bus becomes ~ree again (no action within a given period o~ time)~ Be-cause o~ the ~act that a~ter the arbitration and theslave selection normally a point-to-poin-t connection is present, other time restrictions may also be applicable.
These restrictions can be chosen to be aptimum ~or the relevant master~slave con~iguration~ so that a higher data -transport speed can be reached. During the data transf`er, protection against bi-t trans~er errors can be realized. This can be achieved by means o~ a so-called "bit-echo" procedure where the receiver re-transmits ~5 (echoes) each bit. The source compare the bit transmitted with the bit received.
It is to be noted that besides the block 26, the block 28 will not always occur~ There are cases where a master having carried out the opening o~ a slave ter-~; 30 minates its eommunication instrue-tion.
In the systems in accordance with the invention7 the transport o~ in~ormation will generally be realized bit serially via the at leas-t one trans~er medium. As has already been described, this presents a synchronization problem when no central clock, crystal oseillators or trimming networks can or may be used.
The "induc-tion" principle in aecordance with the ., .

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P~IN 9736 13 17.3.81 invention enables the clocks in the system~ which may be present per module or possibly per group of modules, to have tolerances. Assume that per active source and/or receiver there is a -tolerance Ri RiTi i~
For e~ampleg a deviation o~ ~rom -20% to ~ 80% results in an Ri = 2.25. Hereina~ter, it is assumed that all periods of each active source and/or receiver are proportional to the clock signal generator (T i)~period associated with the active source and/or receiver~
Figure 2 shows a multi-source/receiver data processing system9 comprising a transfer medium in the form of a single line~ The letter C in Figure 2 denotes the single-line bus via which a logic level O or 1 can be transported. The references M1, M2~ ... Mn denote data sources and data receivers~ These m~y be active and pas-sive sources and/or receivers. Because it is not relevant for the description o~ the invention that in addition to active sources and/or receivers there may also be passive sources and/or receivers9 it is assumed hereina~ter that only active data sources and receivers are present. These will be referred to hereinafter as module.
Each module is capable of reading or writing data, or both, ~rom or to the lineg however, in order to establish a communication connection all modules must be capable of reading and writing communication control in-formation ~rom and to the bus. To this end~ each module comprises an output CW (module M1)9 CW (module M2)~o for writing to the bus and an input CR for reading from the bus. The information on C is the information on the inputs CR (moclule M1) J CR (module~ ), ... CR (module Mn).
For the writing it is assumed that the bus line C has a ; wired logic gate function: a wired AND-gate or a wired ~R~gate~ In view of the examples chosen for the ~urther description and the selected signal de~inition o~ the o-gic le~el "busy" = 7'10w" = 0 and "free" = "high" = 1~ the logic AND-function is used for determining the logic le-vel on -the bus. The level on the line C is thus determin-PT-~ 9736 14 17.3.81 ed by C = CW (M1) . CW (M2) .... As is known, a wired AND-gate can be realized, for example, by means of open-collector bus drivers.
Figure 3 shows a time diagram for the example shown in Figure 2. In this time diagram 7 C denotes the signals on the bus~ CW(M1) and CW(M2) denote the signal states on the write outputs of the modules M1 and M2~ In this example it is assumed that both modules request com-munication. Furthermore, in this example the clock sig-nal generator of the module M1 is faster than that of M2.Viewed in time, the following takes place:
1) A previous master of the system (a module Mi) has terminated its use of the buso

2) If the logic level of the C~line does not change after a fi~st period of time TA1 (so in this case for M1), the bus is considered to be "free" (C=1). If the bus assumes the logic level "busy" (C-O) before expira-tion of the period of time TA1, the bus is considered to be busy, A waiting period until the bus becomes free is then necessary~ (See to the left of 1).

3) After TAI, there is a waiting period until the expiration of the second period o~ time TB1 before the module M1 starts to use the bus. This is realized by the supply of a starting bit: CW (M1~ supplies the logic level "busy", so that C becomes O. Meanwhile, module M2 has passed its first period of time TA2 and it detects - on the line C that ~ becomes OO The module M2 reacts thereto by outputting the logic "busy" level via its output CW(M2). This does not -take place immediately be~
cause -the module has a response time. This response time ; is denoted by the reference TR2. The said periods of time, the response time and the tolerances of the clock signal generators which influence the whole procedure will be dealt with hereinafter in order to provide an insight into the interdependence.
The part between 1) and 3) is denoted by the letters WBF in Figure 3, so it concerns the action "wait-PHN 9736 15 17.3.81 ing until the bus is ready", i~e. -the issuing o~ all re-quests (start) by all active particip~lts.

4) The start bit has a duration (T11) (rnodule M1) or (T12) (module M2), respectively. On the line C
S this is Tsb in view o~ the wired AND-~unc-tion. Subse-quently, a data bit (level high or low) is applied to the buso This is done by the active participant module M1 as well as by M20 The ~irst data bit applied is the bit of highest order o~ the identity o~ each of the modules r~1 and M2.

5) At the instant t=T21, the data bit on C is read by the module M~. At the instant t-T22, this data bit is read by the module M2. So, reading -takes place later in M2 in view o~ its slower clock.
lS This part of the communication concerns the ac-tion ~or executing a selection ~rom the ac-tive partici-pants on the basis o~ identity data. The master is -thus determined, This is also referred to as arbitration. The modules compare their bits by way o~ the wired AND=~unc-tion: ~irst their bit o~ highest order and -the *esult thereo~ is that a presen-ted "low" signal overrules a presented "high" signal 7 As soon as an active participant detects9 via its read inpu-t, that a "high" signal applied thereby is obviously made "low" by another signalj this participant withdraws its participation, thus accepting that it has lost the arbitratior.. During the next phases, this module is no longer an active participant and keeps its output at the logic level "high"- CW(Mi) = 1 (like all other non-participants).

6) A~ter T31 or T32, a stop bit is despatched (by the participants still active). This bit is a logic "high" signal~ -

7) As ~rom a ~urther ~irst period o~ time TE1 or TE2, the (still) active participants check whether a transition occurs on the line C: C ~ O. This indi-cates a new start bito This part o~ the procedure concerns the treatment o~ the ~irst data bit: TFB in Figure 3.
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P~ 9736 16 17~3.81

8) The waiting sub 7) lasts until a further second period of time (TF1~ has expired. The said "induc-tlon" principle agai~ occurs: after TEI (f`or module Ml) and TE2 (~or module ~ ), which periods can again be denot-ed as a f`irst period of` time 9 a waiting period expiresuntil olle o~ the two modules passes i-ts own second period of time 1`~1 and TF29 respecti~-~elyO Module M1 ~irst reaches its TF1 (f`aster clock) and a new start bi-t then appears on the line C f'or both modu~es, Howe~-~er, as mentioned sub 3) 9 module M2 lags slightlys a~ter its response time TR2 .
Af`ter TF13 a transition occurs C=1-~ O: a new start bit. From then on all phases ~ 8) are completed again: TSB treatment of` the second da~a bit, etc. This is repeated at least until all data bits required for esta-blishing the communication connection have been dealtwitho Reference is again made to the blocks and the des-cription given with ref`erence to Figure 1 7 where the ~act is mentioned that~ once -the connection has been establish-ed, the time restrictions may change so that a faster point-to-point data transf`er between a master and a sla~e is possible.
An explanation o~ the relationship between the abo~e periods of time is important f`or a proper under-standing of the inven~ion. The ~ollo~ing can be calculat-ed f`or the embodiment described ~ith ref`erence to the Fi-gures 2 a~d 3. Assume that Tci is the local clock signal generator period of a module Mi, The design of` a module is assumed to be so that all relevant periods of` time are deri~ed from said period Tci;
TRi = aRi-TCi; T~i = a~i-TCi ; TBi = a~i.Tci ; Tli = ali.
~r~i; T2i = a2i.Tci ; T3i - a3i.Tci ; TEi = a~i.Tci;
Fi = aFi-TCi-.~(1).
Therein, the symbols aji are constants. aAi and aEi are internal preparation time f'actors. aAi concerns the num-ber o~ clook periods required by a module Mi for request-ing a communlcation connection. aEi concerns the number .

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a P~IN. 9736 17 of clock periods required b~ a module Mi for presenting a stop bit (after T31) after a data bit. In order to achieve the described object, i.e. a proper communication connection by means of a single line without severe requirements being imposed on the clocks in this system, the symbols aBi and aFi should apply to the entire system and not onl~ per module Mi. This is because the said second periods of time TBi and TFi are critical for a proper execution of the actions. The conditions to be satisfied by aBi and aFi will be derived hereinafter.
The time diagram of Figure 3 shows the conditions to be satisfied for a proper execution of the actions:
R ~ Tl ~ 2A) Tl ~ T2 --~ -(2B) T2 ~ T3 ~ (2C) T3 ~ -F ____--(2D) TE ~ -F - ----(2E) TF < -A ___-- (2F) TA ~ TB ~~~~~~~~ -(2G) wherein:
TR = max ~T T ----------T
Tl = min. (Tll,T12 ----------Tln) Tl - max. (Tll,T12 -~ -----Tln) T2 = min. (T21,T22 ----------T2n) etc.
A similar remark applies to Ri= tTci, so Tci = max (Tcl, Tc2,....Tcn) and Tci = min. (Tcl, Tc2,----Tcn). Therein, T means a maximum period of time and T a minimum period of time. The tolerance factor Ri = Tci/Tci is defined.
Usin~ this value and (1) and ~2):
ali/aRi ~ Ri ---------(3A) a2i/ali > Ri ----~----(3B) a3i/a2i ~ Ri ---------(3C) aFi/aEi ~ Ri ---------(3D) aAi/aFi > Ri ---------(3E) aBi/aAi ~ Ri --~--(3F) ~ .~ 6 ~ 8 PHN. 9736 18 and, moreover, aEi ~ a31 (at least unequal)...(3G).
Assuming that normally an as high as possible com-munication speed will be desired, (3~-3F~ with (3G) can be written as follows:
ali = Ri.a ___ ___---(4A) a2i = Ri.ali ~ --(4B) a31 = Ri.a2i -----~ (4C) a = Ri.a3i ------ ---(4D) a = Ri.a _____~_---(4E) a = Ri.a ______--- (4F) It follows therefrom that:

aFi = Ri.aRi = Ri.Vi (5A) (aAi = Ri.aRi = Ri.Vi (5B) aBi = Ri.aRi = Ri.Vi (5C) and aEi ~ Ri-a _~ --------(5D) This is applicable per module. Because for these symbols it is important to make the actions (bus "ready", "selection of master") perfect for the entire system, ~he highest value of aBi = aB and aFi = aF must be chosen as the system constant from the set of associated products. Therefore, the largest product of the factors Ri and Vi from the set of all products of Ri and Vi of the modules is decisive. Modules having a large cloc~ tolerance and a long response time produce large products of Ri and Vi, but moduIes having a small clock tole-rance and a very long response time and vice versa also pro-duce large products of Ri and Vi~ This largest product is denoted as R.V. The dependencies of the second periods of ; time are thus fixed:

a~ = R6.V and aF = R~.V ~ (6) Thus, TBi = R . Tci and TFi = R .V.Tci .... (7) Therein, V = Vp, the response time factor of the given moduIe Mp for which the largest product V.R is formed with Rp = R of this module. The response time of this module is TRp = V.Tcp. Therefrom, the smallest possible ' ~,1 P~ 9736 19 17.3.81 -two periods of time TB ~ R . TRp and TF ~ R TRp follow 9 ~ . ( 8), The TF is a measure for the minimum cycle ("frame") duration for the communication of a data bit during an action concerning a communication~
In practice, the internal response time TRi of a module Mi cannot be indefinitely minimized; this de-pends on the selected implementation. In the case of com-munication with a programmed microprocessor, a TR of, for example~ 10 microseconds is feasible nowadays. In the case of full hardware realization of the means, for exam-ple9 2 microseconds - 0.2 microsecond seems feasible for TRi. In the case of crystal-controlled clocks, R is ~ery near 1, but if use is made of inexpensi~e clocks, for example, comprising simple RC-oscillators (which is as-sumed in this context), R may be a factor 4 or even more.
Numerical example of a feasible situation:
Assume R = 4 and TRp = 10 microseconds. -B = 4 .10 ~
L~o ms and TF = T ~ am~ -~2.6 ms, so ~ =
20 ~ = 10.l~ ms. TB = 160 ms.
As a worst case, the communication speed in the case of an action is then appro~imately 99 Baud.
If TRp _ 2 - 0.2 microseconds (due to hardware provided for this purpose, see Figures 14 and 15), the 25 said lowest speed is increased to some 500 - 5,000 Baud~
It is to be noted that -the TRi can be reduced also when the procedure is controlled by means of a pro-grammed signal processor. To this end, a simple "high/lowl' le~el de-tector can be i~cluded between the bus line C and the module. The detector operates as follows: as soon as the bus changes to ~'low" (C--~0), it sets the CW~Mi) to 0 ~ia a circuit.
It is to be noted that it follows from the foregoing that for the definition of the system in ac-cordance wi-th the present application the largest permis-sible product (R,V) can be determined. In other words, taking into account a "worst" permissible module yet being PHN 9736 20 17.3.81 included in the system~ the cer-tainty that the procedure will be correctly executed is given by taking into ac-count the product (R.V).
Figure 4 shows a multi-source/receiver data processing system in which the single line bus of Figure 2 is extended with an extra line~ This two;line bus, each line o~ which is suitable ~or the transport o~ a logic level 0 and 17 iS less inexpensive than the one-line bus but offers the advantage that a higher communication speed can be achie~ed. M1, M2, ... Mn again denote mo-dules which can act as active participants. K is a con-trol line and D is a data line. Eaoh module comprises a write out~ut KW to the control line and a read input KR
~rom the control line K. Each module ~Irthermore comprises a write output DW to the data line and a read input Prom the data line D. Both lines have the wired AND-propertyo K = KW(M1).KW(M2) .~. and D = DW(M1~ . DW(M2)....
Figure 5 shows the time diagram associated with the system shown in Figure 4. In principle more or less the same happens as in the case o~ Figure 3, the distri-bution o~ the actions among the lines K and D being theessential dif~erence. It is ag~in assumed that the module M1 is fas-ter than M2. ~iewed in the time, the ~ollowing takes place:
1) A pre~ious master has terminated the use of the bus.
All active participan$s start counting down the period TAi, awaiting whether the bus is "ready" (C = 1).
2) I~ tha K line does not change its logic level a~ter the ~irst period o~ time TAi (in this case for module M1 the TA1), the bus is considered to be "~ree"~ When the bus assumes the logic le~el "busy" (K = 0~) be~ore e~Y
pira-tion of the period of time TAi, the bus i5 considered to b~ in use. A waiting time then expires until the bus becomes free. In Figure 5 the busy state o~ thebus is de-noted by the reference BIU. When the bus is ready (a~ter TAi), a data bit (DB) is applied to the line D via out put DW(M1) at 2). The same is applicable to the module M2 .~ .

, .. . . .

s ~ a PHN 9736 21 17J3~81 after the expiration of its first period of time TA2~ Via output DW(M2) a data bit (DB) is applied to D~ The wired AND-~unction of the li.ne D determines the result of -the two applied data bits (a "O" erases a "1").
3) The module (in this case M1), which ~irst detects that its second period of` time TBi (in this case TB1) has ex-pired applies a logic level O to the K line~ via the write output KW(M1)~ K becomes O~ Other modules which have mean~
while detected the expiration of their first period of time TAi react thereto: "induction"~ and write (after their response time TRi) also a O o:~ the K line. In ~igure 5: at 3) a~er TR2 a O is written on the line K via write output K~(M2), This p~ase is the action wàit~until-bus "ready": ~BF in Figure 5.
~) After the abo~e K--~O action, the data line D is.
sampled: each module participating in the action samples the line D after a time TSi (the differences are caused again by the clock tolerences). T~e le~el o* line D is thus applied to the m~dules ~ia their input~. DR(M1) and ; 20 DR(M2)o~
~) After the sampling, all relevant modules supply a lo-~ic le~el 1 to *he ~ line via their output KW(Mi), Module M1 does so a~-ter the period of -time T21. M2 and any other ~ modules do so at other instants T2i~ where:
: 25 6) at the instant 6) all modules have made the line K = 1 via their output KW(Mi). The line K is then also at the level 1 (wi~ed AND)~
7) After having detected the transition 6)? all.acti~e partioipants apply a new data bit (DB) to the line D.
Module M1 does so after the period of -time TEi after the insta.nt 6)~ TEi is a period of time required in the mo-. dule Mi for applying a new data bit to the line D. Other modules do the same~ in any case before e~piration TFi.
TEi and TFi are said first and second period of time again. Thus, "ind:uction" again occurs.
8) After the second period of time TF1~ the line K again ~ becomes O. At this instant it is sure that all active par-.:~
~ .

.
. ' P~ 9736 22 17.3 S1 ticipants have applied -their new data bi-t to the line D.
(Module M2 did so at 7), see line DW(M2) in Figure 5).
The wired AND~function of the data line D again determines the result of the applied data bits. The phase between 3 ahd 8) is the action for the communication of the first bit9 denoted by TFB. The phases 4) - 8) are completed as many times as necessary for establishing -the communica-tion connect;on, which means at least until the arbitra-tion and "open sla~e" phase has been comple-ted~: communica-tion of the second bit (TSB) etc. For this example a cal-culation o~ the periods of time in relation to the clock signal generator tolerances is again given. Tci is again the local clock period of the module Mi. All relevant periods of time are derived from this period per moduleO

TR = aRi Tci; TAi = aAi . Tci, TBi Bi T i = asi . Tcl; T2i ~ a2i ~- Tci; TEi = aEi Tcig FFi = aFi , Tcio (j) Therein7 the symbols aji are constants. a~i and aEi are again internal preparation time factors. aAi concerns the number of ciock periods required in a module Mi ~or a re-quest for establishing a communication connection. aEi concerns the number of clock periods required by a module Mi for applying a ~ew data bit (after -the *etching from, for example, a memory~ to the bus. Like before~ aBi and aFi must be applicable to the entire system rather than per module. Hereinafter~ the conditions to be satisfied by aBi = a~ and aFi = aF will be deri~ed for the two-line system.
The time diagram of Figure 5 enables proper e~ecution of the action only if the following requirements as satis-fied:
Rl~ ~ . O . . . . ~ . . . . O . (2A) ,~,

9 ~ ~

PHN. 9736 23 E ~ -F ~~ (2B) F ~ -A ------(2C) TA C ~ ----------(2D) Using the defined Ri = Tci/Tci, the following can be derived from l~ and 2):
a2i/aRi ~ Ri ----------(3A) aFi/aEi ~ Ri -~ ---(3B) aAi/aFi ~ Ri --~ --(3C) aBi/aAi ~ Ri -~ ---(3D) In view of the fact that normally a situation with the : highest possible communication speed will be desired, (3A - 3D) can be written as:

a2i = Ri-aRi --~ -----(4A) aFi = Ri.a i ~ -------(4B) aAi = Ri.a i -~ -------(4C) aBi = Ri:a i ~~~~~~ (4D) It.follows.therefrom that aFi = Ri-aEi ~ Ri.Vi ------____(5~
(aAi = R i-aEi = R i:.Vi --------(5B) :~ aBi = R i-aEi = R i.. Vi.--______ It thus appears.that the response time factor Vi = aEl is the preparation time factor for the presentation of ~: a new data bit.
Like previously for the one-line system, the constants aBi = aB and aFi = aF.again have to be selected as the highest value of the product (R.V) from the set of pro-ducts (Ri.Vi). The dependencies of the second periods of time are thus fixed: aB = R3V and aF = R.V ... (6).
: Therefore, T~i = R3.V.Tci and TFi = R.V.Tci ... (7).

.

:.

a Pl~ 9736 2L~ 17.3. 81 Therein7 V = aE (= Vp) is the preparation time fac-tor of the module Mp for which -the largest product (RDV) is form-ed. rhe response time of this module is ("ready" time) TEp = V.Tcp.
The smallest possible second periods of time are then-TB = R3. TE and ~ = R ~ _____________(8) As regards the minimum cycle ~frame) period for the communication of a data bit during an action, it fol-lows (see also Figure 5) from (8) and (4A) with (1):
= T~ + ~ = R. ~ ~ Ro~

so that T ~ = R( ~ Rp)~ o~ (8A) Assume, as will often b0 the case in practice, that Ep Rp 7 ~ - 2R.TRp. This is more fa~our-able than in the case of the one-line system9 A relation~
ship exists with respect to R instead of to R . In the case of R = 4~ this alxeady ma~es a di~ferenc~ of a factor 64~ Taking into account the 2R9 this is thus a factor 32.
A numerical example- assume R = ~9 TR = 10 microseconds (so TEp is also 10 microseconds).
~ is then 2,4.10 = 80 microseconds, and T~ = 640 microseconds. The worst case is then: ~ =
R. ~ = 320 rnicroseconds, which means a lowest com-munication speed of approximately 3000 Baud.
The speed can again be increased by simply ar-ranging a "highjlow" le~el detector between the K line and the module inputo KR(Mi), As soon as a 1 ~0 transition occurs~ the detector circuit ensures that -the line K be-comes 0~ The response time TRi is thus substantially reduced.
During the data communication phase (after the establishing of a communication connection) 7 a module ac-ts as a transmitter (source) and another module re-cei~es the da-ta (recei~er). It may be necessary to pro-~ ~ .

P~N 9736 ~5 17~3.81 tect the data transport against communica-tion errors.
This can be realized by making the rec0iver return each bit received ("echo"). The transmitter verifies the bit received with the bit just transmitted. This alternating transmission and reception of the data bits of course, re-duces the communication speed.
The described one-line and two-line systems of-fer an ample illustration of the "induction" principle.
It is to be noted that a number of lines can be readily increased: for example, a three-line system in which there are two control lines and one data line. The in-duction principle can then also be usedO However, the ef-ficiency decreases, because the increasing number of lines has a cost increasing effect, which is contrary to the aim of the present system. Even thou~h the communication speed is further increased in the three-line system, the simplicity is lost. In the -three-line system, communica tion errors can be detected in the 6ame manner as describ-ed above for the two-line system.
Figure 6 illustrates a system comprising a transfer medium formed by three lines. There are two con-trol lines KA and KB and one data line D. The modules M1, M2, ... Mn comprise terminals via ~ich they are connect-ed to these lines: One output terminal KAW(Mi) whereby control data is written from module Mi to the line KA and an input -terminal ~AR(Mi) via which control information is read by module Mi from the line KA. Similarly there are provided an output terminal KBW(Mi) and an input ter-minal KBR(Mi) for the writing on and reading of the con-trol line KB~ Furthermore, each module comprises a dataline write terminal DM(Mi) and a data line read terminal DR~Mi). In view of the time diagrams of the Figures 3 and 5, an associated time diagram will be self-explanatory and will not be described herein. The foregoing can be summarized as follows:
As has already been stated in the preamble, at least i our line s are requir ed :t`o r an asynohro nou s oommlmio a ti on ' ~-J ~ ~
PI~ 973~ 26 17.3.81 on a bus~
~ When ~ewer lines are available~ time-dependent determi-nations must be introduced.
- The present application offers -the time dependent deter-minations and a simple solution for the communication viabuses comprising at least one transfer medium It is to be noted that the invention is not restricted to one-line, two-line or three-line buses, but in practice the four-line solution with a handshal~e procedure will usually be preferred in the case of more than thrae lines.
- The communication speed ln the present systems is great-ly dependent on the wors-t case clock inaccuracy of the mo-; dules. The one-line system is very simple and cheap for applications in notably consumer products etc. However, it has the drawback that a receiver cannot reduce the speed of the source wherefrom it receives data. The two-line system comprises an additional line which not only ena~les a higher communication speed, but also mitigates the drawback of the one-line system~ This is because (see Figure 5) a master as well as a slave module of the sys-tem can reduce the data speed by maintaining the line K
at O for a chosen period of time (instant (6) is then shifted to the righ-t in Figure 5)l~ The three-line system generally does not produce a communication speed which is twice as high. There~ore, when three lines are available, the system utilizing the two-line principle is to be pre-ferred: one line is then the control line and the two other lines serve as two parallel data lines.
~his kind of three-line bus is illustrated in 3a Figure 7. There are provided one control line K and two data lines DA and DB. The modules M1~ M2, r ~O Mn comprise a control line write terminal KW(Mi) and a control line read terminal ~R(Mi). For each of the data lines the~-comprise a data line write terminal DAW(Mi) and DBW(Mi) and a data line read terminal DAR(Mi) and DBR(Mi).
The following is a detailed description of em-bodiments of a multi-source/receiver data processing sys-:

,, . ~ , .

9 ~ ~
PEIN 9736 27 17.3.81 tem in which the bus consists of a single transfer medium.
Figure 2 shows the general diagrc-un of such a system. The modules Mi may be digital signal processors. These proces-sors comprise their one memories and can perform given tasks. When communication with other modules is required, the bus is utilized~ The processors comprising memories are preferably of the type in which so-called micropro-cessors are used as the processor. When the~r comprise me-mories, arranged on the same chip or no-t9 these modules are also referred to as microcomputers. An example of such a microcomputer is the type 8048~ An input/output terrninal (I/0), for example, the terminal 34, thereof can be used as the write output CW as well as the read input CR~ (See the program). Use can alte rnati vely be made of i two tenninals: an I/0 terminal 34 (P17) as CR and an I/0 terminal 38 (P27) as CW. Fur-thermore, a processor of this kind requires a separate input -terminal (No. 6) for re-ceiving interrupts (INT). This can also be considered to ~e CR, be it for a gi~en purpose which will be described hereina~ter (Figures 11 and 12). Figure 8 shows the fore-going again: Ci in the Figures 8a and 8b denotes clock signal generators.
Figure 9 shows how a processor comprising an interrupt input INT, for example, the 8048, can execute interrupts: as from SRT _ start in block 30~ each time the question is asked: is there an interrupt INT (block 32)?, If negative (N) 9 an instruction o:~ the main program is executed: MPI in block 3L~. After that it is checked again (back to block 30) whether there is an interrupt.
-~ 30 IE there is ~) interrupt (Y), the interrupt program is completely executed- IPIS (block 36). ~fter that, it is again checked whether there is an interrupt (block ~), etc. This method of interrupt execution is a specific propert~ of, for example 7 the 8048.
A microprocessor such as -the 8021 which does not know an interrupt~ comprises an input terminal which can be defined as interrupt 9 SO that the interrupt opera--~ .

.....

P~N 9736 2~ 17,3.81 tion can be included in the total prograrn.
Figure 10 shows a flow chart of a feasible pro--cessor main programu Such a main program may be of any type and in the described embodiment it consists o~:
block 3~ start BEGo This is followed by initialization INIT, block 40. In block 42 local operations LOP of the main program are executed. It is each time checked whether there are interrupts (see Figure 9)~ When the main progr~m reaches a posi-tion where communication with ano-ther module is required, the processor in this posi-tion submits a request for communication: REQ. This means that -this module wishes to become the rnaster of the sys--tem. This request must be dealt wi-th. This can only be done if the bus is "ready" for -this action. This check is made in block 44: RDY?. In this example, these are the said means ~IS. When -the bus is "ready", the acknowledge signal (ACK) for the action is gi~en (Y of block 44).
This block 44 is of major importance, because it is the subject of the present application~ Block 44 comprises the progr~nmed function means which are the said means whereby it can be determined whether the bus is "read~"
for the execution of actions concerning the communication.
When the permission is not gran-ted (N of block 44), a new attempt is made, etc. When permission is granted (Y)~
the system transfer operations TOP for the data transport, for example~ transmission9 are executed~ block 46. At -the end thereof, the bus is released again, signal REQ, and return to block 42. The interrupt input (inputs) is (are) then enabled again for the reception of interrupts (enable interrupts), because -these inputs are blocked ("disabled interrupt(s)") during the request for permis-sion (block 44) in order to pre~ent intermedia-te inter-rupts from disturbing the process, see also the descrip-tion with reference -to Figure 13. When (see dotted part of Figure 10) a data source and/or recei~er consists of a first sectio~ and a second section, the first section ~ being a digital signal processor ~hich performs the ::
~, .

9 ~ ~
PI-~ 9736 29 17.3.81 source and/or receiver function, and the second section, also referred -to as arbitrator, comprises the said means, a request ~EQ from block 42 will be applied to the arbi-trator (block 43). Therein pe~mission is awaited, again S see block 44, ACK. After termination of the transfer7 the arbitrator releases the bus again: REQ(block 48). This should also be detected by the arbitrator: block 50. If yes (Y), ACK becomes ACK and the process returns to block 42. If no (N)~ 48 is repeated. It is to be noted that said block 44 is so important because the conflict as to who will be master arises when several modules arrive in their rele~ant block 44. It is notably important that a slow module is not pushed aside by a faster module.
Therefore, the described "induction" is necessary. The lS operation thereof will be described in detail hereinafter (see Figure 13 and Figure 15 with Figure 16~.
The fact should also be noted that when a module ; is the master~ it indicates a slave. To this end, it is despatches an identity o* the slave and tries to inter-rupt the slave. This is why the INT inputs are shown in the embodiments of the Figures 8a and 8b. Figure 11 shows what happens. In block 52, the interrupt INT ap-pears which is applied by the master to all other sources and receivers via the bus. (In practice, it is INT as the signal INT in view of the notations: inpu-ts INT). In block 54, all sources and receivers compare the presented identity i with their own identity i. If no (N), the in-terrupt is terminated: END~ block 58. If yes (Y~, the transfer operation TOP (for example, receiving) is e~ecuted in block 56. After termination, END follows, block 58, Block 54 contains the identity comparison for the slave selection. This will be described in deta~l hereinafter in Fi~ure 12.
Block 60 is the beginning BEG. In block 62 a bit counter position bt becomes O and the -time counter position Tt beoomes 0~ In block 64 there is a waiting ~'!
.' ' ~: .

PHN. 9736 30 period until a period of time Tt = T21 (assume Mi is the relevant module) (see T2i in Figure 3) has expired. At T2i, an identity bit present on the bus is sampled as a data bit, block 66. This is bit bt of the identity j which is applied from terminal P 17 (see Figure 8) into a register of the processor, btj: = P17. The bit counter is incremented by one: bt + 1, block 68. In block 70 it is checked whether the number of desired identity bits (or more if desired for other purposes), for example, bt = 4, has been reached. If not (N~ r there is a waiting pe~riod until Tt = TEi (see Figure 3): block 72. As soon as the change over of the bus C to "O" is detected (block 74) (P17 must be O) (see Figure 3, TFi~, a new start is made: counter Tt: = O (block 75) and back to block 64. When the number bt = 4 is reached, block 70 (Y~ r the content of the register in which the identity j is stored is compared with the identity of the relevant module r block 78. If i ~ j, it is not intended to be a slave and the interrupt program stops: END, block 82 (= block 58 of Figure 11). If i = j, this module is selected as the slave and the transfer operation TOP will be executed, block 80 (block 56 r Figure 11). This is followed by block 82, END.
Thus, for slave selection any source and receiver other than the master itself is interrupted and forced to perform the identity comparison. This is time consuming:
the sources and recei~ers which detect i ~ j have been interrupted in vain, so the interruption of their main program is unnecessary. This drawback can be mitigat d by ~ 30 the introduction of a so-called conditional interrupt - mechanism. The identity comparison is then performed with-out direct interruption of the processor itself. If i = j indeed, there i5 an interrupt of the processor itself.

.~

9 ~ 8 PHN. 9736 31 Figure 13 shows a flow chart of the bus "ready?"
test (block 44 of Figure 10). In this example/ use being made of a digital signal processor wherein the said means HS are thus represented by programmed function means, the ; 5 functioning of HS is illustrated. The start is indicated with SRT by REQ (see Figure 10)~ block 84. In block 86 the interrupt input (inputs) are disabled: DABINT. It is thus prevented that a module is interrupted when the module itself performs an action in order to make a re~uest.
In block 88 the. time is reset: Tt = O; this is realized by the resetting of a counter CR to O (CR : = O). In block 90 it is tested whether the line C which enters via the termi-nal P17 has the level "1l'. If not (N), the bus is busy and another attempt is made by returning to the block 88. If P17 = 1 (Y) in block 90, the counter CR is incremented by one by means of the clock signal generator for this module ~ Mi, CR : = CR + 1 .(block 92). In block 94 it is tested whether the counter position CR = aAi has been reached.
This aAi, therefore, again is the previously mentioned time factor aAi- If CR = aAi' Tt aAo Ai called first period of time. Block 94 thus contains the first detecting means: FDETM for the first period of time TAi. If this position CR = aAi has not yet been reached (N?, the program returns to the block 90. If aAi has been reached,.the module is ready for.the action. In block 96 the bit counter bt is set to O : bt : = O; furthermore, it is checked ~block 98) whether the line C still carxies a "l":.so that it indicates busy, in this case "bus ready".
If line C:and hence P17 Y O (N of.block 98), the bus is : 30 "ready":and the next action may commence. As long as C
remains 1 in block 98 (Y!:, the counter CR -~ CR + 1 ~ (block 1003. In block 102 it is checked whether the posi-tion CR = aB has been reached~ If~(Y?, Tt = TBi = aBTci-~ Block 102 thus con.tain.s the second detecting means SDETM.
:~ 35 This position aB will, therefore, be stored as a system ~' ,~ .

~ t3~
P~ 9736 32 17.3.81 constant in the memory o~ the processor (like the above aAi which, howe~er, is a da-ta of the module Mi itself).
When the position aB has been reached (Y)~ the next action may be started. As long as this position has not yet been reached (N), the program returns to 98~ It is checked again whether C = P17 as already become "0". This may have occurred in the meantime because in another module the second period of time TBj has meanwhile expired. If yes (which means N in this case), this action t'bus ready"
is terminated. (Point 103 in Figure 13). If no, which means P17 = 1(Y), CR is incremented by one again etc. The line "IND" in Figure 13 thus concerns the so-called in~-duction. The counter CR does not ad~ance -to ~ if pre-viously another mod~le has reached its period of time TBj = aB.Tcj and signals this by making C = 0 = P17~ If Mi has meanwhile passed at least TAi = aAi~ Tci, i-t also detects that the bus is l'ready". All requesting modules (REQ) have then terminated their action concèrning the maki1lg of a request (start)O This is the point ~3) in Figure 3~ Thus bus is C = 0. The next action may commence after -the rele~ant processors, detecting this C = 0, ha~e ; set their write output (P17 or, for example, P27) to 0 (block 104). The next action, starting with a start bit, concerns the determination of the master of the system on the basis of priority and or identity data. In block 104 not only the write output CW (referred to hereinafter as P17, see also Figures 8a and 8b) bec~mes 0, but also the time : = 0 by the resetting of the counter CR : = 0.
The counting of the time starts again. A wai-ting perio~
expires until Tt _ Tli = aliTci (for the start bit), block 106. The write output CW (P17) -then supplies the first data bit of the identity and/or priority: P17 : ~
bti (block 108). An encircled A at the bottom points to the encircled A at the top where -the process continues.
In block 110 a waiting period expires until Tt = T2i.
j CR is then a2iO This is point (5) in Figure 3 where the line C is sampled. In block 112 it is detected wh~t is P~-~ 9736 33 17~3p81 carried by the line C: -the wired AND of the applied bits bti etc., denoted by P17 = W~B. Read input CR (P-l7) reads this. When all rele~an~ (in -this case first~ bits are equal, Y of block 112 is the output for all modules. How-e~er, if this bit of one or more modules is O and whilstit is 1 for the other module (modules) 9 the arbitration is lost by the latter module (modules) and they arrive at output N of 112~ The modules no longer participate in the selection of the master, This is executed per bit of the identity and/or priority, so tha-t ultimately one remains as the master. After N of block 112, the interrupt (in-terrupts) of the module (modules) is (are) unblocked again in block 114 so that they are enabled again: EABINT.
Thus, for this (these) module ~modules) the actions for establishing a communication connection (so as the master) ha~e not had any result, so they reach the situation N of block 44 (Figure 10) as indicated in block 116 of Figure 13.
For the modules which are still in the selec-tion process, the process continues via Y of 112: the bit ; counter is incremented one position bt-~ b-t * 1 (block 118). In block 120 it is checked whether -the maximum num ber o~ priority and/or identity bits (bt max.~1~ has al-ready been reached. If yes (Y)~ the selection process is terminated and the (r~ow sole) module having reached this ; point is the master o~ the sys-tem: block 122 indicates this by Y, 44, which refers back to the Y output o~ block 44 o~ ~igure 10 : ACK~ l`he transfer of data may then com-mence: TOP, etcO of Figure 10. If the maximum btmax has not yet been reached, (N) block 120, a waiting time ex-pires until Tt = T3i = a3iTci, counter CR = a3i (block124~. The bit period of bti has thus expired and the module (Mi) sets the out P17 : = 1, block 126. This is CW (Mi) = 1 after point (6) in Figu:r0 3~ After a response time Tt = TEi = a~i o Tci, it will ~ /ertain that this ~r~ . module Mi has again presented the C = 1 to the C line via P17 as the write output~ block 128. Thus, this Pl~ 9736 34 17.3.81 concerns, the first period of time for -this action with preparation time factor aEi. The process waits for this occurrence in block 128 7 which thus contains the so-called first detecting means FDETM for this action. In block 130 it is checked whe-ther the C line itself indeed becomes 1 due to the applica-tion of the 1 from the write output CW (P17)~ This is realized via CR (P17) as the read inputO If C = P17 - 1 (Y), no module has yet reached its second period of -time TFi. The coun-ter CR is again

10 incrernented by one: CR-~ CR ~ 1, block 132~ In block 134 it is checked whether the CR position reached has mean-while become equal to -the response time factor aF7 Thus, this concerns the so-called second detecting means SDETM
for this action. If this posi-tion aF has not yet been reached (N), i-t is checked again whether another module has changed~ by -the reaching of this position aF, the C = P17 = 1 into C = 0 (so block 130 again). If C - P17 = 1 remains, 132 again etc. When C has meanwhile been made 0 by another module, N of block 130 is ap-2a plicable: the induction occurs and the process returns to poin-t 103. This is point (8) in Figure 3. A next data bit is applied: block 108 supplies -the next data bit bti (second etc.) which is evaluated again via the wired AND (block 112), etc. If no other module has previously counted down aF, at a given instant CR = aF is reached in block 13~ in the relevant module~ ~ia Y of 13L~ this means that point 103 of the process is reached. This continues until ei-ther the module is rejected from the selection process: N of block 112, or the module is assigned as the master: Y o~ block 120, which is achieved after compari-son of the last bit and it appears in 120 -that ~urther selection is not necessary: bt = btmax ~ 1.
Figure 1l~ shows a block diagr~m of a data source and/or receiver~ consisting of a first sec-tion DL1 and a second section DL2. DL2 is the section which embodies the source and/or receiver function. Via a request output REQ~ DL1 is connected to a request input REQ o~ DL2. ~ia 4~
P~ 9736 35 17.3.81 an acknowledge input A~K, DL1 is connected to an acknow-ledge output of DL2. DL2 comprises the said means HS. The clock signal source for DL1 is connected to DL2 via C1.
DL2 is connected to the bus llne C ~ia by way of a said write output C~ and read inpu-t CR~ DL1 itself is connect-ed to an interrupt input INT and to the bus line C by way of one (or possibly two lines) from input/output terminal (terminals) I/O with form input and output connections.
The INT has the same function again as previously, see Figure 8 etc. The I/O connection becomes effec-tive when the connection master-slave has been established and the data tra~sfer is executedO
The impor-tant aspect is that the means HS in DL2 are especially designed to enable determination, with-out involving DL1, whether the bus is "ready1' for execut-ing said actions. For the relationship with what happens in the main program of a module Mi, of which DL2 forms part, reference is made to Figure 10 and the description of notably the blocks 43, 48 and 50 denoted by broken lines.
Generally, the action concerning the master se-lection is also incorporated in DL2.
Figure 15 shows a detailed diagram of the sec-tion DL2 of Figure 14.
Figure 16 shows a time bit ~address and data content) diag~am associated with Figure 15~
Instead of an elaborated logic circuit compris-ing many logic components (such as many gates, two-state elements, etc.), in Figure 15 a solution is chosen where the said means are: a read-only memory ROM, an address counter AD~R, a logic AND~func-tion elemen-t, in this case the NAND-gate 140~ Furthermore, in this example arrange-ments are made so that the selection action can take place in the identity comparison means present in the section DL2 J These comparison means ID~OMP co-operate with the read-only memory ROM addressed by the counter AD~R and a flipflop DFF and an exclusive OR-gate 1420 There are also g ~ ~
P~ 9736 36 17.3.81 provided an open-collector inverter 144 and an open-col-lector NAND 146, which together ~o~m the write output CW.
Elements 148 and 150 are ~urther inverters. 141 is a NOR-gate~ The operation will be described in detail with re~erence to Figure 16. Therein, the addresses A~O, ...
n, n+1, n+2~ n~3) 9 the periods o~ time Tt and the as-sociated time factors aAi, aB, ali, ... aF which represen-t address parts o~ addresses A o~ ROM are sta-ted at the le~t. At the right there are stated the contents o~ the memory locations which appear on outputs DO, 1, 2~ 3, 4, 5 3 6 o~ ROM in reaction to relevant addressing.
Assume that there is no request: REQ = O. As-sume line C = O~ so -the O is present on the output of gate 141, so that CLR = O, so that any position present on adder ADCR is then clearedl The counter obtains the position A (O... n, ...) = O and hence all outputs re-ceive a 0. I~ due to A(...n~1, and/or n+2, ...) one or more outputs were 1, they are no longer soO
Assume that there is no request: REQ = O and assume that the line C = 1; a O is then also present on the output of gate 141 and the same GC curs: clear~
Assume that there is a request- REQ = 1 and as-sume that the line C = O (so "busy"): same as above again~
Assume there is a request REQ = 1 and C - 1:
all inputs o~ 141 are then O (because Dl~ = o, LD = 1 so a~ter inverter 150 also a O on gate 141)9' so that CLR Y 1 and the address counter ADCR indeed starts to count, The clock pulses via Cl (~rom the module clock signal generator) are counted. The addresses passed through by ADCR A(O), A(l), etc. still produce a O ~or ; all D. Whcn :Line C = 1 becomes C = O, the procedure drops back: clearing o~ counter ADCR~ This means that the bus does not permit the request, because it was still busy with a previous communication. I-t is -to be noted that at REQ = 1, the identitY and/or priority data IDi o~
module i are stored in a register IDCOMP via input Lo Subsequently~ this register is enabled, "~ or shi~ting :: '' . ' .

9~
P~ 9736 37 17.3.81 the content to the right on its clock inpu-t D . I~
REQ ~ 1, C = 1 and ADCR reaches the position aAi9 ~or which Tt = TAi (see Figure 3) (the ~irst period o~ time), a 1 appears on output D4 o~ ROM, whereby gate 140 is pre-pared. This means that ~rom this instant the "induction'tcan occur. The counter meanwhile continues counting, dur-ing which no ROM outputs change. When counter ADCR
reaches position aB, the period o~ time Tt Y TBi, so the second period o~ time, is reached. In this position, out-put D1 o~ ROM becomes 1. Via inverter 144, having an opencollector, the line C is made O (point (3) in Figure 3)~
This also takes place when a O is applied, to the line C
itsel~ be~ore the position aBO This is possible because another module may have reached its TB sooner. Via in-verter 14~, the NAND 140 is opened (because D4 was al-ready 1) and hence LD becomes 0~ so that counter ADCR is ~orcibly loaded with a position aB (aB is soldered in the counter and is loaded into the counter on load com-mand). The induction has then occurred and D1 = 1 will appear, and hence this module will present C = O via a write output CW. Subsequently, the start bit (piece (3) -(4) in Figure 3) is transmitted: C = O until Tt = Tli =
ali.Tci is passed. The counter ~DCR continues ~rom aBD
(No clearing occurs, because D4 is O again5 so LD = 1 and via inverter 150 a O on an input of NOR 141, which means CLR = 1)o In position aB ~ ali D2 = 1~ Gate 146 thus opens, which means that a (highest order) bit o~ the identity and/or priority data IDi, present in the regis-3n ter IDCOMP~ is applied to the line C. Thus~ an 1/0 is writ-ten as a 0/1 on the line C. tPoint (4) in Figure 3)~
~ith the bits o~ other modules~ the wired AND-~unction occurs on C. During ~urther counting until aB ~ a2i is reached, ROM always supplies a 1 on its output D2, so that said bit remains presented. Moreo~er~ DO is also 1 and the ; flip~lop DFF is clocked thereby (it was already prepared by REQ = 1), Point (5) in Fi ure 3 (sample). The input of ~: .
, .
.

, 9 ~ ~
Pl~ 9736 38 17.3~81 DFF carries the signa]. which is present on the output of the e~clusive OR-gate 142. This signal is the result o~
the exclusive OR-function on the bit which is applied from the module itsel~ ~rom the IDCOMP and the bit which is presen-t on the line C. This may be the sarne (both O
or both 1), or di~erent~ If the same, a 1 is present on the input o~ DFF, so that on the ou-tput thereof an 1 also appears; this 1 is retained at least ~or as long as no new DO = 1 appears as the clocking pulse. The said 1 ad-dresses ROM on address section A(n~3) = 1, so that thetotal address A(a2i,0,0,l~ is present. I~ the said bits are not the sarne, a O appears at the output o~ the DFF
and the address section A(N+3) = O. The ~otal address is then A(a2i,0,0,0). The ~oregoing means that in the case o~ correspondence the arbitration is positive. The module may continue -to participate in the arbitration on a next bit. The memory ROM is then addressed in a given section by the said A(N~3) ~ 1, so that the module sti.ll has a chance o~ becoming the masterO In the case o~ non-corres-pondence, the arbitration is nega-tive. The module cannot become the master, because a module (modules) o~ higher identity number and/or priority also have REQ = 1.
~xample of arbi-tration: identities M1 = O a~ter inversion, applied to line C 10.
identities M2 = 10 a~ter inversion, applied to line C 01.
identities M3 = 11 a~ter inversion, applied to line C 00.
For the highest order bit~ line C produces O through the wired ANDo With the rneans IDCOMP, together with DFF and 142, this produces in:
M1 a O on output o~ DFF~ so A(n~3) = O negative~
M2 a 1 on outpu-t o~ DFF, 90 A(n~3) = 1 positive~
M3 a 1 on output o~ DFF, so A(n~3) = 1 positive.
Therefore, only M2 and M3 participate in the ~urther ar-bitration (~or the second bit). For the second bi-t it is applicable tha-t C = O a Thus, a O appears in M2 on the P~ 9736 39 17.3.81 output of DFF, so A(a~3) = O, 50 negative. It is only for M3 that A(n~3) = 1, so positive. M3 is selected. The following takes place in the ROM: in the case of "nega-tive", addressing takes place in the part of ROM for which the address portion A(N~3) = O, during which the address coun-ter counts further. In this part of ROM, in any case D1 = D2 = D3 - O. Thus, no further bits are pre-sented for arbitration. CW is then always 1 and has no further effect. Due to D3 = O, no ACK occurs to signify that this module is not granted permission for a data transport as the master of the systema Meanwhile, count~
ing continues on the counter ~DCR (all modules; however, only the module (modules) still participating in the fur-; ther arbitration have an e~fect on the line C)~
The counter ~DCR reaches the time Tt = TBi~T3i, where position aB + a3i is reached (point (6) in Figure 3). All outputs Do, ... 6 = O. On the line C level 1 is present (stop bit after point (5) of Figure 3). The counter continues to aBi ~ aEi (point (7), Figure 3).
The first pe*iod of time TEi a~ter TBi is then reached again~ Induction can occur: output D4 = 1~' thus prepar-ing gate 140 againQ D6 is also 1. The memory ROM thus reaches the part which is addressed by the address part A(n~2) = 1. Therein, the control bits are stored for the treatment of the second bit of the priority and/or iden tity data D ( In this example with D5 and D6, 2 = 4 bits are assumed). The counter ADCR continues until it reaches the position aB + aF~ which means the second period o~
time T~i = aFOTci after TBi. Thus D1 = 1 again (and D6 remains 1 in view of the later treatment of the second bit). The seoond bit is shifted out o:~ the register IDCOMP and is prepared on gate 146. At the same time O
appears on line C due to D = 1. Via CR, this line applies a 1 to the already enabled gate 140. LD = O again occurs, so that the counter ADCR is forced to the position aB
again. As from this point (point (8) in Figure 3 the cycle starts again from position aBO The counter ad-( ' .

a PHN 9736 40 17~3.81 vances to Tt = TBi ~ Tli where the second bit of thepriority and/or identity data passes via the g~te 142 (via D2 = 1) to the line C, etc.
If on the line C a O is read via CR before the counter reaches the position aB ~ aF~ aB is already load-ed in-to ADCR (induction) and the process proceeds to the new cycle (point (~) Figure 3). Therefrom, the new cycle for the arbitration of the next bit starts, see above, etc.
When a module obtains each time the result "positi~e", A(n-~3) always remains 1, at the end o~ the cycle for the last bit (so in this case four) at the ad-dress A(aB ~ aF, 1,1,1) a 1 will be present on output D3, which means ACK = 1, and the module is thus selected as lS the master.
It will be clear that the response time TRi of the set-up shown in Figure 5 will be small. This is be-cause the ROM is addressed directly at the location where D1 = 1 in the case o~ induction in th~ module Mi (assume TBj is reached~ which means C = O by module Mj). Thus9 this module Mi also causes C _ O. TRi is determined com-pletely by the circuit. This opposes the TRi in e~ample of Figure 13. The programmed digital signal processor thereof has to perform, either after the block 98 (N) or after the block 102 ~or the case TAi/TBi and after block 130 (N) or after the block 134 for the case TEi/TFi, pro-gram s-teps in order to ensure tha-t a O appears on its ter-minal CW = P17 (block 104) (and for Tt = 0~ moreover9 the counter becomes CR : = O). This requires more time, TRi thus being larger than when it is determined by the cir cuitry. In order to solve this problem, a ~Iready/busy~
logic level transition detector can be included between the bus and the programmed digital signal processor used as a data source and/or data receiver.
This is shown in Figure 17. The detector con-sists of an inverter 152 and a NAND-ga~e 154. The inver-ter 152 receivas a signal from the bus line C and the .~

6~
P~ 9736 41 1773.81 gate 154 recei~es a signal from the inverter 152 as well as from the processor Mi (8048). The outout o~ 154/of con-nected to the bus line C again~
The output P27 is in this embodiment a terminal of the processor Mi (in this case the ~o48) which is defin-ed during the actions of the present application so that P27 becomes 1 for CR - aAi (block 94, FDETM) and for CR = aEi (block 128, FDETM of Figure 13). The following then takes place: gate 154 is prepared. Assume that a 0 level reaches the inverter 152 via C; via 154~ a 0 is also applied from this module Mi to the line C. Therefore:
as soon as the line C becomes 0 after TAi or T~i of a mo-dule Mi (by Mi itself at TBi or TFi, respecti~ely, but notably by another module Mj at TBj and TF , respectively), Mi ensures that C becomes 0. TRi is thus reducedO The ter-minal P27 is further defined so that it becomes 0 again when the processor supplies a 0 at pin P17 (P17 : 0) (block 104), so that the detector has no further effect (always 1 supplied from the output of gate 154).
It is to be noted that, obviously instead of using a terminal (P27) a solution can be chosen wherethe gate 154 is controlled without invol~ing the proces-sor. In Figure 17 this is shown within the stroke/dot box by way of example for the p0riod of time TAi. There is provided an additional counter ~ETCR which produces a car-ry CY when the 0 position is reached. The line on whichCY appears is connected to the gate 154. The operation is as follows: the processor terminal P16 is defined as the inverse clear input (CLE)of the counter DETCR whereby the counter is no-t cleared only during the action (P16 = 1~ during which TAi has an effect. Furthermore~
in spite of the control via LD and CK7 the counter is ne-ver of importance and C~ also carries 0 signal. Each time when a transition from 0 to 1 occurs on the line C~ the counter DETCR is loaded by LD = I with a value equal to aAi; a previously reached position, which may have been reached during a previous attempt to count down -aAi, is ~:
.~ ~

~ .

P~ 9736 L~2 17,3,81 then erased. Terminal TO o~ the processor is defined as a clock output via which counting pulses reach the coun-ter DETCR which counts down.
~hen the counter position O is reached, so TAi is reached, the following happens: CY applies a carr~
signal to gate 154 which is thus prepared. l~hen Mi it-sel~, or notably another module Mj, causes -the line C to become O, gate 154 also supplies a O for the line C via inverter 152. The fast reaction is thus obtained again and TRi is reduced. The counter itself does not advance7 because CY = 1 blocks the actuation input: ENA = 1, so actuation is O. Thus, CY remains 1 7 This con-tinues until completion of this action, which means in this example that P17 : - O P16 is then O again so CLE = O, which means that the counter is cleared, so that CY becomes O
again and the gate 154 is no longer prepared. The detector can e~ert no further effect.

.~

Claims (18)

PHN. 9736 43 THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PRO-PERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A multi-source/receiver data processing system in which the data source (sources) and data receiver (receivers) are connected to a communication bus which con-sists of at least one transfer medium which is suitable for the transport of at least one logic level (0 or 1), charac-terized in that - the system comprises a plurality of clock signal generators having different tolerances, and - in the source (sources) and/or receiver (receivers) there are provided means (HS) whereby it can be determined for all sources and/or receivers (Mi) which actively partici-pate in an action concerning a communication (active par-ticipants) whether said bus (C) is ready for executing said action, said means (HS) comprising - first and second detecting means whereby it can be deter-mined that during a first and a second period of time, respectively, (for example, TAi and TBi) the communication bus is ready for the relevant action, the first period of time being smaller than the second period of time (for example, TAi < TBi), the first period of time being determined by a preparation time factor (for example, aAi) of the relevant active participant (Mi), the second period of time being related to the largest product (R.V) of the set of products (Ri.Vi) of all potential active partici-pants, the product (Ri.Vi) being formed per active partici-pant (Mi) by a tolerance factor (Ri) of the clock signal generator for the active participant (Mi) and a response time factor (Vi) of this active participant (Mi) - when an active participant (Mi) detects that the second period of time (TBi) has expired, the bus (C) is (in-deed) ready for executing the relevant action and can thus be occupied by this action for this active parti-cipant and all further active participants (Mj, Mk ...) which have meanwhile detected, at least during their PHN. 9736 44 relevant first period of time (TAj, TAK, ...), that the bus (C) is ready.

2. A multi-source/receiver data processing system as claimed in Claim 1, characterized in that the said means (HS) are adapted to determine that the communication bus (C) is ready for executing an action concerning the making of requests (start) by several active participants (Mi) for establishing a communication connection.

3. A multi-source/receiver data processing system as claimed in Claim 1, characterized in that said means (HS) are adapted to determine that the communication bus (C) is ready for executing an action concerning the execution, on the basis of priority and/or identity data, of a selection procedure from several data sources and/or receivers (active participants Mi) requesting a communication connection.

4. A multi-source/receiver data processing system as claimed in Claim 1, characterized in that the communication bus consisting of at least one transfer medium comprises a wired logic gate function (wired AND or wired OR) per con-nection of an active participant (Mi).

5. A multi-source/receiver data processing system as claimed in Claim 1 or 2, characterized in that the bus con-sists of a single transfer medium, the minimum second period of time (TBi) satisfying per potential active parti-cipant (Mi) the expression TBi = aB.Tci = (R6.V).Tci, in which Tci is the period duration of the clock signal gener-ator for this active participant (Mi).

6. A multi-source/receiver data processing system as claimed in Claim 1 or 3, characterized in that the bus con-sists of a single transfer medium (C), the minimum second period of time (TFi) satisfying per potential active parti-cipant (Mi) the expression TFi = aF.Tci = (R4.V)Tci, Tci being the period duration of the clock signal generator for this active participant (Mi).

7. A multi-source/receiver data processing system as claimed in Claim 1 or 2, characterized in that the bus con-sists of two transfer media (K,D), the minimum second PHN. 9736 45 period of time (TBi) per potential active participant (Mi) satisfying the expression TBi = (R3.V).Tci, in which Tci is the period duration of the clock siynal generator for this active participant (Mi).

8. A multi-source/receiver data processing system as claimed in Claim 1 or 3, characterized in that the bus con-sists of two transfer media (K, D), the minimum second period of time (TFi) satisfying per potential active parti-cipant (Mi) the expression TFi = (R.V).Tci, in which Tci is the period duration of the clock signal generator for this active participant (Mi).

9. A data source and/or receiver adapted to partici-pate actively in an action concerning a transfer in a system as claimed in Claim 1, characterized in that the data source and/or receiver comprises at least one control input (CR) and one control output (CW), the said means in the source and/or the receiver:
- switching over a logic level "ready" on the communication bus to a logic level "busy" via the control output (CW), after detection in the second detecting means that the said second period of time (for example, TBi) has expired, - supplying, via the control output (< W), also the logic level "busy" when via the control input (CR) the logic level "busy" produced on the bus by another active parti-cipant is received and, moreover, the source and/or receiver itself has meanwhile determined, by means of the first detecting means, that at least the first period of time (for example, TAi) has expired, so that the source and/or receiver can be activated to participate in the execution of a relevant action.

10. A data source and/or receiver as claimed in Claim 9, characterized in that it is a digital signal PHN 9736 46 1703.81 processor which comprises programmed function means which comprise said means and an input of which acts as said control input (CR) and an output as said control output (CW).

11. A data source and/or receiver as claimed in Claim 10, characterized in that for the source and/or re-ceiver there is arranged a logic level "ready"/"busy"
transition detector whereby a "ready"/"busy" transition on the communication bus result in a reduced response time for the supply of the logic level "busy" to its con-trol output (CW) by the data source and/or receiver it-self if, moreover, it has meanwhile detected that at least the first period of time has expired.

12. A data source and/or data receiver as claimed in Claim 9, characterized in that the source and/or re-ceiver comprises a first section (DL1) and a second sec-tion (DL2), said first section (DL1) embodying mainly the source and/or receiver function and being connected, via at least one request output (REQ) and an acknowledge in-put (ACK), to the second section (DL2) which comprises a relevant request input (REQ) and an acknowledge output (ACK) and which furthermore comprises said means (HS) for determining whether the communication bus is ready for executing an action concerning a communication, for which purpose the second section can be connected to the bus for example, C) by way of said control input (CR) and control output (CW).

13. A data source and/or data receiver as claimed in Claim 12, characterized in that said second section (DL2) also comprises identity comparison means (IDCOMP) whereby the identity of the data source and/or receiver itself can be compared with an identity presented via the communication bus.

14. A data source and or receiver as claimed in Claim 12, characterized in that said means in the second section comprise a read-only memory (ROM), an address counter (ADCR), and a logic AND-function element (140), the read-PHN 9736 47 17.3.81 only memory being addressable by the address counter;
the address counter counts clock signals, subject to the condition that the bus is "free", which are supplied by the first section via a clock signal generator input (C1), after first a request signal has been received via the request input (REQ); when the counter position is reached which represents the first period of time (for example, TAi), the addressed read-only memory produces an output bit whereby the logic AND-function element (140) is pre-pared; when the counter position is reached which repre-sents the second period of time (for example, TBi), or sooner when via the control input (CR) the bus "ready"
signal changes over to the bus "busy" signal so that the counter (ADCR) is forced, via AND-function element (140) to the counting position of the second period of time (for example, TBi), the location of the read-only memory then addressed also supplies the logic level "busy" to the control output.

15. A data source and/or data receiver as claimed in Claim 14, characterized in that the read-only memory (ROM) addressed via the address counter (ADCR) is suit-able for executing the identity comparison in co-operation with the identity comparison means (IDCOMP).

16. A multi-source/receiver data processing system as claimed in Claim 1, characterized in that the communi-cation bus consists of two transfer media (K, D), one of which serves as the control transfer medium (K) and the other serves as the data transfer medium (D), at least each active participant (Mi) comprising a control medium write terminal and read terminal (KW(Mi) and Kr(Mi)) and a data transfer medium write terminal and read terminal (DW(Mi) and DR(Mi)).

17. A multi-source/receiver data processing system, as claimed in Claim 1, characterized in that the communi-cation bus consists of three transfer media, two of which serve as control transfer media (KA, KB) whilst the third serves as a data transfer media (D), at least each active PHN 9736 48 17.3.81 participant (Mi) comprising control transfer medium write terminals and read terminals (KAW(Mi), KBW(Mi) and KAR(Mi), KBR(Mi))), and a data transfer medium write terminal and read terminal (DW(Mi) and DR(Mi)).

18. A multi-source/receiver data processing system as claimed in Claim 1, characterized in that the communi-cation bus consists of three transfer media, one of which serves as a control transfer medium (K) and the other two serve as data transfer media (DA and DB), at least each active participant (Mi) comprising a control transfer medium write terminal and read terminal (KW(Mi) and KR(Mi)) and data transfer medium write terminals and read terminals (DAW(Mi), DBW(Mi) and DAR(Mi), DBR(Mi)).