CA1161959A

CA1161959A - Mnos storage cell

Info

Publication number: CA1161959A
Application number: CA000351670A
Authority: CA
Inventors: Erwin Jacobs; Ulrich Schwabe; Dezso Takacs
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1979-05-10
Filing date: 1980-05-09
Publication date: 1984-02-07
Also published as: GB2049279B; FR2456368A1; JPS55151368A; DE2918888A1; FR2456368B1; US4330850A; GB2049279A; DE2918888C2

Abstract

ABSTRACT OF THE DISCLOSURE

The invention relates to a MNOS memory cell arrangement in VLSI
(very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate elec-trode is split into two electrodes, which can be operated in different ways and which are superimposed one upon another. These gate electrodes are connec-ted via self-aligned, overlapped contacts. This arrangement avoids "short channel erasure", even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.

Description

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BACKGROUND OP Ttl~ INVENTION
Field of the Invention:
The invention relates to memory cell arrangements, processes for operating such arrangements and methods of fabricating such arrangements.
Somewhat more particularly, the invention relates to a memory cell arrange-ment comprised of a semiconductor body of a first conductivity type in which a plurality of MNOS components, including source and drain zones of a second conductivity type, which is opposite to that of the first conductivity type, are arranged and includes a multi-layer gate insula~ing layer which covers the surfaceofthe semiconductor body in the region between the source and the drain zones.
Prior ~rt:
The operation mode of a MNOS (metal-nitride-oxide semiconductor) memory cell is based on the fact that in a MNOS field effect transistor, the conductance state which is determined for a given gate voltage and the thresh-old voltage of the transistor, respectively maintained, are altered by charges which are trapped in the gate double insulating layer. During pro-gramming, a positive voltage pulse causes negative charges to be stored at the nitride-oxide interface and inside the nitride, respectively, in the addressed transistors, thereby rendering such transistors permanently blocked.
The charges disintegrated by a pulse of the reverse polarity or by other erasing processes. One such process, some~imes referred to as "short channel erasure" comprises connecting a positive voltage pulse to the source and drain zone while connecting the substrate and gate to ground potential.
The manufacture of highly integrated circuits (VLSI-very large scale integration-technology) necessitates relatively thin gate oxides (having a maximum thickness of about 50 nm) and relatively flat diffusion zones ,J''~

3 ~
,, ` `

(smaller than about 0.5 J~m). These requirements result in a reductlon in the avalanche breakdown voltage at the drain-side of the pn-~unctions. In instances of short channel erasure of silicon dioxide/silicon nitride double insulating layer memory elements (MNOS transistors), the erasure process (sometimes refer-red to as a punch-through breakdown) is complicated because the transistors break down before the erasure voltage is reached at the pn-junction of the source-drain zone.
In device components which exhibit a relatively low degree of in-tegration, premature pn-avalanche breakdown of short-channel transistors is avoided, for example, by using thick gate oxide layers (100 to 200 nm) or by producing deep-diffused source/drain zones (1 to 1.5~um). Another means oE
avoiding premature pn-avalanche breakdown comprises of providing a so-called split gate arrangement which is characterized by a thick gate oxide at the drain edge (see I.R. Cricchi et al, Technical Digest IEDM, Washington, D.C. page 126, 1973~.
However, when higher degrees of integration are required (VLSI
technology), split gate arrangements can no longer be utilized. Further, additional reductions of the channel length involve serious technological dif-ficulties.
SUMMA_RY OF THE INVENTION
The invention provides a MNOS storage cell arrangement wherein break-down at the source and drain edges is avoided and "short channel erasure'l problems in FLSI structures having the MNOS storage cells of the invention are resolved.
In accordance with the principles of the invention, there is pro-vided in a memory cell comprised of a semiconductor substrate of a first con-ductivity type, said substrate having arranged in the surface thereof a plurality of MNOS components including source and dr~in zone~ of a seconcl cond~ctivity ~ype 5 g opposite to that of said first conductivity type, and a multi-layer gate in-sulating layer which includes a gate electrode and covers a surface of said semiconductor substrate in the regions between said source and drain zones, the improvement comprising wherein said gate electrode comprises first and second gate electrodes which are superimposed one upon another (dual gate) and are connected via self~aligned overlapped contacts, said second electrode being located above said first gate electrode and edges of said second gate electrode being arranged so as to be vertical relative to the plane of said semiconductor substrate surface and self-aligned to edges of said source and drain zones;said cell having a storage nitride layer partially extending beyond the region of a channel zone toward the region of said source and drain zones.
In certain embodiments of the invention, the edges of a second gate electrode, which is located above a first gate electrode (storage gate) are arranged so as to be vertical relative to the plane of the substrate surface and self-aligned relative to the edges of the source and drain zone, while the nitride storage layer partially extends beyond the region of the channel zone toward the source and drain zone.
In certain embodiments of the invention, the double gate electrodes are constructed in double-polysilicon technology. Further, in the practice of the invention one can use silicides, particularly molybdenum, titanium or tungsten silicides. In preferred embodiments of the invention, the semiconduc-tor body is composed of doped silicon.
BRI~F DESCRIPTION OF THE DRAWINGS
. . . _ ~
Figure 1 is an elevated, partial, cross-sectional and somewhat schematic view of a memory cell arrangement with a double gate electrode con-structed and operable in accordance with the principles of the invention;
Figure 2 is a somewhat similar view taken through a two-trans:Lstor .- 1 l 61~
~ .
:

storage cell constructed and operable ln accordance with the principles of the invention (with the switching translstor on the right);
Figures 3 - 8 are elevated, partial, cross-sectional~ somewhat schematic views of a device undergoing a fabrication sequence in accordance with the principles of the invention;

':,?~ 3a-1 ~ 6~9~

Figure 9 is a somewhat sectional view taken along lines IX-IX of Figure 2 illustrating a layout of a MNOS storage cell have a three-transis-tor arrangement constructed and operable in accordance with the principles of the invention; and Figure 10 is a somewhat schematic view of a circuit diagram for a cell having a 2 x 2 - 2-transistor MNOS memory matrix constructed and oper-able in accordance with the principles of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The invention provides an improved MNOS memory cell useful in VLSI
technology and having a multi-layer gate insulating layer covering surface areas of a semiconductor body in the regions between the source and drain zones wherein the gate electrode is split into two electrodes which are superimposed upon one another, connected via self-aligned overlapped con-tacts and which are operable in different ways; a method of fabricating such MNOS memory cells and a process of operating such cells.
In the development of the invention, it was noted that when a conventional gate electrode is split into two electrodes which are super-imposed one on another and which are operated in different ways, the ICT
(inversion charge transistor) effect [described in detail by R.R. Troutman et al, IEEE Journal of Solid State Circuits, SC13, page 490, (1978)] is used to produce a strong erasing field beneath the storage gate of MNOS
transistors. As can be seen from Figure 1, because of the symmetrical field distribution and the fact that the equipotential lines 11 extend essentially flat beneath the storage gate 8, and earlier punch-through breakdown is achieved. The storage nitride 6, which remains beneath the ICT gate lO, amplifies the electrical field above the inversion layer 3, approximately in accordance with the relation:

1 :~ B1~35~
, ..

Si3N4 ~ ~ SiO2 when compared with a conventional SiO2 insulating layer. A further e~ect of the nitride layer is to reduce the potential drop in the edgc zone of the poly-Si 2 (structure 10) and to displace the gate-controlled avalanche break-down at the source and drain edges (corner breakdown) toward higher voltages.
In this manner, the breakdown probability shifts from the undesired avalanche breakdown toward the desired punch-through breakdown. At the same time, the erasing effect can be amplified by shortening the length of the storage gate 8.
In an exemplary embodiment of the invention wherein a n-channel ~NOS
transistor operates as a memory cell, a strong erasing field beneath the storage nitride layer is produced by simultaneously connecting the source and drain zones to an erasing voltage in the range of 10 to 30 volts and connect-ing the gate electrode ~ (poly-Si 2) to a voltage exceeding 0 volts. In pre-ID
ferred embodiments, this gate voltage (gate ~) is in the range between about 5 to 20 volts and the source/ drain voltage is about 25 volts. The substrate~
and gate electrode ~ carry ground potential.
Further details of the inventive principles can be derived from the following discussion, taken in conjunction with the drawings. Figure 1 illus-trates the potential distribution during short channel erasure beneath a MNOS storage cell having a double gate electrode in accordance with the in-vention. In this arrangement, structure 1 is a p doped (100)-orientated sili-con crystal body; structure 2 is a n -doped source and drain zone; structure 3 is an inversion layer; structure 4 is a tunnel oxide; structure 5 is a gate oxide (SiO2); structure 6 is a storage nitride layer; structure 16 is an oxynitride layer; structure 7 is an insulating oxide; structure 8 is a poly-19~9 Si 1 layer which functions as a storage gate; structure 9 is an intermediate oxide and structure lO is a poly~Si 2 layer which acts as a second gate. The equipotential lines located beneath the storage gate 8 are schematically indicated at 11.
As can be seen from Figure 1, the inversion zone 3 is essentially flat where it enters the region beneath the storage gate 8 Since the inver-sion layer is designed to be self-aligned relative to gate ~, an extremely short channel length (up to a maximum of about l~m)can be obtained so that the breakdown field is further increased.
Figure 2 illustrates a section taken through a two-transistor stor-age cell ~with the switching transistor on the right) constructed in accor-dance with the principles of the invention. The reference numerals are identical to those used above in conjunction to Figure 1 and refer to similar structures.
The fabrication procedure for producing, for example, a n-channel polysilicon-gate-MNOS memory transistor of the invention is described below in conjunction with Figures 3 - 8.
Figure 3 illustrates a p-doped (100)-orientated silicon substrate 1 which, via an isoplanar process, also known as a LOCOS (local oxidation of silicon) process, is provided with a structured Si02 layer 12 (so-called field oxide layer) to divide-up the active transistor zones. Although not shown in the illustrationJ in this process, the p-doped silicon substrate 1 is first coated with a 150 nm thick silicon oxide layer and then coated with a 100 nm thick silicon nitride layer. After structuring, a 700 nm thick Si02 layer 12, which acts as a thick oxide, is oxidized onto the silicon sub-strate and thereafter the silicon nitride layer is removed.
Next, as illustrated at Figure 4, a 3nm thick Si02 layer 4, which ~ 3~

functions as a tunnel oxide is deposited onto the entire substrate surface.
Then a so-called storage nitride layer 6 is applied in a thickness of about 40 nm and structured via conventional mask technology so that it remains in select regions of the memory transistor and at areas at which the overlapped polysilicon-metal contact will be produced.
Thereafter, as shown in Figure 5, a 50 nm thick SiO2 layer 5, which acts as a gate oxide, is applied viathermo-oxi~ation, during which the sur-face of the silicon nitride layer 6 is transformed into an approximately 15 nm thick oxynitride layer 16. As an alternative to thermal oxidation, a SiO2 layer can be deposited and it then functions as a blocking layer in place of the oxynitride layer.
Next, as illustrated in Figure 6, a polysilicon layer 8 (Poly-Si 1) is deposited in a thickness of approximately 500 nm and is structured. In order to improve the clarity of the illustration, the two SiO2 layers 4 and 5 have been shown in Figure 6 and subsequent illustrations as a single layer 5a. Otherwise, all structures shown are referenced with the same reference numerals as set forth earlier in conjunction with Figure l. The zone outlined by dash-dot line C in Figure 6 is a sub-zone of a storage transistor whereas the dash-dot line D encloses a normal transistor of the arrangement.
After the deposition and structuring of the Poly-Si 1 layer 8, which functions as a storage gate, an insulating oxide layer 7 is applied in a thickness greater than about 50 nm, up to 250 nm and structured as shown.
Next, a polysilicon layer 10 (Poly-Si 2), which functions as an ICT gate is deposited and structured.
Then the source-drain zones are produced via arsenic-ion implant-ation through the oxynitride/nitride layers 16, 6 and the gate oxide 5 at a concentration of, for example, 1-1016 As cm 2 at 150 keV (schematically indicated by arrows 18) so that the n -zones 2 are forrned (Figure 8).
After implantation and annealing, an intermediate oxide 9 is applied a thickness of about 70 nm and then structured in a conventional manner to produce contact holes. Thereafter, metallization and application of a pro-tective layer, for example in the form of phosphorous glass, occurs as in a conventional double silicon gate process (now shown).
The polysilicon zones 8 and 10 for the polysilicon-metal contact above the thick oxide layer 12 are not positioned on a SiO2 layer as is nor-mal, but instead are positioned on the silicon nitride layer 6. In this manner9 no underetching of the polysilicon layers 8 and 10 occurs during etching of contact holes ~which would allow the edges of the applied metal paths to break-off) because the nitride layer 6 functions as an etch-stop means. Further, this allows the attainment of a self-aligned, overlapped polysilicon contact which represents the connection of the gate electrodes of the two switching transistors. The space requirements for a contact is reduced to less than half the normal contact surface. Consequently, the packing density of the cell is substantially increased. This is a further advantage of devices constructed in accordance with the principles of the invention.
Figure 9 illustrates a layout of a MNOS storage cell in a three-tran-sistor arrangement taken along line IX-IX of Figure 2. The various structure details which have been described in conjunction with Figures 1-8 are here referenced with the same reference numerals used earlier. In Figure 9, the shaded zone represents contact holes 17: the strip zone 20 is the metaliza-tion and the broken-line zone 19 represents the MNOS mask.
Figure 10 schematically illustrates a cell arrangement of a 2 x 2-

2-transistor MNOS memory matrix. In this illustration, Sl and S2 are source J :~ 6 ~

terminals; Dl and D2 are drain terminals; Xl and ~2 are word lines, Gl and G2 are bit lines; and C is the ICT (inversion charge transistor) gate line.
As can be seen from the symmetry of this arrangement, any desired n m matrix (wherein n and m are integers ) can be formed from the 2 x 2 - 2 transistor MNOS memory matrix.
As is apparent from the foregoing specification, the present inven-tion is susceptible of being embodied wi~h various alterations and modifi-cations which may differ particularly from those that have been described in the preceding specification and description. For this reason, it is to be fully understood that all the foregoing is intended to be merely illustrative and is not to be construed as being restric~ive or otherwise limiting of the present invention, excepting as it is set forth and defined in the heretoappended claims.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. In a memory cell comprised of a semiconductor substrate of a first conductivity type, said substrate having arranged in the surface thereof a plurality of MNOS components including source and drain zones of a second con-ductivity type opposite to that of said first conductivity type, and a multi-layer gate insulating layer which includes a gate electrode and covers a surface of said semiconductor substrate in the regions between said source and drain zones, the improvement comprising wherein said gate electrode comprises first and second gate electrodes which are superimposed one upon another (dual gate) and are connected via self-aligned overlapped contacts, said second elec-trode being located above said first gate electrode and edges of said second gate electrode being arranged so as to be vertical relative to the plane of said semiconductor substrate surface and self-aligned to edges of said source and drain zones; said cell having a storage nitride layer partially extending beyond the region of a channel zone toward the region of said source and drain zones.

2. In a memory cell as defined in claim 1 wherein said semiconductor substrate is composed of doped silicon.

3. In a memory cell as defined in claim 1 wherein said first and second gate electrodes are constructed in double polysilicon gate technology.

4. A memory cell as defined in claim 1 wherein said first and second gate electrodes are composed of a silicide.

5. A memory cell as defined in claim 4 wherein said silicide is selected from the group consisting of molybdenum silicide, titanium silicide and tungsten silicide.

6. A memory cell as defined in claim 1 wherein said cell is integrated into a semiconductor body in the form of a matrix.

7. A process of operating a memory cell as defined in claim 1 wherein said source and drain zones are simultaneously connected to an erasing voltage in the range of about 10 to 30 volts and the second gate electrode is connected to a voltage exceeding 0 volts while the first gate electrode and semiconductor substrate are connected to ground potential whereby a relatively strong erasing field is produced beneath a storage nitride layer.

8. A process for operating as defined in claim 7 wherein said second gate electrode is connected to a voltage in the range of about 5 to 20 volts.