CA1159154A - Sequential chip select decode apparatus and method - Google Patents

Sequential chip select decode apparatus and method

Info

Publication number
CA1159154A
CA1159154A CA000367804A CA367804A CA1159154A CA 1159154 A CA1159154 A CA 1159154A CA 000367804 A CA000367804 A CA 000367804A CA 367804 A CA367804 A CA 367804A CA 1159154 A CA1159154 A CA 1159154A
Authority
CA
Canada
Prior art keywords
subsystem
rows
memory
address
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000367804A
Other languages
English (en)
French (fr)
Inventor
Chester M. Nibby, Jr.
Dana W. Moore
Robert B. Johnson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1159154A publication Critical patent/CA1159154A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
CA000367804A 1980-01-08 1980-12-31 Sequential chip select decode apparatus and method Expired CA1159154A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/110,523 US4323965A (en) 1980-01-08 1980-01-08 Sequential chip select decode apparatus and method
US110,523 1980-01-08

Publications (1)

Publication Number Publication Date
CA1159154A true CA1159154A (en) 1983-12-20

Family

ID=22333491

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000367804A Expired CA1159154A (en) 1980-01-08 1980-12-31 Sequential chip select decode apparatus and method

Country Status (4)

Country Link
US (1) US4323965A (cg-RX-API-DMAC7.html)
JP (1) JPS56103751A (cg-RX-API-DMAC7.html)
AU (1) AU534703B2 (cg-RX-API-DMAC7.html)
CA (1) CA1159154A (cg-RX-API-DMAC7.html)

Cited By (1)

* Cited by examiner, † Cited by third party
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US9406993B2 (en) 2011-08-23 2016-08-02 Mesaplexx Pty Ltd Filter

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US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
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US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
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US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
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US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
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US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
JP5242397B2 (ja) 2005-09-02 2013-07-24 メタラム インコーポレイテッド Ｄｒａｍをスタックする方法及び装置
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US7724589B2 (en) 2006-07-31 2010-05-25 Google Inc. System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8006044B2 (en) * 2006-12-21 2011-08-23 Intel Corporation Flexible selection command for non-volatile memory
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
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CN111240581B (zh) * 2018-11-29 2023-08-08 北京地平线机器人技术研发有限公司 存储器访问控制方法、装置和电子设备

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US3440615A (en) * 1966-08-22 1969-04-22 Ibm Overlapping boundary storage
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources
US4236203A (en) * 1978-01-05 1980-11-25 Honeywell Information Systems Inc. System providing multiple fetch bus cycle operation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9406993B2 (en) 2011-08-23 2016-08-02 Mesaplexx Pty Ltd Filter

Also Published As

Publication number Publication date
JPS56103751A (en) 1981-08-19
AU6565080A (en) 1981-07-16
JPS6259820B2 (cg-RX-API-DMAC7.html) 1987-12-12
US4323965A (en) 1982-04-06
AU534703B2 (en) 1984-02-09

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