CA1154103A - Control circuitry for gated diode switches - Google Patents

Abstract

CONTROL CIRCUITRY FOR GATED DIODE SWITCHES

Abstract:
A gated diode switch requires a voltage applied to the gate which is more positive than that of the anode or cathode in order to break current flow between the anode and cathode. In addition, a current of at least the same order of magnitude as flows between anode and cathode must be sourced into the gate of the switch to break current flow. The use of a second gated diode switch coupled by the cathode thereof to the gate of a gated diode switch which is to be controlled provides a high voltage and current capability circuitry for cutting off (interrupting) or inhibiting current flow through the gated diode switch. The state of a gated diode switch is thus controlled by a second gated diode switch. The state of the second gated diode switch is controlled by a voltage control circuit having only relatively modest current handling capability.

Description

1~L54:~L()3 1.

Technical Field This invention relates to control circuitry for use with gated diode switches.
sackground Art Gated diode switches (GDSs) have an ON
(conducting) state and an OFF (blocklng) state. These switches are capable of blocking relatively large potential differences in the OFF state. The OFF state occurs when the potential of the gate is held more positive than that of both the anode and the cathode.
The magnitude of the needed potential of the gate relative to the anode and cathode to turn oef a GDS is a function of the geometry and doping levels of the semiconductor regions of the GDS. Conduction between anode and cathode is cut off (interrupted) because carriers from the cathode are diverted out of the gate and carriers from the anode are repelled before they can reach the cathode. The control circuitry used to apply a blocking voltage to the gate must be able to sustain a more positive voltage than is at the anode and cathode and must be able to supply current which is at least of the same magnitude as flows through the switch itself.
GDSs of the type referred to above are relatively new in the art and, accordingly, there is little published information describing the control circuitry utilized therewith.
It is desirable to have solid-state control circuitry for use with GDSs which can be fabricated on the same substrate as the switches which are to be controlled.
Summar~_of the Invention In accordance with an aspect of the invention there is provided circuitry for use with a first gated diode switch of the type comprising a semiconductor body a bulk portion of which is of a relatively high resistivity, a first region of a first conductivity type and of a ~. `

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relatively low resistivity, a second region of a second conductivity type opposite that of the first cond~ctivity type, the first and second regions being connected to output terminals of the switching device, a gate region of the second conductivity type, the first, second and gate regions being mutually separated by portions of the semiconductor body bulk portion, the parameters of the device being such that, with a first voltage applied to the gate region, a depletion region is formed in the semi-conductor body which substantially prevents current flowbetween the first and second regions, and that, with a second voltage applied to the gate region and with appropriate voltages applied to the first and second regions, a relatively low resistance current path is 15 established between the first and second regions by dual carrier injection characterized by a second gated diode switch of the same type as said first gated diode switch, an output terminal of the second gated diode switch being coupled to the gate of the first gated diode switch; and a 20 voltage control branch circuit coupled to the second gated diode switch for controlling conduction between the first and second regions thereof.
A solution to the proble~ of controlling the state of a first gated diode switch (GDSl) in accordance 25 with the present invention is circuitry characterized in that it comprises a second gated diode switch (GDS2) coupled by the cathode thereof to the gate of GDSl and a voltage control branch circuit coupled to GDS2 for controlling conduction between the anode and cathode 30 thereof.
The state of GDS2 is controlled essentially by the voltage control branch circuit which selectively adjusts the gate-anode voltage. A relatively low voltage pulse triggers the voltage control circuit. The voltage 35 control circuit has high voltage capability but only modest current supply capability. Thus, any steady-state 4~3 2a.

current flowing through GDS2 must be of only a modest value for the voltage control circuit to be capable of switching GDS2 ~rom the ON to the OFF state.
With GDS2 in the OFF state the potential of the gate of GDSl is at a level that is no more positive than that of the anode and cathode thereof and, accordingly, GDSl is in the ON state and conduction between the anode and cathode thereof can , i, : .

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occur. To switch GDSl to the OFF state requires that ` the potential of the gate thereof be increased to a '~ value more positive than that of the anode and cathode i.~ and that electrons, at least of the order of magni-~s 5 tude as flows between ca~hode and anode thereof, be collected at the ga~e and then pulled out of the ~' gate. Considered from a circuit design view, the pulling out of electrons from the gate of GDSl is the equivalent of the driving ~sourcing) of positiye charge ~current) into the gate of GDSl. The anode ;~ of GDS2 is coupled to a potential sowrce which is selected to be more positive than the potential at ' the anode of GDSl. ~hen GDS2 is in the ON state the potential at the gate of GDSl ~also the cathode of GDS2) is more positive than that at the anode ' of GDSl, and GDS2 is capable of supplying sufficient ' positive current such'that GDSl is switched to or maintained in an OFF state.
These and other features of the invention are better understood from a consideration of the - following detailed description taken in conjunction with the accompan~ing drawings.
~Brie Description of the Dr'aw'i'ngs FIG. 1 illustrates a switch with an ' 25 embodiment of control circuitry in accordance with the invention;
FIG. 2 illustrates a bidirectional switch which also can be controlled by the control circuit of FIG. l; and ~' 30 FIG. 3 illustrates a switch with another ~` embodiment o control circuitry in accordance with ~' the present invention.
Detailed Description . Referring now to the FIG. 1, there is ~ 35 illustrated control circuitry 10 ~illustrated within :' the larg0r dashed line rectangle) which is coupled to a gated diode switch GDSl having anode, rathode, . `;-!

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and gate terminals.
. Control circuitry 10 comprises a gated diode switch GDS2 having anode, cathode, and gate terminals, first and second current limiters 5 CLl and CL2, an n-p-n transistor Ql, p-n diodes Dl, D2, and D3, resistors Rl, R2, and R3, and capacitor Cl. Ql may be denoted as a switching - device. The base may be denoted as a control terminal and the collector and emittter which may be denoted as first and second output terminals.
The anodes of Dl and D3 and a first terminal of CLl -~ are all coupled to a terminal 12. The collector of ~ Ql is coupled to the cathode of D3 and to a : terminal 11. The cathode o~ Dl is coupled to the gate : 15 of GDS2 and to a terminal 20. The base of Ql is coupled to an input terminal 16 through diode D2.
The emitter of Ql is coupled to one terminal of Rl and to a terminal 17. A second terminal o Rl is coupled to a terminal 18 and to power supply VSS.
A second terminal of CLl is coupled`to power supply ~Vl and to a terminal 14. CL2 is coupled by a first terminal to the cathode of GDS2~ the gate of GDSl, and to a terminal 22. CL2 is coupled by a second terminal to power supply -V3 and to a terminal 28.
A third current limiter CL3 is coupled by a first ,~ terminal thereof to terminal 20 and by a second terminal thereof to a power supply -V4 and to a terminal 26. CL3 and -V4 are both optional. -V4 .;} can be the same as VSS or -V3 in potential.
The anode of GDS2 is coupled to one terminal of R3 and to a terminal 21. A second terminal of R3 is coupled to a first termi.nal of R2 and to a terminal 23 and to a first terminal of Cl. A second terminal of R2 is coupled to power supply ~V2 and to a terminal 24. A second terminal of Cl is coupled to terminal 18. ~Vl is selected to be more positive in potential than ~V2.

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The combination of Dl, D2, D3, Ql, CLl, Rl, and CL3 Cillustrated within dashed line rectangle A) serves as a voltage control branch circuit and is adapted to set the potential of the terminal 20 Cthe gate terminal of GDS2) so as to control the state of GDS2. Cl and R3 are optional. Without Cl and R3, terminals 21 and 23 would be directly connected together.
Cl serves as a limited source of charge which is used to aid in the switching of GDSl to the OPF state.
` 10 ~ithout Cl it is necessary to have greater steady-state current flow through GDS2 when it is in the ON state ~i in order to inswre that there is sufficlent available current that can be supplied to the gate of GDSl to turn GDSl off.
. 15 The basic operation is as follows: Assuming the anode and cathode terminals of GDSl are coupled to +220 volts and -220 -,rolts, respectively, conduction can occur between the anode and cathode thereo~ if the gate Cterminal 22~ is less positive than +220 volts.
Conduction is cut off Cinterrupted~ by increasing the potential of the gate Cterminal 22~ above +220 volts and by providing a source of positive current which 10ws into the gate Cterminal 22) of GDSl. With ~Vl =
+280 volts, VSS = ~ero volts, ~V2 = ~250 volts, -V3 =
. 25 -250 volts, -V4 - -250 volts and current limiters CLl, CL2, and CL3 limiting current therethrough to 50, 5, and 5 microamperes, respectively, circuitry lO is ' capable of providing the needed potentials at terminal 22 and the source of current into term,inal 22 necessary 30 to control the state of GDSl.
Assuming first that it is desired to allow ;~3 conduction through GDSl, an input signal having a ?." potential level between O and 0.4 volts ls applied to ;, terminal 1,~,. This biases Ql off and allows terminal 12 35 to assume a potential of approximately +Vl ~approxi-' mately +280 volts). Without CL3 present, Dl conducts `,~ in the forward direction until terminal 20 reaches within ':.
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several tenths of a volt of thc potential of terminal 12 and then ceases to conduct. With CL3 present there is a flow of current fro~ ~Vl through CLl, Dl, CL3 and into -V4. CLl and CL3 are selected such that the 5 voltage appearing at terminal 20, with Ql biased off, is at a level which is significantly more positive than that of ~V2. Por thls case, terminal 20 likewise assumes a potential of close to ~280 volts. This ;~ condition biases GDS2 to the OFF state and thus isolates terminal 22 from potential ~V2. Terminal 22 there-fore follows the negative potential -V3 ~-250 volts~
S until the gate-to-anode junction of GDSl becomes forward-~, biased. Terminal 22 no~ remains at a potential close ;i to but not greater than the po~ential of the anode of , 15 GDSl. Accordingly, GDSl is biased to the ON state and ~, conduction occurs between the anode and cathode thereof.
', The current flowing ro~ the anode to gate of GDSl is limited by CL2 to an insignificant fraction o the anode-to-cathode current through GDSl.
~ 20 If GDS2 had been in the ON state prior to the .~$ application o the 0-0.4 volt input level to terminal S~'! . 16, then positive current flows from ~Vl, through Dl, and into the gate of GDS2. CLl is selected to allow ,~ a greater current flow therethrough than through CL2 ~, 25 to insure that sufficient positive current is available . to flow into the gate of GDS2 so as to cut off conduction ~i between the anode and cathode thereof. Only a relatively ~ modest amount o positive current must flow into the ,~' gate of GDS2 to cut off conduction therethrough since the conduction through GDS2 is only 5 microamperes. It is thus not necessary to use a high current device to ` provide the needed current sourcing unction necessary to cause GDS2 to assume the OPF state.
` The potential of terminal 16 is raised to a ' 35 level of 2-5 volts to cause GDSl to switch to the OFF
!,'' (blocking) state. This input voltage level biases Ql ON and allows Ql to operate in saturation. The potential . .,~, .
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o terminal 12 is pulled down to approximately ~1.6 volts ~assuming an input ~oltage at terminal 16 o 2 volts, a VCF.~SAT) o~ 0.3 volts for Ql and a voltage drop across D3 of 0.7 yolts). The potential of terminal 12 at this time is a function of the input voltage level, the VC~CSAT) of Ql and the forward voltage drop across D3.
~ithout CL3 present, terminal 20 is pulled to a value close to that of ~V2 or to a more negative potential because of leakage through Dl. The potential of terminal 2Q cannot drop below one diode voltage drop below the potential of the anode of GDS2 because a junction diode comprising the anode and gate of GDS2 beco~es ~orward-biased and pulls up the pokential of terminal 2U. ~ith i CL3 present, terminal 20 is rapidly and actively held at a value close to one diode drop below the potential of the anode of GDS2. In either case, this suitches GDS2 to the ON state.~ This causes the potential of ;, terminal 22 to be at ~V2 minus the voltage drop across R3 and R2 and minus the orward voltage drop across the anode-cathode of GDS2. The voltage drops across R2, R3, and GDS2 are selected such that the potential o$
terminal 22 is more positive than ~hat o the anode o$
GDSl by a suf~icient amount to switch GDSl to the OFF
(blocking) state. In addition, there is a sufficient -positive current flow inko the gate of GDSl to switch it to the OFF state. Once GDSl is switched of the ; current 10w into the gate thereof ceases. The geometry and impurity concentrations of GDSl determine exactly how much more o a positive potential must exist at the gate relati~e to the anode and cathode to turn -~l GDSl of$.
-; Minority carriers emitted at the cathode o GDSl and collected by the gate constitute the equivalent of positive current flow ro~ ~V2 through R2, R3, ~`~ 35 GDS2, and into the gate of GDSl. This current 10w can }i be substantial and as a result it is necessary to have ~`'! a high voltage and current device such as GDS2 to ,~

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~L~S~ 3 ` -8-switch GDSl to the OFF state. The high cost of a high ~; voltage and high current transistor limits its appli-cation in this control circuit.
R2 and R3 limit current flow from +V2 ~hrough ~`~ 5 GDS2, and into the gate of GDSl. In addition, R3 limits current flow from Cl. This helps insure against the burn out of GDSl and/or GDS2. In many telephone switching applications GDSl operates with only 48 volts ~etween anode and cathode when in the ~ 10 OFF state; however, it is possible that + 220 volts ;~- exist at the anode and/or cathode due to ringing, ~- testing, coin telephone controlling, and induced 60 Hz voltages and, accordingly, control circuit 10 is designed to block these high voltages.
When Ql operates in saturation the base-collector junction thereof is potentially forward-biased. D3 serves to help insure against a flow of ~ current from input terminal 16, through the collector-- base junction of Ql and then through Dl.
The circuit of FIG. 1, excluding CL3, R2, R3, and Cl, has been fabricated on a single integrated ~-circuit chip.
~ The fabricated control circuit allowed the blockin~
; of 500 volts across the anode and cathode of GDSl ands 25 cut off (interrupted) 100 miliamperes of current flow therethrough. ~he values of Rl and R3 are 1000 and ; 30ao ohms, respectively, without Cl and R2 being used and with R3 coupled directly to +V2. Cl and R2, when used, reduce the time needed to switch GDSl from the !' 30 ON to the OFF state. One preferred value of Cl is ;~ 0.1 ~F with Rl = 1000 ohms, R2 = 2x105 ohms, and 1 R = 3000 ohms.
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~ Refexring now to FIG. 2, there is illustrated a ~,.'' .
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g bidirectional switch which comprises gated diode switches GDS3 and GDS4, with the anode of GDS3 coupled to the cathode of GDS4, the cathode of GDS3 coupled to the anode of GDS4, and the gates of both being coupled together. The gates of GDS3 and GDS4 can be coupled to terminal 22 of the control circuit 10 of ; FIG. 1 instead of GDSl being coupled thereto. The state of GDS3 and of GDS4 can thus be controlled in essentially the same manner as is described for the aontrol , 10 of GDSl.
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Referring now to FIG. 3, there is illustrated control circuitry 100 which is coupled to a gated ~` diode switch GDS10 having anode, cathode, and gate terminals. Control circuit 100 is similar to control ~ 15 circuit 10 of FIG. 1, except that diodes Dl and D3 ; are eliminated and a current mirror circuit con-`~ figuration comprising p-n~p transistors Q2 and Q3 is used. Q2 and Q3 are switching devices in which the bases may be denoted as control terminals and the collectors and emitters may be denoted as first and second output terminals, respectively. Components ~ and terminals of FIG. 3 which are similar to those of ,~ FIG. 1 have the same reference denotation with an additional "0" at the end. -The emitters of Q2 and Q3 are coupled together to terminal 140 and to power supply +V10. The bases of Q2 and Q3 are coupled together to the collector of Q2 and to a first terminal of CL10 and to a terminal 30. The collector of Q3 is coupled to the gate of GDS20, a first terminal of CL30, and to a circuit terminal 200. Essentially all other components and interconnections are similar to those of the circuitry - of EIG. 1.

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The combination of D20~ Q10, R10, Q27 Q37 CL10, and CL30 'illustrated within dashed line -` ` rectangle B) is denoted as a voltage control branch circuit and is adapted to set the potential o terminal 200 so as to control the state of GDS20.
~ With an appropriate high level voltage i; Ctypically +2 to 5 volts~ applied to terminal 160, ~ Q10 is biased on and conduction from power supply `?," ~V10 through Q2, CL10, Q10, R10, and into po~er ~`~ 10 supply VSS0 occurs. Q2 and Q3 are essentially -` identical transistors. It is well known that this configuration of Q2 and Q3 results in essentially the same current flow through Q2 as flows through Q3. With -` Q10 biased on~ the potential o$ terminal 200 is at the ;~ 15 potential o$ ~V10 minus the VCE of Q3. With a low ``"
~`~ level input signal ~0-0.4 volts) applied to ter~inal 1607 Q10 is biased off and there is no conduction through Q10 and Q2. Thus there is no conduction through '`~ Q3. Terminal 20Q is thus pulled towards the potential of approximately -V40 until the anode-gate junction of GDS20 is for~ard-biased and causes terminal 200 to . assu~e a potential level near but somewhat less positive than that of ~V20.
~V10 is selected to be more positive than , 25 ~V20 and the potential of -V~0 is selected to be more negative than ~V20. The operation of GDS20 to control the state of GDS10 is essentially the same as has ~een described for the operation of GDS2 of FIG. 1. The use - of the same potentials for the power supplies of FIG. 3 as the corresponding power supplies of FIG. 1 results in ~ a circuit which facilitates the control of the state of GDS10 with ~220-volts at the anode and/or cathode. The varying of the potential of terminal 200 causes GDS20 to , operate in a similar mode as corresponding GDS2 o~
FIG. 1. Thus the state of GDSlQ is controlled in the same manner as the state of corresponding GDSl of FIG. 17 . ~, . .

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The complementary transistors Q10 and Q2 or Q3 can be fabricated on the same integrated circuit chip as GDS20 with both formed using dielectric isolated structures.
;~ The embodiments described herein are intended to be illustrative of the general principles of the ~ present invention. Various modifications are possible `~ consistent with the spirit of the invention. For example, various other control circuits can be substituted for those illustrated coupled to the gates of GDS2 and GDS20 of FIGS. 1 and 3, respectively, in order to provide the voltage levels and current drive (sourcing) capability needed to control the state thereof. Still further, the n-p-n transistors can be replaced by p-n p transistors provided the polarities o~ the power supplies are appropriately modified as is well known in the art. Still further Rl and R10 can be pinch -~
resistors. StiIl further the emitters of Ql, and Q10 can be coupled directly to VSS and VSS0, respectively.
. In this case, current limiting means, typically a resistor, would then be inserted in series with the - respective input terminals, 16 and 160.

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Claims (16)

Claims:

1. Circuitry for use with a first gated diode switch of the type comprising a semiconductor body a bulk portion of which is of a relatively high resistivity, a first region of a first conductivity type and of a relatively low resistivity, a second region of a second conductivity type opposite that of the first conductivity type, the first and second regions being connected to output terminals of the switching device, a gate region of the second conductivity type, the first, second and gate regions being mutually separated by portions of the semiconductor body bulk portion, the parameters of the device being such that, with a first voltage applied to the gate region, a depletion region is formed in the semi-conductor body which substantially prevents current flow between the first and second regions, and that, with a second voltage applied to the gate region and with appropriate voltages applied to the first and second regions, a relatively low resistance current path is established between the first and second regions by dual carrier injection CHARACTERIZED BY
a second gated diode switch of the same type as said first gated diode switch, an output terminal of the second gated diode switch being coupled to the gate of the first gated diode switch; and a voltage control branch circuit coupled to the second gated diode switch for controlling conduction between the first and second regions thereof.

2. The circuitry of claim 1 CHARACTERIZED IN THAT
the voltage control branch circuit coupled to the second gated diode switch comrises a first switching device having a control terminal and first and second output terminals, and a first current limiter coupled to the first output terminal of the first switching device.

13.

3. The circuitry of claim 2 FURTHER CHARACTERIZED BY
a second current limiter being adapted to limit current to a significantly lower magnitude than the first current limiter and being coupled to an output terminal of the second gated diode switch.

4. The circuitry of claim 3 CHARACTERIZED IN THAT
the switching device is a junction transistor with the collector being coupled to the first current limiter.

5. The circuitry of claim 4 CHARACTERIZED IN THAT
the first current limiter is adapted to be coupled to a first potential source and that the output terminal of the second gated diode switch is adapted to be coupled to a second potential source which is less positive than the first potential source.

6. The circuitry of claim 5 FURTHER CHARACTERIZED BY
a first resistor coupled to the second output terminal of the first switching device and by a second resistor being coupled to an output terminal of the second gated diode switch.

7. The circuitry of claim 6 FURTHER CHARACTERIZED BY
a third resistor and a first capacitor which are both coupled to the second resistor.

8. The circuitry of claim 7 FURTHER CHARACTERIZED BY
a third current limiter coupled to the gate region of the second gated diode switch.

9. The circuitry of claim 5 FURTHER CHARACTERIZED BY
a first diode having a cathode coupled to the gate of the second gated diode switch and having an anode coupled to the first output terminal of the first switching device.

14.

10. The circuitry of claim 9 FURTHER CHARACTERIZED BY
a second diode having an anode which serves as an input terminal and having a cathode which is coupled to the base of the transistor.

11. The circuitry of claim 10 FURTHER CHARACTERIZED BY
a third diode having an anode coupled to the anode of the first diode and having a cathode coupled to the first output terminal of the first switching device.

12. The circuitry of claim 5 FURTHER CHARACTERIZED BY
second and third switching devices each having a control terminal and first and second output terminals;
the second output terminals of the second and third switching devices being coupled together to a first circuit terminal and being adapted to be coupled to the first potential source;
the control terminals of the second and third switching devices and the first output terminal of the second switching device being coupled together to the first current limiter and to a second circuit terminal; and the first output terminal of the third switching device being coupled to the gate of the second gated diode switch and to a third circuit terminal.

13. The circuitry of claim 12 CHARACTERIZED IN THAT
the second and third switching devices are both junction transistors with the control terminals being the bases and the first and second output terminals being the collectors and emitters, respectively.

14. The circuit of claim 1 being CHARACTERIZED IN THAT
the voltage control circuit branch comprises a first switch branch having a control terminal which is coupled to an input terminal and having first and second output terminals, a second switch branch having a control 15 .
terminal coupled to the first output terminal of the first switch branch and having first and second output terminals with the first output terminal being coupled to an output terminal of the second gated diode switch, and a level shifting branch having a first terminal coupled to the second output terminal of the second switch branch and having a second terminal coupled to the gate of the second gated diode switch.

15. The circuitry of claim 14 CHARACTERIZED IN THAT
the first switch branch is a n-p-n transistor, the second switch is a p-n-p transistor, and the level shifting branch is a p-n diode.

16. The circuitry of claim 14 CHARACTERIZED IN THAT
the first switch branch is a first n-p-n transistor and the second switch branch is the combination of a p-n-p transistor, a second n-p-n transistor, and a third n-p-n transistor.
the collector of the first n-p-n transistor is coupled to the base of the p-n-p transistor;
the collector of the p-n-p transistor is coupled to the base of the second n-p-n transistor;
the emitter of the second n-p-n transistor is coupled to the base of the third n-p-n transistor;
the emitter of the third n-p-n transistor is coupled to an output terminal of the second gated diode switch; and the level shifting branch comprises first, second and third p-n diodes which are serially connected together with the cathode of the first coupled to the anode of the second and the cathode of the second coupled to the anode of the third.