CA1153795A

CA1153795A - Digital phase/frequency locked loop

Info

Publication number: CA1153795A
Application number: CA000405177A
Authority: CA
Inventors: Gordon C. K. Tsang
Original assignee: MULTI - DIMENSION Ltd
Current assignee: MULTI - DIMENSION Ltd
Priority date: 1982-06-15
Filing date: 1982-06-15
Publication date: 1983-09-13

Abstract

DIGITAL PHASE/FREQUENCY LOCKED LOOP

ABSTRACT OF THE DISCLOSURE

A digital extended linear phase range phase-frequency detector is applied in a phase locked loop to provide a low noise frequency spectrum output and a fast acquisition time. This phase-frequency detector comprises a differential latch, an up/down counter and a digital to analog (D/A) converter.
The D/A converter may be a resistor network type or a digital frequency rate multiplier. The loop provides a large pull-in range and locking range. The initial acquisition can be further aided by external logic or processor control.
If phase error is not considered, the circuit can be arranged as a frequency locked loop. An input frequency to be tracked is applied to the count-up input of the counter. The D/A converter receives the counter's parallel output and provides an analog signal representative of the counter value. The analog signal is filtered and applied to a voltage controlled oscillator, the output of which is applied to the count-down input of the counter.

Description

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This c~pp~ication is reltLted to my Canadian paten~ application Serial No. 380,712 filed June 26, 1981.
This invention relates to a frequency or phase locked loop in which frequency or phase comparison between an input signal and a signal fed back from a voltage controlled oscillator is accomplished by digital means.
A phase locked loop (PLL) is a circuit that permits an external input signal to control the frequency and phase of an oscillator in the loop.
The loop oscillator frequency can be the same as, or a multiple of, the input frequency. They are often used in circuits such as tracking filters, FSK decoders, Fhl stereo decoders, FM demodulators, frequency synthesizers and pulse code modulation synchronization.
Normally, most phase comparators or detectors behave linearly only when there is a small phase error; when the phase error exceeds a certain range, the detector's non-linear response causes intermodulation noise~
slipping cycle and out of lock problems. The present invention, on the other hand, can provide linear phase-frequency detection, as in charge-pump phase-locked loops, but over a much larger active phase range.
In the present invention, the phase comparator ltselt is comprisecl of a digital up/down counter means. The loop has extremely wide locking and pull-in ranges and, in one early prototype, was tested to lock from a frequency of less than lKHz to approximately 5MHz, and depending on components used appeared to be able to lock between less than 1 Hz to microwave range by adjusting the time constant of a filter connected to the output of the com-~ parator. The acquisition range is theoretically infinite. The filter used - does not require large time constant external elements needed in prior art phase locked loop circuits, since in the present invention the equivalent time constant of the low pass filter is amplified by the count ratio of the counter ,, ~

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means. Only a small time constant is reqllired ln the external filter.
Furthermore, due to an integration effect by the up/down counter, the loop's bandwidth depends on the count ratio, as does the pull-in range of the loop. There:~ore, for an equivalent loop's noise bandwidth design, this invention requires a smaller external low pass filter time constant than other phase detectors. The smaller external low pass filter time constant provides the possibility of using a small value low leakage capacitor. Noise generation due to the loop's filter leakage is small.
Concerning acquisition, there are two modes of operation that can be provided by this invention. The first is self-acquisition and the second is external aided acquisition.
For the first mode, the invention provides a limitation of counting when the system is out of lock. When the input frequency is much higher than the feedback frequency, the up/down counter counts up and stays at the maximum until the feedback frequency is slightly higher than the input frequency.
Similarly, when the input frequency is much lower than the feedback frequency, the counter stays at the minimum until the input frequency is slightly higher than the feedback frequency. In either case, self acquisition can be achievecl.
For the second mode, the invention provides external logic means (normally processor~ control which aids fast acquisition. When the input frequency is unknown and there is an out of lock situation, the counter means will be enabled section by section. This is equivalent to providing a phase locked loop with variable bandwidth since fast acquisition is easier to obtain with broad loop bandwidthO There is another method to achieve acquisition nearly instantly. All count ratios from the up/down counter for input fre-quencies of interest may be stored by the external logic means. ~henever there is a need for frequency changing or locking again, the appropriate count

- 2 -ratio can be immediately trans~erred from the external logic means to the up/down counter means.
Parallel outputs of the counter means may be converted into an analog signal by a translation means such as a resistor network type D/A
converter. Other kinds of D/A conversion are also possible such as frequency rate multipliers or switching capacitor types.
The circuit according to the invention can also be used in con-junction with a frequency rate multiplier, instead of a D/A converter, for accurate control of apparatus which depends on an average voltage input and which incorporates a low pass filter action, such as the rotation rate of a motor.
If the counter is of low capacity, e.g. 1 or 2 bits, the circuit according to the invention can closely track the phase of an input signal, as well as its frequency. However, if a counter of fairly large capacity, e.g. 8 bits ~binary), is usedJ the phase of the VCO may differ substantially from that of the input frequency, even though the frequency will be accurately followed. For lack of a better term, the circuit according to the invention may be called a phase/frequency locked loop.
In accordance with one broad aspect of the invention there is provided a phase/Erequency locked loop comprising a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback sigilal pulses, a first output connected to a count-up input of a digital up-down counter, and a second output connected to a count-down input of said counter, said counter having parallel outputs connected to a digital to analog converter having an output for providing an analog output signal representative of a count in said counter, the output of the digital to analog converter being connected to control a voltage controlled oscillator which 7~

generates said ~eed~ack signal pulses at a rate corresponding to said analog output signal, said differential latch being so constructed that non-overlap-ping output pulses are produced at said first and second outputs in response to pulses applied to said first and second inputs.
In accordance with another broad aspect of the invention there is provided a frequency locked loop comprising a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a coun~-up input of a digital up-down counter, and a second output connected to a count-down input of said counter, said counter having parallel outputs which, except for the least significant bit, are connected to a digital to analog converter having an output for providing an analog signal representative of a count in said coun-ter, the output of the digital to analog converter being connected to control a voltage controlled oscillator which generates said feedback signal pulses at a rate corresponding to said analog output signal, said differential latch being so contructed that non-overlapping output pulses are produced at said first and second outputs in response to pulses applied to said firs-t and second inputs.
In accordance with a further broad aspect o~ the invention there :is provided a phase/frequency locked loop comprislng a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a count-up input of a digital up-down counter, and a second output connected to a count-down input of said counter, said counter having parallel outputs connected to translation means for generating said feedback signal pulses at a rate related to the output of the counter, said differential latch being so constructed that non-overlapping output pulses are produced at said first and second outputs in

3~ 5 response to pulses applied to said first and second inputs.
A better understanding of the invention will be obtained by reference to the detailed description below, in conjunction with the ~ollowing drawings, in which:
Figure 1 is a block schematic of a basic form of the invention, Figure la is a waveform diagram used to illustrate the operation o~
the invention, Figure 2 is a block diagram of the preferred embodiment of the invention, Figure 3 is a block diagram of the invention illustrating the use of external logic control, Figure 4 is a logic diagram of a preferred form of differential latch which may be used with the invention, and Figure 5 is a partly block schematic and partly detailed schematic diagram of another embodiment of the invention.
Turning now to Figure 1, input signals from an input source 1 are applied via line 50 to one input of a differential latch 2 having an output Qll line 52 to the count-up input CU of a digital up/down counter 4. Counter ~
may comprise a plural:ity of ~-bit sections, e.g. two sections. The parallel outputs 5 of counter ~ are connected to corresponding inputs of a digital-to-analog converter 6. The output of digital-to-analog converter 6 is connected to the input of an optional low pass filter 7 of conventional form. The output of the filter 7 is connected to the input of a voltage controlled oscillator 8 the pulse output of which is connected via a line 51 to a second input of the differential latch 2. ~n optional divider 9 may be connected in series hetween ; the voltage controlled oscilla~or 8 and the differential latch 2 if the output o the ~C0 is a multiple of the input frequency from source 1.

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In operation, input signal pulses, which can be generated by an oscillator or derived from another source which is to be tracked, are applied to the up-count input of counter 4 through differential latch 2. The operation of the differential latch will be described in more detail later. The counter

4 counts up by one with each pulse of the input signal on line 50.
The resulting count signal in counter 4 is applied in parallel via lines 5 to the digital-to-analog (D/A) converter 6. The analog voltage output of D/A converter 6 is applied through low pass filter 7 to voltage controlled oscillator (VCO) 8. VC0 8 produces an output signal having a pulse repetition rate which is dependent on the amplitude of the analog voltage signal from filter 7. The output of VC0 8 is applied via output 53 of differential latch 2 to the down count input CD of counter 4. As a result counter 4 is caused to count down by one with each pulse from VCO 8.
In the stable condition, the output pulse rate of VC0 8 (divided or multiplied if necessary) is the same as the pulse rate of the input signal.
Consequently for every input pulse applied to the up count terminal, there is a pulse applied to the down count terminal of counter 4. The resulting binary output signal from counter 4 is, in the ideal condition, essentialLy stable, causing a constant analog output voltage from D/A converter 6. ~ilter 7 thus has virtually a D.C. signal to filter. The unchanging D.C. signal applied to voltage controlled oscillator 8 causes a stable output signal to be generated.
Immediately, it will be observed that the signal applied to VCO 8 always has a finite average level. In the event the input frequency or leading phase slightly increases, the difference between the phase of the input signal and the phase of the signal from VCO 8 results in a longer duration of the higher count in counter 4. For example, in the steady state, the count in counter 4 might alternate between, say, 181 and 180 (decimal) in response to :

~3'~5 pulses froDI the input sowrce l ancl the VC0 8 but a slight incre.lse in the input frequency would result in the counter 4 holding the count 181 for a longer time. Conversely, if the resulting outpu~ frequency from the voltage controlled oscillator 8 increases slightly, the difference between the phase of the input signal and the phase of the signal from VC0 8 results in a shorter duration of the higher count (181 in the example). In other words, the average count in counter 4 varies and this results in a higher or lower average ampli-tude analog signal being generated by the D/A converter 6 which, in turn, results in the output frequency of the VC0 8 being raised or lowered.
If the input frequency or leading phase increases by a sufficiently large amount, the average count of the counter 4 will increase correspondingly.
In the case of the example given, the count in counter 4 might then alternate between, say, 184 and 183, for a higher average count than before. The reverse would happen for a sufficiently large decrease of the input frequency.
A higher average count of the counter 4 results in a higher average amplitude analog signal being generated by the D/A converter 6. This results in the output frequency of VC0 8 being raissd, increasing the rate of the down count in counter 4. The duration of higher count or the average count of counter 4 thus decreases, causing the average analog output signal to reduce.
If the resulting OlltpUt frequency rom VC0 8 increases to a higher level, the difference between the phases of the input signal and the signal from VC0 8 results in a shorter duration of higher count or lower average count of counter 4. This results in a lower average amplitude signal being generated in D/A converter 6. This results in the output frequency of VC0 8 being reduced. The circuit has thus been found to be highly stable.
Of course a person skilled in the art understanding this invention will reali~e that with the addition of an inverter at the output of the D/A

converter or fllter, the voltage applied to the voltage controlled osciLlator will be driven oppositely to that described abov0, and hence ~he input signals applied to the up and down count inputs of the counter should be reversed.
It was noted above, that in an early prototype of this invention, the circuit was measured to be stable with input signals varying from less than lKHz to approximately 5M~1z with adjustments to the time constant of filter 7. It appears to be able to lock between frequencies a-t least between less than l Hz and microwave range if appropriate devices are used in -the ci-rcuit.
As will be explained in more detail below in connection with Figures 2 and 3, the counter may be pre-set to any desired count via lines 24 from external logic means, e.g. a microprocessor. Also, the counter can be set to maximum count in the event of a carry C from counter 4, this carry being applied via AND gate 21, when enabled by a pulse SLD~ to the PE ~pre-load enable) pin of counter ~. The timing and duration of SLD is controlled by logic circuitry but the duration is selected in dependence on the time constant of filter 7; i.e., it must be sufficient to allow the filter to "settle" after its input is suddenly changed, assuming the optional filter 7 is used.
While the above explanation of the operation of the invention is ideal, a practical circuit requires certain additional elemen-ts. ~or example, one cannot simultaneously count up and co~mt down in a digital up-down counter.
Consequently a differential latch is provided whereby non-overlapping input and output signals of the voltage controlled oscillator can be applied to the up-count and down-count inputs of the counter. Ihe differential latch 2 ensures that, when a pulse leading edge from the input source 1 is changing to high, resulting in a count up of counter 4, a pulse leading edge from voltage control oscillator 8 will not be passed through -to the down count input of counter ~
immediately, and vice versa. Preferably, it is the leading edge of both the 7~
input and voltage controlled oscillator signals which cause up and down counts to occur in counter 4.
As a result of the incremental and alternating increase and decrease of the count in counter ~, the actual output signal jitters about a higher and lower count, as explained above. Consequently the analog output signal of D/A
converter 6 is not a clean, level D.C. signal, but actually is a very low amplitude pulse signal superimposed on a DC signal, varying at the difference frequency between the input and feedback signal from the voltage controlled oscillator. The low pass filter clearly need only have a relatively short time constant as compared to prior art filters used to filter the signal applied to the voltage controlled oscillator in a phase locked loop.
As mentioned above, carry C output of the counter is connected so as to set the counter high. Thus, if the input frequency is very much larger than the feedback frequency, a carry signal is generated and sets the counter so that all counts are at high ~maximum) level, resulting, of course, in maximum voltage being applied to VC0 8.
The borrow B output is connected through an inverter 10 to reset the counter to zero. Therefore, i the input frequency is very much lower than the feedback frequency, a borrow signal is generated, which resets the counter to zero, resulting in mininum voltage being applied to VC0 8.
It should be noted that up-down ccunters require edge triggering, and since both the up and down counts may not be low at the same time, the differential latch circuit is utilized to eliminate any missing clock inputs, retaining either one of the two inputs high at any given time.
It should also be noted that the present circuit differs from a traditional phase locked loop, in that the latter creates a zero phase error signal or a 50% duty cycle square wave signal when both the input and feedback error signals are oE the same frecluency, while the present circui-t creates phase between the two signals which can be between zero and 360 degrees when their frequencies are equal. After it has been locked, it avoids the cycle slipping problem caused by noise jitter input.
Figure la is a waveform diagram illustrating the operation described above. Waveorm 200 depicts a representative input signal, waveform 201 depicts a representative feedback signal from VCO 8, and waveform 203 repre-sents the output signal from D/A converter 6. It may be seen that the widths of the pulses in waveform 203 represent the phase difference between the input and feedback signals. The amplitude of waveform 203 is the average count output divided by the counter's colmt ratio and multiplied by the peak-to-peak D/A converter output scale. The height of ripple (pulse) of waveform 203 is one divided by the counter's count ratio and multiplied by the peak-to-peak D/A converter output scale.
The waveforms of Figure la are primarily intended to show timing relationships rather than amplitude relationships.
After filtering in filter 7 the filtered signal applied to the voltage controlled oscillator 8 is shown as waveform 204.
The voltage controlled osclllator can of course be driven at a zo multiple ~or fraction) of the input signal. In this case a divider 9 (or rate multiplier) would be used to generate the feedback signal applied to differen-tial latch 2 via line Sl.
Turning now to Figure 3, the phase/frequency detector and low pass filter are shown as a single block 3010 The input signal to be tracked is applied to the input of phase-frequency detector block 301 via signal line 50.
The output signal from the low pass filter of block 301 controls the voltage controlled oscillator 8. The feedback signal from the voltage controlled , .. ~

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oscillator 8 is fed to another input of phase-frequency detector block 301 via signal line 51. The detail~d schematic of block 301 is shown in -figure 2 which will be descrlbed below. Thus the servo loop is colmpleted. At the same time, count ratio data may be outputted by external logic ~eans such as a processor or logic control 300 to phase-frequency detector and low pass filter block 301 via signal lines 24. The data entering block 301 is enabled by signal SLD on line 13. The selection of the number of up-down counter stages in block 301 is controlled by signal SEL on line 22. Detailed operation will be described later. The up-down counter output can be inputted by the pro-cessor or logic control block 300 via signal lines 5~
Referring to Figure 2, which is more detailed than Figure 1, asignal which is to be tracked is applied by source 1 via signal line 50, differential latch 2 and selector 17 to the count-up input CU of up-down counter 3. The carry signal from the C output of co~mter 3 is applied via selector 19 to the count-up input CU of up-down counter ~1. The parallel outputs 5 of counters 3 and ~ are connected to corresponding inputs of digital-to-analog converter 6. The output of D/A conve:rter 6 is connected to the input of a low pass filter 7 of conventi.onal form. The output of the filter is connected to the input of a voltage controlled oscillator 8, the output of which is connected via a circuit path 51, to the i.nput of the differential latch 2. An optional divider 9 may be connected in series with the circuit path between the voltage controlled oscillator and the differential latch.
The operation of counting up with the input signal and down with the feedback signal is as described above in connection with Figure lo Turning back to Figure ~, a pair of 4 bit up-down counters 3 and is connected as an 8 bit counter. The selection of sections in the counter can be programmabLe, by signal S~L Oll line 22, thus providing controllable loop bandwidths.
Selectors 17 and 18 block output signals from differential latch 2 to counter 3 when four bit mode is set by select signal SEL 22 (SEL signal low). At this time, output signals from differential latch 2 are routed through selectors 19 and 20 to counter 4. Thus only the most significant 4 bit counter is activated, i.e. counter 4.
When SEL 22 is set to select 8 bit mode (SE~ signal high), output signals from differential latch 2 are routed to counter 3 through selectors 17 and 18. Carry and borrow signals from counter 3 are routed through selectors 19 and 20 to counter 4.
Any predetermined count ratio may be loaded into the counters 3 and 4 from external logic control means~ e.g. a microprocessor, via lines 24 and OR gates 40-47. A carry C from counter 4 is applied via delay device 10, inverter 23 and OR gates 40-47 to set counters 3 and 4 to maximum count.
The carry C output of counter 4 is connected to the PE ~pre-load enable) inputs of co~mters 3 and 4 through the delay device 10 and AND gate 21. The borrow B output of counter 4 is connected through a delay device 11 and inverter 12 to the MR (reset) inputs of counters 3 and 4. The delay devices 10 and 11 are used to guarantee minimum pre-load and reset timing of the up/down counter but are not essential.
The QO - Q3 parallel outputs 5 of both counters are connected to the parallel inputs of digital-to-analog converter 6. The parallel outputs 5 of both counters may also be read or inputted by external logic or processor via lines 5 and 24 as shown in ~igure 3. The output o~ converter 6 is connec-ted to the input of a low pass filter 7 of conventional construction, which may be a passive filter comprised of series resistor 14, shunt resistor 15 and ~ PJ~.~

capacitor 16 comlected to its output. Resistor 1~ is connected to the frequen-cy control input of voltage controlled oscillator 8. The output of voltage controlled oscillator 8 comprises digital pulses.
Turning to Figure 4, the operati.on of the differential latch 2 will now be explained. In this preferred embodiment the differential latch utilizes four flip-flops 100, 101, 102 and 103. The DATA D and SET S terminals of flip-flops 100 and 102 are connected to a source of potential PV(high), and the DATA D and CLOCK C terminals of flip-flops 101 and 103 are similarly connected. I'he Q output of flip-flop 100, the Q output of flip-flop 103, the output of AND gate 111, and the output of NAND gate lC6 are connected to corresponding inputs of NAND gate 104. The output of NAND gate 104 is connec-ted to an input of NAND gate 109 and the SET terminal of flip-flop 101. The Q
output of flip-flop 100 is connected to the input of delay device 113. Delay device 113 is used to guarantee that a low pulse width will be generated at the Q output of flip-flop 101. The output of the delay device 113 and the Q
output of flip-flop 100 are connected to inputs of OR gate 11~. The output of OR gate 114 is connected to the R terminal of flip-flop 101. The output of NAND gate 10~ and the Q output of flip-flop 102 are connected to inputs of NAND gate 106. The Q output of flip-flop 101 and -the output of AND gate 111 are connected to inputs of AND gate 105, which has its output connected to the R terminal of flip-flop 100. The Q output of flip-flop 102 and the output of NAND gate 112 are connected to inputs of NAND gate 109. The output of NAND
gate 109 is connected to the input of a delay device 110 and the input of AND
gate 111. The output of AND gate 111 is connected to an input of AND gate 105 and AND gate 107.
The Q output of flip-flop 101, the Q output of flip-flop 102, the output of A~lD gate 111 and the output of NAND gate 108 are connected to inputs `~j" ,;

s of NAND gate 112. The ou-tput o NAND gate 112 is connected to an input of NAND gate 108 and to the S terminal of flip-flop 103. The Q output o:E flip-flop 102 is connected to the inpwt of delay device 115. Delay device 115 is used to guarantee a minimum pulse wldth from the Q output Oe flip-flop 103.
The output of the delay device 115 and the Q output of flip-flop 102 are connected to inputs of OR gate 116. The output of OR gate 116 is connected to the R terminal of flip-flop 103. The output of NAND gate 112 and the Q output of flip-flop 100 are connected to the inputs of NAND gate 108. The Q output of flip-flop 103 and the output of AND gate 111 are connected to inputs of AND gate 107, the output of which is connected to the R terminal of flip-flop 102.
In operation, assuming that a positive edge appears on the input signal lead 50, causing the output of flip-flop 100 to go high, if there is simultaneously a low level on the Q output of flip-flop 102, there will be a low output from NAND gate 10~ and thus the Q output of flip-flop 101 is set to low. Due to the low level of the Q ou-tput of flip-flop 101, the flip-flop 100 is reset through AND gate 105. The low level Q output of flip-:Elop 100 delayed by delay device 113 will reset the flip-flop 101 again. Thus a narrow low level pulse is generated at the Q output of flip-flop 101. This low level pulse is applied to the count up input CU of the up-down counker via line 52.
Similarly, the presence of a feedback positive edge appears on signal path 51, causing the Q output of flip-flop 102 to go high. If there is simultaneously a low level on the Q output of flip-flop 100, there will be a low level output from NAND gate 112 and thus the Q output of flip-flop 103 is set to low. Due to the low level Q output of flip-flop 103, the flip-flop 102 is reset via AND gate 107. The low level Q output of flip-flop 102, delayed by delay device 115, will reset the flip-flop 103. Thus a narrow low level - 1~ -. ~

pulse is generated at the Q output oE flip-flop 103. This low level pulse is applied to the count-down input CD of the up-down counter via line 53.
If a positive edge is applied to flip-flop 102 on line 51 slightly later than one applied to flip-flop 100 on line 50, and either the Q output of flip-flop 100 is high or the Q output of flip-flop 101 is low, the low level signal required to set flip-flop 103 is prohibited by NAND gate 112. Flip-flop 102 will latch the high signal ~mtil the generation of a low level pulse at flip-flop 101 is completed. At this time, a low level signal output from NAND gate 112 sets the flip-flop 103 and another low level pulse generation cycle is carried out at the Q output of flip-flop 103. Similarly, if a positive edge is applied to flip-flop 100 slightly later than the one applied to flip-flop 102, a low level pulse will be generated at the Q output of flip-flop 103 first and then another low level pulse will be generated at the Q
output of flip-flop 100 afterwards.
If positive going pulse edges arrive at flip-flops 100 and 102 at almost the same time, the output of AND gate 111 is connected to the inputs of AND gates 105 and 107 which are used to reset both input signals if a latch up race condition occurs. Delay device 110 is used to provide temporary disable of any illegal set pulse to flip-flop 101 or 103 which is due ko reset timing offset of flip-flops 100 and 102 generated from NAND gate 104 or 112 during the time that NAND gate 109 output resetting action is in progress.
Similar to other phase locked loop circuits, component values used depend on the loop bandwidth requirement, damping factor, D/A converter output voltage scale and voltage controlled oscillator gain. In a successful proto-type, a natural frequency was 1 KHz, damping factor was .707, voltage controlled oscillator gain was lOOKHz per volt, D/A converter peak to peak output was 10 volts, resistor 14 was i,ooo ohms, resistor 15 was 220 ohms and capacitor 16 was 100,000 picofarads. The D/A converter was an 8-bit type with current to voltage conversion built-in. Delay devices were 15 ns digital type.
It has been found that the invention described above has an extremely wide lock range and capture range. The structure operates as a frequency and phase comparator, of a type which has been found not to lock onto harmonics of the reference signal.
It should be noted also that if the parallel outputs of the counter to the converter are arranged such that the count up and down of the least significant bit is not sensed by the digital-to-analog converter, the circuit represents an extremely large time constant digital filter. In this mode of operation, it may be considered as a frequency locked loop.
The circuit can be used as a modulator and demodulator for FSK, since the circuit clearly reacts with the frequency of the input signal. The input signal can of course be received from any desired source, or can be generated by a crystal or other oscillator.
Digital-to-analog converters are commonly fabricated using a resistor network. The resistor network can be made non-linear in order to provide an inverse curve to any non-linearity in the response characteristic of the voltage controlled oscillator 8. A highly linear circuit can thus be achieved.
Lowest noise and intermodulation can be achieved in this way.
It is also contemplated that to follow fast changing input frequen-cies~ such as would be used for navigation, radar, con~unication channel selection, etc., the counters can be preset to specific counts in order to preset specific frequencies at a rapid rate, which can be effected either under process or other logic control.
It is also contemplated that a plurality of phase locked loops as described above can be connected in parallel or series to generate very stable ~3'7¢~

frequencies having different intcrval digital time constants. The signals can be mixed together to obtain extremely high resolution stable signals, e.g., for use in a frequency synthesizer, but still with a very ast capture time and clean frequency spectrum, which as is well known is very complicated to achieve.
Figure 6 is a bloc~ schematiG of a second embodiment of the invention.
An input signal source 1 is connected to differential latch 2, which itself is connected to the up count and down count inputs of up-down counter 4. The parallel outputs 5 of counter 4 are connected to parallel inputs of a frequency rate multiplier 31. The C output of counter 4 is connected to the PE input of counter 4 through the delay device 10. The B output of counter 4 is comlected to the MR input of counter 4 through delay device 11 and inverter 12.
A high duty cycle fixed frequency signal 30 ~e.g. approximately lOKHz, the duty cycle and frequency limit determined by the characteristics of the driver transistor and motor described below) is applied to the clock C
input of frequency rate multiplier 31. The output 0 of frequency rate multi-plier 31 is connected through a very low value resistor 32 to the input of a vmos type driver transistor 33. The drain of trans:istor 33 is connected to a D.C. motor 34 which has a diode 37 connected in parallel, the other terminal of which is connected to a power source with voltage VCCu In a successful prototype, the up/down counter 4 was two 4 bit binary up/down counters cascaded into an 8 bit oneO The frequency rate multi-plier 31 was two 4 bit binary multipliers ~CD4089) cascaded in an "addition"
mode. Diode 37 helps to remove back EoM~F~ and transients during switching.
A rotation rate sensor 35 (e.g. hall effect sensor) is located adjacent a rotating element of motor 3~. Its output is connected to the input of sense amplifier 36. Amplifier 36 provides a digital output connected to the :input 51 of cli~ferential latch 2.
Any differences between the frequency or phase o~ the feedback signal with the input signal results in a change in the count output from counter ~ thus applying a different binary value to rate multiplier 31. The number of pulses applied to D.C. motor 3~ thus changes, which eEfectively increases or decreases the average D.C. level, causing a corrective change to the D.C. motor rotation rate.
The high frequency harmonics are filtered by the mechanical time constant of the motor, and clearly only the average direct current applied to the motor will be sensed. A stable speed control is thus obtained.
The sensor 35 can be a llall effect sensor located adjacent the shaft of the D.C. motor, or can be a slotted ring used in an optical sensor by which pulses of light are sensed and amplified, or some other device providing a similar effect.

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SUPP~EMENTARY DISC~OSURE
The arrangement described in the principal disclosure operates entirely satisfactorily. ~lowever, it is possible to simplify the differential latch and two examples are shown in ~igures 4a and 4b in which parts similar to those used in Figure 4 are designated by the same reference numerals.
Turning to Figure 4a, the differential latch utilizes fli.p-flops 100, 102 and a number of logic gates. The DATA D and S terminals of flip-flops 100 and 102 are connected to a source of potential PV (high). The output of OR gate 114, the output of NAND gate 106 and the output of NAND gate 112 are connected to inputs of NAND gate 104. The Q output of flip-flop 100 is connected to the input of delay device 113. Delay device 113 is used to guarantee a minimum low pulse width timing at the output of NAND gate 104.
The output of delay device 113 and the output Q of flip-flop 100 are connected to inputs of OR gate 1140 The output of NAND gate 104 is connected to the R
terminal of flip-flop 100. The output of NAND gate 106 and output of NAND
gate 108 are connected to inputs of OR gate 109. The output of OR gate 109 is connected to one input of NAND gate 106 through inverters 110 and 111. The output of NAND gate 104 and the Q output of flip-flop 102 are connected to other inputs of NAND gate 106.
The output of OR gate 116, the output of NAND gate 104 and output of NAND gate 108 are connected to inputs of NAND gate 112. The output of NAND
gate 112 is connected to an input of NAND gate 108, an input of NAND gate 104 and the R terminal of flip-flop 102. The Q output of flip-flop 102 is conncc-ted to the input of delay device 115. Delay device 115 is used to guarantee a minimum pulse width from the output of NAND gate 112. The output of the delay device 115 and Q output of ~lip-flop 102 are connected to inputs of OR gate 116. The output of NAND gate 112 and the Q output of flip-flop 100 are

5~

connected to inputs of NAND gate 108.
Assume initially that both flip-flops 100 and 102 are reset so that their Q outputs are low. The Q output of flip-flop 100 is applied to one input of NAND gate 108 and the Q output of flip-flop 102 is applied to one input of NAND gate 106; thus at this time the outputs of NAND gates 106 and 108 are high. The low Q outputs of flip-flops 100 and 102 are applied via OR
gates 114 and 116, respectively, to an input of NAND gate 104 and NAND gate 112, respectively, so that their outputs are high at this time.
If an input pulse is received on line 50, i~s positive going edge will cause the Q output of flip-flop 100 to go high and this high will be applied via OR gate 114 to NAND gate 104. Thus, the output of NAND gate 104 will now go low and keep the outputs of NAND gates 106 and 112 high and flip-flop 100 will be reset. The low from NAND gate 104 is applied to the count up input ~CU) of the up-down counter. The high Q output of flip-flop 100 is also applied to one input of NAND gate 108, the other input of which is already high. Thus, the output of NAND gate 108 will now go low. The output of NAND
gate 112 stays high. The delay device 113 ensures a minimun pulse width from the output of NAND gate 104.
If a feedback pulse is received on line 51 ~with no input pulse on line 50), its positive going edge will clock flip-flop 102, causing its Q
output to go high. This high will be applied via OR gate 116 to NAND gate 112, the other inputs of which are already high. Thus, the output of NAND
gate 112 will go low and this low will be applied to ~he count down input CD
of the up/down counter via line 53.
The low from NAND gate 112 will also be applied to an input of NAND
gate 104, keeping its output high, even if a reference pulse is now received on line 50. Flip-flop 102 is reset by the output of NAND gate 112 and delay 115 ensures a minimum width output pulse from NAND gate 112.
If a positive going pulse edge is applied to flip-flop 102 on l:ine 51 slightly later than one applied to flip-flop 100 on line 50, elther the output of flip-flop lO0 will be high or the output of NAND gate 104 will be low. In either case, one input of NAND gate 112 will be low so that its output is held high. Flip-flop 102 will latch the high signal until the output of NAND gate 104 goes high again to enable NAND gate 112, at which time its output goes low, flip-:Elop 102 is reset, etc., as before. Similarly, if a positive going pulse edge is applied to flip-flop 100 slightly later than one applied to flip-flop 102 on line 51, one input of NAND gate 104 will be low so that its output is held high. Flip-flop 100 will latch the high signal until the output of NAND gate 112 goes high again to enable NAND gate 104, at which time its output goes low, flip-flop 100 is reset, etc.
If positive going pulse edges arrive at flip-flops 100 and 102 at almost the same time, the outputs of NAND gates 106 and 108 could both go low which would mean a deadlock condition. This condition is sensed by OR gate 109 which, with both inputs low, produces a low output. This low level signal is applied to one input of NAND gate 106 via invcrters 110 and 111 and causes the output of NAND gate 106 to go high. Thus a low level pulse is produced at the output of NAND gate 104 first and then another low level pulse is produced at the output of NAND gate 112. As a result, the latch-up ~deadlock) condition is resolved. Inverters 110 and 111 are used to delay the reset signal to prevent any oscillation occurring during the resetting of the latch-up condi-tion.
Another version of a differential latch is shown in Figure 4b in which pulses from a local oscillator are used to synchronize the timing which may be required for some applications.

~,, s Turning to ~igure ~b, this version of differential latch is imple-mented in a synchronous sampling pulse generation circuit. The data D and S
terminals of flip-flops 100 and 102 are connected to a source of potential PV
(high~. The S and R terminals of flip-Elops 101 and 103 are also connected to a source of potential PV (high). The Q output of flip-flop 100 and the Q
output of flip-flop 103 are connected to inputs of AND gate 120. The output of AND gate 120 is connected to the data D input of flip-flop 101. The output of a local oscillator source 130, typically 20 M~l~, is connected to the clock C input of flip-flop 101 and the input of inverter 121. The Q output of flip-flop 101 is connected to the reset terminal R of flip-flop 100 and one input of AND gate 123. The output of flip-flop 102 is connected to one input of AND
gate 123. The output of AND gate 123 is connected to the D input of flip-flop 103. The output of inverter 121 is connected to the C input of flip-flop 103.
The Q output of flip-flop 103 is connected to the R terminal of flip-flop 102 and one input of AND gate 120.
In operation, a positive edge appearing on the input signal lead 50 causes the outpu~ Q of flip-flop 100 to go high and it is latched unt:il it is reset by a low level pulse applied to its R terminal input. If there is simultaneously a high level on the Q output of flip-flop 103, the output of AND gate 120 will be high. Within one clock period of local oscillator 130, this high level signal applied to the D input of flip-flop 101 is clocked to cause the Q output of flip-flop 101 to go low. This low level signal is applied to the R terminal of flip-flop lO0, thus resetting the Q output of flip-flop lO0 and causing a low output from AND gate 120. When the next positive edge of a pulse from the local clock source 130 appears again at the C input of flip-flop lOl, the low level signal at the D input of flip-flop 101 is clocked to reset flip-flop 101 and cause the Q output of flip-flop 101 to .' ;~

S

go high again. As a result, a low level pulse oE duration e~ual to a local clock period is generated from the Q output of flip-flop 101 after a positive edge of a pulse appears on the reference signal line 50. This low level pulse is applied to the count-up input CU of the up-down counter via line 52.
Similarly, a positive edge appearing on the feedback signal lead 51 causes the output of flip-flop 102 to go high and it is latched. If there is simul-taneously a high level on the Q output of flip-flop 101, the output of AND
gate 123 will go high. Wi~hin one clock period of the local oscillator 130, this high level signal applied to the D input of flip-flop 103 is clocked to cause the Q output to go low. This low level signal is applied to the R
terminal of flip-flop 102, thus resetting the Q output and causing low output from AND gate 123. When the next positive edge of inverted local clock appears again at the C input of flip-flop 103, the low level signal applied at the D
input of flip-flop 103 is clocked to reset flip-flop 103 and cause the Q
output to go high again. As a result, a low level pulse of one clock period is generated from the Q output of flip-flop 103 after a positive edge appears on the feedback signal line 51. This low level pulse is applied to the count-down input CD of the up-down counter via line 53.
If a positive edge is ap-plied to flip-flop 102 on line 51 at almost the same time as one applied to f]ip-flop 100 on line 50, they will set the Q
outputs of both flip-flops 100 and 102 high and cause high signals to be applied to the D inputs of both flip-flops 101 and 103. At the same time, clock signals applied to the C inputs of flip-flops 101 and 103 are 1~0 degrees apart due to the inverting action of inverter 121. Thus the priori~y of low level pulse generation at the Q outputs of flip-flops 101 and 103 is resolved due to non-overlap of clock edges applied to the C inputs of flip-flops 101 and 103. Depending on chance, a positive edge may be applied first to either ~3~

the C input of -~lip--flop 101 or the C input of flip-flop 103. Assuming it is applied to the ~lip-flop 101 first~ a low level pulse signal is generated at the Q output of flip-flop 101 as described before. At the same time, the output of AND gate 123 is set to low by this low level pulse and thus the generation of a low pulse at the Q output of flip-flop 103 is prevented.
After the generation of the low level pulse at the Q output of flip-flop 101 finishes, the AND gate 123 output is enabled to be high again. The next positive edge ~half a clock period later) applied to the C input of flip-flop 103 will enable ~he generation of the low level pulse at the Q output of flip-flop 103. Similarly, the second case is that the generation of the low level pulse is carried out first at flip-flop 103. Then it is followed by another low level pulse generation at the flip-flop 101. As a result, the circuit provides resolving means through a local clock source for a possible race condition. If positive edges are applied to input 50 and feedback line 51 at almost the same time, the differential latch circuit will provide non-overlap-ping low pulses on signal paths 52 and 53 with a half a local clock period separation and no extra clock pulse will be missed or induced.
Flip-flops 101 and 103 constitute pulse width synchronization latches. These latches and associated logic means provide (a) low level output signal pulses of a local clock period duration, ~b) a minimum o~ half a local clock period separation between low level output signals applied to the up and down inputs of the counter.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A phase/frequency locked loop comprising a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a count-up input of a digital up-down counter, and a second output connected to a count-down input of said counter, said counter having parallel outputs connected to a digital to analog converter having an output for providing an analog output signal repre-sentative of a count in said counter, the output of the digital to analog converter being connected to control a voltage controlled oscillator which generates said feedback signal pulses at a rate corresponding to said analog output signal, said differential latch being so constructed that non-overlap-ping output pulses are produced at said first and second outputs in response to pulses applied to said first and second inputs.

2. A phase/frequency locked loop as defined in claim 1 in which the output of the digital to analog converter is connected to the voltage controlled oscillator via a low pass filter.

3. A phase/frequency locked loop as defined in claim 2 in which, during stable operation, the counter alternates between a lower and a higher count and said analog output signal comprises a low amplitude pulse duration modulated signal superimposed on a D.C. signal, the average amplitude of said modulated signal representing the instantaneous phase difference between the input signal and the feedback signal and said D.C. signal representing said lower count.

4. A phase/frequency locked loop as defined in claim 1, 2 or 3, in which the digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output.

5. A phase/frequency locked loop as defined in claim 1, 2 or 3, in which said digital up-down counter has a variable number of stages.

6. A phase/frequency locked loop as defined in claim 1, 2 or 3, in which said digital up-down counter has a variable number of stages, and in which the digital up-down counter includes a CARRY output and a BORROW
output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output.

7. A phase/frequency locked loop as defined in claim 1, 2 or 3 further including:
(i) means for presetting the counter, from external logic means, to a particular output value, (ii) means for transferring the counter's output value to said external logic means, (iii) means for selectively activating a number of counter sections from said external logic means.

8. A phase/frequency locked loop as defined in claim 1, 2 or 3, in which said digital counter has a variable number of stages and in which the digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output, said phase/frequency locked loop further including:
(i) means for presetting the counter, from external logic means, to a particular output value, (ii) means for transferring the counter's output value to said external logic means, (iii) means for selectively activating a number of counter sections from said external logic means.

9. A phase/frequency locked loop as defined in claim 1, 2 or 3 in which, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch.

10. A phase/frequency locked loop as defined in claim 1, 2 or 3, in which said digital up-down counter has a variable number of stages, and in which the digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output, and wherein, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch.

11. A phase/frequency locked loop as defined in claim 1, 2 or 3, in which said digital counter has a variable number of stages, and in which the digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output, and wherein, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch, said phase/frequency locked loop further including:
(i) means for presetting the counter, from external logic means, to a particular output value, (ii) means for transferring the counter's output value to said external logic means, (iii) means for selectively activating a number of counter sections from said external logic means.

12. A frequency locked loop comprising a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a count-up input of a digital up-down counter, and a second output connected to a count-down input of said counter, said counter having parallel outputs which, except for the least significant bit, are connected to a digital to analog converter having an output for providing an analog signal representative of a count in said counter, the output of the digital to analog converter being connected to control a voltage controlled oscillator which generates said feedback signal pulses at a rate corresponding to said analog output signal, said differential latch being so contructed that non-overlapping output pulses are produced at said first and second outputs in response to pulses applied to said first and second inputs.

13. A frequency locked loop as defined in claim 12 in which the output of the digital to analog converter is connected to the voltage controlled oscillator via a low pass filter.

14. A frequency locked loop as defined in claim 12 or 13, in which the digital up-down counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high value upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output.

15. A frequency locked loop as defined in claim 12 or 13, in which the digital up-down counter has a variable number of stages and includes a CARRY
output and a BORROW output, further including means for presetting the counter to a high value upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW
output.

16. A frequency locked loop as defined in claim 12 or 13 in which, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch.

17. A frequency locked loop as defined in claim 12 or 13, in which the digital up-down counter has a variable number of stages and includes a CARRY
output and a BORROW output, further including means for presetting the counter to a high value upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW
output, and in which, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch.

18. A phase/frequency locked loop comprising a differential latch having a first input adapted to receive input signal pulses, a second input adapted to receive feedback signal pulses, a first output connected to a count-up input of a digital up-down counter, and a second output connected to a count-down input of said counter, said counter having parallel outputs connected to translation means for generating said feedback signal pulses at a rate related to the output of the counter, said differential latch being so constructed that non-overlapping ouput pulses are produced at said first and second outputs in response to pulses applied to said first and second inputs.

19. A phase/frequency locked loop as defined in claim 18 in which said translation means comprises a frequency rate multiplier connected to receive the parallel outputs of the counter and providing an output to drive a D.C.
motor, means for sensing rotational speed of the motor providing said feedback signal pulses.

20. A phase/frequency locked loop as defined in claim 19 wherein the output of the frequency rate multiplier controls a transistor connected in series with said motor and a source of clock pulses is connected to a clock input of said frequency rate multiplier.

21. A phase/frequency locked loop as defined in claim 20, in which the counter includes a CARRY output and a BORROW output, further including means for presetting the counter to a high count upon the presence of a signal at the CARRY output and for resetting the counter to zero upon the presence of a signal at the BORROW output.

22. A phase/frequency locked loop as defined in claim 18, 19 or 20 in which, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch.

23. A phase/frequency locked loop as claimed in claim 21 in which, in the event of substantially coincident pulses applied to the first and second inputs of said differential latch, no output pulses are produced at the first and second outputs of said differential latch.

CLAIMS SUPPORTED BY SUPPLEMENTARY DISCLOSURE

24. A phase/frequency locked loop as defined in claim 1, in which said differential latch includes means for storing the input signal and the feedback signal of the voltage controlled oscillator, and logic means which, in the event of substantially coincident pulses at said first and second inputs, produces an output pulse first on a predetermined one of said first and second outputs followed by a pulse on the other output, said latch having means for ensuring a minimum pulse width of output signals applied to the up and down count inputs of the counter via said first and second outputs.

25. A phase/frequency locked loop as defined in claim 24 wherein said means for ensuring a minimum pulse width comprises gate means having a first input to which a signal is directly applied and a second input to which the signal is applied via delay means.

26. A phase/frequency locked loop as defined in claim 24 including dead lock detection means responsive to detection of a latch-up condition in the differential latch circuit to provide a signal enabling a low level pulse to be generated from one of said first and second outputs first and then another low level pulse from the other output.

27. A phase/frequency locked loop as defined in claim 24, including means for resetting said signal storing means after a low level pulse is generated at the corresponding output of the differential latch.

28. A phase/frequency locked loop as defined in claim 1, in which said differential latch includes means for storing the input signal and the feedback signal, said phase/frequency locked loop further comprising a local clock source, pulse width synchronization latches and logic means responsive to provide (a) low level output signal pulses of a local clock period duration, (b) a minimum of half a local clock period separation between low level output signals applied to the up and down inputs of said counter via said first and second outputs.

29. A phase/frequency locked loop as defined in claim 28, including means for resetting said signal storing means once a low level pulse is generated at the corresponding output of the differential latch.