CA1153460A - Signature verification system - Google Patents

Abstract

Abstract A video display terminal is disclosed which may simultaneously display graphics and alphanumerics on the same screen and in superimposed relationship. The terminal may take the form of an intelligent, processor driven terminal having a conventional bus architecture.
Data may be inputted by way of a keyboard or other peripheral, such as a host computer, and stored in a read/write memory, such as a random access memory (RAM).
Data stored in the RAM may be outputted and displayed on the terminal display screen. In addition, graphics picked up by a closed circuit TV camera may be dynamically displayed on the terminal screen in real time. The graphics information may then be frozen and transmitted to a remote location, such as a host computer, for long term storage. The static graphics thus recorded can be called up and redisplayed on command at the same or a different video display terminal communicating with that host computer. Alphanumeric information associated with that graphic image may also be entered at the terminal and recorded at the host computer. Both the graphics and alphanumerics may then be simultaneously displayed in superimposed relationship, if needed, on a video display terminal. One particular application of this system is in signature verification such as might be used by a teller at a branch bank or by a sales clerk in a department store for validating signatures.

Description

VIDEO DISPLAY TERMINAL FOR SIMULTANEOUSLY
DISP~ING GRAPHICS AND ALPHANUMERIC5 Backqround and Field of the Invention This invention relates to a video display terminal which can dynamically and in real time display graphical information as picked up by a closed circuit TV camera.
The terminal can also display graphic information superimposed on alphanumeric information. The invention will be described with particular reference to a data processing system employing video display terminals, such as point-of-sale terminals or bank teller terminals. It is to be appreciated, however, that the invention may also be used in such other applications as require dynamic display by the video display terminal of 9raphics picked up by a closed circuit TV camera in real time and~or the display of graphical information which may be æuperimposed on alphanumeric information~

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Siynature veri~;cation systems are known in the art, one example of s~lch bei~g d isclosed in the patent to D.
Domike et al., United States Patent No. 4,101,959. That patent discloses a system employing a television camera to capture a written signature The camera is focused on a signature-bearing card, with the resulting video information being recorded at a main processor. The infor~ation can later be retrieved for display on the screen of a video display terminal along with certain alphanumeric data.
This system does not permit the display of the signature on the screen of the video display terminal in real time as it is being viewed by the camera. The operator is thus unable to adjust the size of the si~nature on the video display scree~ prior to recording data representative of the signature.
Moreover, in the subsequent display of the signature and related alphanumeric information, the display is divided into two areas, each area providing display of but a single type of data. More specifically, these ~wo areas ~f the screen are dedicated to the display of tl) graphics, i.e., the signature, and (2) alphanumeric data, such as that which might provide information pertinent to the account associated with the signature. By dedicating a portion of the screen to graphics alone~ however, the ab;lity to write alphanumeric data into the otherwise blank spaces in tha~ portion of khe screen is lost.

S ~x_of the nvention It is there~ore an object of the present invention to provide a video display system employing a television camera for capturing graphic in~ormation while providing dynamic display of the captured data on the screen oE a video display terminal in real time.
It is a still further object of the present invention to provide a video display terminal permitting simultaneous display of alphanumeric data and graphics in superimposed relationship so as to thereby make more efficient use of the display screen.
It is a still ~urther object of the present invention to provide a video display terminal employing dot matrix displays of both alphanumerics and graphics wherein an identical dot matrix is used or both.
In accordance w~th one aspect of the present invention, a video display terminal ls prov;ded for simultaneously displaying alphanumeric images and graphic images in superimposed relationship. The video display terminal includes video display means responsiv~ to bilevel video signals for displaying images represented thereby. First image generating means supplies ~irst bilevel video signals representative o the alphanumeric ~53~

imayes, and second image generating means separately and independently supplies second bilevel video signals in synchronism with the first bilevel video signals, with the second ~ilevel video signals being representative of graph;c images. Means are also provided for combining the first and second bilevel video signals so as to provide a third bilevel video signal having characteristics such that, when applied to the video display means, both the alphanumeric images and the graphic images represented hy the first and second video signals will be displayed in superimposed relationship.
In accordance with another aspect of the present invention, the second image generating means includes means, such as a TV camera, for converting a visual, graphical image into said second bilevel video signals, wherein the second bilevel video signals are dynamically generated so as to be variable in accordance with variations in the visual image.

Brie~ Deseri~tion of the Drawings The foregoing and other objects and advantages of the invention will become more readily apparent from the following description o~ the preferred embodiment of the invention as taken in conjunction with the accompanying drawings whérein:

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Fi~. 1 is a general block diagram of a data processing system employîng a host computer and plural remote video display terminals;
Fig. 2 is a block diagram of the terminal T2 of Fig.
1;
Fig, 3 is a more detailed block diagram of the signature verification circuitry and a portion of the video displa~ circuitry of the video display terminal of Fiq. 2; and Fig. 4 is a schematic illustration of the control logic circuitry employed in Fig. 3.

Detailed Description GENERAL DESCRIPTION
Reference is now made to the drawings wherein the showings are for purposes of illustrating a preEerred embodiment of the invention only and not for purposes of limiting the same.
Fig. 1 is a general block diagram of a data processing system incorpora~ing the present invention. The processing system employs a host computer HC having a mass storage ~evice DS and a communications interface CI for communicating with plural remote video display terminals such as Tl-T3. Conventionally, communication between the terminals and the host computer will take place over ordinary telephone lines via appropriate modems. The . -, ,~ ;

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video ~splay terminals Tl-T3 are identical, and therefore only termina~ r~ will be described hereinafter in detail~
- As shown in Fig. 2, terminal T2 is a processor-driven terminal employing a conventional bus architecture. The bus structure is divided into an address bus Ar~, a data bus DB, and a control bus CB. By way of an example only, the address bus may be a sixteen bit bus and the data bus an eight bit buso An inter~ace to the host computer HC is obtained with a conventional input/output circuit IO which may, for example, be a universal synchronous/asynchronous receiver/transmitter (USART) coupled to a modem of any appropriate construction. The input/output circuit IO communicates with the address bus, the data bus, and the control bus.
Also connected to the various buses is a microprocessor 10, serving as the central processing unit, and external memories 12 and 14. Memory 14 stores the operating programs for the CPU and may take the form of a read only memory ~ROM). The individual instructions are obtained from the memory 14 in response to addresses placed on the address bus AB by a program counter within the CPU. The memory 14 presents the addressed instructions on the data bus DB for use by the microprocessor in executing a given operating program.
Random access memory (RAM) 12, on the other hand, provides .--s ~

6~3 storage for data to be manipulated by the processor.
Character data to be aisp~ayed by the ~erminal video display 16, for example, is conventionally stored in the RA~l 12. This data may be entered from an input peripheral such as keyboard 18 or downloaded from the host computer HC.
The downloading of data for display will be controlled by the operator through commands entered into the ~eyboard 18. The downloaded data, in the form of character codes, will be entered into memory 12 from which ;t can be retrieved for display by the video display 16. Signature data ~or other graphics) may also be retrieved from the host computer, and will be entered into a separate read/write memory in the signature verification unit (to be described hereinafter). This graphics data is then also available for display by the video display.
For convenience o~ description, the video display 16 will often be referred to as simply CRT 16. Of course, CRT 16 includes not only.a cathode ray tube, but also suitable horizontal and vertical deflection circuitry as well as a blanking/unblanking circuit. Preferably, the deflection control circuitry included in CRT 16 deflects the electron beam in a TV-type raster scan, the scanning of which is controlled by horizontal and vertical synchronizing signals (H5, Vs) generated by the video control circuit 20. In this type of display, each ~53~

horizontal scan line generates a linear segment or "stroke" of each of the characters being displayed at that vertical position of the screen. Each of these character segments is composed of 9 portions, or "dots", with the intensity of the displayed image being independently controllable for each dot of each scan. Since, in the embodiment being described, thirteen horizontal scans are required to scan one complete line of characters, each character may be considered to be composed of a 9 x 13 dot matrix.
The character codes stored in memory 12 are used as addresses to obtain dot patterns from a read only memory (ROM) located in the video control circuit 20. The video circuit 20 assembles the appropriate dot patterns for each 1~ horizontal scan, thus generating a video signal which would normally be applied directly to the video (i.e., intensity) input into the CRT 16.
In accordance with the principles of the present invention, however, the video signal is instead routed through a circuit 50, occasionally referred to hereinaf~er as the signature verification unit. The signature verification unit 50 generally includes a TV camera 70, a signature verification control circuit 58, and an ~or~
- gate 60. The signature verificati~n control cir~uit 58 responds to the analog video signal developed at the TV
camera 70 to dynamically generate a real time, digital 3~6~

video sign~l therefrom. Alternatively, the data for generating this signal m~y be downloaded into the circuit 58 from the host computer~ This video signal is bilevel, like the video signal generated by the video control circuit 20, and is synchronized ~herewith. Because of this, a composite video signal may be formed by simply "or"ing the two signals together, as by "or" gate 60. The resulting signal is applied to the video input to the CRT
16, and results in the display of an image which is the superimposition of the displays which would have been provided by either source (video control circ~it 20 or signature verification control circuit 58) separately~
The two images may interlace with one another or may, in fact, even overlap.
Since the generation of the digital video signal, when derived directly from the camera, occurs dynamically and in real time (i.e., at the same time as it is being viewed by the camera), adjustment of the focus or zo~m can be undertaken while the display is viewed on the screen of the CRT 16. Since the two video signals are superisnposed, characters from video circuit 20 may be written beside, above, below, or even on top of the graphics from circui 58.

VIDEO CONTROL CIRCUIT
Reference is now made to Fig. 3 which illustrates in greater detail a portion of a video control circuit 20 . ~ .. , .. _,_ _ _.. _ _"__~, , ~53~

from a typical in~elligent terminal together with the slgnature verification unit S0 of the present invention.
The video control circuitry 20 serves to control the generation of alphanumeric characters on the face of the cathode ray tube 16. In a conventional fashion, a read only memory (ROM) 52 stores the font of dot patterns for the various characters and symbols to be displayed by the cathode ray tube 16. As stated previously, each dot character or symbol is displayable within a 9 x 13 dot matrix pattern. The dot pattern for each character is stored as a sequence of thirteen, 8-bit bytes. The eight bits of each byte represent eight of the nine dots in a single horizontal slice of the character. The ninth dot is always blank, for reasons which will become apparent hereinafter.
The address for addressing a dot pattern stored in memory 52 is obtained from the character codes supplied to the data bus DB by memory 12. These coded data characters may first be buffered, as with a line bufer, or may be supplied directly from the data bus one character code at a time to the address input to ROM 52. The total address includes the character code supplied to the ROM ~eight bits, in the example being described) as well as a line count code LCo to LC3 obtained from a suitable timing 2S circuit 54. Essentially, the character codes each address a thirteen byte dot pattern for the corresponding ~5.~6~3 character, with the four bit line count selecting a particular one of the thirteen bytes of that dot pattern.
During the generation of a line oX characters with a TV raster scan, each scan line lays down one slice or dot pattern segment of each of the characters on a line.
Succeeding scans provide the remaining slices or dot segments. Consequently, thirteen scan lines are required to scan a 9 x 13 dot character field. This means that~
for each character generated, the memory 52 must be addressed at least 13 times to retrieve the thirteen slices thereof. Characters to be displayed in a given line may be recirculated in the line bufer (not shown) thirteen times, with the line count LCo through LC3 being incremented with each recirculation. The address for each dot pattern segment, then, is a combination of the line count together with the character code obtained from the data bus DB or the line buffer.
Each time a line segment dot pa~tern is outputted from memory 5~ it appears as an eight-bit byte. This byte is loaded in parallel into an output shift register 56 when that register receives a load pulse (B) rom timing circuit 54. After each load pulset the dot pattern byte is shifted in bit serial fashion out of the output register 56 in synchronism with shift or clock pulses (A), also supplied by timing circuit 54 to the shift input of register 56. The resulting serial bit stream is directed 3~

by way of an 0~ gate 60 to the C~T 16, where ;t controls th~ blanking/unblanking operation of the scanning electron beam in conventional fashionO
The timing circuit 54 provides the p~lses on lines A
and B, and also generates horizontal and vertical synchronizing pulses (Hs and Vs) in synchronism therewith. As ~ar as the pulses on lines A and B are concerned, timing circuit 54 may be thought of as performing a pulse distributing function. A regular clock signal is generated in the circuit 54, and is gated to lines A and B so that eight sequential clock pulses appear on line A, followed by a single clock pulse on line B.
This cycle repeats every nine clock periods. Thus, in an interval of nine clock periods, the eight clock pulses on line A shift a character slice out from shift register 56, with the ninth pulse reloading the shift register. It is thus the ninth clock pulse which accounts for the remaining dot in the nine dot wide character field.
As the beam in the CRT 16 is being scanned ~0 horizontally across the CRT screen, a dot pattern is displayed in each line segment in accordance with the associated bit pattern outputted from register 56. At the end of a ~can line, the timing circuit 54 will generate a horizontal synchronization signal HS to cause the beam

2~ to fly back or retrace to the opposite side of the screen, where it will be in a position to ~ommence tracing of the , . . .. ..... . .. , .. . _ ., _ .. . ~ . .... .. .. .. . _ .. ~ _ . . . _, . . .... _ , . , . . _ . _, ~ , .

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next scan line across the face of the cathode ray tubeO
This next scan line will be below ~he last scan line since the vertical de1ecti~n signal (~enerated by a deflection circuit in the CRT) will have changed somewhat since the last scan. These scans will continue from the top to the bottom of the screen, witlJ each thirteen scan lines displaying a single character line. After the bottommost visible line of characters is traced, the timing circuit 54 provides a vertical synchronization signal Vs to th~
cathode ray tube to cause the beam to retrace to its beginning position, normally located in the upper lefthand corner of the CRT. Raster scans will continue in this manner, providing the display of the characters on the CRT
screen.
The number of visible character in a screenful of characters will be determined in large measure by the size of the cathode ray tube. In the example being given, the CRT screen may provide 40 alphanumeri~ characters per line with 12 lines of visible data characters.
The discussion of Fig. 3 has thus far related to what may be considered as a typical intelligent video displa~
terminal that is interactive with a host computer such as host computer HC. This terminal has been described herein with respect to terminal T2 and it is to be appreciated ~hat various different structures may be employed to obtain an equivalent architecture of an intelligen~

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terminal. In such terminals as applied to bank teller operations and the like, an ope~ator may utilize a keyboard such as keyboard 18 to retrieve a fil2 with respect to a particular account from a memory storage location within the disk storage DS. The accessed data will be downloaded into the read/write memory 12 at the terminal. When the data is to be displayed, it will be supplied to the video control circuit 20 via the data bus DB so as to generate the appropriate characters on the face of the cathode ray tube 16, utilizing circuitry such as that described hereinbefore with reference to Fig. 3.
The description which follows will be di~ected to the additional portion of terminal T2 dealing with the signature verification unit 50 illustrated in Figs. 2, 3 and 4 and to the manner in which this circuitry converts a typical intelligent video display terminal to signature verification use in accordance with the objects of the present invention.

SIGNATURE VERIFICATION CIRCUITRY
The signature verification unit 50 (Fig. 2) may be interconnected to the typical processor-driven terminal as shown in Figs. 2 and 3 to convert that terminal to signature verification use. The output of the video control circuit 20, which is normally connected to the blanking/unbl~nking control of the cathode ray tube 16, wi~l instead be connected through the signature verification unit 50 in the ill~strated embodimentO
The signature verification unit 50 includes a control circuit 58 to be described in greater detail hereinafter~
This circuit uses a closed circuit TV camera 70 as a signature or graphics capture unit, and generates a graphics v;deo signal therefrom. This signal is added to the video output of video control circuit 20 by an OR gate 60. The signature verification unit is connected to the terminal bus structure in the same manner as other peripheral circuits and its operation is controlled by ~he microprocessor over this bus structure. One additional requirement will be that the ROM 14 have sufficient capacity to include some additional firmware associated with the signal verification control. This is indicated in Fig. 1 as the extended memory portion 14'.
Attention is now directed to the more detailed illustration of Fig. 3. ~ere the TV camera 70 receives its horizontal and vertical synchronizing signals ~S and Vs from timing circuit 54 in parallel with CRT 15. The scanning of the video imaging tube thus takes place in synchronism with the raster scanning of the CRT. A
signature card 80 bearing a signature 82 or other graphics to be viewed is placed within the camera lfi Vi~W, as shown in Fig. 3. Preferably the camera i~ a fixed ~ocus camera, although focus controls may be used i~ desired. The . '. ~ f ~

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ca~era will preferably be proviaed with a zoom lens or telephoto lens arrangement indicated at 84 so that signature data seen on the screen of the cathode ray tube 16 may be ad justed so as to, for example, fill the screen, The video signal outputted by the TV camera is an analog signal and is applied to a threshold comparator 86. This comparator compares the analog value with a threshold signal, as for example from a potentiometer 88 The switching characteristics of this comparator may include some degree of hysterisis. The comparator provides a binary level output indicative of either "on"
or "off" conditions. This of course will correspond to the black or white areas noted by the camera during the scanning of the signature card~ These on/off (binary "1"
or binary "0") signals are then supplied as a serial bit stream to the input of a series-in/paral~el-output shift register 90. The binary "1" signals are of variable duration dependent upon the black-white scan image.
The serial stream of video data is converted into eight-bit data words by clocking the output of the threshold switch into the shift register in synchronism with shift pulses obtained from line A. Each eight bits loaded into the shift register represent a data word for storage in RAM 94. The R~M 9~is loaded with this byte by changing the address provided to the RAM~by the address counter (also referred to as a refresh ~ounter) ~6. This .

"freezes" the data stored in the previously addressed location to the value of the byte proviaed to the data input of the RAM at the time the address was changed. The clocking of the address counter is performed by every ninth clock pulse by utilizing the B line as the count input thereto. A~ter each byte is loaded into the RAM, a new data word is entered into the shift register by the next eight clock pulses, and so on in continuous fashion.
Thus, a train of parallel eight-bit data words representative of the black-white or grey tone scan image is supplied at the output of register 90, and loaded into the RAM 94 at consecutive locations.
The data-in and address inputs to RAM 94 may be derived from several sources. During the display of graphics, the data-in port to the RAM will be connected to register 90 and the address input port will be connected to counter 96. In certain other modes, to be described hereinafter, the address and data inputs of the RAM will instead be connected to the address and data ~uses AB and DB of the terminal, thus allowing access to the RAM 94 by the microprocessor 10 in the same fashion as other memory devices 12 and 14. Multiplexers 92 and 95 are connected respectively to the data and address inputs of the memory for providing the appropriate connections in the different modes. These multiplexers are commonly controlled by a control signal C2 derived from control logic 106. When ~3~

C2 is in one logic state, the RAM will be connected to b~lses AB and DB, as described above. When C2 is in the other logic state, however, the inputs to the RAM will instead come from register 90 and counter 96. The 5 read/write control inp~t to RAM 94 is also controlled by a siqnal (C3) derived from logic 106, and will be set as appropriate to the mode of operation of the unit 50 at any given time. During the dynamic signature display mode, line C3 will hold the RAM in the write moae continuously, so that the data in the RAM 94 is continuously updated.
The memory must be sufficiently large to store the TV
scan data. In the example being given it is contemplated that a full screen includes 360 dots per line by 156 lines which would amount to a total of 56,160 dot positions on the screen. Since this is coded as eight-bit bytes of data (with every ninth bit interval being used for loading purposes, and thus not stored in the RAM), a full screen of data would require 6,240 bytes of storage. This would fill the screen with graphic data. In the described embodiment of the invention, graphics data is used only on one half of the screen, preferably the upper half, so only half that amount of data storage (3,120 bytes) need be provided. Memory 94, therefore, must be ~ufficient~y large ~o store this graphics data. In he embodiment being described, RAM 94 actually includes somewhat greater - t

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storage capacity so that certain other data may be stored therein. This additional memory space is used in the data compression and expansion operations described hereinafter.
Since the graphics data is written into the random access memory 94 at addresses obtained from the address counter 96, the counter must provide addresses for 3,120 bytes of graphics data. The address counter is preferably a resetable counter which may be adjusted to a reset count provided by a thumbwheel 98 or perhaps hardwired in at the factory. Assuming that the upper half of the screen is used for graphics data, this reset count will correspond to the completion of the first 78 scan lines of display.
A comparator associated with circuit 96 will compare the contents of the thumbwheel 98 and the refresh counter 96, and will provide an output having a value depending upon the relative values thereof. Once the address counter has supplied addresses for 78 scan lines of graphics data, the output of the comparator will set a flip-flop, also included in the circuit 96, which in turn will reset the counter to zero. ~he counter will be held in a reset condition by the flip-flop until the flip-flop is, itself, reset upon the return of the electron beam to the top of the screen.
It is to be appreciated that for each scan line there will be 40 sequential addresses provided for the 40 bytes of data. During the dynamic display operation each of the ~3~

graphics data by~es will be con~inuously wr;tten over on a byte-by-byte b~sis until the operator has decided to freeze the data to obtain a static signature display.
This will be discussed in greater detail hereinafter.
As graphics data is being written into memory 94 during the dynamic display mode, the 3,120 eight bit bytes of graphics data is also being sequentially supplied at the output of the memory and loaded into a parallel~input/serial~output shift register 100. This loading again occurs on each ninth clock pulse by connecting timing line B to the load input of that register. Each byte of data that is loaded into the output shift register 100 is shifted out in serial fashion by clock pulses obtained from line A supplied to the shift input of this register. This serial stream of data is supplied as dot pattern segments to the on/off intensity control of the cathode ray tube 16 by way of an ~ND gate 104 ~when enabled) and OR gate ~0. Gate 104 is enabled by the control logic circuit 106 under firmware control during periods when the unit is in a graphics display mode o~ operation.
The control circuit 106 which generates the control signals Cl-C4 may of course take many forms. It may, for example, be simply a latch loaded from time to time with an appropriate control word frcm thè data bus. In the illustrated embodiment, however, ~Fig. 4) the control ~; - *
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circuit 106 comprises an address decoder 130 controlling a series of set/reset flip-flops 132i 134. The decoder 130 monitors the addresses provided on the adaress bus, and, when one of a n~mber of predetermined a~dresses occurs, provides a logic "1" signal on a corresponding one of the output lines. Each of the output lines will be at a logic "0" level when not selected in this manner. Each of the flip-flops 132, 134, etc. may thus be set or reset by the application of selected addresses to the address bus by the microprocessor.

MODES OF OPERATION
Upon power-up and whenever reset thereafter, the terminal wlll display a menu identifying the various modes of operation and the codes which must be entered into the keyboard to call them. Other promptin~ messages may also be displayed by the terminal, as appropriate, durin~
operation. Although many operational modes may be provided, only the dynamic display mode, record mode, and signature recall mode will be described since only these need be understood for a full and complete appreciation of the present invention.
Dynamic Dis~lay Mode:
When initially capturing a si~nature, the operator will request the dynamic display mode via the keyboard 18. The processor, under firmware control, will ~pply .. . .. . . _ . __ . _ ,_ . . ..... ,. _._.. _ ., _ .. ,., . _.. _ _ .. _ . ._.. _ _ ._ ...... _ _ _ _ appropri~te power and control signals to the camera and will cause coaltrol logic 106 to set loyic signal Cl and thereby enable gate 104. Control logic 106 will also be caused to set RAM 94 in~o a WRITE mode and to connect the inputs of the RAM to register 90 and counter 96. The signature 82 on the card 80 will thus be captured by the TV camera and recorded in the memory 94, as well as being displayed on the upper hal of the screen of the cathode ray tube 16. The manner in which this is accomplished has been described previously. During this period the lens on the camera may be adjusted to bring the signature to the proper size-and focus as the operator desires to have it recorded.
Record Mode:
If the operator is satisfied with the adjustment of the signature on the screen of the cathode ray tube he will enter a RECORD code by way of keyboard 18. This t again under firmware control, ~ill cause a recording of the graphics onto the disc storage DS at the host computer HC. If desired, the graphics may be recorded in the same manner as they are entered into memory 94; ~hat is, with a total of 3,120 bytes of graphic data words. Thi~, however, will reguire subs~antial communica~ion time and memory storage space. Preferably, the processor has additional firmware by which the data i5 compressed and then forwarded t~ the host computer for storage at disc storage DS in a compressed format. Various firmware programs may be used ~o achieve th;s result.
Upon entering the RECORD mode of operation, the processor removes the WRITE signal from memory g4 so that graphics data is frozen. The READ command supplied on the control line C3, however, permits the memory 94 to be interrogated. The input port 120 is enabled by control line C4, thus connecting the RA~ output into the microprocessor data bus. The signal on control line C2 is also changed so that the RAM is now connected at its data and address inputs into the data and address buses of the microprocessor. The MPU thus has complete access to the RAM in this mode. Under the firmware control, the compression routine will cause a reading of the data in memory 24 pursuant to addresses supplied on the address bus AB and will then compress the data and store it in a compressed form in temporary locations in a different ` portion of the memory 94. Pre~erab~y, after 200 by es of compressed data have been stored, a routine in the firmware (memory 14') will send this compressed block of data to the host computer ~C for s~orage in the disc storage DS. The processor will then compress the next portion of the signature data, and so on until all the signature data has been compressed and forwarded to disc 2~ storage. The terminal will then automatically revert to a ~3~6~ , selection mode, at which point the operator at the terminal may select a signature recall, as desired.
In addition to the graphics, additional information relative to the signature may be entered by way of the s keyboard and displayed on the screen in alphanumeric form. This data might include, for example, a customer name identifying the individual whose signature is being displayed, together with his account number, account status, social security number, etc~ This data may be recorded alonq with the compressed signature data at the disc storage, thereby providing keys for recalling a signature from the computer memory by any of terminals Tl, T2, etc. for signature verification purposes~
Signature Recall:
To recall a signature from the host computer, the operator will enter a command calling for a signature display mode, followed by a signature file key identifying the individual signature (account number, short name, social security number, etc.~. This, under firmware control at the terminal, will cause the screen on the cathode ray tube to switch into a graphics~alphanumerics display mode in which the recalled signature will be displayed on the top half of ~he screen together with predefined customer data which ~ay be confined to the 2~ b~ttom six character lines o~ the screen~ If desired, however, predefined customer data, in the form of -~ ~r ~6 alph~numerics, may also be superimposed on a portion of the upper half of the screen so that both the graphics data and some alphanu~erics data are superimposed. This is possible because the two video signals are generated S separately and are joined by the OR gate 60 to provide a composite signal.
In the signature recall mode of operation, the processor causes data stored at the host computer associated with the signature key to be downloaded to the terminal. The alphanumeric data is written into memory 12 in tlle normal manner, whereas the qraphics data is written into the signature memory 94 which will again be connected to be accessible to the microprocessor, in the manner described above, and which will now be in a WRITE mode.
The data being written into memory 94 at this time is compressed data having a length of perhaps 300 900 bytes as opposed to the uncompressed length of the si~nature of 3,120 bytes.
After all of the data has been received and stored in a temporary storage location in memory 94, the irmware will call up a routine for decompressing this data. The decompressed data is again stored in the signature display portion of the signature verificat~on memory at addresses corresponding with the first 78 scan lines. ~he ~ontrol line C2 will then be set to disconnect the RAM 94 fr~m the data and address buses, and to instead reconnect it to .

counter 96 and register 90. The RAM will also be placed in a read mode via control line C3, thus maintaining the signature data in a static condition. Gate 104 is then enabled, causing the graphics data now being outputted from the memory to be displayed on the upper half of the screen o cathode ra~ tube 16 in the manner described hereinbefore.
Thus, the signature bytes will be addressed one at a time by counter 96, starting with the first byte of the first scan line on the cathode ray tube. The bytes outputted from memory 96 represent eight bit dot patterns and will be loaded into the output shift register 100. So long as AND gate 104 is enabled, these dot patterns will be serially supplied to the intensity control of the cathode ray tube 16. During the firs~ 78 scan lines, the signature or other graphics will be displayed on the upper half of screen 16. Alphanumeric data will also be displayed, generally on the bottom half of the screen. As will be recalled, the alphanumeric data is supplied by the data~ bus DB as partial ad~resses to memory 52 from which dot pattern segments are ~upplied to the output ~hift regi~ter 56. From there they are shifted out to provide a serial dot pattern stream, which is applied to the cathode ray tube 16. The alphanumeric data, again7 may include such items as account number; ~hort name, 50cial ~e~urity number, ~redi~ balanc~, and ~he like.

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As stated previously, it may be desirable in some cases to utilize a portion of the upper half of the screen for the display of alphanumerics. Much of the upper half of the screen will be blank since the signature will not require all of the space available. Consequently, alphanumeric aata may be entered and stored in memory locations corresponding to any desired portion of the upper ha~f of the screen, as well, and the dot patterns for this data will be outputted from the shif~ register 56 at the same time that dot patterns representing graphics are supplied to the output shi~t register 100. These two dot patterns will be superimposed by the OR gate 60 to provide a composite signal to the cathode ray tube 16.
Consequently, both alphanumeric data and graphics data may be displayed in the same area of the cathoae ray tube screen.
In summation, it is seen that the signature verification system enbances a video display terminal of the type described here;n by permitting signature capture as with a closed circuit TV. This si~nature data as obtained by the TY camera provides a serial stream of data which may be written into a disc file once the operator has decided to freeze the signature data. During ~he dynamic display mode, the operator may adjust the s~e of the signature on the upper half of the screen as he wishes it to be recorded. A ~ignature obtained by one of the ~ ~34~
-~8-systems terminals may then be recorded at a central station for la~er recall by any of the local or remote terminals within the system. Recall of a signature from storage (by account number, etc.) is obtained by entering a suitable command on a keyboard at one of the terminals.
The recall of a signature results in the signature being displayed on the upper half of the cathode ray tube screen, together with six lines of alphanumeric data being displayed on the lower half of t~e screen. The desired alphanumeric and graphic data may also be superimposed on the upper half of the screen.
Although the invention has been described with respect to a preferred embodiment, it is to be appreciated that various modifications and arrangements may be made without departing from the spirit and scope of the appended claims.

Claims (13)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A video display terminal for simultaneously dis-playing alphanumeric images and graphic images in superimposed relationship, comprising:
video display means responsive to bilevel video signals for displaying images represented thereby;
first image generating means for supplying first bi-level video signals representative of alphanumeric images and having first and second signal levels;
second image generating means for separately and in-dependently of said first image generating means supplying second bilevel video signals having first and second signal levels in synchronism with said first video signals and being representative of graphic images, whereby said signals may assume three different concurrent instantaneous signal level conditions which are: a) simultaneous occurrence of said first signal levels, b) simultaneous occurrence of said second signal levels, c) simultaneous occurrence of said first and second signal levels;
means for combining said first and second bilevel video signals to provide a third bilevel video signal which assumes a first level in response to said signal level condition a) or c) and a second level in response to said signal level con-dition b) and has characteristics such that when applied to said video display means both said alphanumeric images and said graphic images represented by said first and second video signals may be displayed in superimposed relationship.

2. A video display terminal as set forth in claim 1, wherein said first and second image generating means each includes dot pattern storing means for respectively storing dot patterns representing alphanumeric characters and dot patterns representing graphical images and wherein means are further provided for reading out the dot patterns stored in said first and second dot pattern storing means in synchronism with one another, whereby the video signals resulting from said reading out are also in synchronism with one another.

3. A video display terminal as set forth in claim 2, wherein said second image generating means further includes means for loading said dot pattern storing means with dot patterns selectively derived either in real time from a visual image or from data communicated to said video display terminal from a remote location.

4. A video display terminal as set forth in claim 3 wherein said second image generating means includes means for converting a visual image to an analog video signal in real time, means for deriving a bilevel signal from said analog video signal, and means for deriving dot patterns from said bilevel video signals for storage in said dot pattern storing means.

5. A video display terminal as set forth in claim 1, wherein said second image generating means includes means for in real time deriving said second bilevel video signal from a visual image.

6. A method of composing a display including a written message and related alphanumeric data, comprising the steps of scanning the written message to derive a real time analog video signal, comparing the analog video with a threshold level to pro-vide a bilevel video signal having first and second signal levels, the instantaneous level of said bilevel video signal depending upon the relative values of said threshold level and said analog video signal, providing a second bilevel video signal synchronized with said first bilevel video signal and having first and second signal levels representative of alphanumeric data relating to said written message, whereby said signals may assume three different concurrent instantaneous signal level conditions which are: a) simultaneous occurrence of said first signal levels, b) simultaneous occurrence of said second signal levels, c) simultaneous occurrence of said first and second signal levels generating a composite video signal incorporating both said first and second bilevel video signals which assumes a first level in response to said signal level condition a) or c) and a second level in response to said signal level condition b) and, applying said composite video signal to a video display means whereby both said alphanumeric data and said written message are simultaneously displayed in real time thereby, and adjusting the displayed alphanumeric data and written message as necessary to compose the desired display.

7. A method as set forth in claim 6, wherein said step of scanning said written image comprises the steps of focusing an image of the written message on a light responsive surface, raster scanning the light responsive surface to generate said real time analog video signal, and adjusting the focused image on said surface, whereby said focused image may be adjusted as it is being displayed in real time by said video display to occupy any de-sired location relative to said alphanumeric data.

8. A method as set forth in claim 6, and further com-prising the step of recording digital data defining both said alphanumeric data and said written message, as thus adjusted, for later display by said video display means or another similar display means.

9. Apparatus comprising:
video display means including a display screen and means for providing a visual display on said display means by raster scanning said screen with an energy beam whose intensity is con-trolled by a video signal applied thereto;
means for providing information identifying alphanumeric characters to be displayed on said display screen of said video display means;
first bilevel video signal generating means responsive to said information to generate a bilevel video signal which, if applied to said video display means, would cause said video dis-play means to display said alphanumeric characters, said signal having first and second signal levels;
means for providing information identifying graphic designs to be displayed on said display screen;
second bilevel video signal generating means responsive to said graphic design information to generate a second bilevel video signal which, if applied to said video display means, would cause said video display means to display said graphic designs, said second signal having first and second signal levels;
said first and second bilevel video signal generating means generating said first and second bilevel video signals in synchronism with one another, whereby said signals may assume three different concurrent instantaneous signal level conditions which are: a) simultaneous occurrence of said first signal levels, b) simultaneous occurrence of said second signal levels, c) simultaneous occurrence of said first and second signal levels; and means for providing a third bilevel video signal which assumes a first level in response to said signal level condition a) or c) and a second level in response to said signal level condition b) and incorporating both said first and second video signals whereby, when applied to said video display means, both said alphanumeric characters and said graphical images will be displayed in superimposed relationship on said screen.

10. Apparatus as set forth in claim 9, wherein each of said first and second bilevel video signal generating means include dot pattern storing means for respectively providing storage of dot patterns representing alphanumeric characters and dot patterns representing graphical images, and wherein said apparatus further includes means for reading out said dot pattern storing means of said first and second bilevel video signal generating means in synchronism with one another, whereby the video signals resulting from said reading out are also in syn-chronism with one another.

11. Apparatus as set forth in claim 9, wherein said second bilevel video signal generating means includes means for in real time converting a visual image into a bilevel video signal synchronized with first bilevel video signal, whereby said video signal is variable in accordance with the variations in said visual image.

12. A video display terminal for dynamically displaying TV camera captured graphic images in real time along with alpha-numeric images, comprising:
graphic capturing means including TV camera means for scanning graphic images and providing, in real time, bilevel video signals representative of the graphic images and having first and second signal levels;
video display means responsive to bilevel video signals for displaying images represented thereby;
means for supplying bilevel video signals represen-tative of alphanumeric images to be displayed and having first and second signal levels, whereby said signals may assume three different concurrent instantaneous signal level conditions which are: a) simultaneous occurrence of said first signal levels, b) simultaneous occurrence of said second signal levels, c) simultaneous occurrence of said first and second signal levels; and means for supplying said graphic image bilevel video signals and said alphanumeric bilevel video signals to said video display means such that both types of images may be displayed by the display means with the graphic image being dis-played in real time comprising means for combining said first and second bilevel video signals to provide a third bilevel video signal which assumes a first level in response to said signal level condition a) or c) and a second level in response to said signal level condition b) and has characteristics such that when applied to said video display means both said alphanumeric images and said graphic images represented by said first and second video signals may be displayed in superimposed relationship.

13. A video display terminal as set forth in claim 12, wherein said TV camera means provides analog video signals and means for converting said analog signals into said bilevel video signals.