CA1149516A - Circuit arrangement for monitoring a pulse sequence on a fail-safe basis - Google Patents
Circuit arrangement for monitoring a pulse sequence on a fail-safe basisInfo
- Publication number
- CA1149516A CA1149516A CA000339168A CA339168A CA1149516A CA 1149516 A CA1149516 A CA 1149516A CA 000339168 A CA000339168 A CA 000339168A CA 339168 A CA339168 A CA 339168A CA 1149516 A CA1149516 A CA 1149516A
- Authority
- CA
- Canada
- Prior art keywords
- inverting output
- circuit
- nonequivalence
- pulse
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Train Traffic Observation, Control, And Security (AREA)
- Electric Propulsion And Braking For Vehicles (AREA)
- Measurement Of Current Or Voltage (AREA)
- Power Conversion In General (AREA)
Abstract
Abstract of the Disclosure A circuit for monitoring the arrival of a pulse in a pulse sequence is disclosed which safely detects errors in the pulse sequence, component failures or interruptions of the power source. The circuit contains only inexpensive, commercially available components and can be used both in signalling equip-ment employing relay technology and in all-electronic equipment. The circuit comprises a bistable multivibrator receiving the pulse and two monostable multivibrators. One of the monostables has an input coupled to the non-inverting output of the bistable and the other monostable has an input coupled to the inverting output of the bistable. A nonequivalence circuit is connected as desired, to the non-inverting outputs of both monostables or to the inver-ting outputs of both monostables to detect nonequivalence of the levels at the monostable outputs selected.
Description
The present invention relates to a circuit arrangement for monitor-ing the arrival of a pulse in a sequence of pulses within a time interval on a fail-safe basis.
A circuit arrangement of this kind is disclosed as an emergency brake circuit in United States patent 4,198,678 which issued on ~pril 15, 1980, to H. Maatje-R. Spannagel. It initiates emergency braking in an automatically controlled rail vehicle if it is not fed with a uniform, un-interrupted sequence of pulses. In the United States 4,198,678, these pulses are signals from an on-board computer whose nonappearance signals a maifunction in the computer.
Such a circuit is not only suitable for the special case described in the above United States patent but can be employed wherever time-varying electrical quantities, such as alternating voltages or pulse sequences, are used to monitor equipment of great safety responsibility in order to detect component failures.
However, the circuit disclosed is relatively costly since it re-quires analog elements (band-pass filter, amplifier) as well as a transfor-mer. Being no all-digital circuit, it is susceptible to drift, which reduces its reliability. The object of the invention is to provide a circuit for monitoring pulse sequences which is free from drift and lower in cost.
This object is achieved by a circuit arrangement for monitoring the arrival of a pulse in a pulse sequence within a time interval on a fail-safe basis comprising: a bistable multivibrator receiving said pulse and having Ml inverting output and a non-inverting output; a first monostable multi-vibrator having an inverting output, a non-inverting output and an input coupled to one of said inverting output and said non-inverting output of said bistable multivibrator; a second monostable multivibrator having an inverting output, a non-inverting output and an input coupled to the other of said inverting output and said non-inverting output of said bistable multivibrator; and a nonequivalence circuit coupled to a selected one of ~ -2-fi~ 6 said inverting output and said non-inverting output of said first monostable ~ multivibrator and also coupled to a like one of said inverting output and said non-inverting output of said second monostable multivibrator to detect nonequivalence of the levels at said selected output of said first and second monostable multivibrators.
In a preferred embodiment, the nonequivalence circuit consists of a full-wave rectifier and a following relay, the inputs of the full-wave rectifier being connected via amplifiers to the outputs of the delay cir-cuits, and the relay having a make contact in a monitoring circuit.
This embodiment is intended for monitoring circuits using relay technology~
In another preferred embodiment, the nonequivalence circuit con-sists of a full-wave rectifier and a variable-gain amplifier, the inputs of the full-wave rectifier being connected via amplifiers to the outputs of the delay circuits, and the variable-gain amplifier having its control input connected to the output of the full-wave rectifier and interrupting the signal flow to be amplified when the levels at the outputs of the delay circuits are equal.
This embodiment is especially suitable for use in all-electronic monitoring units.
As a further alternative, the nonequivalence circuit may consist o~ an exclusive-OR gate followed by a device indicating a fault or initia-ting safety measureS.
The design and operation of the circuit arrangement according to the invention will now be described in detail with reference to the accompanying drawing, in which:
~2a-~ 5~L6 A.C.Knight-2 Fig.l shows an embodiment of the circuit arrangement according to the invention, and Fig.2 shows a timing diagram.
In Fig.l, the outputs Q and Q of a b;stable multivibrator FF, whose input E
is fed with the pulse sequence, are coupled, respectively, to one of the two inputs of two monostable multivibrators MF1 and MF2, whose dwell times are tl and t2. The outputs Q1, Q2 of the monostable multivibrakors are coupled to the inputs of a nonequivalence circuit A and are monitored by this circuit for nonequivalence. The nonequivalence circuit A contains a full-wave rectifier GL having its inputs connected via amplifiers PWl and PW2 to the outputs Q1 and Q2 of the monostable multivibrators. The outputs of the full-wave rectifier energize the operating coil of a relay R hav;ng a make contact a. The latter is included in a monitoring circuit K-K' and opens th;s circuit when the relay releases.
If a pulse sequence Jl with the period t is applied to the input of thebistable multivibrator FF, the two outputs are alternately low and high, as shown in Fig.2 by the puls~ sequences J2 and J3. The two monostable multivibrators are triggered alternately by the positive edges at the out-puts of the bistable multivibrator and provide pulse sequences J4 and J5 at their outputs Ql and Q2. If the dwell times ~1 and 12 of the monostable multivibrators are equal to the pulse period t, the levels at the outputs Ql and Q2 are always symmetrically different. The output potentials are amplified by the amplifiers PWl and PW2 and applied as square-wave voltages with the period 2t to the full-wave rectifier GL, which provides a constant dc voltage U. The relay R is energized. A capacitor C connected across the relay winding smoothes any short-time drops in voltage caused by small deviations of the pulse period t from the dwell times of the monostable multivibrators.
If a pulse of the pulse sequence J1 fails to arrive (in Fig.2, the 5th pulse of the pulse sequence Jl), one of the monostable multivibrators will not be triggered. The symmetric difference of the outputs Ql and Q2 will disappear, and the dc voltage U will collapse. As a result, the relay R releases, and the monitoring circuit is opened by the contact a.
If the circuit arrangement according to the invention is to monitor a sinusoidal alternating voltage rather than a pulse sequence, a threshold switch may be placed in front of the input to the arrangement. The remainder of the circuit remains unchanged.
Although only non-inverting outputs Ql and Q2 are shown in Figure 1 it IYill be clear to those skilled in the art that monostable multivibrators MFl and MF2 also have non-inverting outputs which would be indica~ed as Ql and Q2, respectively. It will also be clear to those skilled in the art that the non-inverting inputs Ql and Q2, instead of outputs Ql and Q2, could be connec-ted to the nonequivalence circuit A via amplifiers PWl and PW2.
~n
A circuit arrangement of this kind is disclosed as an emergency brake circuit in United States patent 4,198,678 which issued on ~pril 15, 1980, to H. Maatje-R. Spannagel. It initiates emergency braking in an automatically controlled rail vehicle if it is not fed with a uniform, un-interrupted sequence of pulses. In the United States 4,198,678, these pulses are signals from an on-board computer whose nonappearance signals a maifunction in the computer.
Such a circuit is not only suitable for the special case described in the above United States patent but can be employed wherever time-varying electrical quantities, such as alternating voltages or pulse sequences, are used to monitor equipment of great safety responsibility in order to detect component failures.
However, the circuit disclosed is relatively costly since it re-quires analog elements (band-pass filter, amplifier) as well as a transfor-mer. Being no all-digital circuit, it is susceptible to drift, which reduces its reliability. The object of the invention is to provide a circuit for monitoring pulse sequences which is free from drift and lower in cost.
This object is achieved by a circuit arrangement for monitoring the arrival of a pulse in a pulse sequence within a time interval on a fail-safe basis comprising: a bistable multivibrator receiving said pulse and having Ml inverting output and a non-inverting output; a first monostable multi-vibrator having an inverting output, a non-inverting output and an input coupled to one of said inverting output and said non-inverting output of said bistable multivibrator; a second monostable multivibrator having an inverting output, a non-inverting output and an input coupled to the other of said inverting output and said non-inverting output of said bistable multivibrator; and a nonequivalence circuit coupled to a selected one of ~ -2-fi~ 6 said inverting output and said non-inverting output of said first monostable ~ multivibrator and also coupled to a like one of said inverting output and said non-inverting output of said second monostable multivibrator to detect nonequivalence of the levels at said selected output of said first and second monostable multivibrators.
In a preferred embodiment, the nonequivalence circuit consists of a full-wave rectifier and a following relay, the inputs of the full-wave rectifier being connected via amplifiers to the outputs of the delay cir-cuits, and the relay having a make contact in a monitoring circuit.
This embodiment is intended for monitoring circuits using relay technology~
In another preferred embodiment, the nonequivalence circuit con-sists of a full-wave rectifier and a variable-gain amplifier, the inputs of the full-wave rectifier being connected via amplifiers to the outputs of the delay circuits, and the variable-gain amplifier having its control input connected to the output of the full-wave rectifier and interrupting the signal flow to be amplified when the levels at the outputs of the delay circuits are equal.
This embodiment is especially suitable for use in all-electronic monitoring units.
As a further alternative, the nonequivalence circuit may consist o~ an exclusive-OR gate followed by a device indicating a fault or initia-ting safety measureS.
The design and operation of the circuit arrangement according to the invention will now be described in detail with reference to the accompanying drawing, in which:
~2a-~ 5~L6 A.C.Knight-2 Fig.l shows an embodiment of the circuit arrangement according to the invention, and Fig.2 shows a timing diagram.
In Fig.l, the outputs Q and Q of a b;stable multivibrator FF, whose input E
is fed with the pulse sequence, are coupled, respectively, to one of the two inputs of two monostable multivibrators MF1 and MF2, whose dwell times are tl and t2. The outputs Q1, Q2 of the monostable multivibrakors are coupled to the inputs of a nonequivalence circuit A and are monitored by this circuit for nonequivalence. The nonequivalence circuit A contains a full-wave rectifier GL having its inputs connected via amplifiers PWl and PW2 to the outputs Q1 and Q2 of the monostable multivibrators. The outputs of the full-wave rectifier energize the operating coil of a relay R hav;ng a make contact a. The latter is included in a monitoring circuit K-K' and opens th;s circuit when the relay releases.
If a pulse sequence Jl with the period t is applied to the input of thebistable multivibrator FF, the two outputs are alternately low and high, as shown in Fig.2 by the puls~ sequences J2 and J3. The two monostable multivibrators are triggered alternately by the positive edges at the out-puts of the bistable multivibrator and provide pulse sequences J4 and J5 at their outputs Ql and Q2. If the dwell times ~1 and 12 of the monostable multivibrators are equal to the pulse period t, the levels at the outputs Ql and Q2 are always symmetrically different. The output potentials are amplified by the amplifiers PWl and PW2 and applied as square-wave voltages with the period 2t to the full-wave rectifier GL, which provides a constant dc voltage U. The relay R is energized. A capacitor C connected across the relay winding smoothes any short-time drops in voltage caused by small deviations of the pulse period t from the dwell times of the monostable multivibrators.
If a pulse of the pulse sequence J1 fails to arrive (in Fig.2, the 5th pulse of the pulse sequence Jl), one of the monostable multivibrators will not be triggered. The symmetric difference of the outputs Ql and Q2 will disappear, and the dc voltage U will collapse. As a result, the relay R releases, and the monitoring circuit is opened by the contact a.
If the circuit arrangement according to the invention is to monitor a sinusoidal alternating voltage rather than a pulse sequence, a threshold switch may be placed in front of the input to the arrangement. The remainder of the circuit remains unchanged.
Although only non-inverting outputs Ql and Q2 are shown in Figure 1 it IYill be clear to those skilled in the art that monostable multivibrators MFl and MF2 also have non-inverting outputs which would be indica~ed as Ql and Q2, respectively. It will also be clear to those skilled in the art that the non-inverting inputs Ql and Q2, instead of outputs Ql and Q2, could be connec-ted to the nonequivalence circuit A via amplifiers PWl and PW2.
~n
Claims (5)
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A circuit arrangement for monitoring the arrival of a pulse in a pulse sequence within a time interval on a fail-safe basis comprising: a bistable multivibrator receiving said pulse and having an inverting output and a non-inverting output; a first monostable multivibrator having an inverting output, a non-inverting output and an input coupled to one of said inverting output and said non-inverting output of said bistable multi-vibrator; a second monostable multivibrator having an inverting output, a non-inverting output and an input coupled to the other of said inverting output and said non-inverting output of said bistable multivibrator; and a nonequivalence circuit coupled to a selected one of said inverting out-put and said non-inverting output of said first monostable multivibrator and also coupled to a like one of said inverting output and said non-inver-ting output of said second monostable multivibrator to detect nonequivalence of the levels at said selected output of said first and second monostable multivibrators.
2. A circuit arrangement as claimed in claim 1 in which the pulse sequence has a pulse period and the monostable multivibrators have dwell times which are substantially equal to the pulse period.
3. A circuit arrangement as claimed in claim 1 or 2 in which the nonequivalence circuit consists of an exclusive-OR gate followed by a de-vice indicating a fault or initiating safety measures.
4. A circuit arrangement as claimed in claim 1 or 2 in which the nonequivalence circuit consists of a full-wave rectifier and a following relay, the inputs of the full-wave rectifier being connected via amplifiers to the outputs of the delay circuits, and the relay having a make contact in a monitoring circuit.
5. A circuit arrangement as claimed in claim 1 or 2 in which the nonequivalence circuit consists of a full-wave rectifier and a variable-gain amplifier, the inputs of the full-wave rectifier being connected via amplifiers to the outputs of the delay circuits, and the variable-gain amplifier having its control input connected to the output of the full-wave rectifier and interrupting the signal flow to be amplified when the levels at the outputs of the delay circuits are equal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19782848641 DE2848641C2 (en) | 1978-11-09 | 1978-11-09 | Circuit arrangement for signal-technically safe monitoring of a pulse train |
| DEP2848641.1 | 1978-11-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1149516A true CA1149516A (en) | 1983-07-05 |
Family
ID=6054259
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000339168A Expired CA1149516A (en) | 1978-11-09 | 1979-11-05 | Circuit arrangement for monitoring a pulse sequence on a fail-safe basis |
Country Status (5)
| Country | Link |
|---|---|
| CA (1) | CA1149516A (en) |
| CH (1) | CH644479A5 (en) |
| DE (1) | DE2848641C2 (en) |
| ES (1) | ES485824A1 (en) |
| YU (1) | YU41895B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3568654D1 (en) * | 1984-09-06 | 1989-04-13 | Siemens Ag Albis | Monitoring circuit |
| DE3625318A1 (en) * | 1986-07-26 | 1988-02-04 | Licentia Gmbh | Arrangement for monitoring two clock signals in a manner which is reliable in terms of signal technology |
| DE3815531A1 (en) * | 1988-05-06 | 1989-11-23 | Heidelberger Druckmasch Ag | METHOD AND ARRANGEMENT FOR MONITORING A CLOCK SIGNAL |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE786226A (en) * | 1971-07-16 | 1973-01-15 | Siemens Ag | RHYTHM CURRENT SUPPLY FOR A TWO-CHANNEL SWITCHING CIRCUIT SYSTEM |
| DE2148072C3 (en) * | 1971-09-22 | 1980-09-04 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Circuit arrangement for monitoring binary signals for non-equivalence |
| DE2440162C2 (en) * | 1974-08-21 | 1981-12-10 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Circuit arrangement for signal-technically safe monitoring of periodic pulses |
| AT342142B (en) * | 1975-06-10 | 1978-03-10 | Siemens Ag Oesterreich | CIRCUIT ARRANGEMENT FOR FAILURE-SAFE SIGNAL PROCESSING |
| DE2701924C3 (en) * | 1977-01-19 | 1987-07-30 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Control device for rail-bound vehicles |
-
1978
- 1978-11-09 DE DE19782848641 patent/DE2848641C2/en not_active Expired
-
1979
- 1979-11-05 CA CA000339168A patent/CA1149516A/en not_active Expired
- 1979-11-07 YU YU272279A patent/YU41895B/en unknown
- 1979-11-08 CH CH998879A patent/CH644479A5/en not_active IP Right Cessation
- 1979-11-08 ES ES485824A patent/ES485824A1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| YU272279A (en) | 1982-06-30 |
| ES485824A1 (en) | 1980-05-16 |
| CH644479A5 (en) | 1984-07-31 |
| YU41895B (en) | 1988-02-29 |
| DE2848641A1 (en) | 1980-05-14 |
| DE2848641C2 (en) | 1982-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102013793A (en) | Novel method for triggering thyristor for converter valve module test | |
| DE2640971A1 (en) | METHOD FOR DETECTING AND DISPLAYING DIRECTION OF ROAD-BASED VEHICLES | |
| CA1149516A (en) | Circuit arrangement for monitoring a pulse sequence on a fail-safe basis | |
| US3829682A (en) | Pulse coded railway signal system | |
| DE59103707D1 (en) | Procedure for error detection and localization of redundant signal generators in an automation system. | |
| EP0323871A3 (en) | Voltage to frequency converter and its application in a fibre optic transmission system | |
| JPS6444154A (en) | Circuit structure for signal decoding in frequency modulation transmission | |
| ES8306654A1 (en) | Security apparatus. | |
| US3740550A (en) | Pulse coded railway signal system | |
| US3946972A (en) | Simplified cab signal receiver circuit | |
| ATE77182T1 (en) | CIRCUIT ARRANGEMENT FOR TIME REGENERATION OF BROADBAND DIGITAL SIGNALS. | |
| US3463143A (en) | Ectopic beat detector | |
| KR940022296A (en) | Secure analog interface | |
| RU1837340C (en) | Device for control of address stub of fire-alarm system | |
| US2959670A (en) | Cab signaling system for railroads | |
| EP0085625A3 (en) | Filtering and frequency detection circuits for delta modulated signals | |
| US3258653A (en) | Device for controlling a monitoring relay | |
| RU2087358C1 (en) | Method of and device for checking vigilance of operator | |
| ATE53914T1 (en) | CIRCUIT FOR MONITORING A HIGH VOLTAGE FUSE. | |
| JPS53100509A (en) | Alarm controlling method | |
| SU917144A1 (en) | Logic probe | |
| RU2003541C1 (en) | Device to determine operatorъs fatigue | |
| SU1624500A1 (en) | Device for monitoring operator activity | |
| JPS56155428A (en) | Sequence monitoring device for question-and-answer type bus | |
| SU1335937A1 (en) | Device for checking phase servo system for serviceability |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |