CA1149500A - Optoelectric device mount - Google Patents

Optoelectric device mount

Info

Publication number
CA1149500A
CA1149500A CA000406067A CA406067A CA1149500A CA 1149500 A CA1149500 A CA 1149500A CA 000406067 A CA000406067 A CA 000406067A CA 406067 A CA406067 A CA 406067A CA 1149500 A CA1149500 A CA 1149500A
Authority
CA
Canada
Prior art keywords
block
stud
tab
mount
electrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000406067A
Other languages
French (fr)
Inventor
Peter S. Zory, Jr.
Harry F. Lockwood
Frederick W. Scholl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Optical Information Systems Inc
Original Assignee
Optical Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/946,592 external-priority patent/US4240098A/en
Application filed by Optical Information Systems Inc filed Critical Optical Information Systems Inc
Priority to CA000406067A priority Critical patent/CA1149500A/en
Application granted granted Critical
Publication of CA1149500A publication Critical patent/CA1149500A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

Landscapes

  • Semiconductor Lasers (AREA)

Abstract

ABSTRACT OF THE DISCLOSURE

A mount for an electronic device such as a laser diode or light emitting diode has a metal stud with a pedstal and a screw portion. An elongated insulated tab is mounted on top of the stud. The tab has an opening at the mounted end and an electrically conducting path along the bottom, which path is perpendicular to and in contact with the stud. A block of high conductivity material is mounted through the opening in the tab and attached to the top of the stud to provide electrical and thermal conductivity therebetween.

Description

The inventlon rel~-tes to a device mount, such as for an optoelectronic device (e.g., a laser diode or light external emitting diode). The mount permits the making of external electrical contact while enabling a coaxial package geometry convenient for good heat sinking and light coupling to and from device(s) within the application.
Semlconduc~or optoelectronic devices are bodies of semiconductor material whlch include regions of oppo-site conductivity type formlng a p-n junction there-between. For some classes o devices, such as dlodelasers and light emitting diodes, when ~n external volt-age is properly applied to the p~n junction, ligh~ is genera~ed internally through the recombination of pairs o~ oppositely charged carriers. For other classes of devices, such as photodetectors, when light tphotons) strike the surface9 electron-hole pairs are formed~
generating an extern~l volt~ge.
A stud mount coaxial package of the type com-monly employed in commercial usage of a semiconductor optoelectronic device is disclosed in U.S. Paten~
3,869,~02. There9 one side of a light emissive semi-conductor device is mounted onto a copper block which in turn is secured on one face of a steel stud having a hole therein. A hollow stem pro~ruding from the oppo-site face of the stud permits passage of a wire through the hollow stem ~or providing the other connection for the semiconductor device. The wire i~ electrically in-sulated from the hollow stem~ However, bonding of the , device to the wire is generally done by "flying le~d"
bonding or hand soldering procedures, nelther of which can easily be autom~ted. Second, the pacXage is limited by its geometry in the ways in which it can be mouneed on, for example, a printed circuit board or in which it can be adapted to readily available con-3~ nectors. Typically, at least one lead o~ the psck~ge 1 must be soldered to an external connectlon. Such
2 soldering, with its attendant heat~ can degrade the
3 device.
~ package 6 for semiconductor optoelectronic devices is disclosed.
7 The package includes a device ~ount~ which provides 8 (1) s-~pport for at leas~ one optoelectronic device, 9 (2) electrical connections thereto and (3) means for removing heat generated during operation of the device.
11 The device mountcomprises a metallic stud of high 12 thermal conductivity and an elongated insulator ~ab, 13 a portion of the bottom of which is mounted on the top 14 of ~he stud. The insulator tab is provided with (1) an opening at the mounted end to expose a portion of the 16 top of the stud and (2) electrically conducting paths 17 in the elongation direction on both the top and bottom.
18 The bottom conducting path provides electrical contact 19 to the stud. The ~op conducting Bath terminates at the opening.
21 The packagecomprises the 22 device mount, t:ogethe~ with ~1) a block of high thermal 23 conductivity~ which is mounted through the opening in 24 the insulator tab and electrically attached to the top of the stud and (2) an isolation pad configured orl one 26 side of the block, at least a portion of which supports 27 an electrically conducting coating which is electrically 28 connected to at lesst one of the top conducting paehs 29 on the insulator tab and elec~rically insulsted from the block. A semiconductor optoelectronic device which 31 hss adjacent regions of opposite conductivity to form 32 a p-n junction is mounted on the block above the iso-33 lation pady with one of the regions being electrically 34 and thermally connected to the block and the other 3S region being electrically connected by a wire lead 36 eO the conductlng portion of the lsolat~on pad.
37 The right angle electrical contact between 38 the isolation pad and the top conductin~ path on the ,, J

, .'' -insulator tab is one key fea-ture. Geometrical (mechanical) contact is achieved by virtue of the package design. The electrical con-tact can be made using conductive epoxy, solder cream, or solder preform. This process is a significant improvement over hand wire bonding or flying lead techniques, which are not easily automated. In contrast, the contact arrangement described can easily be automated.
Furthex, in practice, the isolation pad is first con-figured on the block, followed by mounting of the device. After attaching the lead, the device can be readily tested by making connections, such as by test probes, to the block and isolation pad~ In this manner, quality control of the devices may be effected at an earlier stage of packaging than hexetofore possible, with consequent savings on process time and energy. Devices which pass testing are then packaged by mounting the block on the stud, as described above.
The package provides a simple means of maintaining coaxial geometry. Each step in the assembly of the package is easily automated, and the finished package can be mounted in a variety of ways so as to achieve light output in a desired direction while maintaining a coaxial geometry. In particular, the package described provides plug-in capability, without the need for soldering to leads.
More particularly in accordance with the invention there is provided a device mount comprising:
(a) a metallic stud comprising pedestal and screw portions of high thermal conductivity; and (b) an elongated insulator tab, a portion of the bottom of which is mounted on top of said stud, said insulator tab provided with (1) an opening therethrough at the mounted end, (2) an electrically conducting layer along the bottom of said insulator tab making electrical-contact to said stud and (3) at least one electrically conducting layer along the top of said insulator tab, terminating at said opening. A block of high thermal conductivity for supporting a device may be mounted through the opening and the insulator tab and electrically attached to the top of the stud and an isolation pad may be configured on the q~

block at least portion of which supporting an electrically con-ducting coating electrically connected to at least one of the top conducting layers on the insulator tab and electrically insulated from the block. The stud on the block may be of copper, the stud may be coated with a metallic film containing gold and the block coated with a film containing indium. The insulator tab may consist essentially of alumina.
Specific embodiments of the invention wi~l now be described having reference to the accompanying drawings in which:
FIGS. la and lb illustrate a prior art package for a diode laser;
FIG. 2 depicts a novel device mount comprising a metallic atud and an elongated insulator tab;
FIG. 3 in crosssection, depicts a semi-conductor optoelectronic device package;
FIG. 4 iS an enlarged view of the encircled portion of FIG. 3;

-3a-FIG. 5 illus~rates a perspective view, partlally broken away, of the psckage shown in FIG.
3, with attached cap seal;
FIG. 6 depicts an example of ~oun~lng the package on a printed circuit board for emission (or ~bsorption) of an ~ptical beam per-pendicular to the pl8ne of the clrcuit board; and FIG. 7 depicts ~n example of mounting the packsge on a printed circuit board o for emission (or absorption~ of an opticsl beam parallel ~o the pl~ne o the circuit hosrd!

The semiconductor optoelectronic devices wh~ch~m~ be beneicially pacXaged in accordance with this disclosure include those semiconductor devices which either upon electrical s~imul~t~on emi~ light ~r upon excitation by incident light generate an electrical signal. The light may be in the W~ visible or rR
regions. Exemplary of the former class of devices are diode lasers nnd light emi~ting diodes. Exemplsry of the latter class of devices are photodetectors.
The dlscussion which follows is given generally in terms relating to light-emitting devlces. However, i~
will also be understood that the elements of the pack~ge described apply as well to light-absorb.~:ng dev~ces.
The semlconductor optoelectron~c devices especlally contemplated are ~hose light-emitting devices such as diode lasers or high radiance light emieting diodes. As is well-known, such devices comprise adjacen~ regions of oppo-site conductivity forming a p-n ~unction. Electricsl connec~ion is made to each of ~he regions for opera-tion of the device. Most preferred device~ contemplated are the well-known double heterostructure diode las~rs formed from multiple layers of gallium srsenide and galliu~ alumi~m arsenide deposited on zn n-GaAs substrste. The ~ s -1 processes and various device configu~ations as such are well-2 known and do not form a part of this invention. The 3 substrate and cap p-GaAs lsyer of such device~ are
4 typically metallized. In packaging such devices, the metallized n-GaA~ substrate is commonly connected to 6 a first electrical connection (cathode) while the 7 metalli~ed p-GaAs layer is bonded to a second elec-8 trical connection (anode) in conjunction with a heat 9 sink or dissipating heat generated during operation of the device.
11 FIG. la show~ a prior art package, shown 12 here about 3x actual size, ~or a diode lsser 10~ The 13 pac~age includes a wire 11, which serves AS B csthode, 14 and a ~tud 12, to whlch is attached a hollow, threaded portion 13, which ~erves as an anode and through which 16 wire 11 p~sses. The threaded portion permits easy 17 fitting in a fastening device or otherwise mounting 18 on a circuit bo~rd to a first electrical connection.
1~ The free end of wlre 11 is typically soldered to a second elec~ric~l connection. The package also includes 21 ~he semiconductor optoelectronic device 10, such as a 22 gallium alusinum arsenide dlode laser, one end 23 (generally p-side) of which is mounted on block 14.
24 Block 14 is electr~cally snd thermally connected to the top of stud 12. The ~nd of the device not connected 26 to the block (generally n-side) is connected to the 27 wire 11 through lead 15. A glass insulating region 28 16 provides electrical insul~tion between wire 11 and 29 stud 12.
In FIG. lb, the package of FIG~ la is shown 31 together with a cap 17 ~itted with a transparent window 32 18, providing a seal around the diode laser. The 33 transparent window permits egress of optical radiation 34 19 generated by the diode laser.
LRad 15 is commonly referred to as a "flying 36 lead", inasmuch as two separate steps are required 37 for attaching both ends o~ the wire. One end is 38 typically bonded at one station, and the other end l is bonded at a second sta~ion, due to the requirement 2 of making a right angle connection, as shown in FIG.
3 la.
4 As can be seen from the prior ~rt device, optical output is approximstely coaxi~l with electrical 6 input~ but the package can only be e~sily mounted such 7 that optical output is perpendicular to the mounting 8 surace~ such a6 a printed circuit board.
9 A novel mount, shown here about 3x actual size, for a semiconductor optoelectronic device ll is illustrated in FIG. 2, which 12 shows a stud 20 comprising a pedest~l 21 and 8 screw 13 portion 22. The stud and pedest~l form a hea~ sink 14 for dissipating heat generated by the device during operation9 ~nd thus comprise a high thermal conductivity 16 material such as copper. For protection agsinst corro-17 sion, the stud may be coated with a noble metsl such 18 as gold or nickel/gold, as i8 custom~ry iin the art.
l9 To the top of the pedestal is mounted an elongated insulator tsb 23. The insulator tab may be 21 of any electrically insulating materisll such as ceramic, 22 snd is preferably electronic grade alumina. A portion 23 of the bottom of the insulator tab is mounted to the 24 stud by brazinjg or soldering. A portion of the end of the insulator tab which i~ mounted on the stud is 26 provided with an opening 24 to expose a portion of the 27 top of pedestal 21. The opening is conve~iently D-28 shaped.
29 On the bottom surf~ce of the insulator tsb is formed a conductin~ surface, or path, 25 which is 31 electrically connected to the stud and may be con-32 sidered to be e ground connection. On the top of 33 the insulator tab is formed at lea~t one electric211y 34 conducting path 26 whlch, like path 25, runs in the direction of elongation. The electricsl conductlng 36 path 26 terminates at the rim of opening 24. At least 37 one path is required in order to make connection to 38 devices contempl~ted for packaging -, ~ . .

~ 7 --1 A second, electrically indep~ndent 2 and geometrically p~rallel path may be provided, ~s 3 shown, where more than one device is employed, such as, 4 for example, where a second device is used for modul~-tion or to provide eedback or other related use in 6 con~unction with ~he first device. Alternat1Yely9 the 7 second path may be provided a~ a redundant back-up 8 contact. ~he dimensions of the insulator tab and 9 paths 25 and 26 are conveniently selected for use in edge connectors, which have standardized pin spaclngsO
11 The conducting paths 25 and 26 are of m~terials 12 that are either easily solderable or otherwise bonded 13 to ~n some fashion or else can withstand insertion lnto 14 wiping contacts such as conventional edge connector 15 pin contacts. Reference to use of the pac~sge 16 in connection with either of these approaches 17 is discussed more fully in connection with FIGS. 6 and 18 7 below. A conv~nient m~erial which meets such re-19 quirements is formed by screening a molybdPnum/manganese composition on~o the ceramic tab in the desired pa~tern, 21 firing at an e~evated temperature, followed by plating 22 wlth gold or nickel/gold. These procedur0s are well-23 known in the art.
24 The semiconductor optoelectronic package is formed, as illustrated in FIGS. 3 26 and 4, by mounting a block 30 through opening 24 onto 27 pedestal 21 of the device mount shown in FIG. 2.
28 The block provides a psth for both electrical ~nd heat 29 transfer and accordingly is of a high electrical and thermal conductivity m~terial, such as copper, 31 silver or metallized beryllia. The block ~s attached 32 to the pedestal by well-known bonding techniques 33 w~ich provide pa~hs for both electrical ~nd hea~
34 transfer. Examples of ~uch bonding techniques lnclude bonding with conducting epoxy, e.g., silver epoxy, 36 soldering, and brazing.
37 Prior to attaching the block to the pedestal, 38 an isolation pad 31 is configured on the block. The x~

1 pad may be discrete, as shown in FIGS, 3 and 4 and 2 may be mounted on a por~ion of the block by solder, 3 epoxy or similar me~ns, If ~n electrlcally insulating, 4 heat conducting ceramic such as beryllia is employed
5 85 the block, the isolation pad may be formed by
6 defining an electrically co~duc~ing area separate
7 from any other electrically conducting ~rea on the
8 block.
9 A discrete isolation p~d may be of any elec-trically insulating material9 such ~s ceramic, ~nd is 11 preferably electronic grsde alumina. At least ~ por-12 tion of one surface (top) is provlded with an electrically 13 conducting coating 32; the opposite surface (bottom) 14 may or may not be provided with a metalllzed coating.
The coatings may be formed in the same manner and com-16 prise the same materials as the conducting psths 25 and 17 26 on the insulator tab, 18 On the upper portion of block 30 is mounted 19 8 semiconductor optoelectronic device 33 having regions of opposite conductivity 33a and 33b9 forming 8 p-n 21 junction 33c. The device is mounted in proximity to 22 the isolation pa~, ususlly about 50~ m away, for con-23 venient interconnection.
24 The block is conveniently coated with indium, tin or other low melting metal or alloy (not shown) 26 prior to configurir.g the isolation pad and mounting 27 the device, since the devi~e (and discrete isolation 28 pad, if provided with a met~lliæed coating on its bottom) 29 msy then be easily soldered to the b~ock, The thick-ness of the metallized coating r~nges from about ~ to 31 4 ~m. The indium coating renders the soldering opera-32 tion quite reproducible and is readily adap~able to 33 batch processing. The indium or other low melting 34 metal or alloy i~ applied to the block by electroplat-35 in~ or vapor deposition, over a ~llm of nickel or other 36 barrier metal (about 0.5 ~m) deposited on the block as 37 a barrier layer to prevent diffusion of copper in~o 38 the device, ~L~f~9553 [) g 1 If block 30 comprises a heat conducting, 2 electrically lnsulating material, such as beryllia, 3 then isolation pad 31 may be configured on the block 4 by leaving a por~ion of the block at the appropriate S location uncoated with the solderable fllm. Alterna-6 tivelyJ a portion of the solderable film m~y be re-7 ~oved to configure the isolation pad. In any event, 8 a portion of the isolation pad msy then be coated with 9 the electrically conducting coating 32, as described above, ~n such a manner as to be electrically insulated 11 from any conduct~ng coating on the bloc~.
12 Forming both the isolation pad and the device 13 on the block permits essy attachment of lead 34, one 14 end of which is bonded to device 33 and the other end of which is bonded to the conductlng portion 32 of 16 the isolation pad. Standard wire bonding techniques, 1/ such as ultrasonic or thermocompression bonding, are 18 conveniently employed in bonding lead 34. As can be 19 seen from the Figures, both ends of lead 34 are in parallel planes in the same dimenslon and requi~e no 21 reorientation of the pack~ge to bond both ends. Con-22 sequently, the bonding operation is readily automsted 23 and msy be done at o~e station.
24 Block 30 and its associated componen~s are then mounted in opening 24, as discussed above. Connec-26 tion of conductlng portion 32 to conducting path 26 27 is then made employing electrically conducting means 28 3S, quch as conducting epoxy9 solder cream or solder 29 pre~orm. Detsils of the mounting of the block and its associated components are shown more cle~rly ln 31 FIG. 4, which is an enlargement of the encircled por~
32 tion of FIG. 3.
33 As wit~ prior art devices, ~ seal msy be 34 provided, flS shown in FIG. 5. A cap 36 with window 37, which is substantislly transparent ~o the radia-36 tion emitted (or absorbed) by the devlce, ls centered 37 around the periphery of open~ng 24 and attached, such 38 as with an epoxy. If electrical isolatlon of a .

5~
- 10 1 metflllic cap from conducting paths 26 is desired9 2 a non-conducting epoxy may be employed. Alternstively, 3 the C8p may be of ceramic or other insula~ive material.
4 A hermetic seal may be formed by a slight modiflcation of the insulator tab~ For example, one 6 modification (no~ shown) comprises forming a ceramic 7 or other insulating ring around opening 24~ having 8 the same diameter 8S cap 36, and crossing over conduct-9 ing pa~hs 26. The top surface of the ring is then me~allized by conven~ional techniques, and the cap ll is bonded, as by welding or soldering~ to the metallized 12 ring.
13 The package described provi~es a 14 simple means of maintaining a substantially coaxial configuration of a semiconductor optoelectronic device.
16 Stimulated emission 38 (or absorbed rsdiation) travels 17 in a direction perpendicular to the thermal reference 18 plane TT (shown in FIG. 3), which is part of a heat 19 sink, such as a chassis, conductive circuit board or other heat spreading device. All steps in the assembly 21 procedure are easily accomplished and easily ~u~om~ted 22 Pack~ging optoelectronic devices as descrihed 2~ provides another benefit. In the 24 sequence o~ processin~, the isolation pad 31 is ~irst configured on the block 30, then one portion of the 26 device 33 is bonded to the block above the isolation 27 pad. The lead 34 is ~hen attached connecting the 28 other portion of the device and isolation pad. At this 29 point, the device m~y be readily te~ted by making con-nections, such as by test probes, to the block and 31 isolation psd. Devices which fail such testing m~y 32 thus be screened out earlier th~n heretofoxe possible, 33 with consequent s8vings on process time and energy.
34 Devices which pass such testing may then be p~ckaged by mounting the block onto pedestal 21, as described 36 above 37 The plug-ln capabillty provided by the pac~age 38 permits mounting the package in a 5~
11 -1 number of diferen~ orients~ions. FIGS. 6 and 7 demon-2 strate two possible way~ of mounting the package, al-3 though there are other w~ys as well. For ex~mple, as 4 shown in FIG. 6, the package may be bolted to a printed S circuit bosrd 50 and at lesst one lead 51 conventionally 6 bonded between at leas~ one conducting path 26 and a 7 first electrical contac~ 52 to make electrical conner-8 tion thereto. Conducting path 25 on the bottom of in-9 sulator tab 23 may make compressive con~act to a second electrical contact 53 on ~he printed circuit board to 11 complete the circuit. A heat sink 54 may be employed
12 as part of the ~ttachment to ~crew portion 2~. Outpu~
13 (or incident~ beam 38 is then perpendicular to the
14 plane of the prin~ed circuit board.
Another configuratlon more convenient for 16 changing components is shown in FIG. 7. A conventional 17 edge connector 60 is attached to printed circui~ board 18 50 with circuit paths (not shown). Such connectors 19 comprise a plurality of wiping contacts for insertion of devices and a corresponding plurality of pin connec-21 tions for externsl elec~rieal connec~ion, as is well~
2~ known. In this configuration, the output (or input) 23 beam 38 is em~tted (or absorbed) parallel to the plsne 24 of the printed circuit board~ whlch is convenient for the u~ual stacked psrallel array of printed circuit 26 boards. A heat sink 53 can also be atta~hed ~o screw 27 portion 22 as desired.
~8 EXAMPLE
__ 29 An elongated insulator t~b of electronic grsde A1203 having the configuration shown in FIG. 2 31 was construceed with a D-shaped opening at one end.
32 The top and bottom of the tab were metalli~ed in the 33 pattern depicted in FIG. 2, employing a layer of Mo-Mn 34 of 0.5 mils thick formed by firing directly on the ceram~c, followed by a plated l~yer of st least l x 36 10 4 inch Ni and a plated layer of at least 5 x 10 5 37 inch Au. A copper stud9 comprislng pedestal and screw 38 portions and costed by plated lsyers of Ni and Au of . .

3S~O
.~

about the same thickne~s aq above,, w~s silver brazed to 2 the bottom of the lnsulator tab9 such that a port~on 3 of the top of the pedestal was exposed through the 4 opening .
A copper block was plated wi~h 0.5 ~ m Ni, 6 followed by 2,~ m In. An isolation pad of electronic 7 grade A1203, metallized top and bottom with nickel and 8 gold, of about the same thickne~ses as the metalli~ed 9 layers on the insulator tab, was attached to the block by soldering. The p-side of a (&a,Al)As double hetero-11 structure diode laser was attached by soldering to ~he 12 top edge of the copper block, on the same ~ide as the 13 isolation pad, about 50,~ m away. One end of a wire 14 lead (Au; dlame~er 1 mil) was attached to the n-slde of the device, and the other end to the exposed top of 16 ehe isolation pad, employing conventional ultrasonic 17 wire bonding.
18 The copper bloc~, with mounted device connected 19 to isolation pad, was placed in ~ jig provided with two test probes for ~aking con~act to the copper block and 21 isolation pad. Followlng successful evaluation of the 22 device, the block was mounted through the opening of 23 the insulator tab on the top o ~he copper stud us~ng 24 silver epoxy, with the block ~nd associated components substantially configured as shown in FIGS. 3 and 4.
26 Electrical connection was made between the isolation 27 pad ~nd the metall~zed paths on top of the insula~ed 28 tab using silver epo~y.
29 Finally~ a metal cap having a transparent window on top W8S attached around the opening of the 31 insulstor tab, employlng 5 non-conducting epoxy. The 32 completed psc~age was then mounted in an edge connector 33 similar to that shown in FIG. 7 and to which electrical 34 connection was made. The packaged diode laser was 3S then sub~ected to further testing and evaluation.

~ .

, -

Claims (6)

-THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OF PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A device mount comprising:
(a) a metallic stud comprising pedestal and screw portions of high thermal conductivity; and (b) an elongated insulator tab, a portion of the bottom of which is mounted on top of said stud, said insultation tab provided with (1) an opening therethrough at the mounted end, (2) an electrically conducting layer along the bottom of said insulator tab making electrical contact to said stud and (3) at least one electrically conducting layer along the top of said insulator tab, perpendicular to the axial plane of the metallic stud terminating at said opening in the insulator tab; and (c) a block of high thermal conductivity for supporting a device, said block mounted through said opening in said insulator tab and permitting light egress to said device, said block being electrically attached to said top of said stud; and (d) an isolation pad configured on said block, at least a portion of which supports an electrically conducting coating which is electrically connected to at least one of said top conducting layers on said insulator tab and electrically insulated from said block.
2. The mount of Claim 1 in which said stud is further coated with at least one conducting metallic film comprising gold.
3. The mount of Claim 1 in which at least a portion of said block is coated with at least one film comprising indium.
4. The mount of Claim 1 in which said insulator tab consists essentially of alumina.
5. The mount of Claim 1 in which said isolation pad comprises a body consisting essentially of alumina, the bottom of which is mounted on one side of said block and at least a portion of the top of which supports said electrically conducting coating.
6. The mount of Claim 1 in which said stud and said block consist essentially of copper.
CA000406067A 1978-09-28 1982-06-25 Optoelectric device mount Expired CA1149500A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA000406067A CA1149500A (en) 1978-09-28 1982-06-25 Optoelectric device mount

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US05/946,592 US4240098A (en) 1978-09-28 1978-09-28 Semiconductor optoelectronic device package
US946,592 1978-09-28
CA000334664A CA1142252A (en) 1978-09-28 1979-08-29 Semiconductor optoelectronic device package
CA000406067A CA1149500A (en) 1978-09-28 1982-06-25 Optoelectric device mount

Publications (1)

Publication Number Publication Date
CA1149500A true CA1149500A (en) 1983-07-05

Family

ID=27166382

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000406067A Expired CA1149500A (en) 1978-09-28 1982-06-25 Optoelectric device mount

Country Status (1)

Country Link
CA (1) CA1149500A (en)

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