CA1143853A - Busy indicating arrangement for bus in a data processing system - Google Patents
Busy indicating arrangement for bus in a data processing systemInfo
- Publication number
- CA1143853A CA1143853A CA000347498A CA347498A CA1143853A CA 1143853 A CA1143853 A CA 1143853A CA 000347498 A CA000347498 A CA 000347498A CA 347498 A CA347498 A CA 347498A CA 1143853 A CA1143853 A CA 1143853A
- Authority
- CA
- Canada
- Prior art keywords
- data
- bus
- information
- interconnection
- dbbz
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 title claims abstract description 31
- 238000012546 transfer Methods 0.000 claims abstract description 23
- 230000000694 effects Effects 0.000 claims description 2
- 230000015654 memory Effects 0.000 description 35
- 230000006870 function Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000003993 interaction Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 241000490229 Eucephalus Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000002405 diagnostic procedure Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000063 preceeding effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
- G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
- Microcomputers (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US1935179A | 1979-03-12 | 1979-03-12 | |
| US019,351 | 1979-03-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1143853A true CA1143853A (en) | 1983-03-29 |
Family
ID=21792737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000347498A Expired CA1143853A (en) | 1979-03-12 | 1980-03-12 | Busy indicating arrangement for bus in a data processing system |
Country Status (10)
| Country | Link |
|---|---|
| JP (1) | JPS6051151B2 (de) |
| AU (1) | AU542538B2 (de) |
| BR (1) | BR8001527A (de) |
| CA (1) | CA1143853A (de) |
| DE (1) | DE3009529A1 (de) |
| ES (1) | ES489424A0 (de) |
| FR (1) | FR2451601A1 (de) |
| GB (1) | GB2044967A (de) |
| IT (1) | IT1129639B (de) |
| SE (1) | SE8001908L (de) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU576348B2 (en) * | 1984-02-29 | 1988-08-25 | Measurex Corporation | Processing information |
| US4669056A (en) * | 1984-07-31 | 1987-05-26 | International Business Machines Corporation | Data processing system with a plurality of processors accessing a common bus to interleaved storage |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2997896A (en) * | 1958-10-08 | 1961-08-29 | Preston Martin | Variable speed drives |
| US3999170A (en) * | 1975-01-08 | 1976-12-21 | Hewlett-Packard Company | Multiple access interconnect system |
| FR2407522B1 (fr) * | 1977-10-25 | 1989-03-31 | Digital Equipment Corp | Systeme de traitement de donnees avec division de l'operation de lecture |
-
1980
- 1980-03-11 ES ES489424A patent/ES489424A0/es active Granted
- 1980-03-11 SE SE8001908A patent/SE8001908L/ not_active Application Discontinuation
- 1980-03-12 BR BR8001527A patent/BR8001527A/pt unknown
- 1980-03-12 DE DE19803009529 patent/DE3009529A1/de not_active Withdrawn
- 1980-03-12 AU AU56376/80A patent/AU542538B2/en not_active Ceased
- 1980-03-12 CA CA000347498A patent/CA1143853A/en not_active Expired
- 1980-03-12 JP JP55031490A patent/JPS6051151B2/ja not_active Expired
- 1980-03-12 GB GB8008339A patent/GB2044967A/en not_active Withdrawn
- 1980-03-12 FR FR8005575A patent/FR2451601A1/fr active Pending
- 1980-03-12 IT IT20544/80A patent/IT1129639B/it active
Also Published As
| Publication number | Publication date |
|---|---|
| FR2451601A1 (fr) | 1980-10-10 |
| DE3009529A1 (de) | 1980-09-25 |
| AU542538B2 (en) | 1985-02-28 |
| ES8103407A1 (es) | 1981-02-16 |
| IT1129639B (it) | 1986-06-11 |
| IT8020544A0 (it) | 1980-03-12 |
| AU5637680A (en) | 1980-09-18 |
| SE8001908L (sv) | 1980-09-13 |
| ES489424A0 (es) | 1981-02-16 |
| JPS55134427A (en) | 1980-10-20 |
| JPS6051151B2 (ja) | 1985-11-12 |
| GB2044967A (en) | 1980-10-22 |
| BR8001527A (pt) | 1980-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4488217A (en) | Data processing system with lock-unlock instruction facility | |
| US4038642A (en) | Input/output interface logic for concurrent operations | |
| US4381542A (en) | System for interrupt arbitration | |
| EP0343770B1 (de) | Mehrfachbus-Mikrorechnersystem mit Busarbitrierung | |
| CA1078524A (en) | Destination selection apparatus for a bus oriented computer system | |
| US5555425A (en) | Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters | |
| US5535341A (en) | Apparatus and method for determining the status of data buffers in a bridge between two buses during a flush operation | |
| US4053950A (en) | Residual status reporting during chained cycle steal input/output operations | |
| US4229791A (en) | Distributed arbitration circuitry for data processing system | |
| EP0535696B1 (de) | Vorrichtung zur Vermeidung von Prozessorblockierungen in einem Multiprozessorsystem | |
| EP0157075A1 (de) | Modulares Datenverarbeitungssystem | |
| EP0311704B1 (de) | Schaltung zur Blockierungsverhinderung von Hochprioritätsanforderungen an eine Systemsteuerung | |
| CA1221173A (en) | Microcomputer system with bus control means for peripheral processing devices | |
| CA1158737A (en) | Shared synchronous memory multiprocessing arrangement | |
| US5047921A (en) | Asynchronous microprocessor random access memory arbitration controller | |
| US4695944A (en) | Computer system comprising a data, address and control signal bus which comprises a left bus and a right bus | |
| US4509115A (en) | Two-port memory controller | |
| CA1103326A (en) | Common polling logic for input/output interrupt or cycle steal data transfer requests | |
| US5805844A (en) | Control circuit for an interface between a PCI bus and a module bus | |
| EP0795157A1 (de) | Busbrücke | |
| CA1143854A (en) | Apparatus for interconnecting the units of a data processing system | |
| GB1589180A (en) | Data processing apparatus | |
| US5951667A (en) | Method and apparatus for connecting expansion buses to a peripheral component interconnect bus | |
| US4245303A (en) | Memory for data processing system with command and data buffering | |
| CA1145001A (en) | Data processing system having centralized bus priority resolution |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |