CA1142445A - Signal-controllable attenuator employing a digital-to-analog converter - Google Patents
Signal-controllable attenuator employing a digital-to-analog converterInfo
- Publication number
- CA1142445A CA1142445A CA000352995A CA352995A CA1142445A CA 1142445 A CA1142445 A CA 1142445A CA 000352995 A CA000352995 A CA 000352995A CA 352995 A CA352995 A CA 352995A CA 1142445 A CA1142445 A CA 1142445A
- Authority
- CA
- Canada
- Prior art keywords
- signal
- digital
- control
- switch
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011159 matrix material Substances 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims 3
- 238000012886 linear function Methods 0.000 claims 1
- 230000005236 sound signal Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/001—Digital control of analog signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/78—Simultaneous conversion using ladder network
- H03M1/785—Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
Landscapes
- Analogue/Digital Conversion (AREA)
- Control Of Amplification And Gain Control (AREA)
- Networks Using Active Elements (AREA)
Abstract
IMPROVED SIGNAL-CONTROLLABLE ATTENUATOR
EMPLOYING A DIGITAL-TO-ANALOG CONVERTER
ABSTRACT OF THE DISCLOSURE
A signal-controllable attenuator comprising a 17-bit multiplying-type digital-to-analog converter having an R/2R
ladder network to set the bit weights, and controlled by a 6-bit remotely-generated command signal to vary the attenuation in steps of 1.5 dB through arrange of 88 dB. The 1.5 dB steps are controlled by a 4-bit code signal responsive to two bits of the command signal. The 4-bit code signal is directed to four successive bit input terminals of the converter. Which four DAC input terminals are selected is controlled by a shifting matrix which shifts the four bits along the DAC input terminals to a position determined by the other four bits of the command signal.
EMPLOYING A DIGITAL-TO-ANALOG CONVERTER
ABSTRACT OF THE DISCLOSURE
A signal-controllable attenuator comprising a 17-bit multiplying-type digital-to-analog converter having an R/2R
ladder network to set the bit weights, and controlled by a 6-bit remotely-generated command signal to vary the attenuation in steps of 1.5 dB through arrange of 88 dB. The 1.5 dB steps are controlled by a 4-bit code signal responsive to two bits of the command signal. The 4-bit code signal is directed to four successive bit input terminals of the converter. Which four DAC input terminals are selected is controlled by a shifting matrix which shifts the four bits along the DAC input terminals to a position determined by the other four bits of the command signal.
Description
~244~
~ BACKGROUND O~ THE INVENTION
Field of the Invention This invention rela-tes to controllable-attenuation devices such as may be used to control the volume level o~ an audio signal. More particularly, this invention relates to .
variable-attenuation apparatus utilizing a digital-to-analog converter.
.
Descri~on of the_Prio_ Art Variable attenuation devices have been used ~or many years in numerous applications. One common application is in the field of sound reproduction where it is desired to adjust the sound level to provide for preferred listening conditions. Such an adjustment can easily be effected by the'use of a conventional potentiometer, as in the usual volume control.~ More recently, however, it has been desired to make such adjustments from a - remote Location,~as by means of'an electrical signal, and this result cannot be achieved economically by conventional volume-control apparatus It has been suggested that a digital-to-analog converter may be employed to adjust the'level o~ an audio signal. Such a proposal is set forth in the article "Get Wide-Range Digitally .
~2~4~ -Controlled Attenuation with a Companding D/A" by Walter Jung and Will Ritmanich, appearing in Electronic Design 23, for November 8, 1978. That proposal however suffers from important disadvantages, particularly in requiring a relatively complex and therefore costly circuit arrangement.
S~ _ .
In a preferred embodiment of the invention to be de-scribed hereinafter in detail, a signal-controlled attenuator is provided utiliæing a multiplying digital-to-analog converter of the type hàving an ~/2R ladder network. In such a network, the atten-uation provided by any one stage differs ~rom the attenuation of any adjacent stage by 6 dB (actually 6.0206 dB); that is, the shunt currents are in a ratio of 2:1 in successive legs of the ladder.
Thus by turnlng on one stage at a time, in sequential progression, the attenuation presented by the ladder circuit can be varied in 6 dB steps.
., , : .
Steps of 6 dB do not provide a sufficiently fine resolu-tion for many applications, including that of attenuating an audio signal. To solve this problem,the digital-to-analog attenuator to be described herein includes means for controlling a set of succes-sive ladder stages of sufficient number to obtain the required resolution. In the present embodiment, the nominal design resolu-- tion is 1.5 dB per step. For that purpose, four successive stages are controlled by a 4-bit code signal having four different codes providing a variability of 0, 1.5, 3.0 and 4.5 dB~ T~e next step to 6.0 dB is obtained by shifting the 4-bit code signal by one ~l~Z~a45 position (towards grea-ter a-ttenuation) to the next successive group of four ladder stages, and returning the ~-bit code to the original O dB code setting. Since the ladder network provides 6 dB per stage, a shift by one ladder posi-tion adds another 6 dB to what-ever attenuation is developed by the 4-bit code. Thus, by return-ing the code to the O dB setting, the one-position shift will xesult in the desired net attenuation of 6 dB, as the next s~ep beyond 4.5 dB.
Further steps in the progression are developed in compar-IO able fashion, based OTl this principle. A practical device construct-ed in accordance with this invention, and employing a 17-bit digital-to-analog converter, provided a total attenuation range of 88.5 dB, in steps of 1.5 dB.
.
Accordingly, it is an object o~ this invention to provide improved signal-controllable attenuation apparatus. A more specific object of this invention is to provlde such apparatus having supe-rior performance specifications and which can be manufactured rela-tively economically. Other objects, aspects and advantages of the invention will in part be pointed out in, and in part apparent from, the following description considered together with the accompanying drawings.
, BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a block diagram o~ one embodiment of the invention; and FIGURES 2A and 2B together present a detailed schematic of a preferred embodiment.
~ BACKGROUND O~ THE INVENTION
Field of the Invention This invention rela-tes to controllable-attenuation devices such as may be used to control the volume level o~ an audio signal. More particularly, this invention relates to .
variable-attenuation apparatus utilizing a digital-to-analog converter.
.
Descri~on of the_Prio_ Art Variable attenuation devices have been used ~or many years in numerous applications. One common application is in the field of sound reproduction where it is desired to adjust the sound level to provide for preferred listening conditions. Such an adjustment can easily be effected by the'use of a conventional potentiometer, as in the usual volume control.~ More recently, however, it has been desired to make such adjustments from a - remote Location,~as by means of'an electrical signal, and this result cannot be achieved economically by conventional volume-control apparatus It has been suggested that a digital-to-analog converter may be employed to adjust the'level o~ an audio signal. Such a proposal is set forth in the article "Get Wide-Range Digitally .
~2~4~ -Controlled Attenuation with a Companding D/A" by Walter Jung and Will Ritmanich, appearing in Electronic Design 23, for November 8, 1978. That proposal however suffers from important disadvantages, particularly in requiring a relatively complex and therefore costly circuit arrangement.
S~ _ .
In a preferred embodiment of the invention to be de-scribed hereinafter in detail, a signal-controlled attenuator is provided utiliæing a multiplying digital-to-analog converter of the type hàving an ~/2R ladder network. In such a network, the atten-uation provided by any one stage differs ~rom the attenuation of any adjacent stage by 6 dB (actually 6.0206 dB); that is, the shunt currents are in a ratio of 2:1 in successive legs of the ladder.
Thus by turnlng on one stage at a time, in sequential progression, the attenuation presented by the ladder circuit can be varied in 6 dB steps.
., , : .
Steps of 6 dB do not provide a sufficiently fine resolu-tion for many applications, including that of attenuating an audio signal. To solve this problem,the digital-to-analog attenuator to be described herein includes means for controlling a set of succes-sive ladder stages of sufficient number to obtain the required resolution. In the present embodiment, the nominal design resolu-- tion is 1.5 dB per step. For that purpose, four successive stages are controlled by a 4-bit code signal having four different codes providing a variability of 0, 1.5, 3.0 and 4.5 dB~ T~e next step to 6.0 dB is obtained by shifting the 4-bit code signal by one ~l~Z~a45 position (towards grea-ter a-ttenuation) to the next successive group of four ladder stages, and returning the ~-bit code to the original O dB code setting. Since the ladder network provides 6 dB per stage, a shift by one ladder posi-tion adds another 6 dB to what-ever attenuation is developed by the 4-bit code. Thus, by return-ing the code to the O dB setting, the one-position shift will xesult in the desired net attenuation of 6 dB, as the next s~ep beyond 4.5 dB.
Further steps in the progression are developed in compar-IO able fashion, based OTl this principle. A practical device construct-ed in accordance with this invention, and employing a 17-bit digital-to-analog converter, provided a total attenuation range of 88.5 dB, in steps of 1.5 dB.
.
Accordingly, it is an object o~ this invention to provide improved signal-controllable attenuation apparatus. A more specific object of this invention is to provlde such apparatus having supe-rior performance specifications and which can be manufactured rela-tively economically. Other objects, aspects and advantages of the invention will in part be pointed out in, and in part apparent from, the following description considered together with the accompanying drawings.
, BRIEF DESCRIPTION OF THE DRAWINGS
FIGURE 1 is a block diagram o~ one embodiment of the invention; and FIGURES 2A and 2B together present a detailed schematic of a preferred embodiment.
2~45 DESCRIPTIO~ OF THE PREFERRED E~ODIMENT
Referring now to Figure 1, the apparatus shown in block outline comprises a conventional multi-stage multiplying digital-to-analog converter 10 (also called a "DAC") of the type utiliz-ing an R/2R ladder network for setting the bit weights in binary progression. The input voltage to be attenuated is applied to the reference voltage terminal 12 of the DAC, and the digital input signal for controlling the attenuation is supplied by a set of digital lines 14 connected to respective switch control ter-minals 16. In the present embodiment, the DAC 10 has a 17-bit resolution, so there is a total of 17 digitallines 14.
-A current output signal is developed from the DAC outputterminal 18 in accordance with the logic pattern (i.e. æero's and one's) of the applied digital signal on the digital lines 14.
This output current is directed to an operational amplifier 20 having a feedback resistor Rf to produce a corresponding output voltage on the amplifier output terminal 22.
: ', The remainder of the Pigure 1 circuitry comprises control apparatus, generally indicated at 30, for determining which of the - 20 digital input lines 14 for the DAC lD will be activated in response to a 6-bit command signal applied to a set of six input terminals 32. Typically this command signal is developed remotely from the attenuator equipment. The 6-bit digital command signal comprises two separate signal groups having different functions. The first 4~
signal group 34 c~mprises the two least-significant bits (O, 1) of the 6-bit signal, and the second signal group 36 comprises the remaining four bits (Nos. 2-5).
The first signal group 34 of the 6-bi-t command signal is directed to the input of a code-developing circuit comprising (in the Figure 1 arrangement) a known read-only-memory device (ROM) 38 arranged to produce on its output lines40 a 4-bit code corresponding to the particular state of the two bits of the applied signal group 34. The second signal group 36 is directed to a conventional 4/16 line decoder 42 which activates one of its sixteen output lines 44 in accordance with the four-bit signal group 36 , The code lines 40 and the decoder ~utput lines ~4 ars connected to and jointly con-trol a shifting matrix generally indicated at 50. This device (details are shown in Figure 2A) serves in known fashlon to transfer the 4-bit code on the four lines 40 to four corresponding successive lines of the. di~ital lines 14 for the DAC 10. Which set of four llnes 14 is selected by the shifting matrlx is determined by which of the decoder lines 44 is activated.
For example, if the left-most line 44a is activated, the 4-bit code from the ROM 38 is transferred to the four left-most digital lines 14a, 14b, 14c, 14d If the next decoder line 44b is activated, the 4-bit code from the ROM is shifted to the right one step, and thus is applied to the next set of successive _ 5 _ ~ ~24~S
digital lines 14b, 14c, 14d, 14e. Accordingly, the 4-bit code signal is in effect directed through a four-bit "window" opening on the 17 switch control terminals 16 of the DAC, with the window being positioned along the array of control terminals in conform-ance with the state of the 4-bit signal group 36.
In a simplified version of the attenuator of the present invention, the ROM 38 is replaced by a buffer/inverter circuit 60 (see Figures 2A, 2B) responsive to the two bits of the command signal group 34. The outer code lines 40a, 40d are maintained at ground potential for all codes. As shown ln Figure 2A, the ~our code lines are connected to respective sets of FET trans--mission gates 62, 64, 66, 68 which are activatable in groups of four by any of the sixteen decoder output lines 44a, 44b, etc.
Each group of four gates, in turn, connects to four corresponding lines of the DAC digital lines 14 to supply the 4-bit code there-to~ when activated by the corresponding decoder lines 44a, etc.
In the partlcular arrangement dlsclosed herein, the four different 4-bit codes for controlling the inputs of the gates 62-68 were selected as follows:
~e CodeAttenuation (dB) 1. 1111 O
- 2. 1101 1.5
Referring now to Figure 1, the apparatus shown in block outline comprises a conventional multi-stage multiplying digital-to-analog converter 10 (also called a "DAC") of the type utiliz-ing an R/2R ladder network for setting the bit weights in binary progression. The input voltage to be attenuated is applied to the reference voltage terminal 12 of the DAC, and the digital input signal for controlling the attenuation is supplied by a set of digital lines 14 connected to respective switch control ter-minals 16. In the present embodiment, the DAC 10 has a 17-bit resolution, so there is a total of 17 digitallines 14.
-A current output signal is developed from the DAC outputterminal 18 in accordance with the logic pattern (i.e. æero's and one's) of the applied digital signal on the digital lines 14.
This output current is directed to an operational amplifier 20 having a feedback resistor Rf to produce a corresponding output voltage on the amplifier output terminal 22.
: ', The remainder of the Pigure 1 circuitry comprises control apparatus, generally indicated at 30, for determining which of the - 20 digital input lines 14 for the DAC lD will be activated in response to a 6-bit command signal applied to a set of six input terminals 32. Typically this command signal is developed remotely from the attenuator equipment. The 6-bit digital command signal comprises two separate signal groups having different functions. The first 4~
signal group 34 c~mprises the two least-significant bits (O, 1) of the 6-bit signal, and the second signal group 36 comprises the remaining four bits (Nos. 2-5).
The first signal group 34 of the 6-bi-t command signal is directed to the input of a code-developing circuit comprising (in the Figure 1 arrangement) a known read-only-memory device (ROM) 38 arranged to produce on its output lines40 a 4-bit code corresponding to the particular state of the two bits of the applied signal group 34. The second signal group 36 is directed to a conventional 4/16 line decoder 42 which activates one of its sixteen output lines 44 in accordance with the four-bit signal group 36 , The code lines 40 and the decoder ~utput lines ~4 ars connected to and jointly con-trol a shifting matrix generally indicated at 50. This device (details are shown in Figure 2A) serves in known fashlon to transfer the 4-bit code on the four lines 40 to four corresponding successive lines of the. di~ital lines 14 for the DAC 10. Which set of four llnes 14 is selected by the shifting matrlx is determined by which of the decoder lines 44 is activated.
For example, if the left-most line 44a is activated, the 4-bit code from the ROM 38 is transferred to the four left-most digital lines 14a, 14b, 14c, 14d If the next decoder line 44b is activated, the 4-bit code from the ROM is shifted to the right one step, and thus is applied to the next set of successive _ 5 _ ~ ~24~S
digital lines 14b, 14c, 14d, 14e. Accordingly, the 4-bit code signal is in effect directed through a four-bit "window" opening on the 17 switch control terminals 16 of the DAC, with the window being positioned along the array of control terminals in conform-ance with the state of the 4-bit signal group 36.
In a simplified version of the attenuator of the present invention, the ROM 38 is replaced by a buffer/inverter circuit 60 (see Figures 2A, 2B) responsive to the two bits of the command signal group 34. The outer code lines 40a, 40d are maintained at ground potential for all codes. As shown ln Figure 2A, the ~our code lines are connected to respective sets of FET trans--mission gates 62, 64, 66, 68 which are activatable in groups of four by any of the sixteen decoder output lines 44a, 44b, etc.
Each group of four gates, in turn, connects to four corresponding lines of the DAC digital lines 14 to supply the 4-bit code there-to~ when activated by the corresponding decoder lines 44a, etc.
In the partlcular arrangement dlsclosed herein, the four different 4-bit codes for controlling the inputs of the gates 62-68 were selected as follows:
~e CodeAttenuation (dB) 1. 1111 O
- 2. 1101 1.5
3. 1011 3 0 ~, 1001 ~-5 ~1~2445 If the first code (1111) is directed to the left-most set of four digital lines 14a, 14b, 14c, 14d, the first four DAC switches 70a, 70b, 70c, 70d are closed. Thus, current flows from the input terminal 12 of the DAC, through the shunt elements 72a, 72b, 72c and 72d of the R/2R ladder 74, and out to the output terminal 18.
Assuming an input voltage ot 12 volts, and shunt resistors of 24K
(with series resistors of 12K), the current through the first ~tage of the ladder will be 0.5 ma, and the currents through the three following successive stages will be 0.25, 0.125 and 0.0625 ma, - 10 in conformance with standard binary weighting. Thus the total output current will be 0.9375 ma. This current is directed tG the operational amplifier 20 which, with a 12.8K feedbacX resistor Rf, will produce an output of 12 volts, corresponding to 0 dB
attenuation.
~: , - ,' The four 4-bit codes on the code lines 40 are designed to provide nominal attenuation steps of 1.5 dB. The fourth step in the cycle of these codes will produce a nominal attenuation of
Assuming an input voltage ot 12 volts, and shunt resistors of 24K
(with series resistors of 12K), the current through the first ~tage of the ladder will be 0.5 ma, and the currents through the three following successive stages will be 0.25, 0.125 and 0.0625 ma, - 10 in conformance with standard binary weighting. Thus the total output current will be 0.9375 ma. This current is directed tG the operational amplifier 20 which, with a 12.8K feedbacX resistor Rf, will produce an output of 12 volts, corresponding to 0 dB
attenuation.
~: , - ,' The four 4-bit codes on the code lines 40 are designed to provide nominal attenuation steps of 1.5 dB. The fourth step in the cycle of these codes will produce a nominal attenuation of
4.5 dB. For the next step to 6 dB, the 4-bit code is returned to its original zero state (1111), and the complete set o ~ code signals 20 is shifted one position to the right, to close the switches for the -next set of corresponding ladder switches 70b, 70c, 70d, 70e.
. . :
For illustrative purposes, Table I sets forth the cur-rents and output levels in detail for the first eight attenuation - steps. It will be evi~lent from these data that the attenuation ~z~s e ~o ~t ~1 _ ~`~D~) ~U~ d' N ~1 Id ~ `Ul OU:)~1~CO ~ ~
h S:: ~ ~t~)o o ~ ~ o o O ~ O ~ .
~I E3 O
,l t-- ~ ~~D00 ~D ~u~
~ ~ m ~ o ~ o o ~I N ~~D1` ~ O N
.
~rl ~9~ ~t~ O O
O ~D~) O ~~D O ~' O CO1`~D U~
~ O
O > ~1 0 0 0 0 0 0 0 0 .
u~
O O I` t~l [' N ~ ~D ~ ~ d' h h ~ D ~ N N
~ ~ . . . . . .. . n~
~ C~ : ' ~
I~
~
~1 O ~ : ', ~ O ~ ,~
O O
u~ m l l O I . ,~ N
~ d' m~ ~ o ~ o ~ o ~ O
I O ~ ~ O O ~ ~1 0 0 ~
. - o . ~ .,, m ", O m o u o n o e ~ O ~ ~, o a) -- ~ D 1` ~ O N ' ~ IJ
~¢
- . --8--1~4Z4~5 steps are not precisely 1.5 dB each; however, as a practical matter attenuation of audio signals does not require high pre-cision. If greater precision is needed, e.g. in other applications, additional resolution can be provided by the use of code signals with a greater range o~- variability, and/ox by using a larger code signal (e.g. 5, 6 or 7 bits) for controlling more stages of the DAC with each set of code signals. An exemplary 5-bit code I arrangement, adapted to be supplied by the ROM 38, is set forth below: ¦
lOStep CodeAttenuatlon (dB) 1. 11011 0 2. lOlll 1.5 3. 10011 3.0 4. 10000 4.5 Further now with respect to the detailed circuit shown in Figures 2A and 2B, it will be seen from the diagram that the preferred embodiment is implemented uslng known CMOS technology.
Thus the digital signal on any of the lines 44a, etc., is con-nected to one each of four pairs of series-connected devices 80a, 20 82a; 80b, 82b; etc., the common terminal between which develops a logic signal (zero or one) for the corresponding bit of the DAC
10. This logic signal is directed by the respective digital line 14a, 14b, etc., to a sequence of buffer/inverters 84a, 84b, etc., which in turn differentially drive the respective ~-channel output switches 70a, 70b, etc. When the code bit on any of the code lines 40 is a "1", the corresponding switch 70 is conditioned to steer the bit current to the output terminal 18.
_g_ , . . .
~14Z445 The line decoder 42 can be entirely of conventional design, utilizing known logic gate arrangements as shown in the circuit diagram. The disclosed apparatus further includes ancil-lary control devices in th~ form of circuitry generally indicated at 90 serving as loudness control switching ~or an audio appli-cation as described above, but sueh eircuitry forms no part of the present invention.
Still other eatures can of course be provided to suit partieular applications. For example, the command signal ean be generated loeally by an up/down eounter deviee operable by eloek pulses controlled from a remote loeation. Thus, the remote signal need provide only for "up" or "down" signals. The state of the eommand signal at any time can if desired be read out, for display or otherwise.
Aecordingly, although a speciflc preferred em~odiment of the invention has ~een set forth in detail, it is to be under-stood that this is for the purpose of illustrating the prineiples of the invention, and is not to be taken as necessarily limiting of the invention which is set forth in the accompanying elaims.
:
-10- .
. . :
For illustrative purposes, Table I sets forth the cur-rents and output levels in detail for the first eight attenuation - steps. It will be evi~lent from these data that the attenuation ~z~s e ~o ~t ~1 _ ~`~D~) ~U~ d' N ~1 Id ~ `Ul OU:)~1~CO ~ ~
h S:: ~ ~t~)o o ~ ~ o o O ~ O ~ .
~I E3 O
,l t-- ~ ~~D00 ~D ~u~
~ ~ m ~ o ~ o o ~I N ~~D1` ~ O N
.
~rl ~9~ ~t~ O O
O ~D~) O ~~D O ~' O CO1`~D U~
~ O
O > ~1 0 0 0 0 0 0 0 0 .
u~
O O I` t~l [' N ~ ~D ~ ~ d' h h ~ D ~ N N
~ ~ . . . . . .. . n~
~ C~ : ' ~
I~
~
~1 O ~ : ', ~ O ~ ,~
O O
u~ m l l O I . ,~ N
~ d' m~ ~ o ~ o ~ o ~ O
I O ~ ~ O O ~ ~1 0 0 ~
. - o . ~ .,, m ", O m o u o n o e ~ O ~ ~, o a) -- ~ D 1` ~ O N ' ~ IJ
~¢
- . --8--1~4Z4~5 steps are not precisely 1.5 dB each; however, as a practical matter attenuation of audio signals does not require high pre-cision. If greater precision is needed, e.g. in other applications, additional resolution can be provided by the use of code signals with a greater range o~- variability, and/ox by using a larger code signal (e.g. 5, 6 or 7 bits) for controlling more stages of the DAC with each set of code signals. An exemplary 5-bit code I arrangement, adapted to be supplied by the ROM 38, is set forth below: ¦
lOStep CodeAttenuatlon (dB) 1. 11011 0 2. lOlll 1.5 3. 10011 3.0 4. 10000 4.5 Further now with respect to the detailed circuit shown in Figures 2A and 2B, it will be seen from the diagram that the preferred embodiment is implemented uslng known CMOS technology.
Thus the digital signal on any of the lines 44a, etc., is con-nected to one each of four pairs of series-connected devices 80a, 20 82a; 80b, 82b; etc., the common terminal between which develops a logic signal (zero or one) for the corresponding bit of the DAC
10. This logic signal is directed by the respective digital line 14a, 14b, etc., to a sequence of buffer/inverters 84a, 84b, etc., which in turn differentially drive the respective ~-channel output switches 70a, 70b, etc. When the code bit on any of the code lines 40 is a "1", the corresponding switch 70 is conditioned to steer the bit current to the output terminal 18.
_g_ , . . .
~14Z445 The line decoder 42 can be entirely of conventional design, utilizing known logic gate arrangements as shown in the circuit diagram. The disclosed apparatus further includes ancil-lary control devices in th~ form of circuitry generally indicated at 90 serving as loudness control switching ~or an audio appli-cation as described above, but sueh eircuitry forms no part of the present invention.
Still other eatures can of course be provided to suit partieular applications. For example, the command signal ean be generated loeally by an up/down eounter deviee operable by eloek pulses controlled from a remote loeation. Thus, the remote signal need provide only for "up" or "down" signals. The state of the eommand signal at any time can if desired be read out, for display or otherwise.
Aecordingly, although a speciflc preferred em~odiment of the invention has ~een set forth in detail, it is to be under-stood that this is for the purpose of illustrating the prineiples of the invention, and is not to be taken as necessarily limiting of the invention which is set forth in the accompanying elaims.
:
-10- .
Claims (8)
1. A digital-to-analog converter providing an attenuation factor varying in accordance with a non-linear function, compris-ing:
a resistor network circuit having input and output terminals;
said resistor network circuit comprising a number N of successive stages of progressively differing attenuation values and each arranged to be connected into or out of the circuit to control the total attenuation between said input and output terminals;
switch means for each of said network stages, respec-tively, to provide for connecting the corresponding stage into or out of said resistor network circuit;
an array of N successive switch control terminals for said switch means respectively with each terminal arranged to receive a corresponding switch-control logic signal for operating the corresponding switch means;
means to receive a digital attenuation-controlling input signal comprising first and second groups of digital signals;
control-signal-generating means responsive to said first group of digital signals and operable to develop a corresponding set of logic signals for defining an n-bit code where n is smaller than N; and shift-position-controlling means responsive to said second group of digital signals for directing to an n-numbered sequential set of said switch-control terminals the respective
1. cont.:
individual binary signals of an n-bit code signal as defined by said set of logic signals, said n-numbered sequential set of switch-control terminals being selected from the total array of N successive switch-control terminals in accordance with said second group of digital numbers, said n-bit code signal being applied to said n-numbered set of switch-control terminals and controlling the on/off status of the corresponding n-numbered set of successive switch means to produce the level of attenua-tion commanded by said digital input signal.
individual binary signals of an n-bit code signal as defined by said set of logic signals, said n-numbered sequential set of switch-control terminals being selected from the total array of N successive switch-control terminals in accordance with said second group of digital numbers, said n-bit code signal being applied to said n-numbered set of switch-control terminals and controlling the on/off status of the corresponding n-numbered set of successive switch means to produce the level of attenua-tion commanded by said digital input signal.
2. Apparatus as claimed in Claim 1, wherein said resistor network comprises an R/2R ladder network with series and shunt elements providing a logarithmic variation of attenuation factor.
3. Apparatus as claimed in Claim 2, wherein said switch means are arranged in series with shunt elements of said ladder network, to divert the shunt current either to the ladder output terminal or to a ground terminal.
4. Apparatus as claimed in Claim 3, wherein all of the switch means are held open except for said n-numbered set of successive switch means being controlled by said n-bit code signal.
5. Apparatus as claimed in Claim 4, including an opera-tional amplifier having its input connected to said network out-put terminal;
a feedback resistor for said amplifier and having a resistance value producing an output corresponding to zero attentuation when the n-bit code closes all n switch means of the set beginning with the highest order stage.
a feedback resistor for said amplifier and having a resistance value producing an output corresponding to zero attentuation when the n-bit code closes all n switch means of the set beginning with the highest order stage.
6. The method of attenuating an electrical signal com-prising the steps of:
applying said electric signal to the analog input of a multiplying-digital-to-analog converter having a bit-weighting resistor network with N separate stages which are switch-control-lable to be inserted into or out of the circuit between said input and the output thereof;
controlling the switching of n successive stages of said resistor network in accordance with a first control signal; and selecting said n successive stages from the total number N stages in accordance with a second control signal.
applying said electric signal to the analog input of a multiplying-digital-to-analog converter having a bit-weighting resistor network with N separate stages which are switch-control-lable to be inserted into or out of the circuit between said input and the output thereof;
controlling the switching of n successive stages of said resistor network in accordance with a first control signal; and selecting said n successive stages from the total number N stages in accordance with a second control signal.
7. The method of Claim 6, wherein said first and second control signals form parts of a digital command signal.
8. The method of Claim 7, wherein said first and second control signals are used to jointly control a shifting matrix to shift an n-bit code signal along the array of converter digital input terminals to a shift position determined by said second control signal.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US4317479A | 1979-05-29 | 1979-05-29 | |
US043,174 | 1979-05-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA1142445A true CA1142445A (en) | 1983-03-08 |
Family
ID=21925869
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA000352995A Expired CA1142445A (en) | 1979-05-29 | 1980-05-29 | Signal-controllable attenuator employing a digital-to-analog converter |
Country Status (6)
Country | Link |
---|---|
JP (1) | JPS55162615A (en) |
CA (1) | CA1142445A (en) |
DE (1) | DE3019964A1 (en) |
FR (1) | FR2458178B1 (en) |
GB (1) | GB2054992B (en) |
NL (1) | NL8003027A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114035469A (en) * | 2021-11-08 | 2022-02-11 | 中电科思仪科技股份有限公司 | General control system and method for program-controlled attenuator |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS589426A (en) * | 1981-07-10 | 1983-01-19 | Sony Corp | Analog-to-digital converter |
AU557017B2 (en) * | 1981-07-21 | 1986-12-04 | Sony Corporation | Analog-to-digital converter |
JPS6094513A (en) * | 1983-10-28 | 1985-05-27 | Victor Co Of Japan Ltd | Sound volume adjusting device |
IT1215237B (en) * | 1985-02-20 | 1990-01-31 | Ates Componenti Elettron | LOW NOISE ATTENUATOR AND HIGH THERMAL STABILITY, OF AN INTEGRABLE TYPE |
JPS61240716A (en) * | 1985-04-17 | 1986-10-27 | Mitsubishi Electric Corp | Digital-analog converter |
GB9004148D0 (en) * | 1990-02-23 | 1990-04-18 | Questech Ltd | Signal processing apparatus |
JP6753665B2 (en) * | 2015-12-03 | 2020-09-09 | ラピスセミコンダクタ株式会社 | Gain control circuit and gain control method |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AT251319B (en) * | 1965-01-20 | 1966-12-27 | Ibm Oesterreich Internationale | Analog-digital or digital-analog converter |
GB1158453A (en) * | 1967-03-01 | 1969-07-16 | Marconi Co Ltd | Improvements in or relating to Pulse Code Modulation Encoders and Decoders |
FR2155877B1 (en) * | 1971-10-13 | 1974-05-31 | Anvar |
-
1980
- 1980-05-23 NL NL8003027A patent/NL8003027A/en not_active Application Discontinuation
- 1980-05-24 DE DE19803019964 patent/DE3019964A1/en not_active Withdrawn
- 1980-05-29 FR FR8011916A patent/FR2458178B1/en not_active Expired
- 1980-05-29 JP JP7215280A patent/JPS55162615A/en active Pending
- 1980-05-29 GB GB8017569A patent/GB2054992B/en not_active Expired
- 1980-05-29 CA CA000352995A patent/CA1142445A/en not_active Expired
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114035469A (en) * | 2021-11-08 | 2022-02-11 | 中电科思仪科技股份有限公司 | General control system and method for program-controlled attenuator |
CN114035469B (en) * | 2021-11-08 | 2024-04-12 | 中电科思仪科技股份有限公司 | General control system and method for program-controlled attenuator |
Also Published As
Publication number | Publication date |
---|---|
FR2458178A1 (en) | 1980-12-26 |
NL8003027A (en) | 1980-12-02 |
DE3019964A1 (en) | 1980-12-11 |
GB2054992A (en) | 1981-02-18 |
FR2458178B1 (en) | 1988-01-29 |
GB2054992B (en) | 1983-06-22 |
JPS55162615A (en) | 1980-12-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4521764A (en) | Signal-controllable attenuator employing a digital-to-analog converter | |
US5243347A (en) | Monotonic current/resistor digital-to-analog converter and method of operation | |
US6307490B1 (en) | Digital to analog converter trim apparatus and method | |
US4468607A (en) | Ladder-type signal attenuator | |
US7468686B2 (en) | Systems and methods for providing compact digitally controlled trim of multi-segment circuits | |
US8599057B2 (en) | Digital-to-analog converter | |
US5283580A (en) | Current/resistor digital-to-analog converter having enhanced integral linearity and method of operation | |
US4430642A (en) | Digital-to-analog converter | |
CA1089102A (en) | High speed monolithic a/d converter utilizing strobe comparator | |
US4868571A (en) | Digital to analog converter | |
US5619203A (en) | Current source driven converter | |
US4338592A (en) | High accuracy digital-to-analog converter and transient elimination system thereof | |
JPH05327376A (en) | Digital control variable gain circuit | |
CA1142445A (en) | Signal-controllable attenuator employing a digital-to-analog converter | |
WO2002082658A2 (en) | Digital to analogue converter | |
US6181263B1 (en) | Signal processor | |
US5257027A (en) | Modified sign-magnitude DAC and method | |
US3789389A (en) | Method and circuit for combining digital and analog signals | |
US5748128A (en) | Reduced current quadratic digital/analog converter with improved settling-time | |
US4118699A (en) | Digital to analog converter with binary and binary coded decimal modes | |
US4591826A (en) | Gray code DAC ladder | |
US5212484A (en) | Digital to analog converter system employing plural digital to analog converters which is insensitive to resistance variations | |
US4542368A (en) | Trimmable resistive scaling network suitable for digital to analog converters | |
US4727355A (en) | Digital-to-analog converter | |
JPS6161577B2 (en) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MKEX | Expiry |