CA1142269A - Multidrain metal-oxide-semiconductor field-effects devices - Google Patents
Multidrain metal-oxide-semiconductor field-effects devicesInfo
- Publication number
- CA1142269A CA1142269A CA000352289A CA352289A CA1142269A CA 1142269 A CA1142269 A CA 1142269A CA 000352289 A CA000352289 A CA 000352289A CA 352289 A CA352289 A CA 352289A CA 1142269 A CA1142269 A CA 1142269A
- Authority
- CA
- Canada
- Prior art keywords
- region
- transistor
- multidrain
- inverter
- drain regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000002513 implantation Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 230000000873 masking effect Effects 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 235000012239 silicon dioxide Nutrition 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000875 corresponding effect Effects 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 102100022749 Aminopeptidase N Human genes 0.000 description 1
- 102100022005 B-lymphocyte antigen CD20 Human genes 0.000 description 1
- 101000757160 Homo sapiens Aminopeptidase N Proteins 0.000 description 1
- 101000897405 Homo sapiens B-lymphocyte antigen CD20 Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 229940090044 injection Drugs 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09403—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors
- H03K19/09414—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using junction field-effect transistors with gate injection or static induction [STIL]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
- H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE:
A metal-oxide-semiconductor field-effect device for constituting a single logic inverter stage. It includes a multidrain transistor of mono-channel metal-oxide-semi-conductor structure and a load element connected to the gate of the inverter transistor. The inverter transistor comprises a single gate region and several drain regions.
The single gate region and the single channel region of the inverter multidrain transistor are superimposed on both implantation planes separated by a thin insulating layer, surround drain regions of the inverter transistor and are entirely surrounded by the single source region of the inverter transistor. For reducing the implantation surface of the device, at least an insulating region lies between two neighbouring drain regions and/or the load element is a resistive region having a high ohmic value.
A metal-oxide-semiconductor field-effect device for constituting a single logic inverter stage. It includes a multidrain transistor of mono-channel metal-oxide-semi-conductor structure and a load element connected to the gate of the inverter transistor. The inverter transistor comprises a single gate region and several drain regions.
The single gate region and the single channel region of the inverter multidrain transistor are superimposed on both implantation planes separated by a thin insulating layer, surround drain regions of the inverter transistor and are entirely surrounded by the single source region of the inverter transistor. For reducing the implantation surface of the device, at least an insulating region lies between two neighbouring drain regions and/or the load element is a resistive region having a high ohmic value.
Description
The present invention relates to improvements of metal-oxide-semiconductor field-effect devices with integrated monochannel structure which are logic gates such as a single inverter stage. The inverter stage includes an inverter multidrain transistor as driver element and a load element.
More particularly, the invention pertains to an inverter multidrain transistor for MOS field-effect devices which comprises a source region, a plurality of separated drain regions and a single gate region. The source region and the drain regions are included in a first implantation plane defined by a major face of a semiconductor substrate of a determined conductivity type. The source region and the drain regions are of the opposite conductivity type to the semiconductor substrate. A single channel region is included in the substrate. The channel region surrounds the drain regions and is surrounded by the source region.
A gecond implantation defines the single gate region which is composed of polycrystalline silicon. The gate region is~above the channel source through a thin insulating layer.
The gate region surrounds over the drain regions and is surrounded over the source region.
Such an inverter multidrain device for MOS field-effect device is disclosed in French Patent Application No. 2,411,512 published on July 6, 1979. The MOS field-effect device comprises an integrated monochannel MOS field-effect transistor as load element. The load transistor may operate in the enhancement or depletion mode. At least the source region of the inverter transistor is connected to the gate region of the inverter transistor. Further-more, in such a gate device, the gate region entirely surrounds over each of the drain regions of the inverter transistor and portions of the channel region of the inverter transistor lay between the neighbouring drain regions.
.
q~
, ,; .
.
1~2269 For such a structure, a relatively large implanta-tion surface is required, especially when using a low current-consuming logic gate. Indeed, since this consumption is proportional to the ratio of W/L where W and L are the width and length respectively of a MOS transistor channel, it turns out that for a low supply current the length L must be long and, consequently, the implantation surface particu-larly of the load transistor is increased.
The principal object of the present invention is to provide multidrain MOS field-effect devices having an integration degree greater than that of the above-mentioned known devices of this type.
Accordingly, the invention provides MOS field-effect devices in which at least one drain region of the inverter transistor is separated from a neighbouring drain region by an insulating region stretching from the first implantation plane to at least beyond the second implantation plàne and/or in which the load element is a resistive region stretching above the first implantation plane through a second insulating layer.
The insertion of insulating regions between neighbouring drain regions of the inverter transistor makes it possible to do away with the intermediate channel portions between the drain regions and to reduce the distance between the drain regions. Preferably, the distance between the contact region of a drain region and a neighbouring insulation region is less than the distance between this contact region and the gate region.
The replacement of a MOS load transistor by a load resistive region having a high ohmic value makes it possible to reduce the implantation surface of the load element.
Preferably, the resistive region is composed of - - polycrystaline silicon. According to an aspect of the ~3 . ~.
.
More particularly, the invention pertains to an inverter multidrain transistor for MOS field-effect devices which comprises a source region, a plurality of separated drain regions and a single gate region. The source region and the drain regions are included in a first implantation plane defined by a major face of a semiconductor substrate of a determined conductivity type. The source region and the drain regions are of the opposite conductivity type to the semiconductor substrate. A single channel region is included in the substrate. The channel region surrounds the drain regions and is surrounded by the source region.
A gecond implantation defines the single gate region which is composed of polycrystalline silicon. The gate region is~above the channel source through a thin insulating layer.
The gate region surrounds over the drain regions and is surrounded over the source region.
Such an inverter multidrain device for MOS field-effect device is disclosed in French Patent Application No. 2,411,512 published on July 6, 1979. The MOS field-effect device comprises an integrated monochannel MOS field-effect transistor as load element. The load transistor may operate in the enhancement or depletion mode. At least the source region of the inverter transistor is connected to the gate region of the inverter transistor. Further-more, in such a gate device, the gate region entirely surrounds over each of the drain regions of the inverter transistor and portions of the channel region of the inverter transistor lay between the neighbouring drain regions.
.
q~
, ,; .
.
1~2269 For such a structure, a relatively large implanta-tion surface is required, especially when using a low current-consuming logic gate. Indeed, since this consumption is proportional to the ratio of W/L where W and L are the width and length respectively of a MOS transistor channel, it turns out that for a low supply current the length L must be long and, consequently, the implantation surface particu-larly of the load transistor is increased.
The principal object of the present invention is to provide multidrain MOS field-effect devices having an integration degree greater than that of the above-mentioned known devices of this type.
Accordingly, the invention provides MOS field-effect devices in which at least one drain region of the inverter transistor is separated from a neighbouring drain region by an insulating region stretching from the first implantation plane to at least beyond the second implantation plàne and/or in which the load element is a resistive region stretching above the first implantation plane through a second insulating layer.
The insertion of insulating regions between neighbouring drain regions of the inverter transistor makes it possible to do away with the intermediate channel portions between the drain regions and to reduce the distance between the drain regions. Preferably, the distance between the contact region of a drain region and a neighbouring insulation region is less than the distance between this contact region and the gate region.
The replacement of a MOS load transistor by a load resistive region having a high ohmic value makes it possible to reduce the implantation surface of the load element.
Preferably, the resistive region is composed of - - polycrystaline silicon. According to an aspect of the ~3 . ~.
.
2;~69 invention, a portion of the gate region of the inverter transistor forms the resistive region which is obtained from masking simultaneously with the gate region of the inverter transistor. According to another aspect of the invention, at least a portion of polycrystalline silicon constituting the resistive region is doped more lightly than the gate region and is obtained from masking the resistive region during the implantation of the source region and the drain regions of the inverter transistor, then from diffusion of impurities of the opposite conductivity type to the semi-conductor substrate only into said resistive region.
MOS field-effect devices comprising an inverter multidrain transistor having at least an insulating region between neighbo~ring drain regions and a load resistive region, or comprising an inverter multidrain transistor having its~gate region entirely surrounding over all the drain regions and a load resistive region, or comprising an inverter multidrain transistor having at least an insula-ting region between neighbouring drain regions and a load MOS transistor afford logic gates having a relatively size-able integration degree.
More particularly, the present invention proposes a multidrain MOS field-effect device comprising an inverter multidrain transistor and a load element wherein a contact region of the load element is connected to the gate region of the inverter multidrain transistor. The inverter multidrain transistor comprises:
a source region and a combination of separated - drain regions included in a first implantation plane defined by a major face of a semiconductor substrate of a determined conductivity type, the sour¢e region and the drain regions both being of the opposite conductivity type to the semi-conductor substrate;
a single channel region included in the semi-.... .
;: ~
.
j :. .
-`` 11~2269 conductor substrate of the determined conductivity type, surrounding the combination of the drain regions and being surrounded by the source region;
a thin insulating layer above at least of the channel region; and a second implantation plane composed of poly-crystalline silicon and defining a single gate region which surrounds the combination of the drain regions and is surrounded by the source region.
The improvement in the multidrain MOS field-effect device includes a relatively thick insulating region extending between two neighboring drain regions of the inverter multidrain transistor and stretching at least from the first inplantation plane to at least beyond the second implantation plane and wherein the gate region entirely surrounds the combination formed by the drain regions of the inverter multidrain transistor and the thick -insulating region.
The foregoing and other objects and advantages of the present invention will be apparent from the following more particular description of preferred embodiments of the invention as illustrated in the corresponding accompanying drawings, in which:
Fig. 1 illustrates the schematic circuit of a single device or a single inverter stage according to prior art and an embodiment of the invention;
Fig. 2 is a sectional view, taken along the broken line II - II
in Fig. 3, showing the structure of the prior art device which comprises an inverter MOS transistor having three drains and a load MOS transistor;
Fig. 3 is a detailed sectional plan view of the device lllustrated in Fig 2;
Fig. 4 is a simplified sectional plan view similar .
.
. ' . . . ..
' .
~1~2Z~9 to Fig. 3, showing the principal implantation regions o~ a prior art inverter transistor hauing three drains;
Fig. 5 is a simplified sectional plan view showing, in comparison with Fig. 4, the insulating regions of an inverter transistor having three drains according to the invention;
Fig. 6 is a sectional view, taken along the line VI - VI in Fig. 7, showing the structure of a device according to the invention which comprises an inverter MOS transistor having three drains;
Fig. 7 is a detailed sectional plan view of the device illustrated in Fig. 6;
Fig. 8 illustrates the schematic circuit of a single device or a single inverter stage havinga resistive load element, according to the invention;
Fig. 9 is a sectional view, taken along the line IX - IX in Fig. 10, showing the structure of a device according to the invention, comprising a resistive load region; and Fig. 10 is a detailed sectional plan view of the device illustrated in Fig. 9.
Before describing the improvements introduced ~y the present invention, the structure of a logic gate device having a multidrain MOS field-effect transistor in accordance with French Patent Application No. 2,411,512 will be recalled with reference being made to Figs. l to 4.
Such a logic gate device having three drains for the inverter transistor is illustrated schematically in Fig. 1.
The logic gate device comprises a transistor 101, hereinafter called an inverter transistor, which controls output levels of the device, and a load element such as a load transistor 20. The inverter transistor has three output draln terminal Dll, D12 and D13, a single gate t~rminal Glo .
.
- .
.
..
11422~9 and a source terminal S10 which is applied to the ground referenced voltage Vss. The load transistor 20 acts as current in~ector (in accordance with the integrated injec-tion logic I2L) for the drain ter~inals of the other multi-drain transistors (not shown) which have their drain terminalsconnected to the gate terminal G1o, due to the fact that it feeds the gate terminal Glo of the inverter transistor lol ~
The inverter transistor 101 has an enhancement mode operation MOS structure with n-type conductivity channel. The load transistor 20 has a depletion mode operation MOS structure with n-type conductivity, for example.
Load transistor 20 has its drain terminal D20 which is connected to the positive terminal VDD of the voltage supply, and has its source terminal S20 which is connected to the input terminal E which receives digital control signals applied to the gate terminal G1o of inverter transistor 101.
When the load transistor is of the depletion mode operation type -to which references will be made hereinafter- source terminal S20 is connected to its gate terminal G20, as shown by the broken-line connection in Fig. 1. In other embodiments, the load transistor may be of the enhancement mode operation type and/or may operate in an unsatured mode for which ïts gate is biased to an appropriate voltage VGG
The structure of the known logic gate device with inverter transistor having three drains will appear more clearly from a description of a production example given with reference to figs. 2 and 3 (or with reference to Figs.
2a to 2g of the previously mentioned French Patent Application).
This production is carried out by planar technique, the various operations of which, namely masking, photoetching, oxidizing, deoxidizing and diffusion are known. It comprises the ollowing steps for obtaining a logic gate device with ..
n-channel MOS transistor and polycrystalline silicon gate region such as shown in sectional plan view in Fig. 3:
a) On the ma]or face of a p-type semiconductor substrate wafer 1 which defines a first implantation plane, an insulating layer such as a thich layer of silicon dioxide 2 is grown;
b) Windows Flo and F20 corresponding to the implantation locations of inverter transistor 101 and load transistor 20 respectively are produced by means of a first masking in the course of which thick silicon dioxide layer 2 is completely deoxidized and substituted by oxidation with thin insulating layers 3 of silicon dioxide of approxi-mately 1000 A in the windows Flo and F20;
c) Second and third maskings for adjusting the threshold voltage of load transistor 20 by ion implantation technique of n-type impurities through thin insulating layer 3 into the channel region C20 of depletion mode load transistor 20, and for defining a first interconnecting plane in the window F20 corresponding to the region of oh~mic precontact 4 which connects the gate and source regions of load transistor 20 and which is achieved by deoxidation of the thin silicon dioxide layer 3, as shown in Fig. 2 and also by the shaded area of thin silicon dioxide layer in the load transistor of Fig. 3;
d) Fourth mas~ing for depositing a layer of polycrystalline silicon 5 of approximately 5000 A defining a second implantation plane mak.ing up the gate regions . ZGlo and ZG20 of inverter transistor 101 and load transistor 20 respectively.; it will be noted that at the neighbourhood of load transistor 20, polycrystalline silicon 5 is also deposited in the ohmic precontact region 4 in proximity of source region ZS20 in order to form the precontact between the gate and source regions of load transistor 20;
e) Diffusion of n-type impurities into the substrate , . . . - ~
wafer 1 through the thin silicon dioxide layers 3 by means of the polycrystalline silicon 5 and the thick layer 2 acting as mask, so as to define on the first implantation plane 1 the source region ZS10 and the square drain region ZDll, ZD12 and ZD13 of inverter transistor 101 and the source region ZS20 as well as the drain region ZD20 of load transistor 20; this diffusion heavily dopes polycrystalline silicon 5 making up gate region ZGlo, which gives it a low resistivity; simultaneously in the precontact region 4, a small quantity of the doping element is diffused through the polycrystalline silicon 5 in order to lower its resistivity and, in consequence, to realize the ohmic precontact 4;
f) Deposition by a second oxidation of a thick silicon dioxide layer 2' protecting all regions of the logic gate device;
g) Fifth masking and second deoxidation of thick silicon dioxide layer 2' as far as the source region ZS10, drain regions ZDll, ZDl2~ ZDl3 and ZD20 implantation plane 1 and as far as the gate region ZGlo on a second implantation plane separated by the thin insulating layers 3 helow the first implantation plane, i.e. as far as the polycrystalline silicon 5, for defining the sinks into which metal layers, usually made of aluminium, are deposited to form the electrode contacts CS10, CDll, CD12, CD13, CD20 and CGlo of the aforementioned regions where contact CGlo is the input terminal of the logic gate device and is also that of the source and gate regions of load transistor 20;
simultaneously with the deposition of the metal layer, the electrodes of the drains and gates of the transistors are formed, shown in thin lines in Fig. 3 or, more generally, when the logic gate device is included in a complex integrated circuit, the metallic interconnections between the different logic gate devices are formed.
According to the embodiment shown in Figs. 2 and 3, . . .
~ i, .
.
,........................ .. . .
. .
:
~l~ZZ69 -to which reference is made hereinafter as a comparison with - the gate device structures according to the invention- it is assumed that a passage for an interconnecting link, which is illustrated by a constriction 6, is superimposed on the gate region ZGlo of inverter transistor 101 between the drain regions ZD12 and ZD13, and also that the drain region ZD20 of load transistor 20 illustrated below the channel C20 in Fig. 3 was not aligned with the other drain regions in order to reduce the implantation surface of the logic gate device. Moreover, with reference to Fig. 3, il will be noted that source region ZS20 of load transistor 20 is ~ngled, so as to achieve, on one side, its ohmic contact with gate regions ZG20 and ZGlo in region 4 and, on the other side, its junction with channel C20 having a width W20 and a length Ll.
Generally speaking, inverter transistor 101 with three drains Dll, D12 and D13 has the structure schematically illustrated in plan view in Fig. 4. It can be seen that the channel C10 of inverter transistor 101 on the first implantation plane may be horizontally superimposed on gate region ZGlo on the second implantation plane and entirely surrounds the three drain regions ZDl1, ZD12 and ZD13. In this way, gate ZGlo presents square section holes~> of c x c atthe bottoms of which drain regions ZDll, ZD12, ZD13 ~25 are implanted on the first implantation plane. These implantations make it possible to define three basic drain-souxce inverter MOS transistor 11, 12 and 13 which are each constituted of a drain region ZDll, ZD12, ZD13 and the source region ZSln defining between them a basic channel Cll, C12, C13 and also to define two drain-drain interconnecting transistor 11-12 and 12-13 which each comprises a drain region ZDll, ZD12 and a source region ZD12 ZD13 defining between them an interconnecting channel respectively Cll_l2, C12 13. ~11 the basic and interconnecting channels have the same length Ll which is equal to the minimum set by the adopted .
g _ ' ~ ' ' :
.
,, , ~ .
manufacturing technology. Their widths are different and depend on their location within the structure. Thus, the width of channel Cll, C13 of extreme basic transistors 11, 13 is approximately equal to 3c,that of the channel of a central basic transistor, such as C12, to 2c and those of the channels of the interconnecting transistor, such as 11-12 and 12-13, to c.
With reference now to Fig. 5, an inverter MOS
transistor 12 having three drains embodying the invention has been shown in similar way to Fig. 4. It can be seen that the structure of this transistor 12 differs from that of the known transistor 101 in that portions of gate region ZGlo lying between two neighbouring drain regions ZDll and ZD12 or ZD12 and ZD13 are replaced by two insulation g I11_12 and ZII2_13. These insulation regions create absolute electrical insulation between the drain regions and are formed of thick silicon dioxide.
The manufacture of inverter transistor 12 is closely similar to that previously described for known inverter transistor 101, with the following exceptions indicated on Figs. 6 and 7.:
- during the first masking at step b, windows Fll, F12 and F13 corresponding solely to implantation locations in basic MOS transistorsll ,12 and 13 are opened as shown in Fi~g. 6, such that interconnecting channels Cll 12 and C12 13 previously defined remain covered by thick silicon dioxide 2 forming insulating regions ZIll_l2 and ZIl2-13; and - during the fourth masking at step d, the layer of poly-crystalline silicon 5 forming gate region ZGlo may cover over a small portion of an insulation region, such as ZIll 12~ or the major part, even all, of an insulating region such as Z12-13' as shown in Fig. 7.
- Consequently, interconnecting transistors 11-12 and 12-13 of inverter transistor 101 are done away with in inverter transistor 12 according to the invention and, in .
.
11~2269 the proximity of insulating regions ZIll 12 and Z12 13' depending on their height illustrated in Fig. 6, there is an absence at least of the first and second implantation planes. Indeed, as shown in Fig. 6, insulating regions ZI
may stretch beyong the source and drain regions in substrate wafer 1, i.e. below the first implantation plane, and also beyond the effective gate region, which interacts directely with the drain and source regions, i.e. above the second implantation plane.
Insulating regions ZI of transistor 12 have, preferably, a length L2 shorter than that Ll of the inter-connecting channels of inverter transistor 101 so as to reduce horizontal pitch Y of the implantation network cor-responding to the distance between two contact locations of lS neighbouring drains which are implanted at nodes of the network and, as a result, to increase the integration degree. Thus, with reference to Figs 4 and 5, if Ll is the length of the channels of the basic transistors of inverter transistors 101 and 12 together with that of interconnecting transistors 11-12 and 12-13 of known inverter transistors 101, the following inequalities exist:
2 ~ 1 and/or: d2 ~ dl where dl is the distance between the gate region ZG and the contact region ZC having a square section c' x c' in a rectangular drain region ZD of Fig. 5, and d2 is the distance between the contact region ZC of a drain region ZD
and a neighbouring insulating region ZI. Practically, the following relationships given as an example can be chosen:
d = 2d pitch Yl (Fig. 4) - 1.25 x pitch ~2 (Fig. 5) c' + 2dl ~ 1.7 x (c' + 2d2) .. .
. ~ . , - , :
, ~ . . . .
114ZZ~i9 It will be noted that the relative increase in the integration degree of a logic gate device embodying the present invention with respect to a disclosed logic gate device in the previously mentioned French Patent Application, comes about to the detriment of width W of the channels of basic transistors 11, 12 and 13. As a result, the maximum permissible current through the device according to the invention is lower (less than - 120 ~A instead of - 200 ~A~
as its switching speed for high output capacitances. Further note will be taken in this respect that, for low output capacitances, the switching speed is enhanced for a pre-determined current due to the fact that the surface of gate ZGlo of inverter transistor 12 and, as a consequence, the gate capacitance is reduced.
Referring now to Figs. 8 and 10, a multidrain MOS field-effect device which comprises the multidrain inverter transistor 101 or 12 and a solely resistive load element 30 is illustrated in accordance with the invention.
The element 30 is a resistor having a high ohmic value, one terminal of which is connected to gate terminal Glo of inverter transistor 101 or 12 and the other terminal of which is connected to positive biased terminal VDD of the supply source, as shown in Fig. 8.
~ Resistor 30 may be made in polycrystalline silicon, jointly with gate region ZGlo of the inverter transistor.
The production of the logic gate device, in comparison with that according to previously mentioned French Patent Application is simpler, since it no longer includes the various steps pertinent to the implantation of the load transistor 20. In addition, the logic gate device has a reduced implantation surface, as a result of the fact that resistive region 30 is smaller than the entire implantation region of load transistor 20.
As shown in Fig. 9 and 10, resistive region 30 is, ~3 . `- . . . .
., , ~
.
, ~ . ...... .
, , , "
for example, located at the extremity of gate ZGlo, on extreme drain region ZD13 side, and at the same implantation plane as ZGlor i.e. on a second insulating layer made up of a thick layer of silicon dioxide 2. Consequently, for the production of a logic gate device with such a resistive region 30, the window F20 is not open to step b (Fig. 2), step c is deleted and during the fourth masking of step d a layer polycrystalline silicon is also deposited in the proximity of the location of the resistive region 30 in a quantity dependent of the desired ohmic value of resistor 30~ The allow for the adjustment of resistor 30 to a high ohmic value, of the order of 25 k~ for example, the true implantation region of the resistor is defined by masking the latter during the diffusion of n-type semiconductor impurities of following step e, which is relative to the ion implantation into source and drain regions ZSlo, ZDll, ZD12 and ZD13. This masking is indicated by a rectangle 31 in Fig. 10. Since gate region ZGlo or more generally, the remainder of the surface of polycrystalline silicon 5 is not masked during step e, gate region ZGlol not comprising resistive region 30, is heavily doped and, consequenly, ; offers a low resistivity. Between steps e and f, an intermediate phase is envisioned for slightly doping resistive region 30 by diffusion of n-type impurities only in region 30 for appropriately setting the high ohmic value of the load resistor.
Figs. 9 and 10 depict also contact region 32 of resistor 30 which is in heavily doped polycrystalline silicon and which is connected to terminal VDD through an aluminium contact region 33.
Such a logic gate device is advantageously used for low frequency and low consumption operation. Indeed, for such an operation, the use of a load transistor 20 implies a relatively large lmplantation region of the load ., .
.~
-.
114Z2~i9 element, since the load current is proportional to the width-to-length (W/L) ratio, which gives rise to a very long length L of the channel of the load transistor. On the other hand, when the load element is a resistor 30 of high ohmic value the size of the load element is reduced.
It will be noted that the two additional embodiments introduced by the present invention may be combined with the structures disclosed in the French Patent Application No. 2,411,512. These combinations are indicated in Figs.
6 and 7 wherein the right hand block is a load element such as a load transistor 20 (Figs. 2 and 3) or a resistor 30 (Figs. 9 and 10), and in Figs. 9 and 10 wherein the left hand block is a multidrain inverter transistor such as 10 (Figs. 2 and 3) or 12 (Figs. 6 and 7). These various combinations are chosen in terms of the utilization of the logic gate device which depends on the principal features such as switching speed, integration degree and consumption.
~ ' .
- -: -.
MOS field-effect devices comprising an inverter multidrain transistor having at least an insulating region between neighbo~ring drain regions and a load resistive region, or comprising an inverter multidrain transistor having its~gate region entirely surrounding over all the drain regions and a load resistive region, or comprising an inverter multidrain transistor having at least an insula-ting region between neighbouring drain regions and a load MOS transistor afford logic gates having a relatively size-able integration degree.
More particularly, the present invention proposes a multidrain MOS field-effect device comprising an inverter multidrain transistor and a load element wherein a contact region of the load element is connected to the gate region of the inverter multidrain transistor. The inverter multidrain transistor comprises:
a source region and a combination of separated - drain regions included in a first implantation plane defined by a major face of a semiconductor substrate of a determined conductivity type, the sour¢e region and the drain regions both being of the opposite conductivity type to the semi-conductor substrate;
a single channel region included in the semi-.... .
;: ~
.
j :. .
-`` 11~2269 conductor substrate of the determined conductivity type, surrounding the combination of the drain regions and being surrounded by the source region;
a thin insulating layer above at least of the channel region; and a second implantation plane composed of poly-crystalline silicon and defining a single gate region which surrounds the combination of the drain regions and is surrounded by the source region.
The improvement in the multidrain MOS field-effect device includes a relatively thick insulating region extending between two neighboring drain regions of the inverter multidrain transistor and stretching at least from the first inplantation plane to at least beyond the second implantation plane and wherein the gate region entirely surrounds the combination formed by the drain regions of the inverter multidrain transistor and the thick -insulating region.
The foregoing and other objects and advantages of the present invention will be apparent from the following more particular description of preferred embodiments of the invention as illustrated in the corresponding accompanying drawings, in which:
Fig. 1 illustrates the schematic circuit of a single device or a single inverter stage according to prior art and an embodiment of the invention;
Fig. 2 is a sectional view, taken along the broken line II - II
in Fig. 3, showing the structure of the prior art device which comprises an inverter MOS transistor having three drains and a load MOS transistor;
Fig. 3 is a detailed sectional plan view of the device lllustrated in Fig 2;
Fig. 4 is a simplified sectional plan view similar .
.
. ' . . . ..
' .
~1~2Z~9 to Fig. 3, showing the principal implantation regions o~ a prior art inverter transistor hauing three drains;
Fig. 5 is a simplified sectional plan view showing, in comparison with Fig. 4, the insulating regions of an inverter transistor having three drains according to the invention;
Fig. 6 is a sectional view, taken along the line VI - VI in Fig. 7, showing the structure of a device according to the invention which comprises an inverter MOS transistor having three drains;
Fig. 7 is a detailed sectional plan view of the device illustrated in Fig. 6;
Fig. 8 illustrates the schematic circuit of a single device or a single inverter stage havinga resistive load element, according to the invention;
Fig. 9 is a sectional view, taken along the line IX - IX in Fig. 10, showing the structure of a device according to the invention, comprising a resistive load region; and Fig. 10 is a detailed sectional plan view of the device illustrated in Fig. 9.
Before describing the improvements introduced ~y the present invention, the structure of a logic gate device having a multidrain MOS field-effect transistor in accordance with French Patent Application No. 2,411,512 will be recalled with reference being made to Figs. l to 4.
Such a logic gate device having three drains for the inverter transistor is illustrated schematically in Fig. 1.
The logic gate device comprises a transistor 101, hereinafter called an inverter transistor, which controls output levels of the device, and a load element such as a load transistor 20. The inverter transistor has three output draln terminal Dll, D12 and D13, a single gate t~rminal Glo .
.
- .
.
..
11422~9 and a source terminal S10 which is applied to the ground referenced voltage Vss. The load transistor 20 acts as current in~ector (in accordance with the integrated injec-tion logic I2L) for the drain ter~inals of the other multi-drain transistors (not shown) which have their drain terminalsconnected to the gate terminal G1o, due to the fact that it feeds the gate terminal Glo of the inverter transistor lol ~
The inverter transistor 101 has an enhancement mode operation MOS structure with n-type conductivity channel. The load transistor 20 has a depletion mode operation MOS structure with n-type conductivity, for example.
Load transistor 20 has its drain terminal D20 which is connected to the positive terminal VDD of the voltage supply, and has its source terminal S20 which is connected to the input terminal E which receives digital control signals applied to the gate terminal G1o of inverter transistor 101.
When the load transistor is of the depletion mode operation type -to which references will be made hereinafter- source terminal S20 is connected to its gate terminal G20, as shown by the broken-line connection in Fig. 1. In other embodiments, the load transistor may be of the enhancement mode operation type and/or may operate in an unsatured mode for which ïts gate is biased to an appropriate voltage VGG
The structure of the known logic gate device with inverter transistor having three drains will appear more clearly from a description of a production example given with reference to figs. 2 and 3 (or with reference to Figs.
2a to 2g of the previously mentioned French Patent Application).
This production is carried out by planar technique, the various operations of which, namely masking, photoetching, oxidizing, deoxidizing and diffusion are known. It comprises the ollowing steps for obtaining a logic gate device with ..
n-channel MOS transistor and polycrystalline silicon gate region such as shown in sectional plan view in Fig. 3:
a) On the ma]or face of a p-type semiconductor substrate wafer 1 which defines a first implantation plane, an insulating layer such as a thich layer of silicon dioxide 2 is grown;
b) Windows Flo and F20 corresponding to the implantation locations of inverter transistor 101 and load transistor 20 respectively are produced by means of a first masking in the course of which thick silicon dioxide layer 2 is completely deoxidized and substituted by oxidation with thin insulating layers 3 of silicon dioxide of approxi-mately 1000 A in the windows Flo and F20;
c) Second and third maskings for adjusting the threshold voltage of load transistor 20 by ion implantation technique of n-type impurities through thin insulating layer 3 into the channel region C20 of depletion mode load transistor 20, and for defining a first interconnecting plane in the window F20 corresponding to the region of oh~mic precontact 4 which connects the gate and source regions of load transistor 20 and which is achieved by deoxidation of the thin silicon dioxide layer 3, as shown in Fig. 2 and also by the shaded area of thin silicon dioxide layer in the load transistor of Fig. 3;
d) Fourth mas~ing for depositing a layer of polycrystalline silicon 5 of approximately 5000 A defining a second implantation plane mak.ing up the gate regions . ZGlo and ZG20 of inverter transistor 101 and load transistor 20 respectively.; it will be noted that at the neighbourhood of load transistor 20, polycrystalline silicon 5 is also deposited in the ohmic precontact region 4 in proximity of source region ZS20 in order to form the precontact between the gate and source regions of load transistor 20;
e) Diffusion of n-type impurities into the substrate , . . . - ~
wafer 1 through the thin silicon dioxide layers 3 by means of the polycrystalline silicon 5 and the thick layer 2 acting as mask, so as to define on the first implantation plane 1 the source region ZS10 and the square drain region ZDll, ZD12 and ZD13 of inverter transistor 101 and the source region ZS20 as well as the drain region ZD20 of load transistor 20; this diffusion heavily dopes polycrystalline silicon 5 making up gate region ZGlo, which gives it a low resistivity; simultaneously in the precontact region 4, a small quantity of the doping element is diffused through the polycrystalline silicon 5 in order to lower its resistivity and, in consequence, to realize the ohmic precontact 4;
f) Deposition by a second oxidation of a thick silicon dioxide layer 2' protecting all regions of the logic gate device;
g) Fifth masking and second deoxidation of thick silicon dioxide layer 2' as far as the source region ZS10, drain regions ZDll, ZDl2~ ZDl3 and ZD20 implantation plane 1 and as far as the gate region ZGlo on a second implantation plane separated by the thin insulating layers 3 helow the first implantation plane, i.e. as far as the polycrystalline silicon 5, for defining the sinks into which metal layers, usually made of aluminium, are deposited to form the electrode contacts CS10, CDll, CD12, CD13, CD20 and CGlo of the aforementioned regions where contact CGlo is the input terminal of the logic gate device and is also that of the source and gate regions of load transistor 20;
simultaneously with the deposition of the metal layer, the electrodes of the drains and gates of the transistors are formed, shown in thin lines in Fig. 3 or, more generally, when the logic gate device is included in a complex integrated circuit, the metallic interconnections between the different logic gate devices are formed.
According to the embodiment shown in Figs. 2 and 3, . . .
~ i, .
.
,........................ .. . .
. .
:
~l~ZZ69 -to which reference is made hereinafter as a comparison with - the gate device structures according to the invention- it is assumed that a passage for an interconnecting link, which is illustrated by a constriction 6, is superimposed on the gate region ZGlo of inverter transistor 101 between the drain regions ZD12 and ZD13, and also that the drain region ZD20 of load transistor 20 illustrated below the channel C20 in Fig. 3 was not aligned with the other drain regions in order to reduce the implantation surface of the logic gate device. Moreover, with reference to Fig. 3, il will be noted that source region ZS20 of load transistor 20 is ~ngled, so as to achieve, on one side, its ohmic contact with gate regions ZG20 and ZGlo in region 4 and, on the other side, its junction with channel C20 having a width W20 and a length Ll.
Generally speaking, inverter transistor 101 with three drains Dll, D12 and D13 has the structure schematically illustrated in plan view in Fig. 4. It can be seen that the channel C10 of inverter transistor 101 on the first implantation plane may be horizontally superimposed on gate region ZGlo on the second implantation plane and entirely surrounds the three drain regions ZDl1, ZD12 and ZD13. In this way, gate ZGlo presents square section holes~> of c x c atthe bottoms of which drain regions ZDll, ZD12, ZD13 ~25 are implanted on the first implantation plane. These implantations make it possible to define three basic drain-souxce inverter MOS transistor 11, 12 and 13 which are each constituted of a drain region ZDll, ZD12, ZD13 and the source region ZSln defining between them a basic channel Cll, C12, C13 and also to define two drain-drain interconnecting transistor 11-12 and 12-13 which each comprises a drain region ZDll, ZD12 and a source region ZD12 ZD13 defining between them an interconnecting channel respectively Cll_l2, C12 13. ~11 the basic and interconnecting channels have the same length Ll which is equal to the minimum set by the adopted .
g _ ' ~ ' ' :
.
,, , ~ .
manufacturing technology. Their widths are different and depend on their location within the structure. Thus, the width of channel Cll, C13 of extreme basic transistors 11, 13 is approximately equal to 3c,that of the channel of a central basic transistor, such as C12, to 2c and those of the channels of the interconnecting transistor, such as 11-12 and 12-13, to c.
With reference now to Fig. 5, an inverter MOS
transistor 12 having three drains embodying the invention has been shown in similar way to Fig. 4. It can be seen that the structure of this transistor 12 differs from that of the known transistor 101 in that portions of gate region ZGlo lying between two neighbouring drain regions ZDll and ZD12 or ZD12 and ZD13 are replaced by two insulation g I11_12 and ZII2_13. These insulation regions create absolute electrical insulation between the drain regions and are formed of thick silicon dioxide.
The manufacture of inverter transistor 12 is closely similar to that previously described for known inverter transistor 101, with the following exceptions indicated on Figs. 6 and 7.:
- during the first masking at step b, windows Fll, F12 and F13 corresponding solely to implantation locations in basic MOS transistorsll ,12 and 13 are opened as shown in Fi~g. 6, such that interconnecting channels Cll 12 and C12 13 previously defined remain covered by thick silicon dioxide 2 forming insulating regions ZIll_l2 and ZIl2-13; and - during the fourth masking at step d, the layer of poly-crystalline silicon 5 forming gate region ZGlo may cover over a small portion of an insulation region, such as ZIll 12~ or the major part, even all, of an insulating region such as Z12-13' as shown in Fig. 7.
- Consequently, interconnecting transistors 11-12 and 12-13 of inverter transistor 101 are done away with in inverter transistor 12 according to the invention and, in .
.
11~2269 the proximity of insulating regions ZIll 12 and Z12 13' depending on their height illustrated in Fig. 6, there is an absence at least of the first and second implantation planes. Indeed, as shown in Fig. 6, insulating regions ZI
may stretch beyong the source and drain regions in substrate wafer 1, i.e. below the first implantation plane, and also beyond the effective gate region, which interacts directely with the drain and source regions, i.e. above the second implantation plane.
Insulating regions ZI of transistor 12 have, preferably, a length L2 shorter than that Ll of the inter-connecting channels of inverter transistor 101 so as to reduce horizontal pitch Y of the implantation network cor-responding to the distance between two contact locations of lS neighbouring drains which are implanted at nodes of the network and, as a result, to increase the integration degree. Thus, with reference to Figs 4 and 5, if Ll is the length of the channels of the basic transistors of inverter transistors 101 and 12 together with that of interconnecting transistors 11-12 and 12-13 of known inverter transistors 101, the following inequalities exist:
2 ~ 1 and/or: d2 ~ dl where dl is the distance between the gate region ZG and the contact region ZC having a square section c' x c' in a rectangular drain region ZD of Fig. 5, and d2 is the distance between the contact region ZC of a drain region ZD
and a neighbouring insulating region ZI. Practically, the following relationships given as an example can be chosen:
d = 2d pitch Yl (Fig. 4) - 1.25 x pitch ~2 (Fig. 5) c' + 2dl ~ 1.7 x (c' + 2d2) .. .
. ~ . , - , :
, ~ . . . .
114ZZ~i9 It will be noted that the relative increase in the integration degree of a logic gate device embodying the present invention with respect to a disclosed logic gate device in the previously mentioned French Patent Application, comes about to the detriment of width W of the channels of basic transistors 11, 12 and 13. As a result, the maximum permissible current through the device according to the invention is lower (less than - 120 ~A instead of - 200 ~A~
as its switching speed for high output capacitances. Further note will be taken in this respect that, for low output capacitances, the switching speed is enhanced for a pre-determined current due to the fact that the surface of gate ZGlo of inverter transistor 12 and, as a consequence, the gate capacitance is reduced.
Referring now to Figs. 8 and 10, a multidrain MOS field-effect device which comprises the multidrain inverter transistor 101 or 12 and a solely resistive load element 30 is illustrated in accordance with the invention.
The element 30 is a resistor having a high ohmic value, one terminal of which is connected to gate terminal Glo of inverter transistor 101 or 12 and the other terminal of which is connected to positive biased terminal VDD of the supply source, as shown in Fig. 8.
~ Resistor 30 may be made in polycrystalline silicon, jointly with gate region ZGlo of the inverter transistor.
The production of the logic gate device, in comparison with that according to previously mentioned French Patent Application is simpler, since it no longer includes the various steps pertinent to the implantation of the load transistor 20. In addition, the logic gate device has a reduced implantation surface, as a result of the fact that resistive region 30 is smaller than the entire implantation region of load transistor 20.
As shown in Fig. 9 and 10, resistive region 30 is, ~3 . `- . . . .
., , ~
.
, ~ . ...... .
, , , "
for example, located at the extremity of gate ZGlo, on extreme drain region ZD13 side, and at the same implantation plane as ZGlor i.e. on a second insulating layer made up of a thick layer of silicon dioxide 2. Consequently, for the production of a logic gate device with such a resistive region 30, the window F20 is not open to step b (Fig. 2), step c is deleted and during the fourth masking of step d a layer polycrystalline silicon is also deposited in the proximity of the location of the resistive region 30 in a quantity dependent of the desired ohmic value of resistor 30~ The allow for the adjustment of resistor 30 to a high ohmic value, of the order of 25 k~ for example, the true implantation region of the resistor is defined by masking the latter during the diffusion of n-type semiconductor impurities of following step e, which is relative to the ion implantation into source and drain regions ZSlo, ZDll, ZD12 and ZD13. This masking is indicated by a rectangle 31 in Fig. 10. Since gate region ZGlo or more generally, the remainder of the surface of polycrystalline silicon 5 is not masked during step e, gate region ZGlol not comprising resistive region 30, is heavily doped and, consequenly, ; offers a low resistivity. Between steps e and f, an intermediate phase is envisioned for slightly doping resistive region 30 by diffusion of n-type impurities only in region 30 for appropriately setting the high ohmic value of the load resistor.
Figs. 9 and 10 depict also contact region 32 of resistor 30 which is in heavily doped polycrystalline silicon and which is connected to terminal VDD through an aluminium contact region 33.
Such a logic gate device is advantageously used for low frequency and low consumption operation. Indeed, for such an operation, the use of a load transistor 20 implies a relatively large lmplantation region of the load ., .
.~
-.
114Z2~i9 element, since the load current is proportional to the width-to-length (W/L) ratio, which gives rise to a very long length L of the channel of the load transistor. On the other hand, when the load element is a resistor 30 of high ohmic value the size of the load element is reduced.
It will be noted that the two additional embodiments introduced by the present invention may be combined with the structures disclosed in the French Patent Application No. 2,411,512. These combinations are indicated in Figs.
6 and 7 wherein the right hand block is a load element such as a load transistor 20 (Figs. 2 and 3) or a resistor 30 (Figs. 9 and 10), and in Figs. 9 and 10 wherein the left hand block is a multidrain inverter transistor such as 10 (Figs. 2 and 3) or 12 (Figs. 6 and 7). These various combinations are chosen in terms of the utilization of the logic gate device which depends on the principal features such as switching speed, integration degree and consumption.
~ ' .
- -: -.
Claims (8)
1. A multidrain MOS field-effect device comprising an inverter multidrain transistor and a load element, a contact region of said load element being connected to the gate region of said inverter multidrain transistor, said inverter multidrain transistor comprising:
a source region and a combination of separated drain regions included in a first implantation plane defined by a major face of a semiconductor substrate of a determined conductivity type, said source region and said drain regions both being of the opposite conductivity type to said semi-conductor substrate;
a single channel region included in said semi-conductor substrate of said determined conductivity type, surrounding said combination of said drain regions and being surrounded by said source region;
a thin insulatin layer above at least of said channel region; and a second implantation plane composed of poly-crystalline silicon and defining a single gate region which surrounds said combination of said drain regions and is surrounded by said source region;
the improvement in said multidrain MOS field-effect device comprising:
a relatively thick insulating region extending between two neighboring drain regions of said inverter multidrain transistor and stretching at least from said first implantation plane to at least beyond said second implantation plane;
said gate region entirely surrounding the combination formed by said drain regions of said inverter multidrain transistor and said thick insulating region.
a source region and a combination of separated drain regions included in a first implantation plane defined by a major face of a semiconductor substrate of a determined conductivity type, said source region and said drain regions both being of the opposite conductivity type to said semi-conductor substrate;
a single channel region included in said semi-conductor substrate of said determined conductivity type, surrounding said combination of said drain regions and being surrounded by said source region;
a thin insulatin layer above at least of said channel region; and a second implantation plane composed of poly-crystalline silicon and defining a single gate region which surrounds said combination of said drain regions and is surrounded by said source region;
the improvement in said multidrain MOS field-effect device comprising:
a relatively thick insulating region extending between two neighboring drain regions of said inverter multidrain transistor and stretching at least from said first implantation plane to at least beyond said second implantation plane;
said gate region entirely surrounding the combination formed by said drain regions of said inverter multidrain transistor and said thick insulating region.
2. A multidrain MOS field-effect device according to claim 1, in which the distance between the contact region of a drain region and a-neighboring insulating region is less than the distance between said drain contact region and said gate region.
3. A multidrain MOS field-effect device according to claim 1 or 2, in which said load element is a load transistor, the source of said load transistor being consti-tuted by an end portion of said gate region of said inverter multidrain transistor.
4. A multidrain MOS field-effect device according to claim 1, wherein said load element is a resistive region stretching below said first implantation plane through a second insulating layer.
5. A multidrain MOS field-effect device according to claim 4, in which said resistive region is composed of said polycrystalline silicon.
6. A multidrain MOS field-effect device according to claim 4 or 5, in which a portion of said gate region of said inverter transistor forms said resistive region which is obtained from masking simultaneously with said gate region.
7. A multidrain MOS field-effect device according to claim 5, in which at least a portion of polycrystalline silicon constituting said resistive region is doped more slightly than said gate region and is obtained from masking said resistive region during the implantation of said source region and said drain regions of said inverter transistor, then from diffusion of impurities of said opposite conductivity type only into said resistive region.
8. A multidrain MOS field-effect device according to claim 4, in which a portion of said gate region of said inverter multidrain transistor entirely surrounds at least a drain region of said inverter multidrain transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FRPV79-12910 | 1979-05-21 | ||
| FR7912910A FR2457605A2 (en) | 1979-05-21 | 1979-05-21 | IMPROVEMENTS ON LOGIC DOORS WITH MULTIDRAIN MOS TRANSISTORS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1142269A true CA1142269A (en) | 1983-03-01 |
Family
ID=9225698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000352289A Expired CA1142269A (en) | 1979-05-21 | 1980-05-20 | Multidrain metal-oxide-semiconductor field-effects devices |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0019560B1 (en) |
| JP (1) | JPS55156359A (en) |
| CA (1) | CA1142269A (en) |
| DE (1) | DE3060914D1 (en) |
| ES (1) | ES491626A0 (en) |
| FR (1) | FR2457605A2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8401117A (en) * | 1984-04-09 | 1985-11-01 | Philips Nv | SEMICONDUCTOR DEVICE WITH FIELD-EFFECT TRANSISTORS WITH INSULATED GATE ELECTRODES. |
| US4684967A (en) * | 1984-05-04 | 1987-08-04 | Integrated Logic Systems, Inc. | Low capacitance transistor cell element and transistor array |
| US4680484A (en) * | 1984-10-19 | 1987-07-14 | Trw Inc. | Wired-AND FET logic gate |
| EP1191601B1 (en) * | 2000-09-21 | 2007-11-28 | STMicroelectronics S.r.l. | A lateral DMOS transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5268382A (en) * | 1975-12-05 | 1977-06-07 | Hitachi Ltd | Semiconductor circuit unit |
| JPS608628B2 (en) * | 1976-07-05 | 1985-03-04 | ヤマハ株式会社 | Semiconductor integrated circuit device |
-
1979
- 1979-05-21 FR FR7912910A patent/FR2457605A2/en active Granted
-
1980
- 1980-05-20 DE DE8080400702T patent/DE3060914D1/en not_active Expired
- 1980-05-20 EP EP80400702A patent/EP0019560B1/en not_active Expired
- 1980-05-20 ES ES491626A patent/ES491626A0/en active Granted
- 1980-05-20 CA CA000352289A patent/CA1142269A/en not_active Expired
- 1980-05-21 JP JP6658280A patent/JPS55156359A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| FR2457605A2 (en) | 1980-12-19 |
| EP0019560A1 (en) | 1980-11-26 |
| JPS55156359A (en) | 1980-12-05 |
| ES8201768A1 (en) | 1981-11-16 |
| EP0019560B1 (en) | 1982-10-06 |
| DE3060914D1 (en) | 1982-11-11 |
| FR2457605B2 (en) | 1982-11-19 |
| ES491626A0 (en) | 1981-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950000141B1 (en) | Semiconductor device & manufacturing method thereof | |
| US5593909A (en) | Method for fabricating a MOS transistor having an offset resistance | |
| KR930001899B1 (en) | Semiconductor device | |
| JP3364559B2 (en) | Semiconductor device | |
| JP3462301B2 (en) | Semiconductor device and manufacturing method thereof | |
| US4475279A (en) | Method of making a monolithic integrated circuit comprising at least one pair of complementary field-effect transistors and at least one bipolar transistor | |
| US5654561A (en) | Insulated gate bipolar transistor with multiple buffer layers | |
| US7186618B2 (en) | Power transistor arrangement and method for fabricating it | |
| US4178605A (en) | Complementary MOS inverter structure | |
| US5397715A (en) | MOS transistor having increased gate-drain capacitance | |
| KR100204805B1 (en) | Method for fabricating transistor | |
| US5721148A (en) | Method for manufacturing MOS type semiconductor device | |
| US4070687A (en) | Composite channel field effect transistor and method of fabrication | |
| US4885618A (en) | Insulated gate FET having a buried insulating barrier | |
| US3883372A (en) | Method of making a planar graded channel MOS transistor | |
| US3639813A (en) | Complementary enhancement and depletion mosfets with common gate and channel region, the depletion mosfet also being a jfet | |
| JP3282375B2 (en) | Complementary insulated gate field effect transistor | |
| KR100231717B1 (en) | Semiconductor device and method of fabricating the same | |
| DE4139039A1 (en) | SEMICONDUCTOR DEVICE | |
| CA1111514A (en) | Multidrain metal-oxide-semiconductor field-effect device | |
| US4816880A (en) | Junction field effect transistor | |
| KR100211635B1 (en) | Semiconductor device and fabrication thereof | |
| KR890004797B1 (en) | Mis type semiconductor device element on a semiconductor substrate having a well region | |
| CA1142269A (en) | Multidrain metal-oxide-semiconductor field-effects devices | |
| US4547959A (en) | Uses for buried contacts in integrated circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |