CA1138118A - Next address generation logic in a data processing system - Google Patents
Next address generation logic in a data processing systemInfo
- Publication number
- CA1138118A CA1138118A CA000342927A CA342927A CA1138118A CA 1138118 A CA1138118 A CA 1138118A CA 000342927 A CA000342927 A CA 000342927A CA 342927 A CA342927 A CA 342927A CA 1138118 A CA1138118 A CA 1138118A
- Authority
- CA
- Canada
- Prior art keywords
- address
- register
- bits
- bit
- routine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
- G06F9/262—Arrangements for next microinstruction selection
- G06F9/264—Microinstruction selection based on results of processing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
- G06F9/4482—Procedural
- G06F9/4484—Executing subprograms
- G06F9/4486—Formation of subprogram jump address
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA000401175A CA1145853A (en) | 1979-01-03 | 1982-04-16 | Next address generation logic in a data processing system |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US000,734 | 1979-01-03 | ||
| US06/000,864 US4224668A (en) | 1979-01-03 | 1979-01-03 | Control store address generation logic for a data processing system |
| US000,864 | 1979-01-03 | ||
| US06/000,734 US4309753A (en) | 1979-01-03 | 1979-01-03 | Apparatus and method for next address generation in a data processing system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1138118A true CA1138118A (en) | 1982-12-21 |
Family
ID=26668073
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000342927A Expired CA1138118A (en) | 1979-01-03 | 1980-01-02 | Next address generation logic in a data processing system |
Country Status (4)
| Country | Link |
|---|---|
| CA (1) | CA1138118A (https=) |
| DE (1) | DE3000107A1 (https=) |
| FR (1) | FR2445987B1 (https=) |
| GB (2) | GB2040519B (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4491908A (en) * | 1981-12-01 | 1985-01-01 | Honeywell Information Systems Inc. | Microprogrammed control of extended integer and commercial instruction processor instructions through use of a data type field in a central processor unit |
| US4450525A (en) * | 1981-12-07 | 1984-05-22 | Ibm Corporation | Control unit for a functional processor |
-
1979
- 1979-12-13 GB GB7942984A patent/GB2040519B/en not_active Expired
-
1980
- 1980-01-02 CA CA000342927A patent/CA1138118A/en not_active Expired
- 1980-01-02 FR FR8000039A patent/FR2445987B1/fr not_active Expired
- 1980-01-03 DE DE19803000107 patent/DE3000107A1/de active Granted
-
1983
- 1983-01-25 GB GB08302033A patent/GB2117943B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB2040519B (en) | 1983-08-17 |
| FR2445987B1 (fr) | 1985-11-22 |
| GB2040519A (en) | 1980-08-28 |
| GB2117943A (en) | 1983-10-19 |
| FR2445987A1 (fr) | 1980-08-01 |
| DE3000107C2 (https=) | 1988-06-01 |
| DE3000107A1 (de) | 1980-07-17 |
| GB8302033D0 (en) | 1983-02-23 |
| GB2117943B (en) | 1984-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4395758A (en) | Accelerator processor for a data processing system | |
| US4272828A (en) | Arithmetic logic apparatus for a data processing system | |
| US3585605A (en) | Associative memory data processor | |
| US4342078A (en) | Instruction register sequence decoder for microprogrammed data processor and method | |
| US4338661A (en) | Conditional branch unit for microprogrammed data processor | |
| US4415969A (en) | Macroinstruction translator unit for use in a microprocessor | |
| US3739352A (en) | Variable word width processor control | |
| US4713750A (en) | Microprocessor with compact mapped programmable logic array | |
| US4312034A (en) | ALU and Condition code control unit for data processor | |
| EP0248436A2 (en) | Method of and apparatus for processing data | |
| EP0011412B1 (en) | Bipartite control store for microprogrammed data processor | |
| CA1181865A (en) | Microprogrammed control of extended integer instructions through use of a data type field in a central processor unit | |
| EP0349124B1 (en) | Operand specifier processing | |
| US3936803A (en) | Data processing system having a common channel unit with circulating fields | |
| US4224668A (en) | Control store address generation logic for a data processing system | |
| US4309753A (en) | Apparatus and method for next address generation in a data processing system | |
| EP0010196B1 (en) | Control circuit and process for digital storage devices | |
| US4320454A (en) | Apparatus and method for operand fetch control | |
| US4373182A (en) | Indirect address computation circuit | |
| US4258420A (en) | Control file apparatus for a data processing system | |
| US4384343A (en) | Firmware controlled search and verify apparatus and method for a data processing system | |
| US4245328A (en) | Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit | |
| CA1138118A (en) | Next address generation logic in a data processing system | |
| CA1145853A (en) | Next address generation logic in a data processing system | |
| EP0066670B1 (en) | Instruction processing in a data processing machine |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |