CA1133148A - Monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits - Google Patents
Monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuitsInfo
- Publication number
- CA1133148A CA1133148A CA336,425A CA336425A CA1133148A CA 1133148 A CA1133148 A CA 1133148A CA 336425 A CA336425 A CA 336425A CA 1133148 A CA1133148 A CA 1133148A
- Authority
- CA
- Canada
- Prior art keywords
- circuit
- signal
- integrated circuit
- monolithically integrated
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000008878 coupling Effects 0.000 title claims abstract description 24
- 238000010168 coupling process Methods 0.000 title claims abstract description 24
- 238000005859 coupling reaction Methods 0.000 title claims abstract description 24
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 239000003990 capacitor Substances 0.000 claims abstract description 20
- 238000002161 passivation Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 3
- 239000010980 sapphire Substances 0.000 claims abstract description 3
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 241000364027 Sinoe Species 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/03—Logic gate active element oscillator
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.
A system is disclosed for coupling electrically isolated circuits in a monolithic integrated circuit. A signal coupler is integrated on a chip together with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor which consists of a coplanar conductor path arrangement embedded into a passivation layer, the passivation layer being applied to an insulating substrate, preferably sapphire.
Description
~3~
BACKGROUND OF THE INVENTION
The invention relates to a monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits.
In most cases circuits operated directly from the mains require electrical decoupling between the input side and the output side with high dielectric strength, e.g. 1.5 kV between the two sides. Previously circuits of this kind have been constructed exclusively from discrete components, such as for exa~ple transformers, capacitors or opto-couplers. Known semiconducto relays are constructed for example with hybrid-integrated components in which case an opto-coupler consists of a photo-diode, a light conducting path, and a photo-transistor. The use of a capacitor for the aforementioned purpose is disclosed for example in the magazine "Elektor", July/August 1976, 7-48/~9 "Kapazitiver TriacKeppler".
One of the disadvantages of the kno-wn circuits is that they are relatively complicated and are also expensive.
SUM~Y OF T~ VENTION
An object of the present invention is to provide a circuit which combines the advantages of high dielectric strength in the path between input side and out~ut side, a smal] space requirement, and low production costs.
The object on which the invention is based is attained by a mono-lithically integrated circuit of high dielectric strength for electrically coupling isolated circuits. A signal coupler is integrated on a chip to-gether with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor -which consists of a coplanar conductor path arrangement which is ~3~
known per se and is embedded into a passivation layer and is applied to an insulating substrate which preferably consists of sapphire.
A coplanar conductor path arrangem~nt of the above m~ntioned type is kncwn from the "Siemens Forschungs- and Entwicklungsberichten", see Vol. 5 (1976) No. 2, page 72-75~ H. Fritzsche; "Capacitances of Coplanar Microstrip Lines in Integrated Circuits".
The invention offers the advantage that a relatively high dielectric strength can be achieved which, when solid silicon techniques are used, can otherwise only be reproduced with extreme difficulty. A further advantage con-sists in that the monolithically integrated circuit corresponding to the inven-tion is small in volume and can be produced with favorable cost.
A further development of the invention is that a plurality of coupling capacitors consisting of ooplanar canductor path arrangements are arranged on the chip. The coupling capacitors are comm~nly interconnected in a series arrangem~nt to form a capacitive voltage divider. me intervals between the con-ductor paths are reduced in comparison to the intervals between the conductor paths in the case of a coupling capacitor consisting of one single coplanar con-ductor path ar~angement.
A further development of the invention offers the advantage that ~he dielectric strength of the path between the input and the output of the overall circuit can be increased.
BKIEF ~ESCRIPTICN OF THE DRAW¢NGS
Figure 1 is the block circuit diagram of an integrated solid body re-lay which is designed in accordance with the invention and the individual cir-cuit zones of which are arranged in integrated fashion on one single chip;
~,~
~33~
Figure 2 is the block circuit diagram of an integrated capacitive coupler for signal transmission which is designed in accordance with the invention;
Figure 3 is a cross-sectional view of a portion of a circuit con-structed in accordance with the invention illustrating the arrangement of coplanar conductor paths 1, 2 in a passivation layer and on a substrate;
Figure 4 is a cross-section through an arrangement corresponding to the invention of a plurality of coplanar conductor paths 1, 2 . . . n;
Figure 5 illustrates the qualitative curve of the break through field strength Ema in dependence upon a spacing d between the conductor paths 1, 2;
Figure 6 is a gate circuit diagram of an integrated capacitive coupler designed in accordance with the invention;
Figure 7 is a detailed circuit diagram forming part of the gate circuit diagram shown in Figure 6 of an integrated capacitive coupler : constructed in accordance with the invention;
Figure 8 is a block circuit diagram of an integrated capaciti~e coupler for power transmission constructed in accordance with the invention;
and Figure 9 is a detailed circuit diagram of the coupler illustrated in Fi.gure 8.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
As already mentioned, Figure 1 is a simplified block circuit diagram of a switch which is monolithically integrated on a chip CH, and which is to switch a load circuit V at the secondary side and contains ~ 33~f~
electrical isolation means GT (solid body rela~). If the primary circuit PS is to be supplied from the secondary side, in addition to a signal coupler SK whichinfluences the secondary circuit SS, an energy transmission circuit, i.e. a p~wer coupler EK, ls also required. The signal path is referenced SW whereas the p~wer supply path is referen oe d EWo As already mentioned, Figure 2 is the block circuit diagram of a cir-cuit for a capacitive signal coupler. At the primary side P a high-frequency signal is produced by an oscillator OSZ which is cantrolled by the signal input E transmitted via the coupling capacitor ~ to the secondary side S, where i-t isamplified and preferably rectified (output signal A) Figure 3 illustrates the arrangement of an integrated coupling capacitor which, embedded into a passivation layer PASS, lies on an insulating substrate SUB (e.g. ESFI-SOS technology). l~e capacitance is produoe d by the coplanar conductor path arrangement l-a-2. An arrangem~nt of this type produces very high dielectric strengths which, using solid silicon technolcgy, can other-wise only be achieved with great difficulty. On passivated surfaces the dielectric strength is in the region of several kV and the capacitance values are in the 100 pF-range.
; ESFI-SOS technology is described in the brochure "Siemens HaIbleiterbauelem~ente fur die Elektronik", order No. B 10/1431, pages 60 and 61.
Sinoe, given small spacings d, the breakthrough field strength EmaX
displays a sharp increase A (see Figure 5) it can be advantageous to connect a plurality of coplanar capacitors (conductor paths) in series while simLltane-ously reducing the spacing thereby achieving high dielectric strengths ~.~.3;3~
and greater coupling capacitances (see Figure ~). In this case the inner conductor paths (2 . . . n-l~ do not carry a fixed potential. An increased dielectric strength of the multi~conductor arrangement is subject to precise symmetrical design of the conductor paths which can be achieved relatively easily with current technology.
In accordance with Figures 3, 4 and 5, the breakthrough voltage (UDB) for two conductors and n conductors is governed by UDB 12 ~ E12 a (1) and UDB ln ~ n E12 a (2) In order to achieve an equal dielectric strength with n conductor paths we must have 12 ~ ~12 _a (3) n a if CKln 7 CK 12 and a~- ~ a A genuine gain can be achieved with respect to the quality (UDB and CK) and area of the coupling capacitor.
In order to further increase the coupling capacitance, the passi-vation layer should possess as high as possible a relative dielectric constant.
Figures 6 and 7 illustrate an example of a capacitive coupling circuit constructed for signal transmission in ESFI-SOS technology. The circuit elements are conventional transistors, diodes, resistors~and capacitors (with the exception of CK), as are used in ESFI technology. As a transmission path of this type displays band-pass characteristics, it is effective to tune 3 ~33~
the oscillator frequency to the middle frequency. This can be achieved by virtue of the selection of the number of stages in the ring oscillator or by modifying the inverter transit time. In this arrangement the input and output stage are referenced STE and STA respectively, the amplifier is referenced VS, and the rectifier is referenced GL.
Figures 8 and 9 illustrate an example of a power supply circuit consisting of a capacitive coupler. The voltage component U+l of an oscilla-tor signal of high frequency (f ) is amplified and the oscillator signal is transmitted via CK to the primary side. Here a current of the value UH -
BACKGROUND OF THE INVENTION
The invention relates to a monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits.
In most cases circuits operated directly from the mains require electrical decoupling between the input side and the output side with high dielectric strength, e.g. 1.5 kV between the two sides. Previously circuits of this kind have been constructed exclusively from discrete components, such as for exa~ple transformers, capacitors or opto-couplers. Known semiconducto relays are constructed for example with hybrid-integrated components in which case an opto-coupler consists of a photo-diode, a light conducting path, and a photo-transistor. The use of a capacitor for the aforementioned purpose is disclosed for example in the magazine "Elektor", July/August 1976, 7-48/~9 "Kapazitiver TriacKeppler".
One of the disadvantages of the kno-wn circuits is that they are relatively complicated and are also expensive.
SUM~Y OF T~ VENTION
An object of the present invention is to provide a circuit which combines the advantages of high dielectric strength in the path between input side and out~ut side, a smal] space requirement, and low production costs.
The object on which the invention is based is attained by a mono-lithically integrated circuit of high dielectric strength for electrically coupling isolated circuits. A signal coupler is integrated on a chip to-gether with a primary circuit and a secondary circuit which is to be coupled to the primary circuit. The signal coupler comprises an integrated coupling capacitor -which consists of a coplanar conductor path arrangement which is ~3~
known per se and is embedded into a passivation layer and is applied to an insulating substrate which preferably consists of sapphire.
A coplanar conductor path arrangem~nt of the above m~ntioned type is kncwn from the "Siemens Forschungs- and Entwicklungsberichten", see Vol. 5 (1976) No. 2, page 72-75~ H. Fritzsche; "Capacitances of Coplanar Microstrip Lines in Integrated Circuits".
The invention offers the advantage that a relatively high dielectric strength can be achieved which, when solid silicon techniques are used, can otherwise only be reproduced with extreme difficulty. A further advantage con-sists in that the monolithically integrated circuit corresponding to the inven-tion is small in volume and can be produced with favorable cost.
A further development of the invention is that a plurality of coupling capacitors consisting of ooplanar canductor path arrangements are arranged on the chip. The coupling capacitors are comm~nly interconnected in a series arrangem~nt to form a capacitive voltage divider. me intervals between the con-ductor paths are reduced in comparison to the intervals between the conductor paths in the case of a coupling capacitor consisting of one single coplanar con-ductor path ar~angement.
A further development of the invention offers the advantage that ~he dielectric strength of the path between the input and the output of the overall circuit can be increased.
BKIEF ~ESCRIPTICN OF THE DRAW¢NGS
Figure 1 is the block circuit diagram of an integrated solid body re-lay which is designed in accordance with the invention and the individual cir-cuit zones of which are arranged in integrated fashion on one single chip;
~,~
~33~
Figure 2 is the block circuit diagram of an integrated capacitive coupler for signal transmission which is designed in accordance with the invention;
Figure 3 is a cross-sectional view of a portion of a circuit con-structed in accordance with the invention illustrating the arrangement of coplanar conductor paths 1, 2 in a passivation layer and on a substrate;
Figure 4 is a cross-section through an arrangement corresponding to the invention of a plurality of coplanar conductor paths 1, 2 . . . n;
Figure 5 illustrates the qualitative curve of the break through field strength Ema in dependence upon a spacing d between the conductor paths 1, 2;
Figure 6 is a gate circuit diagram of an integrated capacitive coupler designed in accordance with the invention;
Figure 7 is a detailed circuit diagram forming part of the gate circuit diagram shown in Figure 6 of an integrated capacitive coupler : constructed in accordance with the invention;
Figure 8 is a block circuit diagram of an integrated capaciti~e coupler for power transmission constructed in accordance with the invention;
and Figure 9 is a detailed circuit diagram of the coupler illustrated in Fi.gure 8.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
As already mentioned, Figure 1 is a simplified block circuit diagram of a switch which is monolithically integrated on a chip CH, and which is to switch a load circuit V at the secondary side and contains ~ 33~f~
electrical isolation means GT (solid body rela~). If the primary circuit PS is to be supplied from the secondary side, in addition to a signal coupler SK whichinfluences the secondary circuit SS, an energy transmission circuit, i.e. a p~wer coupler EK, ls also required. The signal path is referenced SW whereas the p~wer supply path is referen oe d EWo As already mentioned, Figure 2 is the block circuit diagram of a cir-cuit for a capacitive signal coupler. At the primary side P a high-frequency signal is produced by an oscillator OSZ which is cantrolled by the signal input E transmitted via the coupling capacitor ~ to the secondary side S, where i-t isamplified and preferably rectified (output signal A) Figure 3 illustrates the arrangement of an integrated coupling capacitor which, embedded into a passivation layer PASS, lies on an insulating substrate SUB (e.g. ESFI-SOS technology). l~e capacitance is produoe d by the coplanar conductor path arrangement l-a-2. An arrangem~nt of this type produces very high dielectric strengths which, using solid silicon technolcgy, can other-wise only be achieved with great difficulty. On passivated surfaces the dielectric strength is in the region of several kV and the capacitance values are in the 100 pF-range.
; ESFI-SOS technology is described in the brochure "Siemens HaIbleiterbauelem~ente fur die Elektronik", order No. B 10/1431, pages 60 and 61.
Sinoe, given small spacings d, the breakthrough field strength EmaX
displays a sharp increase A (see Figure 5) it can be advantageous to connect a plurality of coplanar capacitors (conductor paths) in series while simLltane-ously reducing the spacing thereby achieving high dielectric strengths ~.~.3;3~
and greater coupling capacitances (see Figure ~). In this case the inner conductor paths (2 . . . n-l~ do not carry a fixed potential. An increased dielectric strength of the multi~conductor arrangement is subject to precise symmetrical design of the conductor paths which can be achieved relatively easily with current technology.
In accordance with Figures 3, 4 and 5, the breakthrough voltage (UDB) for two conductors and n conductors is governed by UDB 12 ~ E12 a (1) and UDB ln ~ n E12 a (2) In order to achieve an equal dielectric strength with n conductor paths we must have 12 ~ ~12 _a (3) n a if CKln 7 CK 12 and a~- ~ a A genuine gain can be achieved with respect to the quality (UDB and CK) and area of the coupling capacitor.
In order to further increase the coupling capacitance, the passi-vation layer should possess as high as possible a relative dielectric constant.
Figures 6 and 7 illustrate an example of a capacitive coupling circuit constructed for signal transmission in ESFI-SOS technology. The circuit elements are conventional transistors, diodes, resistors~and capacitors (with the exception of CK), as are used in ESFI technology. As a transmission path of this type displays band-pass characteristics, it is effective to tune 3 ~33~
the oscillator frequency to the middle frequency. This can be achieved by virtue of the selection of the number of stages in the ring oscillator or by modifying the inverter transit time. In this arrangement the input and output stage are referenced STE and STA respectively, the amplifier is referenced VS, and the rectifier is referenced GL.
Figures 8 and 9 illustrate an example of a power supply circuit consisting of a capacitive coupler. The voltage component U+l of an oscilla-tor signal of high frequency (f ) is amplified and the oscillator signal is transmitted via CK to the primary side. Here a current of the value UH -
2 f osc CK flows. The current is rectified and the storage capacitor ESPis charged. The stored energy is adequate to temporarily supply the primary circuit ~ith current.
Although various minor modifications may be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent warranted hereon, all such embodiments as reasonably and properly come within the scope of our contribution to the art.
Although various minor modifications may be suggested by those versed in the art, it should be understood that we wish to embody within the scope of the patent warranted hereon, all such embodiments as reasonably and properly come within the scope of our contribution to the art.
Claims (12)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits, comprising: a signal coupler integrated on a chip; a primary circuit on the chip; a secondary circuit on the chip to be coupled to the primary circuit; the signal coupler having an integrated coupling capacitor formed of a coplanar arrangement of spaced conductor paths embedded into a passivation layer, the passivation layer being arranged on an insulating substrate.
2. The circuit of claim 1 wherein the insulating substrate comprises sapphire.
3. A monolithically integrated circuit of claim 1 wherein a plurality of coupling capacitors formed of coplanar conductor path arrangements are positioned on the chip, the coupling capacitors being commonly interconnected in a series arrangement to form a capacitive voltage divider, and spacings between the conductor paths being reduced in comparison to spacings between conductor paths in the case of a coupling capacitor of a single coplanar conductor path arrangement.
4. A monolithically integrated circuit of claim 3 wherein the passivation layer has a high relative dielectric constant.
5. A monolithically integrated circuit of claim 1 further including a signal input arranged to be influenced from outside of the chip and a signal output arranged to influence circuits external to the chip, the primary circuit having oscillator means for emitting an AC signal when it receives a relevant signal via the signal input, the secondary circuit having an amplifier and a rectifier between an output of the amplifier and the signal output, means for input coupling AC signals emitted from the oscilla-tor via the coupling capacitor into an input of the amplifier such that a signal corresponding to the signal supplied to the signal input can be obtained from the signal output.
6. A monolithically integrated circuit of claim 5 wherein the oscillator means oscillates at a predetermined frequency which is a middle frequency of the overall circuit having band-pass characteristics.
7. A monolithically integrated circuit of claim 6 wherein the oscillator means comprises a ring oscillator of a logic-linking element and at least one inverter connected to an output of the logic-linking element, the number being selected so as to determine the oscillating frequency of the oscillator.
8. A monolithically integrated circuit of claim 6 wherein the oscillator has a ring oscillator and comprises a logic-linking element and at least one inverter which is connected to an output of the logic-linking element, can be determined via the selection of the inverter, a transit time of the inverter being selected so as to determine the oscillating frequency of the oscillator.
9. A monolithically integrated circuit of claim 1 further including power coupler means for power supply of the primary circuit from a secondary voltage source, said power coupler means being arranged on the chip and designed substantially the same as the signal coupler, said power coupler means including at least one oscillator at its input end and at least one rectifier at its output end.
10. A monolithically integrated circuit of claim 9 wherein the output signal of the oscillator is connected for amplification by an ampli-fier and the rectifier is followed by a power store means from which short-duration pulses can be taken for power supply of the primary circuit.
11. The circuit of claim 10 wherein the power store means comprises a storage capacitor.
12. A monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits, comprising: a primary circuit and a secondary circuit integrated on a chip; a signal coupler connected to couple signals between the primary and secondary circuits; said signal coupler comprising spaced parallel conductor paths embedded in a passivation layer on an insulating substrate so as to form an integrated coupling capacitor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DEP2842319.0 | 1978-09-28 | ||
| DE19782842319 DE2842319A1 (en) | 1978-09-28 | 1978-09-28 | MONOLITHICALLY INTEGRATED CIRCUIT WITH HIGH VOLTAGE RESISTANCE FOR COUPLING GALVANICALLY ISOLATED CIRCUITS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1133148A true CA1133148A (en) | 1982-10-05 |
Family
ID=6050752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA336,425A Expired CA1133148A (en) | 1978-09-28 | 1979-09-26 | Monolithically integrated circuit of high dielectric strength for electrically coupling isolated circuits |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4339668A (en) |
| JP (1) | JPS5546594A (en) |
| CA (1) | CA1133148A (en) |
| DE (1) | DE2842319A1 (en) |
| FR (1) | FR2437698A1 (en) |
| GB (1) | GB2035702B (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4853523A (en) * | 1987-10-05 | 1989-08-01 | Pitney Bowes Inc. | Vault cartridge having capacitive coupling |
| US4802027A (en) * | 1987-10-05 | 1989-01-31 | Pitney Bowes Inc. | Data storage device coupled to a data storage interface |
| CA1294333C (en) * | 1987-10-12 | 1992-01-14 | Marie-Christine Rolland | Radio receiver antitheft device used namely in passenger cars |
| JPH0563615A (en) * | 1991-08-30 | 1993-03-12 | Ncr Corp | Capacitive coupling device |
| US6728113B1 (en) | 1993-06-24 | 2004-04-27 | Polychip, Inc. | Method and apparatus for non-conductively interconnecting integrated circuits |
| WO1998044687A1 (en) * | 1997-03-31 | 1998-10-08 | Hitachi, Ltd. | Modem using capacitive insulating barrier, insulating coupler, and integrated circuit used in the modem |
| US6023202A (en) * | 1998-02-13 | 2000-02-08 | Hewlett-Packard Company | Ground return for high speed digital signals that are capacitively coupled across a DC-isolated interface |
| KR19990072936A (en) | 1998-02-27 | 1999-09-27 | 가나이 쓰도무 | Isolator and modem unit using the same |
| US7356952B2 (en) * | 2002-06-17 | 2008-04-15 | Philip Morris Usa Inc. | System for coupling package displays to remote power source |
| US7170927B2 (en) * | 2002-08-16 | 2007-01-30 | Texas Instruments Incorporated | Methods and apparatus for an ADSL transceiver |
| JP2006121046A (en) * | 2004-09-24 | 2006-05-11 | Meiko:Kk | Circuit board |
| US7425760B1 (en) | 2004-10-13 | 2008-09-16 | Sun Microsystems, Inc. | Multi-chip module structure with power delivery using flexible cables |
| US8624740B2 (en) * | 2005-02-04 | 2014-01-07 | Philip Morris Usa Inc. | Controllable RFID card |
| US7429984B2 (en) * | 2005-02-04 | 2008-09-30 | Philip Morris Usa Inc. | Display management system |
| US7504905B1 (en) | 2008-01-30 | 2009-03-17 | The United States Of America As Represented By The Secretary Of The Navy | Method for coupling a direct current power source across a dielectric membrane or other non-conducting membrane |
| US7741896B2 (en) * | 2008-02-15 | 2010-06-22 | Avago Technologies Ecbu Ip (Singapore) Pte. Ltd. | High voltage drive circuit employing capacitive signal coupling and associated devices and methods |
| WO2012065229A1 (en) | 2010-11-18 | 2012-05-24 | The Silanna Group Pty Ltd | Single-chip integrated circuit with capacitive isolation |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4042948A (en) * | 1959-05-06 | 1977-08-16 | Texas Instruments Incorporated | Integrated circuit isolation with mesas and/or insulating substrate |
| US3519901A (en) * | 1968-01-29 | 1970-07-07 | Texas Instruments Inc | Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation |
| US4024626A (en) * | 1974-12-09 | 1977-05-24 | Hughes Aircraft Company | Method of making integrated transistor matrix for flat panel liquid crystal display |
| GB1537843A (en) * | 1975-11-17 | 1979-01-04 | Nat Res Dev | Charge-coupled devices |
-
1978
- 1978-09-28 DE DE19782842319 patent/DE2842319A1/en not_active Withdrawn
-
1979
- 1979-09-11 FR FR7922667A patent/FR2437698A1/en active Granted
- 1979-09-14 US US06/075,679 patent/US4339668A/en not_active Expired - Lifetime
- 1979-09-26 CA CA336,425A patent/CA1133148A/en not_active Expired
- 1979-09-27 JP JP12469279A patent/JPS5546594A/en active Pending
- 1979-09-28 GB GB7933651A patent/GB2035702B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2437698B1 (en) | 1984-08-10 |
| DE2842319A1 (en) | 1980-04-17 |
| FR2437698A1 (en) | 1980-04-25 |
| GB2035702A (en) | 1980-06-18 |
| GB2035702B (en) | 1983-03-02 |
| JPS5546594A (en) | 1980-04-01 |
| US4339668A (en) | 1982-07-13 |
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