CA1132251A - Data handling equipment for use with sequential access digital data storage devices - Google Patents

Abstract

A B S T R A C T

The invention provides in a disc buffer peripheral access-unit a random access memory which is equivalent in storage size to one complete disc track, and includes command and status registers located at the start and finish addresses respectively of each sector of the track. When a transfer is required, the control-register of each sector involved in transfer is programmed with the track-identity by the disc-handler process.
When a sector is read-out and stored in the corresponding area of the buffer, the relevant status-register is correspondingly updated. This permits processor interrogation, of the status-register for the particular sector at any time. Multiple transfers may be performed by using a status/command resister-map in a storage segment accessible to the disc-handling process.

Description

` 113~ZS~

~he present invention relates to data handling equipment for use with sequential access digital data storage devices.
In such devices the actual bulk storage media employs magentic disc ordrum storage devices. In such devices the , 5 access time for any particular sector ~aries in accordance ', with the distance that sector is away from a read-write head on the particular track. On average the access time is one half of a bulk storage device revolution and for a fixed head disc this may be of the order o~ lO milliseconds. Such a large average access time renders the disc bulk store when used wi,th a compu-ter system somewhat inefficient.
~, In such circumstances the disc handler process is called , upon to sort the accesses in relation to the appearance order of the sectors requested. ~his sorting process is not only time consuming but requires to be continuously performed and requires to continuous1y be aware of the current position.
Accord1ngly lt is an object of the present invention to provide data handling equipment for use with a sequential access digital data storage device~which equipment removes the requirements for such sorting operations to be performed and allows the d1sc~and data processing system to function autonomously. ' ~ ,~
According~to the 1nventlon there 19 provid~ed a data , handling equipment, for use with a sequential access dig1tal data storage device having informat1on stored in tracks~each t,rack having~an equal number of n sectors, whioh equipment `~ includes a d1rect access store comprising (1) ~ contiguous ; ~ 3 storage looat1ons formed into a work~116t, there be1ng~one 1~3Z25~

location in the work list f'or each sector of a track of the digital data storage device each location storing a work item which includes a dlrect access store addre,ss outside the work list or an idle code, and (ii) a data buffer for . ' the sto.rage of transfer data storage areas each of which i~
dynamically allocated for the storage of the information invalved in a data transfer, each data storage area comprising a transfer : descriptor, a transfer word count and a defined storage areaspecific to the number of data words into which or from which the data words of -the required digital data storage device data transfer are to be written or read and the equipment includes an inspection register which interrogates the work items in sequence in synchronism with but one sector in ~ advance of the positioning of the read~write heads of the 15 sequentlal access digital data storage device and the ~:~ equipment is arranged when a work item is detected by the interrogation register to use the direct access store address in that work ltem to gain access to the transfer data storage : area allocated to the data transfer whioh is to commence ~,:
at the start of the next sector to pass the read/write heads of the sequential access digital data,storage device and the ' equipment includes means for reading the transfer descriptor ~ (i) to seleot the sequential access storage-device track to be ,~ used for the~transfer and (ii) condition a sector count register with the number of sectors to be lnvolved in the ' transfer which sector count register is arranged to be decremented for each sector involved in the transfer as a 28 sector passes the read~write head and the equipment includes ~: :

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means for terminating -the transfer when the con-tents of the sector count register reaches zero by overwriting the corresponding work list entry with the idle codes.
~he invention should be more readily understood from the following description which should be read in conjunction with the accompany drawings.
Of the drawings Fig. 1 shows a block diagram of a system suitable for the incorporation of a data handling e~uipment according to the invention.
~ig. 2 shows a block diagram of an access unit of Fig. 1 suitable for use with the data handling equipment of the invention.
~ Fig. 3 shows a diagram of the buffer store of -the ;~15 embodiment of the invention.
Flg. 4 a, b and c show a block diagram of the data and buffer ~; control unit.
Whlle ~lgS. 5 to 7 shows flow~ dlagrams of the operation ~;~ of the data and buffer control unit.
Considering firstly Flg. 1, it will be seen that the modular data processing system in which the embodiment of ~: :
`~ ~ the invention is most advanta~eously-incorporated include~s (i) a number of peripheral equipments~such as PD (magnetic ~; ~ 25 : ; :
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disc or drum), PP (page printer) and serially activated peripheral equipment which are se~ved byleads PSi~e and PS~ 7 (i~ three memory modules SMl, SM2 and SM3, (iii) three processor modules CPUA, CPUB and cPUa and (iv) a pair of multiplexors MPXN and MPXM. Such a system conforms basically to that disclosed in B~P. Specification 1,394,4~
Eaeh processor module is provided wlth a discrete data communication path or bus (PBA, PBB and PBC). ~ach processor bus P~A, PBB, PBC is -terminated upon a separate port of (i) 3 each storage module access unit (i.e. access units SAl, SA2 r and SA3 of storage modules SMl, SM2 and SM3 respectively) and (ii) each multiple~or MPXN and MPXM. ~ach multiplexor multiplexes the demands on the busses onto a single peripheral 1, - data bus (PDN and PDM) which is terminated upon a separate ,~ 15 port of each peripheral equipment access unit (PAD, PAX, PAB
and PAP). A multiplexor module is incorporated into the system to remove the need for a variable port facility on each peripheral equipment access unit and each channel module access unit. Consequently the peripheral equipment access units are rendered insensitive to growth in the form of additional proeessor or storage modules.
All the aecess units and the multiplexor modules are 1~ provided with the facility of~recognising coded informatlon !r applied to the busses terminated upon their ports whieh 1, corresponds wlth their own system address identity and of multiplexing such addressed demands into the module, equipment ~' or perlpheral bus they serve. ~he storage module aceess 28 unlts (SAl, SA2 and SA3) and multiplexors MUXN and MUXM are ~ 5 ~

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very similar in construction one giving access to a stOrQge module whereas the other gives access to a peripheral bus;
both include facilities for queuing demands in priority order.
~ach peripheral equipment access unit functions in a similar manner to a store access unit giving addressed access to a small number of peripheral equipment administration registers which include command, data and status registers.
~rom the above it can be seen that the data processing ; system configuration is such that each processor module is able to directly address any storage location, any peripheral equipment command, data or status register as though it were part of a common pool of storage equipmen-t. As a consequence no input/output instruotions per se are required in the processor - module's instruction reper-toire as simple memory read andwrite instructions are sufficient to communicate with the peripheral eqUlpment administrationregisters. Similarly data trans~ers between peripheral equipments and the store may be controlled by a process executing similar memory read and write instruction on storage locations and periphe~al equipment administration reglsters completely independently from the functioning of the rest of the system. Such a system ~ . .
~- is described in B.P. Specification 1,394,431.
-he disc controller (~ig. 2) of the inven~lon contains two sections: ~
(1) The Access Uni-t~which is functionally common to all modules attached to the Parallel Bus of a multi-processor system of the type defined above, and ~ ;~
28 ~ (2) The Gontrol Unit whioh lS particular to disc type :: : .
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~ 3Z~51 handling and is responsible to the processing s~stem for the provision of facilities appropriate to the disc operation.
~he In-terface between the Access Unit and the Control Unit is ter~ed the LOCAL IN~ERFAC~ and -the Interface between the Control Unit and the disc is-ter~èd the DISC IN~RFAC~.
~ig. 2 shows a block diagram o~ the equipment required in the disc peripheral equipment access unit. Basicall~ the access unit consists of an access section AS and a control unit CU. ~he access section terminates the two peripheral ; buses PDN and PDM and provldes input and output gating PIG
and POG together with demand interrogation logic DIN and DIM
for each peripheral bus. Each demand output is connected to a demand sorting circuit DS whlch resolves concurrent demands and operates the selected input and output gating arrays~
Also included in the access section is an access control circuit AC whlch synchronises the execution of the chosen cycle~,~ such as~Read, Read~and Hold, Wrlte~or Reset as defined b~ the atate~of the peripheral bus control signal leads. ~he `~ 20 ~ ~ access control;~clrcult AC also lncludes tlming pulse~
generatlon equlpment for the transmlsslon of command,~address, data and~parity~signals into the~control~unit CU and arrange-ments ~or receptlon~of~tlming and oontrol~slgnals from the co~trol~unit.
~25~ The control~unit;Is~functlonally Spllt into three pa~ts;
he~Diac Interface Controller,~(2) ~he Additional ~unctions Controller and (~ ho Dat~ and ~ f~r~C~n ro_ler ~L~;3Z;25~3L

Disc Interface Controlle~ (DIC) Contains:-- (a) 1ine drivers and receivers to dirèctl~ comrnunicate with the disc.
(b) ~iming controls necessary to convert the timing signals to and from the disc to those of the two Parallel and Serial;Registers, the Cyclic Redundancy Check Code Generator, and the two Serial Parity airCUitS ~
(c) A wired Disc Identity.
Additional Functions Controller (AFC) ~, Contains:-(a) A command Register.
; (b) A Status Register.
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(c) An Inspection Register.
(d) A group Diagnostic Register.
- (e) Circuitr~ to request internal transfers.
Data and Buffer~Controller (D~BC) . .
~ Contains:-~ , , (a) A Buffer and its addressing Control Mechanism.
(b~ Data Address, Data Out and Data In Registers.
- (c) ~wo Parallel and Serial Registers.
(d) A Gycllc Redundancy Cheokcode Generator (e) ~egisters associated with the ~ransfer Capabllity ~ mechanlsm, Track and Sector, Sector count, Checkcode verifler and ~ransfer Word count.
(f) A ~uffer ~ransfer Pointer Register.
28 (g) Sectors per '~rack and words per Sector Register and , ~3Z;ZS~

counters. ~ ~
(h) Module Address and Inverse Address Register Mechanisr~s.
(i) ~ocal Interface control Méchanism.
(j) Ci~cuitry to request and control internal transfers, namely:-(1) A queue ` ' (2) A microprogram.
(~)'An address mechanism for specifying source and destination of internal transfers.
, (k) Security checks to ensure valid disc data transfers.
.
~he Controllers are all micro-program controlled and flow diagrams showing their f'unctional operation are shown in ~t Figs. 5 to 7. , ' .'~
The Control Unit accepts and 1nterprets system commands to produce the corresponding effects upon the Disc. It . !
similarly accepts and staticises conditions relating to the operational state of the Disc and makes these available to ~ the processing~system. ~hese f'acilitie~s are provided by the f ,~ processor addressable COM~L4~D REGIS~ER and S~A~US REGI~ER ~-~ ,.
; 20 respectively.
he basic data handling facilities wi-thin the Control .
Unit are provided~by a large dlrectly addressa'ole register area termed the BUF~ER whlch is used for both data in and , data out transfers.
~he Gontrol Unit also provides a system initi~alisation facility to enable a predetermined area of the Disc to~be ;~ ~ automatically read and loaded i~to the Buffer where it~ lS i`
~ 28 available to Prbcessors performing~validation and initlalisation i~

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functions.
Once the initialisation mode has been entered the Control Unit will only allow the Processing system to access the first four locations of the Register Structure~ It will ; 5 not operate as a normal disc until the appropriate bit in the Status Register has been reset by the Processing SysterQ
writing to the Gommand Register.
~or the Processing System -to operate the disc in the normal mode, it must load the buffer with a transfer descriptor or so-called Transfer Capability (~C ~ig. 3) followed by an area which is either loaded by the Processing Systëm in the case of a '~
write or which is to be loaded by the Control Unit with data to ,~
be read from the disc. In order to initiate the transfer the Processing System must put into a work list WL a Buffer ~ransfer Polnter or work item WI which (a) polnts to the address X in the Buffer of the first word of the transfer descriptor or ~ransfer Capability (~C), (b) states whether a Read or a Write (indicated by the C BI~S) is to be performed and (c) is placed in a~location in the work list which is permanently linked with the angular position on the~disc where the transfer lS to start. ~his enables - several transfers ~o be set~up by the Processing System and then performed by the Control Unit in a sequence determined by the angular position of the disc, thereby reducing the transfer time to a minimum. ~When a transfer has been successfully oompleted the Control Unit~over`writes the corresponding location in the work list with all ones. If -the transfer in some way faults then the Control Uni-t stops all disc transfers and sets the `28 appropriate fault bit in the Status Register. The Processing 1 0 . '' r ~,, . , ,:~: . , .

2ZSl System can then, by inspecting the work list, dete-r~ine which transfers have been cornpleted and by reading frorn the wired Disc Identity ~rack and Sector Register the sector during which the fault occurred can ~e determined.
RE ISTER S~RUC~URF
; ~he addressable area of the Control Unit, containing 4096 locations, can be divided into those areas which exist inside the Buffer Random Access Memory and those which exist as individual registers.
The locations in the Buffer can be written -to and read from while the addresses allocated to an individual register may only be capable of one operation.
In the Initialising Mode there will be 4 individuall~J
addressed external registers, the first 4, 0-~, and the Buffer will contain 4092 locations 4-4095.
ln the Normal Mode there will be up to 64 individually addressed external registers, the first 64, 0-63, and the Buffer will contain 4032 locations, 64-~095.
Module Address Register .
20 ~ ~he Module Address register function is provided for system testing purposes such that when this "register" is addressed together with a read command, the Control Unit causes the 24 bit address used to address the disc controller to be returned as the data word of the Read Cycle. ~he address lS wr1tten into the data out reg1ster DOU~ and signal MAR causes the contents of DOU~ to be written into , ~
tqe D~N reg1ster. Whenever the address is access the 'Busy' 28 signal is generated a~d the 'Status' signal is inhibited.
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Inverse Address Re~iste:r ~he Inverse Address register function is provided for sJste~
testing as abo~e, except that when this "regis-ter" is addres~ed together with a Read Command, the ~ontrol Unit causes the inverse of the 24-bit Module Address in DOU~ to be returned as the data word of the Read Cycle under the control of signal IAR. I~henever this address is accessed the 'Status' signal is generated and the 'Busy' signal is inhibited.
Status Re~lster ~he Status Register which is located in the additional function controller AFC records information relating to the operational state of the Control Unit and conforms basically to any of the status register of the multi-processor s~stem of 3.P.
Specification 1,394,431. ~he occurrence of any Status condition is indicated when the appropriate position is set to a Logic 'one' state. All unspecified bit positions will be set to the ~ogic 'zero' state. The conditions which control the setting and ~ ~ resetting of the Status Indicators are described in the `~ following paragraphs.
Bit l Out of Service hls indicator reflects the sense of the "set out-of-service blt" ln the Command Register. It is set when the ; Command lS present and is reset when the Command is remov;ed.
it 2 Stopped ~his indicator reflects the sense of the stop ~it , ~
~ in the Command Reglster. It is set when the Command is `~ present and is reset when the Command i9 removed.
28 it 3 ~rozen .

: ., ~ - 12 _ .

-22Sl . . .
; This statUCi bit becom~es set when a fault has been detected and all -transfers -to or irom -the disc are inhi~ited.
It is reset onl~ when all the faul-t bits in the status registe~
which can cause the Frozen bit to becoMe set ha~i/e been rese-t.
The fault bits which cause a freeze are:- Data Check ~aultj Invalid Transfer Capability; Transfer Timeout; Write Parity ~ault;
Power ~ault; Disc Not Rotating; Internal Parity ~ault; Data Buffer Overflow; Words/Sector ~ault; Sectors/Track ~ault.
Bit ~ Data Check ~ault This status bit becomes set when the Cyclic Redundanc-y Check-~
code has failed when reading data from the disc. The bit is reset by writing a ~ault Reset to the Command Register.
Bit 5 Routinin~ ~ault This status bit becomes set when the Cyclic Redundancy Checkcode has fa1led while routining the disc. Routinin~ is .: i suspended whlle this bit is set. The bit is reset by writing ;~ a ~ault Reset to the Command Register.
Bit 6 Write~Parit~ ~ault This status bit becomes set when an internal serial - t 20~ transPer has a Parity ~ault~ Th1s bit lS reset by wrlting a ault Reset to the Command Register.
Bit 7 Internal Parit~ ~ault ~
This s~tatus bit becomes set when an internal parallel transfer has a Parit~ ~ault. The~ bit is reset b~J writing a '~
~ 25 ~ ~ault Reset to the Command Register.
;~ ; Blt 8~ Invalid Transfer Capabllit~
: ~his status bit becomes set whe~ a Write ~ransfer ~ 28 Capabllity has~an~invalid cheokcode. ~he bit is reset by ~ : _ 1 3 _ ' . . , ,' ', ' j ~ ' . ' . , ,' ,, ' , ' , ~ ~ . .

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writing a ~ault Reset to the Comrnand Reg:ister.
Bit 9 Transfer ~imeollt ~his status bit becomes set if the Control unit, havirl~ set up a transfer, fails to find the sector to which a transf'er is to ,~ 5 be made b~ the time two sector Markers have occurred. The bit is reset by writing a Fault Reset to the Cornmand Register.
Bit 10 Power Fault ~, This status bit becomes set when a Power Failure has been detected by the Control Unit. This bit also becoraes set when a Force Power ~ault is written to the Comraand Register.
When -this bit is set i-t holds several circuits in their rese-t ; states. The bit is reset by writing a ~ault Reset to the Command Register.
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~;~ Bit 11 Data Buffer Overflow ' ~ This status bit becomes set when the Control Unit attempts to access a storage locatlon outside the Buffer while transferring data to or from the disc. ~he bit is reset by writing a ~ault Reset to the Command Reglster. ' ,~' Bit 12 Words per Sector Fault~
~his status bit becomes set when -the Sector Marker ~ does not occur at the programmed interval specified by the ,~ sectors per track and words per Sector Register. ~he bit~
is reset by writlng a ~ault Reset to the Command Register.
~;, Bit13 Secto~rs ~er_~rack Fault ~ t ,~' 25 ,~ ~ his status~bit becomes set when the Index Marker do,es~not occur at the programmed interval specified ~ the sector,s~per track and words per Sector Register. The bit ii3 ,` . ~ :
28 reset b~ writing a ~ault Reset to the Command Register.~ ' ;~ .. ~ s ,,~ , ' - 14 ~
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Bit 14 r~ufl`~r Parit~r Fault I'his status bit becomes set when a Processor parall~
transfer has a de-tected Parit~J Fault. When this bit becorrles set the 'Status Wire' is set. '~he Buffer Parity Faul-t ~it is only reset by writing to the Command Re~ister.
~it 15 ~ufI~er Pa~ Inverted '~his Indicator reflects t'ne sense of the 'Invert ~uffer Parity' bit in the Command Register. It is set when the Command is present and is reset when the Comrnand is removed.
3it 16 Data Check Inhi'oited ~his Indicator reflects the sense of the 'Inhibit Data Check' bit i~ the Corr~and Register. It is set when th~s Command is present and is reset when the ~ommand is removed.
~it 17 Routinin2~Inhibite-d his Indicator reflects the sense of the 'Inhibit Routining' bit in the Command Register. It is set when the Command is present and is reset when the Command is removed.
-Bit 18 Initlalisin~
~ ~nis~status blt becomes set when the disc is Inltlalising from start up area one. ~his may be due to external control or by the '~Set Inltlalislng~l' blt bei.ng set ln -the Command ; Register. It is reset when the Command is removed.
it 19 Initi ~ ~ ~
~ '~hls status~bit~becomes~set~when the~dlsc is itialising from start up area two. ~his may be aue to extern~_~control or~b~ the~'Set~Initlalising 2' blt belng 28 set in the~Com~and Register. It is reset when the Command 1~L3f~ZS~
is :~ er.loved .
~it 20 ~reeze Inhibited . . . _ t~his indicator reflects the sense of the Inhibi-t reeze bit in the Comrnand Register. It is set w'nen the Command is present or when Initialising is taking place, and is reset when the Command is removed.
Bit 21 Disc No-t Rotating ~ his status bit becomes set when the Ro-tation speed of the disc falls below a nominal value. ~he bit is reset by writing a ~ault Reset to the Command Register.
Wnen the Control Unit is switched on Power ~ault is set and all other bits are reset.
When Initialisation commences one of the Initialising bits, the Routining Inhibited bit and the ~reeze Inhibited bit are set, all the other Status bits are reset.
Command Refrister ~ he Command Register which is located in the additional functions controller~A~C~interprets the Processing System Com~ands pertinent to the Control Unit opération. ~he~
register oonforms to the format of the Command Register~
for all access~unlts ln the multi-processor~system of '' B.P. Specifloation~1,394,~31. Each 1ndicator bit of the Command Register controls a function or facility provided " , :~
by the Control Unit. ~he significance of each position in

2;~ the Command Xeglster is given below.
: ~ , ach Command is present when the appropriate bit is set to the logic one state. ~ach Command can be set by~a : : :
-' ~ocal Interface Write Cycle specifying the aommand Register a~d - 16 - ~ ~
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containing in the data word a logic one in the appropriate position. Some Command Bits are set when Initialising commences.
Bit 1 ~et Out_of Serl~ice ~he setting of this command causes the Out of Service Lamp to be illuminated and sets the Ou-t of ~ervice Indicator in the jStatus Register.
Bit 2 ~ault Reset r~he setting of this command causes -the Status bits 13 in the StatUs Register relevant to f'ault conditlon to be reset~ 7 Bit 3 Stop ~; ~he set-ting of this command causes the transfer of ., .
erial Data to or from the Disc to be stopped immediately.
'he remaining parts of the Control Unit function normally in order that test may proceed.
Bit 4 Invert Buffer Parit~
~he parlty urltten to the data Buffer by the Procéssing System is~always odd over address and data. ~he Parity~read from the~Buffer by the Processing System is odd over address 20~ and data provldlng~that the Buffer Parlty Inverted Status bit is not~s~t. ~When the Buffer Parity~Inverted bit is set, even parity will be~written to and read~rom the Buf~er for internal transfers; even parlty ~ill be~;read`from the Buffer by the Processing System, r~his is provided for testing the parity 25 ~ checklng circults.
Bit 5 Inhlbit ~reeze he setting~of this bit inhiblts the ~rozen s-tatus~bit~
2&~ ~ becomlng~set ald a ~reeze taklng pIac~ hls is lnt~nded~t~ be :: 5 ll~ZZS~

useZd during Ini-tialising and diagnosing only.
FZlit ~Z lnhil?it Data CheZ~k The setting o~ t~lis bit inhibits the Data Chec~ ~Zault Status bit from becoming set and causes all zeros instead of ~rack and Sector to be loaded into the C~clic Redundancy Check Code Generator at the start of eVerrJ sector.
3i-t 7 Inhibit Routining IZhe setting of this bit inhibits the operation of the ' Routining Mechanism.
;0 Bit 8 Set Initialisin~ 1 ~he setting of this bit by the Processing S~stem causes the Initialising 1 sequence to be performed. Initialising also occurs when the ~Ztatus Register has not been written to for approximately one second. When the bit is reset by the `~ 15 Processing System, even if Initialisation has not been . . , ,~ ~ completed, the Control Unit lS able to accept normal Dlsc Transfers.
Bit 9 Set Inltialls~ 2 As for~l but Inltlalising data comes from a dlfferent location on the aisc~
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Bit 10 ~Zo ce Power Fault lhe settlng of this diagnostLc comma~d caUses the ; Power Fault Status bit to become set.; It then resets ltself.
Blt 11 ~Zorce Index Marker `~ 25 ~ ~he setting of this dl~agnostlc command~ CaUSeB the ~ ~
disc~interface to simulate the receipt~of an Index Marker. Z
It then resets~ itsef.
28 Bit 12 ; - 18 Z5~

~he setting of this diagrlostic command causes the disc intèrface to simulate the receipt of a Sector Marker.
It thell resets itsel Bit 13 Force Read W~ite ~lock Pul~s The settin~ of these 5 diagnostic com~ands causes the ;~
disc interface to simulate the receipt of a number of Read~dJrite Cloc~ pulses. ~he number of pulses sirnulated is directly dependent on the written binary code. l'he Command ; Register should not be written to again until the pulses requested have been simulated (1 micro second per pulse).
Bit 14 lnhibit Disc Not Rotating ;: .
~he setting of this diagnostic command inhibits the ~isc Not Rotating Status bit from becorning set.
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Sectors per ~rack and Words ~er Sector Re~is-ter (S/~ C Fig. 4a) ;~ 15 ~his register is loaded, b~ the Processing S~Jstem from the local~lnterface overlead DSA before operating the disc under the control of th~e data source enable signal on lead DS3,- with the number of words in a seGtor and the number of sectors ln a track. At the star-t of every sector .~ 20 the value in the least significant part of~the Sectors per rack and Words per Sector Register is loaded into the ~ords per sector counter WPSC. ~his colmter is decremented over lead DSWC after~each word ls transferred. ~he count should reach zero as evldenced on lead SWC=O~when the last word in ~25 the sector has been transferred, and before -the next Sector Marker has occurred. ~ If either of these conditlons is not fulfilled,~then the Words per Sector Fault bit lS set in 28 ~ ~ the Status Reglster~ For diagnostlo purposes the value in the .
9~
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Sectors per Track and Word or Sec-tor register may be changed to te,st the setting of the fault bit. '~he func-tion of the Sectors per q'rack Counter SP~C is sirQilar. Of the 24- bit ,/ord in regis-ter S/~WC bits 0 to 7 indicate Words per Sector while bits 8 to 17 indicate Sectors per ~rack.
red Disc Identit~_~ ack and Sector Re~is-ter ~his Register is located in the disc inter~'ace controller DIC (Fig. 2) and is a modified form of the ~rack and Sector Regis-ter which is part of the ~ransfer Capability. ~he Disc Interface writes over leads WDI onto the buffer highway BH~I of Fig. 4c the Disc Identity to the ' field which is not used to specify ~rack and Sector. Providing a transfer is not in the process of being set up, then the Register is incremented every sector, to specif~ the ~rack ,~ 15 : and Sector. ~his 24 bit pattern is loaded into the Cyclic Redundancy Check Code Generator at the start of every sector.
t may be read by the Processing System to determine the angular position of the disc at a given point in time or to determine the address at which a freeze occurred because of ';
' 20 a fault.
~, Buffer ~ransfer Pointer Regi er (B~P Fig. 4a) his Register once loaded from the buffer highway BE~W
causes a transf~er to commence. It contains a pointer bits ~ 0 to 11 to the start of a l~ransfer Capabilit~ and hence ; 25 the Data IransIer Areà in the Buffer~ ~he pointer is used to,address the buffer over leads BAL when enabled by the ~icro-command BIP ~BA. Register B~P is,normally loaded by the 2~ Additional Functions Controller applying data to the buffer -- 20 - ~

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highwa~ overleads DSA, from the Work ~ist, when miero-corrl~rland load B~P oceurs. r~O read the full transfer capability the address in register B~P can be increManted under micro-cor~na~Ld INC B~P control.
Register Bl'P is cleared on Initialisation in ordcir to point at a wired-in ~ransfer Capabili-ty. '~he Most significant bit is used to produce micro-conditional si~nals " write (W) if a logic one a~ld read (R) if at logic zero.
'~rack and Sec-tor Register (~SR ~ig 4b) ~ 10 'l'his Register is loaded under the control of the ;~; miero-eommand LOAD '~C2 with the seeond word of a 'L'ransfer Capability from the buffer highway BH/W. Its track field bits 7 to 15 is used to specify the traek to be aeeessed on the dise while bi-ts O to 7 define the seetor. '~he information is applied to~the dise interfaee eontrol unit over leads DA.
he two flelds are eombined with the wired Dise Identity as described~above.
Seetor~Coun ~ er ~SCR ~ig. 4b) his~register is loaded from the buffer highway ~H/W
under tke~eontrol of the micro-eommand LOAD ~C3 with the third word of a ~ransfer Capability. It only statieises the least signiflcant bit~s whleh form the Seetor C~ount. Once a transfer has eommeneed, the seetor eount is deeremented by miero-eommand D~C SC after ever seetor. ~When the seetor count equals~zero 25 ~ the mlero-eondltlonal signal SC=O is~produeed. ~ ~
- The seetor eount is normally limited to the number of seetors per traek, but it ea~n be greater than this, as for 2~ example during Initialisatior~
: :: ~ - : , .
~ 21 , ~zzs~

mlln~f~r ~,~orcl Counl R ~is-ter ('r'1~J(,R F:ig. ~
Thls regis-ter is loaded from t,he '~uffe~ higrLhl~ray ;~ ;J
under the control of micro-command LO~D ~l~C with tlne word immediately following the ~ word mlransfer Capability. It contains the nurnber of words to be invol~ed in the required disc trans er. ~he register contents are decrernented under -the control of micro-co~mand D~C IWC after each wo~d is transferred until it reaches zero when i-t generates the micro-conditional signal ~WC=0 Check Code Verifier (CCV Fig. 4o) his verifier is loaded from the buffer highway BH/W
~; with the f`irst word of a ~ransfer Capability, the modified second word, i.e. Wired Disc IdentitJ I'rack and Sector, and the third word of the ~ransfer Capability. lhë three word '~
~ransfer Capabil1ty is checXed for validity, on a wri-~e, b~J a 6 b1t check code in its third word.
C~clic _ dano Check Code Genera-tor (CRCG i~. 4c) he Cyclic Redundancy~Chec~ Code uses the generator polynomial; x16 + x2~+ x + l and will~detect any one, two or 20 ~ three~bit~errors, and~any burst errors of 24 bits or less.
If~the generator 1s~f`irst cleared, lt will perform a modulo 2 division of` xl7 M(~) by the genera-tor polynomial, where M(x) is the message polynomial representlng the 1nput~seria1 data.
When the ser1al data~has been clocked in,~the generator will 25 ~ conta1n the remainder resulting from th1s d1vis1on.
he Generator is loaded in parallel at the sta~t o~
every sector w1th a 16 bit pattern~from the w1red D1sc~Iden-tity 23~ ~rack and Sec-tor Register. ~he data for~-that~sector to~be ~ 22 ~

~3~;Z51 written -to or rea-l from the disc is then passed serially through it. On a write, when the last bit of data has bee~
passed t'nrough, the rernainder isseriall~ writ-ten or1-to the disc immediatel~ following the data. On a read, when the data and the previously written checkcode has been passed through the generator1 the remainder in the gene~ator should be all zeros. If the remainder i5 no-t all zeros ag indicated by ZD then one of the Data Check ~ault bits i~ set in the Status Register.
;~ 10 Parallel a~d ,Serial Regrister 1 (PSRl ~ir~. 4C) Parallel and Serial Register 2 (PSR2 ~i~r. 4c) hese two Registers are identical in function, the duplication being necessitated by timing considerations.
~he Registers can be written to and read from, with data from the buffer over the buffer hlghway, in order to transfer data to or from the disc~ ~or write to the disc . ~:
operations, while one register is being emptied serially the other is being loaded in parallel: for read operations, while ~ . ~
one is being loaded serially the other is being emptied in 20~ parallel. At the end of every 24 bits their roles are~
reversed~ When data is written in parallel and then read in parallel the data lS inverted. ~here is an lnversion in the ~ ;
serial path via the;disc.
~ Inspectlon Reglster~
;~ 25 ~he Re~glster whlch is located ln the additional functions co~troller is loaded with a work item from the Work ~ist shown ; in Fig~ 3 whenever there is no Disc data transfer in progress 28 and a Sector Marker occurs. If the location contains all ones : : . : ;

:~

~32ZS~

it is considered as being an invalid -~ointer and igrloIed ~ha address of the loca-tion in the Work List is depende:~lt on the angular position of the disc and is the one in advance o~ the sector curren-tl~ under the disc 'heads'.
When the Work ~ist is deemed to contain a valid pointer, the pointer is transferred to the Buffer ~ran.sfer Pointe-r Register. ~nen the disc data transfer has been cornpleted, the location in Work ~ist, which supplied the Pointer, is overwritten with all ones.
orecast Re~:ister (FDA Fi~. 4b) ~ ~nen the Processing System has read ~rom the Buffer, ;~ the ~orecast Register is used to enable the contents of the ~ next location in the Buffer to be loaded into the Data In -~ Register (DIN) so that if the Processing ~Js-tem then reads - from this subsequent location during the next Local interference transfer the data will be made available~without naving to wait for the Buffer to be accessed. ~;
he Forecast Reglster FDA~is loaded from the data~
address reglster under the ccntrcl of the micro-commands 20~ ~OAD DADDS. Other micro-commands cause the Forecast ~egister ~`
to address the 3uffer (FDA-B~) and the contents o~ FD~ to be incremented~ C ~DA).
he ~orec~ast Register whlch can be read by the ~ ~
Processing System, by addresslng any of 4 locations, will Z5 ~ contain, depending on which location is accèssed.
(a) ~he current co~tents~of the Buffer ~ransfer Pointer :: ~ : :, , : : , Register.
~28 ~b) ~he last address used to refresh -the Buffer.
:

:

ZSl (c~ '~he last ~uf:~r address accecced ~~ t~e rd~i.-tional 'unc-tions Controller.
or (d) mhe con-tents oi t're Data rddres.c, Re~is-ter on -t're last write access b~J t~e Processi.ng s7sLe.rfl to ~-1 address not in the L'irst 6L- locations; the conten~C
of the Data Addiress Register incremented by one c:E
the last read access by ~the Processi.ng s7s~erl1 to an address not in the fir3t 64 loca-tions, (assur;1ing the increment time o~ 2 rnicro seconds has elasped).
I~owever, if all the accesses since the Forecast .i Register was last read from have been withi~ the irst 64 locations, the contents will have remair1ed unchanged.
: Local Interface Re~is-ters These registers called Data Address (DADDS), Data Out (30U~) and Data In (DIN3 are used to trans~er Data to and rom the Local Inter~ace. Imhe Local Interface when doing a Write operation will send an Address o~er leads ~I0~ which ~ is loaded into the Data Address Register (DADDS) under the ~20 clock oontrol of~an address vaIld clock signal A~C and~then Data which is loaded into the Data Out Register (DOU~) under ;~
-the control of a;data;~alld clock s~i~nal~DV~ `or a Eead the Local~Interface sends~an Addre~ss,~but~Da~a is supplled b~
the Data and ~uffer Controller to the~Data In (DIN)~Re~gister, the Data;is then trans~erred to the ~ocal InterLace o~er leads ~-~
IIN~ under clock sig--n ~1DIN.
e Data Address Reglster is written to -3y the 28 - Processlng sy~stem~on ever~ Local Interf'ace transfer.~ It can be 2 5 ~

~ "

~3ZZ~i~

read from b~ thc- Processirlg system by re(lding the ~Grecast I~egister for test pu~poses. ~'he Da-ta 0ut Register is l~/r:itte;~
to by the Processing system on eve~ Local Interface Write transfer. It can not be dlrectly re~d from t'ne ProcessiL!g s~stem. ~he Data In Register is read ~rom b~ the Proce~sin~
system on every ~ocal Interface Read transfer. It can not be directly written to by the ~rocessing system.
! Work ~ist (W~ Fi~. 3) ~he 256 Work ~ist Registers (assuming 256 sec-tors per ; l0 track) are provided to store several work item comlmands from ~;~ the Processing system whichare to be execu-ted in the minimum possible time. ~ach ~ocation in the Work ~ist corresponds to a sector of ~he disc. (e.g. Address l28 is sector 0, ~ .
address 129 is sector l, ......... Address 38~ is sector 255~.
~he Work L}st is scanned when no Disc data transfer is in progress, by~copying a work~item into the Inspection Register ;` in the addltl~onal ~unctlons controller. ~he~looatlon copied is the one correspondlng~to the next s~ector to come under the ;~
'heads'.
20 ~ If the~looatlon contalns all onea then it lS regardedas empty~and~lgnored~and the next l~ooatlon is read when;-che 'he~ads' reach;the;~next sector.~ When~a location is found~to COntaln a valld message the contents of the~locatlon are ;~
copled~lnto the Buf~er ~ransfer Polnter Regl:ster. ~he~;loadin~
~25~ o~ the~uffer rans~er Polnter causes~the~appropriate actions to be per~o~-med so~that the Dlsc data trans~er maJ comménce at ~he start of~the~ne~t sector.
28 ~ Data~Buffer (~FE~ b) 2S~L

~he D~ltl ~u:f:f~;r 1~'aose lv~out is skLG~lJ~l ir~ ?~iG~JicL-c sto~a~ f~lci]i~v~ bv-twverL tk~v P~ocv~ssinG s-~s-te~n ~rld -b~Lv Disc to vnable thG two to run a-t tkeir Gwn spred, a~ld so '~eep the time to do a Disc d~ta tr~ns'er to a r~inirf,u~ n~ O r~
- 5 copied from the Work List into the ~uffer Trans~er Pointrr ~-, Regis-ter specifies a pointer tG the Data Buffer, arLd al,,o "! specifies whether -the Disc data transfer is to be a r'ead OJ:
,~ ` a Write~ ~his pointer specifies -the ~tart of a T_ansfer Area which contains a ~ransfer Capabilit~ imrnedia-tel~ followed by a '~ransler Word ~ount and Data Trarlsfer Area. There ca be several - Valid 'rransfer Areas in the Data Bu:.fer at one time.
~,ransfer Ca~ bili,t~ (~rc }?ig. _) A 'rransf`er Ca~ability is gerlerated by the Processing system in order~to address an area on the Disc. It consLsts oi three 2~ blt words in ~o:rma-t shol~m at i;hr bot-tom ol` b'lg. ~. f ~; The~flrst word is all zeros. The second word con-tains the ~rack and Sector at which the transfer s-tart. '~he -thlrd word contains the number of sectors that this capabili~y refers 20 ~ to.
he chech code as explainbd above lS a check over the three words. The bits called empty in~the second word are replac~ecl with the Wired ~isc Identity by the Contlol Unit.
he generation of the chLeck code lncludes -the ~lrea Disc ;25 Identity bits~and not ;the emp-t~ blts.
~ransle-r Word~Coun 'C
he ~ransfer Word Count~defines -t~e rumber of locatioLls 28 in the Data Trarsfer Area. ~or a read o~oeratlon ~rom t-he Disc, ~, ~32ZS~

~,herL tne lrlumbe:c oi data words IGad Iro-lrl the Disc e~uals the ''rans,el l,lold ~ount -the Disc data trarlsf'er is stGpr,ed. I-t ~,rill al~ead~ have been stopped if the number of Eector, read fro~
the Diso equalled the Sector Count. For a write operation to the Disc, when the number of data words wri-tten -to the Disc ~, equals the ~ransfer Word Count, the remaining l~rords that ca 'oe written before the number of sectors written to thc 3,isc equals the Sector Count are written wi-th all bits a-t ~ero.
~he Disc data transfer is stopped w'nen the nurnber of sector-`~ ~,rritten to the Disc equals the ~ec-tor Count.
Dia~nost ~ isters tDREG BI,OCK ~
; ~hese eight Registers enable the sta-tes of certain internal signals to be monitored by the Processing s~stem for test purposes. Depending on which Register is accessedO
'5 Conditlonals O to 7 ~ can be selected b~ Bit O ,~
~ CondltionaIs 10 to 17 ~ can be selected b-~ Bi,t 2 ;~ Slots O to 7 can be selec-ted b~ Bit 2 Slots 10 to~l3,~and can be selected by Bi-t-3 ' Conditionals 20 to 23 ;~ ; Before consldering the operatlon of the disc controller ~ it is convenient to define the signals which are generated : ~ :
within the varioUs units of the controller which will~be used in the~flow dlagrams~of ~igs. 5 to 7 to show the controller 2~J ~ operation.
,Si~nals Ori~ina~lng in- the Addi,tonsl ,Functions or ~' 9C Interfaoe Controllers ord ~equest ~WRq~) ~hls is a flag set b~ the 4ddltlonal .

~32Z5~

:
Flmctions Controlleir orl a l~lrt~;TE c~cle ,r~l~e~
one of the Parallel-Seria] regi.AJters is tG
be loaded. '~he flag is reset ~J the Data and Bu:.fer CGntroller ll~en the loadi~g has been carried out.
~` Word Read~J (WRF) '~his :is a flag set by the Additional Funct:ions Controller on a E'~AD c;ycle~
when one of the Parallel-Serial registers is to be unloaded. '~he flag is rese-t by the Data and Buffer Controller when the unloading has '~ee~
carried out.
On Sector (OS~) A flag controlled Gy the disc interface controller which indicates that the R/W heads are located on the first sector of a transfer, and thé raising of which resets the 'Awaiting of Sector' flag. ~he flag should remain up until the end of the transfer, unless the ~ disc goes loff sector' during~a transfer.~
Microprogra~Queue A flag which requestsatransfer~ia Request~(MQRF) ~ the buf~e~r data hlghuay BH~I, as~
speclfled by~ a Source/Destinatlon code.
he flag is reset by the Data and Bu~fer Controller, wh~en the~transfe~
has~been carried out.
28 ~ Slx ~lt Souroe Code(SC) A~unldireo-tlonal parallel hlghway carrices .
~ ;29 _ ~ ~

:: : ~ . ' :
, " ~: ~ "~ , " " ~ ,~, , ,; , - ";, , ~

Z~25~L
,; , .
a 6 bl-t bina~ codrJ, w'nicr. specifie~
the source ~:o-c data trancfe;~s initiated bJ the ~dditional Fu~lctions Co7ltroller (see table 1).
~ 5 . Six ~it A unid.irectional parall~-1 hi~hwa~Js ; Destinat-lon Code (DC) carries a 6 blt- binary code, ~lhich speci~i.es the destination(s) for the : above transfer.
Read-Write Clock A cloGk provided for serial snifting ~10 (R/WC) ~ o~ data into or out of -the Parallel -Serial.registers, the CRC generator, and the Serial Parity generators and ; checkers. ~ :
Master Clook~(MC)~ A clock synchronls;ed to the rotation ~ ~: of the disc. ~ ~
Index Mark (~IC)~ Clock~wh1ch occurs~at the beglnnlng of :Sector 0.
Se;ctor~Mark (BC)~ A~.clock~which occurs~ at the b~oundar~
o~each~se:ctor.
: Read`Data (RD) ~ A serial; hlghwa~carrying READ~data from~the disc, to the Parallél~and Serlal~Register and Serlal Parit~
Checker~l s.
~ : Enable~Al~ l~ hesë sign~ls control the rout~lng o~
:~ 2~ the~R/WC to~one~or other of thè~Parallel~
a~d Se~rial~Registers a~d~to ~he~
;Serial Pari ~;~Generat:ors~ nd~C ckèrs.~ ~;
he~Parallel:~oad~CIock~is route~ ~o ZZS~

-the P & S .regist,er not receivi.ng the :E~/WC
. ~ , . . . ~
E:NA~ E A]. ~L3LE B] R/~ o:r DIhGi~OSTIC
C.LOCK ROU'l~ D 5~0 __, . _ .. __ ~ _ . . _... _ . ,~
O 1 P & S Re gister 2 ._ ___ P ~ S Regiister 1 _ . . _ Enable A2~B2 ~hese signals set the rnode controls on Parallel and Serial Regist(,r.s 1 and 2, select o~e or o the, of the . Parallel and Serial Registers as a Write Data sb-urce and enable the parallel unloading of one or other of the Parallel and Serial Registers~
CRC l~nable ~his signal selects the CRC generator . as the WRI~:13 DA~A source when the last data bit has been sampled by the disc.
CRC Enable ~ ~his sig~nal inhibi-ts the outputs of both Parallel and Serial Registers ~
, , , when the CRC output is the WRI~E DAq:A ~ .
source ~:
PBL :Enable ~: ~his signal selects the pre-amble/post-arnble genera tor as the WRI~E DA~A
: ~ : s ourc e .
P13L E~able ~ his signal inhibits the out~?ut o~ ~,h.e : ;~ CRC generator when the pre-amble/~ost-amble generator is the source of WRI~
-DA~A.

-25~

IE~`4BLE ~ l/~LE¦ Ol~C CKC PBI. ¦ PBL ¦,J~lrLI~ D.'T~ ¦
A2 i ~2 ENAB~E h~-LB~ EIif~ ~ SOU~C~
._ . ._ . __ _ .. ~
1 0 1 0 1 0 1 ~ G 1 1 o 1 o 1 P~S P~G 2 ~ X X 1 0 0 1 CRC GEi`~f I X 1 0 1 0 ~ 'D

12 Bit Buffer A unidirectional 12 bit hig;rLwa~, Address IIighway enabling the Addirional ~'unctions (B~/WA~ Controller to address the ~uffer.
~he logic on this highway is inverse at the interface.
'l~C to DABCrf A 24 bit unidirectional high~,~ay for Data ~ighway parallel transfer of data from registers in the AFC to locations in the Buffer .
~ or to registers in the D~BCU, the - transfer being under microprogram control. ~ogic on this hi~hway is inverse.
Command Register~ Up to 2~ signals for carrying Commands Ou-cputs ~ from the Oommand Register to -the Data ;~
and Bu~fer Controller. ~
Pre-amble/ - ~or devices in which pre-amble and Post-amble ~ ~ post-amble are generated in the;~FC, these signals must be supplies~to tne ~` 25; ~ DABCU.
Sl~nals Ori inatin~ in the Data and Buffe~ Controller 3Z'~5~L

~eset Wol-d Request A ~i~,;r~tiv~ going pulc,e which rcs-,-ts t'ne Word Requ~st Flabr.
B;eset Word Read~ A nega1,ivc~ ~oing pulsc l~r~lic~i resets th_ Word ~eacly i?lag.
~ransfer Corr~plete A flag ~ ich is rai~ed half' a Sector (~1?) ~ ai'~tor t'ne Sector Count has been decremented -to zero.
Awaiting on Seetor A f`lag 1~hich is set at sorne ins-tant a''t;er (AOS~) the Data and Buf'f'er Controller's Bul,i'er ,mransfer Pointer Counter has been loaded, and which indiea-tes ~kat the controller is ~.
, , read~ to proceed with the t:ranS:-e CRC Result ,mhe output of an all zeros ~etector, connected across the CP~C checker~ A
.:
-~, 15 low signal indicates that the C~C ' ~ ~ :
check has passed.
Reset Mieroprogram mhe neg~ative going pulse whlch rese-ts Queue Réquest~ the mieroprogr~am Queue Request Flag.
In praetice the~flag wlll be~ resc-t b~
O ' the destination eloek.
D~3CU to AFC~ A~24~blt unidirectlonal hlghway for Data~Xig~way ~ parallel transfer of' data frorn~the Buffer or from~reSlsters wlthln~the DAB~U, to~desclnations in the~G, the 2~ transfers being~ under mlcroprogram control~. L~oeic on~this hlghwa~ is true.
rack and~Sec-tor~ A unldlreetlonal hLghway Carrylng mrack 28 Xlghwa~J ~ an~ Seetor lnformatlon~to the~AFC~,mhe ZZ5~

infor.~sLv.tion is ~tv. !.id ~,t,~len '1'.'1{., 'Al~tait:ing on Secbo~' flat, . rai,-flv Logic o~ -t~is highwa~ is t uo.
Status Register ~Jp to 24 sitgnals for sfvtting selfcted _npu-ts bits in the Status ~.e,ist~r.
Read-Write A Read-Wri-te Coinmand Si~Pnal, l,lhiCh T~lhfn Comr.~and low specifies a æhD.
Des-tination Clocks ~'he followinv clock pulses are proviled 'o~J -the microprograrn for parallel transf~rs in the direction DAeCU to ~FC:--(a) One clock pulse for the Com[nand Reglster (b) Ore clock pulse for the Q~C ieg~isteLCv (c) One clock pulse for -the DiatPnostic register(s) ;
nable ,Si~nals (a) ~e fol].owlng enable signals are provided for parallel t~~ansfers in the direction A~C to D~RCU:-One enable signal for Wired~Disc Identit,~J, ~rack &~d Sector.~ ~
One enable signal for~C register sources.
One enable slgnal ~or;the~Dlagnostlc reglster 30urce(s).
One ehable signal for Status Register outputs. -~
(b) ~he following ena'~le signals are 25 ~ provided for paDallel transfers~in tha direction DABCU to A~C:-One enable signal for lnputs to the Comr~and Reglster.
~` 2~ ~wo ena~le signals for inputs to the A~C Register(s).

-- ~ L~

`~ 113ZX:S~L

OnG enabl.e signal ~or inpu-ts to the Diagnos1,ic i~e~-,ister(s).
~xtansion Fi.elds ~ 3 bi.t source co~c- and a 2 'oiu d~istina-tion code is ~,?ro~lidod L'or the A~C source and d.estination ~ields.
l'he various enable sign.als can be used in conjunction wi-th dGcoders to provide oxtensiGn lields in acco:rdance 1~lith Table l.
13 ~lot 06 ~oad Enable ~ microprograrn generatrJd sigina.l~ ~7hic~l : lowers the buf~'ered ~nable Al/Bl si~nals and raises the bufI'ered A2/~2 si.ginal his signal is low when -the slo-t is ~; ; ' anabled.(Note: 'Ghis load is carried ou~
; ;5 ~ ~just after the Sec~or Mark when a WRITE c~cle is in prograss)~.-Co~l-troller O~eration : AB deflned above when the~prooessing system requires -~o ~ operata the disc~in normal moda it ~irst loads the bu~fer :~7ith -~ ~ 20~ a worX item involvlng a transfer~oa~ablllty. ; ~ :
While the~oontrol unlt~ls~not~involved in a -transfer the inspection;:register receivas the successive items work st~in~synchronlsatlon with the oeourranoe ~of sector ma ks and one se~ctor:~ln~advance of the;curren~posltionlng o~^ the 2~ read/wrlt~e heads~of the disc. Whe~ a v~alld worl~ i~tem ls:found a diso transf~ operation ~ inltlated.
.5C Data_'~'ransfers ~r nln the Da~ta and Bu~fer ~ontrollé~
2~ s far ~as the ~uffer and Dsta~Control.'Ler lS concarnod ~ ;

ZZSl ~ ere is onlL~ one basic l~odr oi o-perat;:ion a~d 1;;~!r~ !oli~l diagrallls O:r Figs . 5 to 7 show the steps in-~to:L~fd. The-opeLatior is initia-tecl by the ~u_~er 'i'ran fei Pointer reO-ist~;r Br'P being loaded. rl'his refistrr will be loaded l~ith a 12 'Di, poin-ter in the leas-t significant bi-ts and '1' i~ the rQost si~lli icant bit for a write (a '0' for read). '~he regis-tfir is loaded from the work lis-t when thr addi-tiGnal Eunc-tions controlier's inspec-tion regis-ter detects a valid entr~J in the wor~ list. Steps Sl to S6 inclusive are -then perforrned.
1~ The first location pointed by the buffer trans~er pointer is the first word of the T-ransfer Capability. T,lis is loaded into the Additional ~unctions Controller and the Checkcode verifier. '~he last two words of -the '~rar~sfer Capabilit~J are -then loaded in the following way:-;~ ~ The flrst ~.rord is read I'rom the buffer and loaded in-to the Track and Sector Register '~SR. This word is then read from the register with the Wired Disc Identity and loaded into the Checkcode verifier CC~
; The second word is read from the buffer and loaded intothe Sector Coun-t register~SCR and Cheokcode verifler CCV.
he Transfer word Count TWC is then loaded into the-ransfer word Count~register TWCR. The C1eckcode ~ust be correct for a write to proceed. Steps S7 to S14 are then performed to set up the data a~d bu~fer controller flags and~reglsters ready for the transfer.
~The actual transfer lS controlled by the DlsC Intel'L'aCe ~` Controller by setting the 'Word Read~J' fl~ag l~rR~ in the case of ~;; 2c3~ a read (step SR3j and the 'Wo~d Reques-t' flaO I~RqI~ for a write - ~6 -~ 2Z5~

(st~p ~71). 'Ih~ 'cr ~nd D~tll Co~ltlol~:~?r r~:,po~lds to t,l~
f'lags ;nd perL'orlns the co~respon~ing Da-ta t;ansi'e~: to o, i'roin -the 3ata l~.^ansfer ~ ea :in the Bu~~'e~ via the intelnal '~uL''e:r hig~.a~J ~ 7. ~ig~ 6 shows -the operations perf'c~-:rned for a read operation whereas ~ig. r~ shows the operations perforislf3d fo;^ a write operation.
~he Buf~'er ~rarlsf'er Polnter is inc~emented a~,,er eVe~J
transfer to or from the Buffer (s-teps SR4 and C'1~J4,). I'he '~ ~ransf'er word count ~IC is decremented af'ter every l~ord transf'er~3d ;
0 to or irom the disc (steps SR4 and S~J4). On a Read whf3rl i-t reackes zero Step SR12 the -transfer is terminated. Orl a Write when i~ reaches zero (step Sl~79) the dis~ is zero i'illed (b~J step SW10) until the end of the r~ransfe~ capabilit~ siY,e.
'he Sector Count is decremented (ste~p SRll or SWll) af-ter eVe~J
15 ~ complete sector. When lt reaohes zero step Sl.~712 the transfer lS terminated.
.: .
he '~rack and Sector Register '~R, is incremented '~
after ever~ comple-te sector (ste-Qs SRll and~SWll). The whole word is used in the Cyclic Redurldancy Checkcode (C.R.C.) '~ '~
~20~ generation. r~he ~rack field is~used~as the ~rack Address~
register for the~disc and is incremented~af-ter the las-t~
` sector~of a track so that a transfer can over-run tracks.
The C.R.C.~Generator is loaded in parallel with~the wired Disc ldentity~rac~ and Sector whenever the Disc 25 ~;~ Intarface Controller requests the transfer ~ia the Addltional ~unctlons Controlle~r'~s~flag tG ~the queu3 in the Buffer and Data controlle~ or~à write the data is then passed seriall~
20 ~ nto the~generator as~lt~ls~beLng written on -to t'ne disc,~to zs~

rl~odii.`y theA ox:l.ginally loadcd ~,at-terr~ he ~elLairldsr i ~h.eQ
1~lritt(3n seriall~ on-to -tke disc d.ixectl~ a.~-te-.c t~Le d.al;a :i.n a secl;or~ ~or a read, -the da-ta and written cr.~c is pai~,secl serially i.nto the gene:rc~.-tor as i-t is baing read frorQ the CL1SC. ~he rernainder at the end of the sectox is checked an~:
should be zero for a successful -trans-:er.
Upon com.pletion of' a sector of a read ox write op,eratior the micro-program returns to s-lep ~1 and then enters a sub-.: rou-tine at ~ ~ig. 5 which causes the various .regi.sters and ~ 10 flags to be reloaded to continue t~e tra:nsfer operation ior:j the next sector ~ia S9 ~ig. 5. Upon completion of a reacL or write opera-tion the micro-program exits at A ~ig. 5 to enter a disc sur~ace routining o~eration.
~he Queue '~he Queue:cyclically allocates internal high~,~Jay trans ers as demands arise to four users. (1) ~he Additional ~unc-t:ions Controllex and the Disc Inte~rfaoe ontroller.~ (2) ~he BuLf`er . and Data Controller. (3) ~he Refresh:Generator and (4) ~he. Processi~ng SJstem 20 ~ ~ ~ The~Refresh~Generator causes~the~Buffer refresh oyole to be lnltlated when required.~
~ ach:controIler:has its own~microprogram,:thre~ of !" ~ wnich have only one ~or two slots and are modified by exterAal co-ntrols, (e~g.~b`y the adclress the Processor asks to access).
Z5 ~ ~he Buffer~and Data ~ontroller~has many~more slots n order -to be able to oontrol tha word transfers on the internal highway îrom t-he t-ime t.he~Buffer ~ransfér Pointex is 23 loaded untll the~end of a Dlsc data;-transfer. ;~

~: : : ., ~3Z~
, Eclch slot eithe-r direc~ speciLie,~ a sGuJce a.nd desl:ination for t-he i.nte~rlal tra~sfcr or sl~eci-ies an external ~ield (e~. Processor's address) ,~llrlich decodes into a source~ or des-tina-tion. Other func-tions such as ''~ pe or C~cle' (Buffer Read~lrite etc.) ard '~ese-t ~'ag' are ge~erated in si-ilar ~as~ions.

.
,.

: : , . , : - ~ 39 :

Claims (19)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. A data handling equipment, for use with a sequential access digital data storage device having information stored in tracks each track having an equal number of n sectors, which equipment includes a direct access store comprising (i) n contiguous storage locations formed into a work list, there being one location in the work list for each sector of a track of the digital data storage device each location storing a work item which includes a direct access store address outside the work list or an idle code, and (ii) a data buffer for the storage of transfer data storage areas each of which is dynamically allocated for the storage of the information involved in a data transfer, each data storage area comprising a transfer descriptor, a transfer work count and a defined storage area specific to the number of data words into which or from which the data words of the required digital data storage device data transfer are to be written or read and the equipment includes an inspection register which interrogates the work items in sequence in synchronism with but one sector in advance of the positioning of the read/write heads of the sequential access digital data storage device and the equipment is arranged when a work item is detected by the interrogation register to use the direct access store address in that work item to gain access to the transfer data storage area allocated to the data transfer which is to commence at the start of the next sector to pass the read/write heads of the sequential access digital data storage device and the equipment includes means for reading the transfer descriptor (i) to select the sequential access storage-device track to be used for the transfer and (ii) condition a sector count register with the number of sectors to be involved in the transfer which sector count register is arranged to be decremented for each sector involved in the transfer as a sector passes the read/
write head and the equipment includes means for terminating the transfer when the contents of the sector count register reaches zero by overwriting the corresponding work list entry with the idle codes.

2. A data handling equipment as claimed in claim 1 in which a total word count is stored in the next location after the transfer descriptor and each sector on the digital data storage device comprises a plurality of words and the equipment includes a transfer word count register into which the total word count is read at the start of a data transfer and which is decremented after every word transferred to or from the digital data storage device and the equipment includes means to terminate a read transfer and means to cause the digital data storage device to write zero fill data in the rest of a sector on a write transfer when the contents of the transfer word count register equals zero.

3. A data handling equipment as claimed in claim 2 in which the equipment includes a buffer transfer pointer register arranged, when no digital data storage device transfer is in progress, to receive the contents of an entry in the work list when the inspection register detects that the entry contains a work item and the equipment is arranged to automatically institute the operations necessary to perform a transfer operation when the buffer transfer pointer register is filled.

4. A data handling equipment as claimed in claim 1, 2 or 3 in which each work item also includes a read/write operation indicating bit.

5. A data handling equipment as claimed in claims 1, 2 or 3 in which the transfer descriptor includes a check code which is used by the equipment to check the validity of the rest of the transfer descriptor.

6. A data processing system incorporating a sequential access digital data storage device and including a data handling equip-ment as claimed in claim 1.

7. A data processing system as claimed in claim 6 and includ-ing a plurality of peripheral equipments including a sequential access digital data storage device, a plurality of memory modules and a plurality of processor modules and in which each peripheral equipment includes an individual access unit and each processor module is provided with an individual data communication path pro-viding processor module access to all access units and each access unit includes an identity address recognition means and a plurality of processor module accessible registers and an accessible register selection means, and in which processor module access to a peri-pheral equipment is performed by extending an address on the pro-cessor module's data communication path which address comprises at least two fields, (a) one field defining the peripheral equip-ment required and being active upon the identity address recogni-tion means of the appropriate access unit and (b) the other field defining the accessible register in the appropriate access unit and being active in the register selection means therein.

8. A data processing system as claimed in claim 7 and in which the accessible registers include a first register which provides storage for peripheral equipment control information and into which processor module generated information is written.

9. A data processing system as claimed in claim 7 or 8 and in which the said accessible registers include a second register which provides storage for peripheral equipment status informa-tion indicative of the current state of the peripheral equipment and from which processor module requested information is read.

10. A data processing system as claimed in claim 7 and in which the accessible registers include a third register which provide storage for data which is to be passed to the peripheral equipment and into which processor module generated information is written.

11. A data processing system as claimed in claim 10 and in which the accessible registers include a fourth register which provides storage for information which is to be extracted from the peripheral equipment and from which processor module requested information is read.

12. A data processing system as claimed in claim 11 in which the access unit for the sequential access digital data storage device includes a forecast register arranged to store the contents of the next following a location in the direct access store which was involved in a data transfer.

13. A data processing system as claimed in claims 6, 7 or 8 and in which any of the locations in the direct access store are selectable by the accessible register selection means.

14. A data processing system as claimed in claim 1, and which for each transfer involving the sequential access digital data storage device are of the processing modules inserts a work item in the work list of the data handling equipment at an address indicative of the sector from which the transfer is to start.

15. A data processing system as claimed in claim 14 in which the data handling equipment comprises a storage device interface controller and additional functions controller and a direct access store controller interconnected by an internal data highway.

16. A data processing system as claimed in claim 15 in which the additional functions controller includes the first register, the second register and the inspection register.

17. A data processing system as claimed in claim 16 in which the direct access store controller includes the third register and the fourth register, the buffer transfer pointer register, the sector count register, the transfer word count register and the registers for use with the transfer description together with means for controlling internal data handling equipment transfers using the internal data highway.

18. A data processing system as claimed in claim 17 in which the direct access store controller includes a queue processor which cyclically allocates demands from the controllers for access to the internal data highway.

19. A data processing system as claimed in claim 18 in which each of the controllers includes a micro-processor.