CA1130459A - Mailing system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A system for mailing articles includes an integrated circuit interface between a scale deflection transducer, a processor and an external memory. The interface includes a multifunction shift re-gister array which is adapted to receive count data indicative of the weight of an article. Communication between the shift register array, the processor and the memory is such that the shift registers are selectively utilized for memory address and data transfer without the necessity of clearing prior operands.

Description

-1~3(~459 This is a division of copending Canadian Application Serial Number 288,514.
The present invention rela-tes to an integrated circuit interfa oe between a transducer, a microprocessor and an external memory adapted for use in a weight measuring environ~ent such as that dis-closed in the following Patents, all cwned by the assignee of the present invention: Weighing with ~bire OptoelectrDnlc Transducer, Canadian Patent 1,053,270 gran-ted February 24, 1979, Leaf Spring Weighing Scale with Op-tical Detector, Canadian Patent 1,071,661 granted February 12, 1980, and Zero Load Adjustment Apparatus for Spring Weighing Scale, U.S. Patent 4,047,586 issued Septe~ber 13, 1977.

BACKGRDUND OF THE INVENTION
1. Field of the Invention This invention relates generally to digital circuits for prxessing signals and more specifically to circuits for providing a multiple function interfaoe to a central prooessing unit.

2. Brief Description of the Prior Art.
Various devices have been heretofore proposed for the purpose of determining the position of a vable element by pro oessing the pulse signal outputs of an electro-optical transducer for applications such as weight measuring environments. Examples of such prior devioe s are illustrated in United States Letters Patent No. 2,886,717 and United States Letters Patent No. 3,487,399.
Earlier signal processing and counting systems employed RC
networks which were time and temperature dependent and did not provide well defined pulse widths. Additionally, csm/ ~ ~

113~4~9 -these systems were highly susceptible to both internal and external noise which resulted in generally po~r reliability.
'~hile the signal prooessing systems aco~rding to the prior art provided reliable signal processing in a wei~ht measuring environ~ent and were adapted to optically define true scale zero disp1acement in an unambiguous manner, various drawbacks have been enoountered in transmitting counter data to microprocessing means for processing. ~he microprocessor was required to perform numerous calculations in determining the article weight from the counter data including the averaging of counter readings and unit conversion from displacement counts to weight units. Further, the microprocessor performed computations to determine postage based upon weight and article destination. Traditionally, such microprocessors utilized separate registers for addressing and data lines which provided inherent limitations in input/output capabilities. With limited register spaoe , the microprooe ssor was required to rapidly unload oounter data, because new counter data was entering. Further, there was a hazard that aount data might be unloaded into the mieropro oe ssor during propagation of a count.

SUMM~RY OF THE INVENTICN
In oompendium, the invention contemplates a mailing system ineluding an optical scale transducer which generates cyclie signal pairs as a result of tare displaoe ment; the signal pairs esm~ ~

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are shapcd to provide digital signals, edge discriminated, and fed¦
to an up~down counter array. A microprocessor interface includes a plurality of multifunction shift registers which receive the out~
puts of the counter stage.s for input into the microprocessor. In order to prevent a counter array reading from being taken during propagation of a count, the counter input signals are monitored to control a time delay coordinated with the count propagation time.
Shift register data can be transmitted to the microproces-sor in either parallel or serial modes,and the shift registers are utilized not only as a link between the counter and the processor, but further as memory address registers and temporary data storage registers.
Implementation of the shift registers is such that new data may be shifted in and stored data shifted out for utilization dur-ing the same clock pulses; further, data may be parallel loaded in to the shift registers without clearing prior data.
From the above summary, it can be appreciated that it is a~
.- object of the present invention to provide a mailing system of the general character described which is not subject to the disadvantaqes aforementioned.
It is a further object of the present invention to provide a mailing system of the general character described which incl-ides' ; a spring scale having an electro-optical transducer, processing cir-cuits for providing weight indicative count signals and a multifunc-; tion register link between the count signals and a microprocessor.
;~ ~ A further object of the present invention is to provide a ;a - lmailing system of the general character described having an in-, ; tegrated circuit interface between an electro-optical scale trans-~ducer and ~ mlcr rocess~r.

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~3S3459 Therefore, in accordance with the present invention there is provided an interface for providing selective information transfer channels between a processing unit, a memory and a peripheral, the interface comprising register means for storing and transferring information, the register means including means for receiving information in a parallel mode and means for transferring information in a parallel mode, the parallel mode transfer means being adapted to address the memory and the parallel receiving means being adapted to load memory information into the register means, the processing unit including means for simultaneous serial loading of address information into the register means and serial unloading of memory information from the register means, the register means being thereby adapted to effect reduced cycle time.

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11~0459 with these ends in view, the invention finds embodiment in certain combinations of elements, arrangements of parts and series of steps by which the objects aforementioned and certain other objects arc hereinafter attained, all as fully described with reference to the accompanying drawings and the scope of wh;.ch is more particularly pointed out and indicated in the appended claims.

BRIEF DESCRIPTION OF THE DR~WI~GS

In the accompanying drawings in which is shown one of the various possible exemplary embodiments of the invention:
FIG. 1 is a schematized block diagram of a mailing sys-i tem constructed in accordance with and embodying the invention ¦ and illustrating a scale transducer interconnected to an inteqra~--ed circuit interface;
¦ FIG. 2 is a further schematized block diagram of the ¦ mailing system illustrating the interaction between the inter-¦ face, a central processing unit, an external memory and thc scalc transducer:
FIG. 3 is a waveform timing diagram of a transducer wave shaping and initial interface circuits of the system:
. FIG. 4 is a schematic diagram illustrating a photocell . array of an electro-optical transducer and a wave shaping cir-cuit which provides pulse waveforms:

~3V459 FIG. 5 is a schematic diagram of initial stages of the interface including edge discriminating circuits which provide multiple counts from the pulse waveforms and further showing a combination logic which decodes direction determinative informa-tion to provide count incrementing and decrementing signals for a counter array; and FIG. 6 is a schematic diagram of subsequent stages of thc interface including the counter array interconnected to multi-function shift registers for loading count data into a proccssor as well as for memory addressing and for temporary data storagc.

DESCRIPTION OF T~E PREFERRED EMBODIMENT
The present invention relates to a mailing system wllich determines the weight of an article by processing a pair of electro-optically generated waveforms which are a function of the displacement of a spring scale. The signals are counted, with the counter signals being fed to a processor for averaging and computation of the load weight. The processor further computes the postage required for the article.
Included in the mailing system are wave shaping circuits j for each waveform, pulse edge discriminating circuits and a combi nation logic for determining the direction of count, i.e. decreas ing or increasing.
~ n integrated circuit interface is provided for receiv-ing and processing the shaped waveform signals. The interface includes an up/down counter array, the outputs of which are fed to a microprocessor through a plurality of multifunction shift _7_ regi.sters with the shift registers serving as memory registers il and as intermcdiate storage registers. Furthcr~ the multifunc-tion shift registers are adapted to be loaded without separatcly clearing prior data.
¦ Referring now in detail to the drawings, the reference ¦ numeral 10 (FIG. 2) denotes generally a mailing system con-! structed in accordance with and embodying the invention Thc ll system 10 is adapted to process electro-optically transduced ¦I signals generated by a transducer 12 upon which a periodic , fringe pattern 14 is projected. The fringe pattern 14 may comprise a moire pattern optically coupled to a tare of a spring scale 16 such that the fringe pattern moves as an optically amplified function of scale tare displacement as more ful~y set forth;in. the oregoi~g patents.~ It , should be appreciated, however, that the present invention is ,¦ well adapted for the processing of cyclic signals generated in any counting environment.
The transducer 12 comprises four phototransistors l8, 20, 22 and 24, all having similar operating characteristics.
ij From an observation of FIG. 4,it will be appreciated that the photQ
il transistor 18 is coupLed between a positive potential and the jj collector electrode of the transistor 24. Thus, the transistors 18 and 20 provide a bias for the phototransistors 22,24, respcc-tively, in lieu of conventional biasing resistors.

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The biasing or compensating phototransistors 18, 20 in-crease the range of output voltage for the phototransistors 22, 24 ~and provide compensation for changes in source radiation, atmospher-ic conditions, temperature changes, etc., which affect the biasing and biased phototransistors simultaneously. Thus, a dynamic bias is provided ~hich maintains the operating characteristics of the phototransistors 22, 24 in a manner similar to that disclosed in ! u. s. Letters Patent No. 3,913,095 issued october 14, 1975 to Dlugos and assigned to the assignee of the present invention.
Movement of the fringe pattern 14 across the phototransis-tor array provides substantially sinusoidal cyclic waveform ouL-puts designated waveform a and waveform b in FIG. 3 from the I collectors of the transistors 22, 24, respectively. Fach of the i!analog waveforms a and b are fed to a wave shaping circuit 2.
comprising a linear voltage comparator Schmitt trigger inverter 26, 28, respectively, to generate a pair of pulse waveforms designated PCl and PC2, ~espectively.
¦ In accordance with the invention, the pulse waveforms PCl ! and PC2 are further processed to provide an indication of the weight of an article placed on the scale 16 through the utilization of an ¦¦integrated circuit interface 33 between the wave shaping circuit 25, a microprocessor 35 an~ anexternalmemory,e.g. a PROM 37.
With reference to FIG. 5 wherein initial circuits of the interface are depicted, it will be seen that a pair of inverters 30, 31 provide inverse waveforms PCl and PC2, respectively, from the signals PCl and PC2.

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The waveforms PCl and PC2 are edge discriminated at a pair of edge discriminators 32 and 34, respec-tively, to provide a pulse waveform PCl~ (indicating a positive going edge of PCl) and a waveform PCl~ (indicatiny a negative going edge of PCl).
Similarly, the edge discriminator 34 provides a waveform PC2 and a waveform PC2~ indicating positive and negative going edges of the waveform PC2. The edge discriminators 32, 34 each comprise a pair of fully clocked D-Type edge-triggered flip-flops operating as shift registers and providing a multiplieation by four, i.e. four pulses for each cycle of the fringe pattern.
Deeoding of the flip-flop outputs by a pair of AND gates pro-vides the transition waveforms PCl~, PCl~, PC2~, and PC2~.

The digital waveforms thus generated are deeoded at a eombination logie 36 which comprises a pair of expandible 4 wide 2 input AND OR invert gates 38, 40, respectively. The eombination logic 36 decodes for count direction information to provide inverse pulse waveform signals INC and DEC indica-tive of increasing and decreasing scale tare displacement, respectively.

With reference now to the waveform timing diagram of FIG. 3, the waveforms a and b are shown progressing first through an up count and then through a down count. The cor-responding digital signals PCl and PC2, the edge discriminated signals PCl~, PCl~, PC2~, and PC2~, and the signals INC and DEC
are also depicted. It will be appreciated that the eombination logie 36 generates the displaeement direction decoded signals INC and DEC in aceordance with the following equations:

-(PCl) (PC2~) + (PC~) (PCl~) + (~Cl)~(PC2~) + (PC2) (PCl~

(PCl)(PC2~) + (PC2)(PCl~) + (PCl)(PC2~) + (PC2)(PCl~) = DEC

~- --10-~, ' 11;~045i9 . . '' In accordance with the invention, the increasing and de-creasing waveforms INC and DEC are provided for processing as inputs to the count up and count down inputs of the first stage of an up/down counter array 42. The counter array 42 is exemplary ¦of many possible variations and has been designed for utiliæation ¦in conjunction with the operating parameters of the leaf spring scale 16 utilizina a moire fringe pattern optical detector and ¦the transducer 12. In such application the spring constant and loptical moire displacement amplification calibration provide a ¦least significant bit indicative of a scale displacement procluced by a specified minimum weight increment. The processing system of the present invention, however, is adapted for application in numerous counting environments, and decoding for weight indicative ¦information is by way of example only.
¦ The counter 42 includes four counter stages 44, 46, 48, ¦and 50, each comprising a four bit binary up/down counter. The ¦counters are cascaded by feeding the borrow and carry outputs to ¦the count down and count up inputs respectively of succeeding ¦counters in the array.
¦ The bit output of each counter stage 44, 46, 48 and 50 ¦is broadside loaded through respective multiplexers into correspond-¦ing four bit nontransparent parallel access shift registers 52, 154, 56 and 58, respectively.
¦ The shift registers 52, 54, 56 and 58 sample and hold the counter bit outputs upon a LOAD REGISTER signal from the micro-processor 35. In order to insure that the shift registers will ¦

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not be loaded with counter bit data during the propagation of a count through the counter array 42, a data ready circuit 60 provides a DATA READY signal which permits loading of the shift registers only after count propagation has been completed.
The data ready circuit 60 includes a NAND gate 62 ~hich samples both the INC and DEC signals. When incoming INC and DEC
pulses enter the counter array 42, a series of low signal pulses is provided as an input to the gate 62 which gate provides corresponding high output signals. only when there is an absense of fringe pattern movement with both the INC and DEC signals ¦high will there be a low output from the gate 62. The high o~t-¦put signal of the NAND gate 62 is utilized to reset a decade ¦counter 64 (7490) having a cycle period at least as grea~ as the ¦time required for propagation of counts through the entire counter ¦array 42.
¦ A high counter reset signal from the gate 62 provides a ¦low DATA READY output signal from the counter 64. The low DATA
READY output signal is inverted and fed to a NAND gate 66 a~ong with a CLOCK signal to provide pulse signals for driving the counter 64. A high DATA READY signal will be provided only after a specified time interval after an absense of fringe pattern move-ment which interval is synchronized with count propagation time of the INC and DEC signals through the counter array 4Z.
The high DATA READY signal is provided at a further NAND
gate 68 along with a LOAD REGISTER control signal from the micro-processor 35 to provide a low parallel load signal to the shift 113~)459 ~registers 52, 54, 56 and 58 which will then sample and hold the counter bit outputs of the various counter stages 44, 46, 48 and 50. _ It should be appreciated that unless the INC and DEC
signals are at rest and therefore the counter array is not receiv1 ing any further incoming pulses, the counter 64 of the DATA READYj circuit 60 is constantly being reset and the DATA READY signal wi l remain low for the propagation to thereby prevent loading of the shift registers with erroneous data.
The direction of scalc tare displacement ls readily exam-ined through the utilization of a latch 70 comprising a JK flip flop which receives the signals INC and DEC. The latch output is further utilized to provide a condition on clearing the counte array 42. Thus, when the scale tare is oscillating about zero displacement, a SCALE CLEAR request signal, clock synchronized at a D flip flop 72 is provided at a NAND gate 74 along with the Q output of the latch 70 to provide a synchronous COUNTER CLEAR
signal assuring that the counters will only clear in the positive edge of zero displacement.
As mentioned heretofore, the mailing system of the present invention is adapted to compute the postage required for the ar-ticle to be weighed on the scale 16. Among the factors in com-puting postage for articles are current postage rate class schedu] e data, zone destination data and conversion data to provide zone destination wherein only a zip code is known. External input to the microprocessor 35 for destination input is provided by a keyboard 76 and an associated input/output interface 78.

~ 0459 In an exemplary application of the systcm 10, counter datc sampling is shifted into the microprocessor 35 and the parallel outputs from the shift registers are utilized as memory address lines for the postage rate PROM 37. In coordination with keyboarc addressing data, the counter bit data is parallel loaded into the shift registers and upon appropriate signal of the microprocessor 35, the information is shifted from the shift registers into the microprocessor. The microprocessor 35 receives the counter bit information four or eight bits at a time and after all 16 bits representing a complete count sample have been received, the sample is stored in preparation for averaging of a series of count samples.
Prior to or after counter sampling is accomplished and appropriate computations have been performed to provide an average weight determination, the microprocessor receives manual input keyboard information relating to the class of transporation and destination.
Only the initial three registers 52, 54 and 56 are pro-vided with addressing ability in the system application i]lustrat-ed; however more registers could be added, if required. Thus, a keyboard generated signal comprising two twelve bit words may be shifted in two stages into the first three shift registers 52, 54 and 5S and will be available for memory addressing. As-suming indirect addressing of tho rate PROM 37, the first twelve bits of the keyboard signal are serial loaded into the shift reg-isters to locate the first segment of the indirect address in the .
rate PRO~ 37 via a plurality of addressing lines A-0 through A-ll.

-1~-: 113V~59 .
An initial eight biL segment of the address data obtained from tlle PROM 37 is utilized as an input to the multifunction shift registers 56, 58 on a plurality of data lines D-O through D-7.
In order to receive the indirect address segment at the shift register 56, 58 the microprocessor 35 first provides an appropriate low SELECT or steering signal to a pair of multiplexers 82, 84, each selectively interconnecting either the stages 48, 50 of the counter array or the data lines D-0 through D-3 and D-4 throuclh D-7, respectively, with the associated shift register 56, 58 for parallel loading at a low SEI,ECT signal.
In order to provide greater versatility for the interface ,, 33, the counter stages 44 and 46 are similarly interconnected to ,~their respective shift registers 52, 54 via corresponding multi-plexers 78 and 80. Separate SELECT signals are provided for the multiplexer pair 78, 80 and the multiplexer pair 82, 84.
In sequence, the second twelve bit portion of the keyboard 'Irate address signal is shifted into the shift register array. It should be appreciated that during the twelve clock pulses within which the second portion of the keyboard address is shifted in, the lleight bits of PROM 37 address data are shifted out to the micro-¦Iprocessor 35 along with four bits of the prior keyboard address (previously in the register 54) which is discarded.
The second portion of the keyboard signal becomes avail-able on the address lines,and eight bits of corresponding address ¦data from the PROM 37 become available on the data lines D-0 through D-7. In the manner previously described with respcct to the prior address data, such data is parallel loaded to the shift registers 56, 58 via the multiplexers 82, 84.

. li3045i9 Subsequently, the final portion of the indirect acldressdata is shiftecl from the shift registers 56,58 into the processor in eight clock pulses to thereby provide the processor with the full 16 bits of address necessary to read the rate table. with respect to such 16 bit address, the first four bits are for refer-ence indicating, for examp]e,the size of the table,while the re-maining 12 bits comprise the table address.
A keyboard generat~d zone destination signal provides a four bit word for storage in a zone register of the processor , 35. If the operator is aware of the destination zip code hut not the zone, a keyboard generated 12 bit zip direct address siynal is utilized to address a zip to zone PROM 86 via the addressinq lines A-0 through A-ll. In a manner similar to that heretofore described with reference to the keyboard rate address signa~s, tl-c ,zip address signal is shifted into the registers 52, 54 and r,G
il to address the PROM 86. The corresponding 4 bit PROM zone data is received through the lines D-0 through D-3 and loaded into thc shift register 58 via the multiplexer 84. The microprocessor ~5 then receives the zone data by shifting it from the registcr 5~.
ith the zone data and rate table address data received in the ¦microprocessor, the microprocessor may proceed to determine the required postage.
Initially, the twelve bit table address is shifted from the microprocessor to the shift registers 52, 54, 56 and utilized Ito address the PROM 37. Computation of postage requires six data ¦words, each comprising eight bits. Two data words are necessary to determine the intercept or equation starting value; two data words are required to determine the equation slope or price in-crement per weight unit; and two data words are required to 113V4~9 determine the equation range capacity or maximum weight for thepostage class.
After the table address data has been utilized to address the PROM via the addressing lines A-O through A-ll, a first eight bit corresponding data word of the PROM 37 becomes available on the data linesD-0 through D-7 of the interface. An appropriatc SELECT signal generated by the microprocessor results in the parallel loading of the data word into the shift registers 56, 58.
It should be appreciated that simultaneously with the loading o~
the data word, the portion of the prior address in the registcr 56 is destroyed.
To obtain the next sequential rate data word, ti-c pro-cessor is programmed to increment the prior address hy one and sequentially serial load the shift registers 52, 54, 56 to provide such address on the addressing lines A-O through A-ll. In ac-cordance with the invention, the multifunction shift registers 52, 54, 56 and 58 provide a savings in handling time by permit-ting the microprocessor to simultaneously receive the eight bit data word stored in the registers 56 and 58, while loading in the next sequential address. Thus, within the twelve clock pulses required to shift in the next sequential address, the eight bit data word;stored in registers 56,58 are pulled into the microprocessor along with four bits of the prior address previous-ly held in the register 54. It should be appreciated that the portion of the prior address is no longer utilized by the pFocessor- -17-~ 1130459 With the next sequential address on the data lines A-0 through A-ll the corresponding eight bit rate data word will be available on the data lines D-0 through D-7 and in a manner iden-tical to that heretofore described with respect to tho prior data word, it is parallel loaded into th~ shift registers 56, 58 and subsequently pulled into the microprocessor simultaneously with the loading of the next sequential address.
After the initial siX data words are received in the microprocessor 35, the processor is programmed to determine whether the information pulled is appropriate for computing thc requisite postage for the destination zone. If the information is not appropriate, the microprocessor continues incrementing the table address to the PROM 37 until the appropriate data words have been obtained for postage computation.
¦ It should be appreciated that the versatility of the intcr--¦face 33 is further enhanced through the implementation of the ¦multiplexers 78 and 80 which increase the parallel loading capacity ¦of the shift register array. Additionally~ it should be noted ¦that the data lines D-0 through D-15 could be utilized as input lines for any peripheral device associated with the system, for example photodetectors monitoring other stages of the system.
Further, the multiplexers could be utilized as a selective inter-connection between the shift registers and any peripheral device rather than the counter stages illustrated.
The microprocessor implementation described is only one example of many possible variations possible in mailing systems.
In addition to the exemplary embodiment herein described, further -lB-11304~9 embodiments of the invention include variations such as utilization of the parallel output lines A-0 through A-ll for unloading counter data. It should be understood that the invention may encompass implementation of the multifunction shift registers as an element of an interface operatively interconnecting any microprocessor, an external memory and one or more peripheral devices.
Thus, it will be seen that there is provided a mailing system which achieves the various objects of the present invention and which is well suited to meet the eonditions of praetieal use.
As various ehanges might be made in the system as above set forth, it is to be understood that all matters herein deseribed or shown in the aeeompanying drawings are to be interpreted as illustrative and not in a limiting sense.
Certain aspects of the foregoing description are also diselosed and elaimed in Applieantls eopending applieation Serial Number 288,514 filed Oetober 12, 1977.

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Claims (5)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An interface for providing selective information transfer channels between a processing unit, a memory and a peripheral, the interface comprising register means for storing and transferring information, the register means including means for receiving information in a parallel mode and means for transferring information in a parallel mode, the parallel mode transfer means being adapted to address the memory and the parallel receiving means being adapted to load memory information into the register means, the processing unit-including means for simultaneous serial loading of address information into the register means and serial unloading of memory information from the register means, the register means being thereby adapted to effect reduced cycle time.

2. An interface for providing selective information transfer channels between a processing unit, a memory and a peripheral device constructed in accordance with claim 1 wherein the parallel load receiving means further includes means adapted to selectively parallel load either the memory information or peripheral device information into the register means.

3. An interface constructed in accordance with claim 2 wherein the selective loading means comprises multiplexing means.

4. An interface constructed in accordance with claim 2 wherein the peripheral device comprises a transducer.

5. An interface constructed in accordance with claim 4 wherein the transducer is operatively coupled to a counting means and the peripheral device information comprises counter information.