CA1130003A - Mailing system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE

A system for mailing articles includes an integrated circuit interface between a scale deflection transducer, a processor and an external memory. The interface includes a multifunction shift re-gister array which is adapted to receive count data indicative of the weight of an article. Communication between the shift register array, the processor and the memory is such that the shift registers are selectively utilized for memory address and data transfer without the necessity of clearing prior operands.

Description

113~003 This is a division of copenaing Canadian Application Serial Number 288,514.
The present invention relates to an integrated circuit .~ .
interface between a transducer, a micropro oe ssor and an external memory adapted for use in a weight measuring environment such as that dis-closed in the following Patents, all owned by the assignee of the present invention: Weighing with Mbire Optoe lectronic Transducer, Canadian Patent 1,OS3,270 granted February 24, 1979, Leaf Spring WeighiDg Scale with Optical Detector, Canadian Patent 1,071,661 granted February 12, 1980, and Zero Load Adjustment Apparatus for Spring ..
Weighing Scale, U.S. Patent 4,047,586 issued Septe~ber 13, 1977.

B~CKG~DU~D OF THE IN~E~TrCN

1. Field of the Invention - , . . .This inventian relates generally to digital circuits for pro oe ssing signals and mDre specifically to circuits for providing a ~wltiple function interfaoe to a central proæssing unit.

2. Brief Cescription of the Prior Art.
Varioùs devioe s have been heretofore prop ed for the purpDse of determining the position of a mnvable ele~ent by pro oe ssing the pulse signal outputs of an electroroptical transducer for applications such as weight measuring enVirQnmentS. Exa~ples of such prior devioes are illustrated iD Uhited States Letters Patent No. 2,886,717 and Uhited States Letters Patent No. 3,487,399.
E ælier signal processing and counting systems employed R~
networks which were time and temperature dependent and did not provide well defined pulse widths. Additionally, , .

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'~hile the signal prooessing systems aco~rding to the prior art provided reliable signal processing in a wei~ht measuring environment and were adapted to optically define true scale zero disp1acement in an una~biguous manner, various drawbacks have been enoountered in transmitting counter data to microprDcessing means for proressing. The microprocessor was required to perform nu~erDus calculations in detenmining the article weight from the oounter data including the averaging of counter readings and unit oonversion fr~n displa oe ment oounts to weight units. Further, the micrDprocessor perfor~ed oomputations to determine postage based upon weight and article destination. Traditionally, such microprocessors utilized separate registers for addressing and data lines which proviaed inherent limitations in input/output capabilities. With limited register space, the microprocessor was required to rapidly unload oounter data, because new counter data was entering. Further, there was a hazard that o~u~t data might be unloaded into the nicropro oe ssor during propagation of a count.

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~ SUMM~RX OF THE INVENlqoN
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In oompendium, the invention contemplates a mailing system including an optical scale transducer which generates cyclic signal pairs as a result of tare aisplaoement; the signal pairs ' ~ : .
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¦ are shaped to provide digital signals, edge discriminated, and fed¦
¦ to an up/down counter array. A microprocessor interface includes ¦ a plurality of multifunction shift registers which receive the out~
¦ puts of the counter stages for input into the microprocessor. In ¦ order to prevent a counter array reading from being taken during ¦ propagation of a count, the counter input signals are monitored to ¦ control a time delay coordinated with the count propagation time.
Shift register data can be transmitted to the microproces-' I sor in either parallel or serial modes,and the shift registers are, ¦utilized not only as a link between the counter and the processor, ~but further as memory address registers and temporary data storage ¦registers.
¦ Implementation of the shift registers is such that new data . ;ma~y~be s~if~ed in and stored data shifted out for utilization dur-ing the same clock pulses; further, data may be parallel loaded in~
to the shift register~ without clearing prior data.
From the above summary, it can be appreciated that it is an ^~
object of the present invention to provide a mailing system of the~
general character described which i9 not subject to the disadvantages laforementioned.
It is a further object of the present invention to provide a mailing ~y~tem of the general character described which incl~ides a spring ~cale having an eleatro-optical transducer, processing ci~-cuits for providing weight indicatlve count signals and a multifund-.tion register link between the count signals and a microprocessor.;
A further object of the present invention is to provide a ¦mailing ~ystem of the general character described having an in-~t ~ i' `" r' tograted circuit interface between an electro-optical scale trans-~ jducer aAd a F 4 ¦ 1 .. .. ............. ..

113~

Therefore, in accordance with the present invention there is provided an interface for providing information transfer channels between a transducer generating cyclic signals and a processing unit, the interface including counter means and means operatively interconnecting the transducer and the counter means, the interface further including register means adapted to receive counter information and control means adapted to prevent the transfer of counter information to the register means during propagation of a count through the .
.10 counter means, the control means comprising timing means coordlnated with count propagation time of the counter means and means monitoring the cyclic signals, the monitoring means being adapted to actuaté the tlming means.

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With these ends in view, the invention finds embodiment in certain combinations of elements, arrangeme11ts of parts and series of steps by which the objects aforementioned and certain other objects are hereinafter attalned, all as fully described with reference to the accompanying drawings and the scope of which is more particularly pointed out and indicated in the appended ~ claimz.

.~ 1 BRIEF DESCRIPTIO~ OF THE DRAWI~GS
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~.~ ¦ In the accompanying drawings in which is shown one of : ¦ the various possible exemplary embodiments of the invention:

.FIG. l is a schematized block diagram of a mailing syci- :

: ~ tem~constructed in accordance:with and embodying the invention '~ ¦ and illustrating a soale transducer interconnected to an inte~rat- -~ :

ed circuit interface:

FIG.~ 2~1S a fu~r~ther schematized block diagram of the ¦~ mailing system illustrating the interaction between the inter-:face,;a ceztra1;~procezs1ng unit, an external memory and thc scale ¦:~transducer~

s ~~ FIG. 3 is~a waveform timing~diagram oLi a transducer w~ve ~shaping and initial~interface circuits of the 9y9tem7 FIG. 4 is a 9chematic dia~gram illustrating a photocell :array of an clectro-opt1ca1 tranzducer and a wave zhapina cir-: cuit which provides pulse waveformst ~ . . ' : ~. : ~ : :
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FIG. 5 is a schematic diagram of initial stages of the interface including edge discriminating circuits which provide multiple counts from the pulse waveforms and further showing a combination logic which decodes direction determinative informa- -tion to provide count incrementing and decrementing signals for a counter array; and FIG. 6 is a schematic diagram of subsequent stages of the interface including the counter array interconnected to multi-function shift registers for loading count data into a processor às well as for memory addressing and for temporary data stor~go.

DESCRIPTION OF THE PREFERRED EMBODIMENT , ~`
The present invention relates to a mailing system ~hich determines the welght of an article by processing a pair of electro-optically generated waveforms which are a function of the displacement of a sprlng scale. The signals are counted, with the coonter sl1gnals belng~fed to a processor for averaging and ¦~computation~of the load weight. The processor further computes the~postage required for the article.
; Inaluded in the mailing system are wave ahaplng circuits for`each wavéform, pulse edge di9criminating circuits and a combi nation logic for determining the direction of count, i.e. decreas ing or increasing-; An Integrated circuit interface is provlded for receiv-ing and processing the shaped waveform signals. ~he interface includes~an up/down counter array, the outputs of which are fed ¦
to a microprocessor throùgh a plurallty of multifunction shift ~'' ', ,''''', ~'1' . ~ .

113~003 registers with the shift registers serving as memory registcrs and as intermediate storage registers. Further, the multifunc-tion shift registers are adapted to be loaded without separately clearing prior data.
Referring now in detail to the drawings, the reference numeral 10 (FIG. 2) denotes generally a mailing system con-¦¦ ,structed in accordance with and embodying the invention. Thcsystem 10 is adapted to process electro-optically transduced signals generated by a transducer 12 upon which a periodic fringe pattern 14 is projected. The fringe pattern 14 may comprise a molre pattern optically coupled to a tare of a spring scale 16 such that the fringe pattern moves as an optically amplified function of scale tare displacement as more li . , .
I fu~y-set fo~th~ th~ ~Qregoing patents. It ¦ should be appreciated, however, that the present invention i~
well adapted for the processing of cyclic signals generated in any counting environment.
The transducer 12 comprises ~our phototransistors ~8, j 20, 22 and 24, all having similar operating charactqristics.
Prom an observation of FIG. 4,it will bc appreciated that the ph~t~
I transistor 18 i5 coupled between a positive potential and the collector electrode of the transistor 24. Thus, the transist4rs 18 and 20 provide a bias for the phototransistors 22,24, r~sp~c-tively, in lieu of conventional biasing resistors.

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The biasing or compensating phototransistors 18, 20 in-¦crease the range of output voltage for the phototransistors 22, 24 Iand provide compensation for changes in source radiation, atmospher-¦ic conditions, temperature changes, etc., which affect the biasing ¦and biased phototransistors simultaneously. Thus, a dynamic bias ¦is provided which maintains the operating characteristics of the phototransistors 22, 24 in a manner similar to that disclosed in ¦U. S. Letters Patent No. 3,913,095 issued October 14, 1975 to ¦Dlugos and assigned to the assignee of the present invention.
Movement of the fringe pattern 14 across the phototransis-tor array pro~ides substantially sinusoidal cyclic waveform out-¦ puts designated waveform a and waveform b in FIG. 3 from the l collectors of the transistors 22, 24, respectively. Each o~ the ¦ ~analog waveforms a and b are fed to a wave shaping circuit 25 ¦compris~ng a linear voltage comparator Schmitt trigger inverter 26, 28, respectively, to generate a pair of pulse waveforms ¦~deslgnated PCI and PC2, respectively.
In accordance wlth the Invention,the pulse waveforms ~l ~a~nd PC2 are fu~rther~processed~to provide an indication of the weight ~of an article placed on the scale 16 through the utilization of an ; int-grated clrcUit interface 33 b-tween the wave ~haping airauit 25, a microproCessor 35 and an external memory,q.g. a PROM 37.
With reference to FIG. 5 whereia initial cireuits of tlle lnterface are~deplceed, it will be seen that a pair of inverters 30, 31 provide inverse waveforms PCl and PC2, respectively, from the signals PCl and~PC2.

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~i 1~3~3 The waveforms PCl and PC2 are edge discriminated at a pair of edge discriminators 32 and 34, respectively, to provide a pulse waveform PCl~ (indicating a positive going edge of PCl) and a waveform PCl~ (indicating a negative going edge of PCl).
Similarly, the edge discriminator 34 provides a waveform PC2 and a waveform ~C2~ indicating positive and negative going êdges of the waveform PC2. The edge discriminators 32, 34 each comprise a pair of fully clocked D-Type edge-triggered flip-flops operating as shift registers and providing a multiplication by four, i.e. four pulses for each cycle of the fringe pattern.
Decoding of the flip-flop outputs by a pair of AND gates pro-vides the transition waveforms PCl~, PCl~, PC2~, and PC2~.

The digital waveforms thus generated are decoded at a combination logic 36 which comprises a pair of expandible 4 wide 2 input AND OR invert gates 38, 40, respectively. The combination logic 36 decodes for count direction information to provide inverse pulse waveform signals INC and DEC indica-tive of increasing and decreasing scale tare displacement, respectively.

2~0 With reference now to the waveform timing diagram of FIG. 3, the waveforms a and b are shown progressing first through an up count and then through a down count. The cor-I ;responding digital signals PCl and PC2, the edge discriminated signals PCl~, PCl~, PC2~, and PC2~, and the signals INC and DEC
are also depicted. It will be appreciated that the com~ination logic 36 generates the displacement direction decoded signals INC and DEC in accordance with the foll~wing equations:
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(PCl) (PC2~) + (PC~) (PCl~) +~ (PC2~) + (PC~) (PCl~

(PCl)~PC2~) + (PC2)(PCl~) + (PCI)(PC2~) + (PC2)(PCl~) = DEC

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1131~ 3 In accordance with the invention, the increasing and de- I -creasing waveforms INC and DEC are provided for processing as inputs to the count up and count down inputs of the first stage of an up/down counter array 42. The counter array 42 is exemplary of many possible variations and has been designed for utilization in conjunction with the operating parameters of the leaf spring scale 16 utilizing a moire fringe pattern optical detector and the transducer 12. In such application the spring constant and optical moire displacement amplification calibration provide a least significant bit indicative of a scale displacement produced by a specified minimum weight increment. The processing system of the present inventlon, however, is adapted for application in numerous counting environments, and decoding for weight indicative information is by way of example only. ¦
The counter 42 includes four counter stages 44, 46, 48, and 50, each comprising a four bit binary up/down counter. The counters are cascaded by feeding the borrow and carry outputs to ohe count down and count up inputs respectively of succeeding aounters in the array. ¦
The blt output of each counter stage 44, 46, 48 and 50 1~
i8 broadside loaded through respective multiplexers into correspon -ing four blt nontransparent parallel access shift registers 52, ¦ ;
54, 56 and 58, respectively.
The shift registers 52, 54, 56 and 58 sample and hold the counter bit outputs upon a LOAD REGISTBR signal from the micro-processor 35. In order to insure that the shift registers will ''`, ' ~ . ~
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11311(~.3 not be loaded with counter bit data during the propagation of a count through the counter array 42, a data ready circuit 6Q
provides a DATA READY signal which permits loading of the shift registers only after count propagation has been completed.
The data ready circuit 60 includes a NAND gate 62 which samples both the INC and DEC signals. When incoming INC and DEC
pulses enter the counter array 42, a series of low signal pulses is provided as an input to the gate 62 which gate provides corresponding high output signals. Only when there is an absense of fringe pattern movement with both the INC and DEC signals high will there be a low output from the gate 62. The high out-~ pùt-signal of the NA~D gate 62 is utilized to reset a decade ; counter 64 (7490) having a cycle period at least as great as thc time required for propagation of counts through the entire counter array 42.
A high counter reset signal from the gate 62 provides a low DATA READY output s~gnal from the counter 64. The low DAT~
- REA~Y output signal is inverted and fed to a NAND gate 66 along ~with a CLOCK signal to provide pulse signals for drivinq the I counter 64. A high DATA READY signal will be provided only after a specified time interval after an absonse of fringe pattern move-ment which interval is synchroni2ed with count propagation time of :
the INC and DEC signals through the counter array 42.
'' The high DATA READY signal is provided at a further NAND
gate 68 along with a LOAD REGISTER control signal from the micro-proressor 35 to vide ~ low parallel load signal to the shiit ::~,' . .
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¦registers 52, 54, 56 and 58 which will then sample and hold the ¦ counter bit outputs of the various counter stages 44, 46, 48 and 1 50.
¦ It should be appreciated that unless the INC and D~C
¦ signals are at rest and therefore the counter array is not receiv ¦ ing any further incoming pulses, the counter 64 of the DATA READY j ¦ circuit 60 is constantly being reset and the DATA READY signal wi remain low for the propagation to thereby prevent loading of the ¦ shift registers with erroneous data.
¦ The direction of scale tare di5placement 19 readily exam-ined through the utilization of a latch 70 comprising a JK flip ~-. ,, ¦ flop which receives the signals INC and DEC. The latch output 1 is further utilized to provide a condition on clearing the counte ¦ array 42. Thus, when the scale tare is oscillating about zero displacement, a SCALE ChEAR request signal, clock synchronized at a D fIip flop 72 is provided at a NAND gate 74 along with the Q output of the latch 70 to provide a synchronous COUNTER CLEAR
~signal assuring~that the counters will only clear in the positive edge of zero dlsplacement.
~AB mentioned heretofore, the mailing system of the presen ~ .
invention is adapted to compute the postage requlred for the ar-~t~icle to be~weighed on the ~cale 16. Among the factors in com-~puting postage for articles are current postage rate class schedu] e ~data, zone~destinatlon data and conversion data to provide zone destination wherein only a zip code is known. External input : to the microprocessQr ~5 for destination input is provided by a . keyboard 76 and an associated lnput/output interface 78.

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Only the Initia1 three reglsters 52, 54 and 56 are pro-~vided with addressing ability in the system application illustrat-ed:~howevèr~more reglsters~could be~added, if required. Thus, a ¦keyboard generated slgnal comprising two~twelve bit words may ~ ¦be shifted in two stages into the first threo shift registers ti~ 1s2, 54 and 56 and wlll be available for memory addressing. As-suming indirect addressing of ths rate PROM 37, the first twelve bits oS the~keyboard signal are serial loaded into the shift reg-~x ~ i~ters to locate the flrst scgment of the indirect address in the rate PROM 37 via a plurality of addressing lines A-0 through A-ll.

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;, An initial eiqht bit segment of the address data obtained . rom the PROM 37 is utilized as an input to the multifunction shi~t registers 56, 58 on a plurality o data lines D-O through D-7.
In order to receive the indirect address segment at the shift register 56, 58 the microprocessor 35 first provides an appropriate low SELECT or steering signal to a pair of multiplexers 82, 84, each selectively interconnecting either the stages 48, 50 of the counter array or the data lines D-O through D-3 and D-4 th~ ugh D-7, respectively, with the associated shift register 56, 58 for parallel loading at a low SELECT signal.
In order to provide greater versatility for the interface ¦33' the counter stages 44 and 46 are similarly interconnected to their respective shift registers 52, 54 via corresponding multi-plexers 78 and 80. Separate SELECT signals are provided for the multiplexer pair 78, 80 and the multiplexer pair 82, 84. :
In:sequence, the second twelve bit portion of the keyboard rate address signal is shifted lnto the shift register array. It ¦should be appreciated that during the twelve clock pulses within ¦which the second portion of the keyboard address is shifted in, the :
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: ~eight bits of PROM 37 address data are shifted out to the micro-: processor 35 along with four bits of the prior keyboard address : ~previou51y in the register 54) which is discaraed.
The second portion of the keyboard signal becomes avail-able on the address lines, and eight bits of corresponding address data from the PROM 37 become available on the datà lines D-O
i through D-7. In the manner previously described with respect to ..

`.ii the prior address data, such data is parallel loaded to the : shi~t registers 56, 58 via the multiplexers 82, 84.
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¦ Subsequently, the final portion of the indirect address ¦Idata is shifted from th~ shift registers 56,58 into the processor j in eight clock pulses to thereby provide the processor with the fUll 16 bits of address necessary to read the rate table. With respect to such 16 bit address, the first four bits are for refer- -ence indicating, for example,the size of the table,while the re-maining 12 bitS comprise the table address.
A keyboard generat^d-zone destination slgnal provides a four bit word for storage in a zone register of the processor 35. If the operator is aware of the destination zip code but not the zone, a keyboard generated 12 bit Zip direct address signal is utilized to address a zip to zone PROM 86 via the addressing lines A-0 through A-ll. In a manner similar to that heretofor~
jdescribed with reference to the keyboard rate address signal~, the zip address signal is shifted into~the registers 52, 54 and 56 I to address the PROM 86.~ ~The corresponding 4 bit PROM zone dat~i :
16 recelved through~the~lines D-O through D-3 and laaded~into tl shlft~reglster 58~vla~the multlplexer 84.~;The microprocessor 35 ;jthen receives th-~zone data~by shifting it; from the register 5h.
itu~tUe zone datal ànd rate table address data received in the ¦mlcroprocessor, th- microprocessor may proceed to determine the ¦reiquired postage.
InitialIy, the twelve bit table address is shifted from i~th-~microproces~or ~to: th- shift r-gist-rs 52, 54, 56 and utilized to address the~PROM 37. Co~putatlon oe postage requlres six data words, each comprising -ight bits. Two data words are necessary ~ to determine tlle intercept or equation 9tartin~ valuc; two data ; word9 are required to determine the oquation slope or price in-crement per weight unit~ and tWo data words are requir`ed to - : ::: - :., - . ,. . -, : . . -, 113~ 3 ¦I determine the equation range capacity or maximum weight for the Il postage class.
After the table address data has been utilized to address the PROM via the addressing lines A-O through A-ll, a first eight bit corresponding data word of the PROM 37 becomes available on ~¦ the data lines D-0 through D-7 of thè interface. An appropriate 1l SELECT signal generated by the microprocessor results in the 1 1l parallel loading of the data word into the shift registers 56, 58.
It should be appreciated that simultaneously with the loading of the data word, the portion of the prior address in the register 56 is destroyed.
To obtain the next sequential rate data word, the pro-cessor is programmed to increment the prior address by one and sequentially serial load the shift registers 52, 54, 56 to provide ¦ ~such address on the addresstng lines A-O~through A-ll. In ac-¦ cordance with the invention, the muitifunction shift registers ,~ -¦ ~52, ~54. 56 and 58~provide~a~savlngs in~handlling time by permit-¦~ting the~mlcroprocessor~to~s~imultaneously receive the eight ~blt data~wordlstored~in the registers 56 ànd 58, while loading n~the next sequential address. Thus~, within the twelve clock I puls-s~requlred to shift in the next sequential addres~, the ~eigh t blt data~wor~ stored in r-gister~ S6,5~ are pullcd into the microprocessor a~long wlth four bit- o~ the prior addreas previous- `
? ~ : ly held in the register 54. ~It shoold be appreciated bhat the 1 portion of the prior~addrqss is no longer ùtilized by the processor. ~

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113~0~

With the next sequential address on the data lines A-0 ¦through A-ll the corresponding eight bit rate data word will be ¦available on the data lines D-0 through D-7 and in a manner iden-¦tical to that heretofore described with respect to the prior data ¦word, it is parallel loaded into the shift registers 56, 58 and ¦subsequently pulled into the microprocessor simultaneously with the loading of the next sequential address.
After the initial si~ data words are received in the ¦microprocessor 35, the processor is programmed to determine whether the information pulled is appropriate for computing the ¦requisite postage for the destination zone. If the information ¦is not appropriate, the microprocessor continues incrementing the table address to the PROM 37 until the appropriate data words have been obtained for postage computation.
¦ It should be appreciated that the versatility of the intcr-¦face 33 is further enhanced through the implementation of the ¦multiplexers 78 and 80 which~increase the parallel loadlng capacity of~the~shift register array. Additionally, it should be noted that the data lines D-0 through D-lS could be utilized as input iines~for any perlpheral device associated with the system, for example photodetoctors monitoring other staqes of the system.
Further, the multlplexers could be utilized as a selective int~r-connection between the shift registers and any peripheral device rather than the counter stages illustrated.
The microprocessor implementation described is only one example of many possible variations possible in mailing systems.
In addition to the exemplarj embodiment herein described, further . ' . .~

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1~3q~ 3 embodiments of the invention include variations such as utilization of the parallel output lines A-0 through A-ll for unloading counter data. It should be understood that the invention may encompass implementation of the multifunction shift registers as an element of an interface operatively interconnecting any microprocessor, an external memory and one or more peripheral devices.
Thus, it will be seen that thexe is provided a mailing system which achieves the various objects of the -10 present invention and which is well suited to meet the conditions of practical use.
As various changes might be made in the system as above set forth, it is to be understood that all matters herein described or shown in the accompanying drawings are to be interpreted as illustrative and not in a limiting sense.
Certain aspects of the foregoing description are also disclosed and claimed in Applicant's copending application Serial Number 288,514 filed October 12, 1977.
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Claims (4)

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:

1. An interface for providing information transfer channels between a transducer generating cyclic signals and a processing unit, the interface including counter means and means operatively interconnecting the transducer and the counter means, the interface further including register means adapted to receive counter information and control means adapted to prevent the transfer of counter information to the register means during propagation of a count through the counter means, the control means comprising timing means coordinated with count propagation time of the counter means and means monitoring the cyclic signals, said monitoring means being adapted to actuate the timing means.

2. An interface constructed in accordance with claim 1 wherein the means operatively interconnecting the transducer and the counter means includes means providing increasing and decreasing count signals, the monitoring means receiving said count signals, and including gate means.

3. An interface for providing information transfer channels between a transducer generating cyclic signals and a processing unit, the interface being operatively connected to said processing unit for facilitating transfer of data thereto, said interface including logic means coupled to the transducer for generating pulses in response to the cyclic signals, counter means and means operatively interconnecting the logic means and the counter means, the interface further including register means adapted to receive counter information from said counter means and control means adapted to prevent the transfer of counter information to the register means during propagation of a count through the counter means from the logic means, the control means comprising timing means coordinated with the count propagation time of the counter means for storing a time interval and means monitoring the cyclic signals, said monitoring means being adapted to actuate the timing means when said propagation of said count through said counter means occurs, inhibiting means for inhibiting the counter information from being transferred to said register means until a predetermined time interval after completion of said count propagation has elapsed.

4. An interface constructed in accordance with claim 3 wherein the means operatively interconnecting the transducer and the counter means includes means transferring increasing and decreasing count signals from said transducer logic means, the monitoring means including gate means for receiving said count signals and for generating a signal in response thereto to said counter means.