CA1126369A - Delay blaster - Google Patents
Delay blasterInfo
- Publication number
- CA1126369A CA1126369A CA316,875A CA316875A CA1126369A CA 1126369 A CA1126369 A CA 1126369A CA 316875 A CA316875 A CA 316875A CA 1126369 A CA1126369 A CA 1126369A
- Authority
- CA
- Canada
- Prior art keywords
- blaster
- delay
- output
- circuit
- firing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
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- Measurement Of Predetermined Time Intervals (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A novel delay electric blaster is provided which provides a firing circuit or pulse after a selected fixed time delay. The blaster comprises a firing circuit with out-put terminals, timing circuit and an interlock circuit together with clock or counter means and electrical energy storage means.
A novel delay electric blaster is provided which provides a firing circuit or pulse after a selected fixed time delay. The blaster comprises a firing circuit with out-put terminals, timing circuit and an interlock circuit together with clock or counter means and electrical energy storage means.
Description
li2~3~9 This invention relates to a delay blaster for the delayed firing of one or more electric igniter cord igniters or electric starters.
It is an object of the present invention to provide a delay blaster, which provides a firing pulse after a selectable fixed time delay.
The invention provides a delay blaster which comprises a firing circuit which includes output terminals for connection to a load consisting of one or more electric starters, a timing circuit to actuate the firing circuit after a predetermined interval and an interlock circuit which enables the timing circuit only when the output terminals are connected to the load and the interlock circuit is then connected to a power supply.
Further according to the invention the timing circuit includes clock means and mean~ to count the output of the clock means, the counting means generating a signal which actuates the firing circuit after the predetermined interval.
Further according to the invention the fi~ing circuit includes electrical energy storage means and means to discharge the storage means into the load.
In order that the blaster of the invention can be used in fiery mines, it further includes means to limit the period for which the storage means is discharged.
Further according to the invention the delay blaster includes a D.C. to D.C. converter, the output of which is connected to the energy storage means and the input of which is enabled when the actuating signal is generated.
The invention is further described by way of example with reference to the accompanying drawings in which:
Figure l is a block diagram of a delay blaster according to the invention, and Figure 2 is a circuit diagram of the delay blaster of the invention.
Referring to Figure l, a delay blaster accord-ing to the invention consists of an interlock circuit lO, a first oscillator 12, a counter 14, a second oscillator 16, a D.C. to D.C. converter 18 and a firing circuit 20.
The interlock circuit 10 has terminals for connection to a power supply 22. The firing circuit 20 has output terminals for connection to a load 24 which in practice consists of one or more electrical starters connected ln serles.
The operation of the blaster of the invention will first be described broadly with reference to Figure 1. The first oscillator 12 and the counter 14 together make up a timing circuit and the second oscillator 16, the D.C. to D~C. converter 18 and the firing circuit 20 make up the output stage of the blaster. To initiate the timing cycle of the blaster, the external blasting circuit, that is, the load 24 must first be connected to the output terminals of the firing circuit 20 and then the supply 22 must be connected to the interlock circuit lO. Should the steps be reversed, the blaster ~ ~26~6~
will not function. The correct operation of the timing circuit is indicated by means of a flashing lamp 26, which is connected to the counter 14. The flash interval is directly related to the total time delay of the blaster.
When the selected time delay has elapsed, the output stage of the blaster is enabled. The second oscillator 16, which is powered by the supply 22, pro-vides an oscillating input to the D.C. convertor 18 and the output of the converter is used to charge a capa-citor in the firing circuit 20. The charging of the firing capacitor is indicated by a lamp 28. The duration of the charging time depends on the condition of the power supply 22 but generally is more than 45 seconds and so provides sufficient time to warn the operator of the blaster that firing is imminent.
When firing takes place, a firing pulse is discharged into the load 24 for a period of approxi-mately 4,5 milliseconds. This enables the blaster to be used in fiery mines.
Once the blaster has fired, it remains inactive irrespective of the resistance of the load which may be connected to the output terminals of the firing circuit 20. A new timing cycle can only be initiated when the correct set-up procedure is followed to enable the interlock circuit 10.
Figure 2 is a detailed circuit diagram of the delay blaster of the invention. The various blocks of Figure 1 can be identified with the circuit components of Figure 2 as follows:
The interlock circuit 10 consists of i.nte-grated circuit modules IC 1 / (I - IV), the first oscillator 12 consists of integrated circuit modules IC 2 / (I - III), the counter 14 consists ofan inte-grated circuit IC 3, the second oscillator 16 consists of integrated circuit modules IC 4 / (I - III), the D.C. to D.C. convertor 18 consists of a tran~former TR 1 and a transistor T 1 connected to the output of the second oscillator 16, and the firing cireuit 20 consists of transistors T 2 and T 3, a diae DCl, a diode D 2, capacitors C 6 and C 7, resistors R 13, R 14, R 16 and R 18, and a current limiting resistor R 15.
A diode D 3 is eonnected to the collector of the transistor T 3.
The lamp 26 is eonneeted to the fourth module of the integrated IC 4 whieh in turn is eonnected to an output terminal of the eounter IC 3, and the lamp 28 is eonneeted in series with the diode D 2 and the remainder of the firing eireuit.
The interlock cireuit 10 also ineludes resistors R 1 and R 2 and a zener diode Z 1 eonneeted in series aeross a key switeh KSW in series with a power supply PM 9.
When the key switeh is elosed, power is applied to the interloek eireuit IC 1 / (I - IV) if the load 24 has been eorreetly eonneeted to the output terminals of the firing eireuit prior to the operation of the key switeh. If the voltage of the power supply PM 9 is greater than a speeified voltage, this voltage ~:iLZ~36~
being monitored by means of the zener diode Z 1, the supply voltage is connected to the first oscillator IC 2 / (I - III) and to the counter IC 3. The clock oscillator produces a periodic pulse train, the period of which i5 determined by the values of the resistors R 7 and R 8 and of the capacitor C 4 and these clock pulses drive the counter IC 3. To indicate that the timing cycle is in progress, the lamp 26, which is a light emitting diode, is pulsed.
The flashing rate of the diode is directly proportional to the period of the pulse train output by the first oscillator 12.
The counter IC 3 counts the pulses and at a predetermined pulse count its output terminal, pin 3, goes high, enabling the second oscillator circuit 16 through the gate IC 4 / (II). The second oscil-lator produces at its output a square wave at a repitition frequency of approximately 100 kHz which drives the transistor T 1 and hence causes an alter-nating input to be applied to the transformer TR 1of the D.C. to D.C. converter. The converter is designed so that its output voltage exceeds a pre-determined value when the voltage of the power supply PM 9 is above a minimum level. The output of the transformer TR 1 is rectified by the diode D 2 and the capacitor C 6 is charged. During charging of the capacitor the lamp 28 which is a light emitting diode is illuminated. This serves as a warning to t:he operator of the delay blaster that the firing of the electric starters is imminent.
. j~
65~
The charging time of the capacitor C 6 is controlled by the value of a resistor R 9 in the base of the transistor T 1. When the voltage on the capacitor approaches a value which is nearly equal to the minimum output voltage of the transformer, the threshold voltage of the diac DC 1 is reached and it therefore conducts switching on the transis-tors T 2 and T 3. The capacitor T 6 is then dis-charged via the current limiting resistor R 15 and the transistor T 3 into the load 24. The duration of the output pulse is dependent on the character-istic of the diac DC 1 and on the time constant of the C 7, R 16 network. The resistor R 16 is chosen so that the current through the diac DC 1 drops below the diac holding current value in 4,5 +0,4 milliseconds. The output pulse of the blaster is terminated when this happens.
The positive output pulse, appearing on the output terminals when the blaster fires, biasses the diode D 1 into a non-conductive mode so that the input of the gate IC 1 / (II) goes high and its output goes low switching off power to the first oscillator 12 and to the counter IC 3. The current consumption of the shot exploder circuitry is then negligible.
The output of the interlock circuit remains low even when a new load is connected to the output terminals. To reset the shot exploder and to start a new timing cycle the key switch KSW
must be turned from the on to the off position and back on again whereupon power is again applied to the oscillator and counter circuitry.
It is an object of the present invention to provide a delay blaster, which provides a firing pulse after a selectable fixed time delay.
The invention provides a delay blaster which comprises a firing circuit which includes output terminals for connection to a load consisting of one or more electric starters, a timing circuit to actuate the firing circuit after a predetermined interval and an interlock circuit which enables the timing circuit only when the output terminals are connected to the load and the interlock circuit is then connected to a power supply.
Further according to the invention the timing circuit includes clock means and mean~ to count the output of the clock means, the counting means generating a signal which actuates the firing circuit after the predetermined interval.
Further according to the invention the fi~ing circuit includes electrical energy storage means and means to discharge the storage means into the load.
In order that the blaster of the invention can be used in fiery mines, it further includes means to limit the period for which the storage means is discharged.
Further according to the invention the delay blaster includes a D.C. to D.C. converter, the output of which is connected to the energy storage means and the input of which is enabled when the actuating signal is generated.
The invention is further described by way of example with reference to the accompanying drawings in which:
Figure l is a block diagram of a delay blaster according to the invention, and Figure 2 is a circuit diagram of the delay blaster of the invention.
Referring to Figure l, a delay blaster accord-ing to the invention consists of an interlock circuit lO, a first oscillator 12, a counter 14, a second oscillator 16, a D.C. to D.C. converter 18 and a firing circuit 20.
The interlock circuit 10 has terminals for connection to a power supply 22. The firing circuit 20 has output terminals for connection to a load 24 which in practice consists of one or more electrical starters connected ln serles.
The operation of the blaster of the invention will first be described broadly with reference to Figure 1. The first oscillator 12 and the counter 14 together make up a timing circuit and the second oscillator 16, the D.C. to D~C. converter 18 and the firing circuit 20 make up the output stage of the blaster. To initiate the timing cycle of the blaster, the external blasting circuit, that is, the load 24 must first be connected to the output terminals of the firing circuit 20 and then the supply 22 must be connected to the interlock circuit lO. Should the steps be reversed, the blaster ~ ~26~6~
will not function. The correct operation of the timing circuit is indicated by means of a flashing lamp 26, which is connected to the counter 14. The flash interval is directly related to the total time delay of the blaster.
When the selected time delay has elapsed, the output stage of the blaster is enabled. The second oscillator 16, which is powered by the supply 22, pro-vides an oscillating input to the D.C. convertor 18 and the output of the converter is used to charge a capa-citor in the firing circuit 20. The charging of the firing capacitor is indicated by a lamp 28. The duration of the charging time depends on the condition of the power supply 22 but generally is more than 45 seconds and so provides sufficient time to warn the operator of the blaster that firing is imminent.
When firing takes place, a firing pulse is discharged into the load 24 for a period of approxi-mately 4,5 milliseconds. This enables the blaster to be used in fiery mines.
Once the blaster has fired, it remains inactive irrespective of the resistance of the load which may be connected to the output terminals of the firing circuit 20. A new timing cycle can only be initiated when the correct set-up procedure is followed to enable the interlock circuit 10.
Figure 2 is a detailed circuit diagram of the delay blaster of the invention. The various blocks of Figure 1 can be identified with the circuit components of Figure 2 as follows:
The interlock circuit 10 consists of i.nte-grated circuit modules IC 1 / (I - IV), the first oscillator 12 consists of integrated circuit modules IC 2 / (I - III), the counter 14 consists ofan inte-grated circuit IC 3, the second oscillator 16 consists of integrated circuit modules IC 4 / (I - III), the D.C. to D.C. convertor 18 consists of a tran~former TR 1 and a transistor T 1 connected to the output of the second oscillator 16, and the firing cireuit 20 consists of transistors T 2 and T 3, a diae DCl, a diode D 2, capacitors C 6 and C 7, resistors R 13, R 14, R 16 and R 18, and a current limiting resistor R 15.
A diode D 3 is eonnected to the collector of the transistor T 3.
The lamp 26 is eonneeted to the fourth module of the integrated IC 4 whieh in turn is eonnected to an output terminal of the eounter IC 3, and the lamp 28 is eonneeted in series with the diode D 2 and the remainder of the firing eireuit.
The interlock cireuit 10 also ineludes resistors R 1 and R 2 and a zener diode Z 1 eonneeted in series aeross a key switeh KSW in series with a power supply PM 9.
When the key switeh is elosed, power is applied to the interloek eireuit IC 1 / (I - IV) if the load 24 has been eorreetly eonneeted to the output terminals of the firing eireuit prior to the operation of the key switeh. If the voltage of the power supply PM 9 is greater than a speeified voltage, this voltage ~:iLZ~36~
being monitored by means of the zener diode Z 1, the supply voltage is connected to the first oscillator IC 2 / (I - III) and to the counter IC 3. The clock oscillator produces a periodic pulse train, the period of which i5 determined by the values of the resistors R 7 and R 8 and of the capacitor C 4 and these clock pulses drive the counter IC 3. To indicate that the timing cycle is in progress, the lamp 26, which is a light emitting diode, is pulsed.
The flashing rate of the diode is directly proportional to the period of the pulse train output by the first oscillator 12.
The counter IC 3 counts the pulses and at a predetermined pulse count its output terminal, pin 3, goes high, enabling the second oscillator circuit 16 through the gate IC 4 / (II). The second oscil-lator produces at its output a square wave at a repitition frequency of approximately 100 kHz which drives the transistor T 1 and hence causes an alter-nating input to be applied to the transformer TR 1of the D.C. to D.C. converter. The converter is designed so that its output voltage exceeds a pre-determined value when the voltage of the power supply PM 9 is above a minimum level. The output of the transformer TR 1 is rectified by the diode D 2 and the capacitor C 6 is charged. During charging of the capacitor the lamp 28 which is a light emitting diode is illuminated. This serves as a warning to t:he operator of the delay blaster that the firing of the electric starters is imminent.
. j~
65~
The charging time of the capacitor C 6 is controlled by the value of a resistor R 9 in the base of the transistor T 1. When the voltage on the capacitor approaches a value which is nearly equal to the minimum output voltage of the transformer, the threshold voltage of the diac DC 1 is reached and it therefore conducts switching on the transis-tors T 2 and T 3. The capacitor T 6 is then dis-charged via the current limiting resistor R 15 and the transistor T 3 into the load 24. The duration of the output pulse is dependent on the character-istic of the diac DC 1 and on the time constant of the C 7, R 16 network. The resistor R 16 is chosen so that the current through the diac DC 1 drops below the diac holding current value in 4,5 +0,4 milliseconds. The output pulse of the blaster is terminated when this happens.
The positive output pulse, appearing on the output terminals when the blaster fires, biasses the diode D 1 into a non-conductive mode so that the input of the gate IC 1 / (II) goes high and its output goes low switching off power to the first oscillator 12 and to the counter IC 3. The current consumption of the shot exploder circuitry is then negligible.
The output of the interlock circuit remains low even when a new load is connected to the output terminals. To reset the shot exploder and to start a new timing cycle the key switch KSW
must be turned from the on to the off position and back on again whereupon power is again applied to the oscillator and counter circuitry.
Claims (12)
1. A delay blaster which includes:
(a) output terminals for connection to a load consisting of one or more electric starters (b) a firing circuit for supplying firing energy to the output terminals;
(c) a timing circuit for actuating the firing circuit after a predetermined interval, the firing circuit being control-lable to be enabled and disabled;
(d) power input terminals; and (e) an interlock means having a first input connected to at least one of the power input terminals and a second input connected to at least one of the output terminals and an output connected to the timing circuit, for sensing if power is supplied to the power input terminals and if the load is connected to the output terminals and for enabling the timing circuit only if the output terminals are first connected to the load and power is then supplied to the power input terminals,
(a) output terminals for connection to a load consisting of one or more electric starters (b) a firing circuit for supplying firing energy to the output terminals;
(c) a timing circuit for actuating the firing circuit after a predetermined interval, the firing circuit being control-lable to be enabled and disabled;
(d) power input terminals; and (e) an interlock means having a first input connected to at least one of the power input terminals and a second input connected to at least one of the output terminals and an output connected to the timing circuit, for sensing if power is supplied to the power input terminals and if the load is connected to the output terminals and for enabling the timing circuit only if the output terminals are first connected to the load and power is then supplied to the power input terminals,
2. A delay blaster as claimed in Claim 1 wherein the timing circuit includes clock means and means to count the output of the clack means, the counting means generating a signal which actuates the firing circuit after the predetermined interval
3, A delay blastes as claimed in Claim 2 wherein the actuating signal is generated when the count means reaches a pre-determined count,
4, A delay blaster as claimed in Claim 2 wherein the clock means generates a periodic pulse train,
5, A delay blaster as claimed in Claim 4 wherein the period of the pulse train is variable so as to adjust the pre-determined interval,
6, A delay blaster as claimed in Claim 2 wherein the firing circuit includes electrical energy storage means and means to discharge the storage means into the load,
7. A delay blaster as claimed in Claim 6 wherein the discharge means is actuated when the voltage of the stored electrical energy reaches a predetermined value.
8, A delay blaster as claimed in Claim 6 which includes means to limit the period for which the storage means is discharged,
9, A delay blaster as claimed in Claim 8 wherein the discharge period is less than 5 milliseconds,
10, A delay blaster as claimed in Claim 6 which includes a D,C, to D,C, converter, the output of which is con-nected to the energy storage means and the input of which is enabled when the actuating signal is generated.
11, A delay blaster as claimed in Claim 10 which includes an oscillator and gate means connected to the input of the converter, the gate means being enabled by the actuated signal so that the oscillator output is applied to the input of the converter,
12. A delay blaster as claimed in Claim 1 or 6 wherein the interlock means includes means which is responsive to the voltage of the power supply and which enables the interlock means if the voltage exceeds a pre-set value,
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ZA00781243A ZA781243B (en) | 1978-03-03 | 1978-03-03 | Delay blaster |
| ZA78/1243 | 1978-03-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1126369A true CA1126369A (en) | 1982-06-22 |
Family
ID=25572653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA316,875A Expired CA1126369A (en) | 1978-03-03 | 1978-11-24 | Delay blaster |
Country Status (2)
| Country | Link |
|---|---|
| CA (1) | CA1126369A (en) |
| ZA (1) | ZA781243B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1987000265A1 (en) * | 1985-06-28 | 1987-01-15 | Moorhouse, D., J. | Detonator actuator |
| WO1987000264A1 (en) * | 1985-06-28 | 1987-01-15 | Moorhouse, D., J. | Detonator |
| BE1005436A3 (en) * | 1990-10-22 | 1993-07-27 | Zeebrugge Forges Sa | Sequential control system |
-
1978
- 1978-03-03 ZA ZA00781243A patent/ZA781243B/en unknown
- 1978-11-24 CA CA316,875A patent/CA1126369A/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1987000265A1 (en) * | 1985-06-28 | 1987-01-15 | Moorhouse, D., J. | Detonator actuator |
| WO1987000264A1 (en) * | 1985-06-28 | 1987-01-15 | Moorhouse, D., J. | Detonator |
| BE1005436A3 (en) * | 1990-10-22 | 1993-07-27 | Zeebrugge Forges Sa | Sequential control system |
Also Published As
| Publication number | Publication date |
|---|---|
| ZA781243B (en) | 1979-10-31 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |