CA1121515A - Mecanisme de selection d'adresse d'antememoire - Google Patents

Mecanisme de selection d'adresse d'antememoire

Info

Publication number
CA1121515A
CA1121515A CA000317477A CA317477A CA1121515A CA 1121515 A CA1121515 A CA 1121515A CA 000317477 A CA000317477 A CA 000317477A CA 317477 A CA317477 A CA 317477A CA 1121515 A CA1121515 A CA 1121515A
Authority
CA
Canada
Prior art keywords
signals
location
group
memory
cache memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA000317477A
Other languages
English (en)
Inventor
Charles P. Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Application granted granted Critical
Publication of CA1121515A publication Critical patent/CA1121515A/fr
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • G06F12/123Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
CA000317477A 1977-12-08 1978-12-06 Mecanisme de selection d'adresse d'antememoire Expired CA1121515A (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85857577A 1977-12-08 1977-12-08
US858,575 1977-12-08

Publications (1)

Publication Number Publication Date
CA1121515A true CA1121515A (fr) 1982-04-06

Family

ID=25328622

Family Applications (1)

Application Number Title Priority Date Filing Date
CA000317477A Expired CA1121515A (fr) 1977-12-08 1978-12-06 Mecanisme de selection d'adresse d'antememoire

Country Status (6)

Country Link
JP (1) JPS5489438A (fr)
AU (1) AU523670B2 (fr)
CA (1) CA1121515A (fr)
DE (1) DE2853165A1 (fr)
FR (1) FR2411465B1 (fr)
GB (1) GB2009982B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4322795A (en) * 1980-01-24 1982-03-30 Honeywell Information Systems Inc. Cache memory utilizing selective clearing and least recently used updating
JPS60181942A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd メモリ制御装置
DE19543193C1 (de) * 1995-11-20 1997-02-13 Daimler Benz Ag Vorbau für einen Personenkraftwagen mit einer Tragstruktur
WO2004046933A1 (fr) * 2002-11-20 2004-06-03 Fujitsu Limited Controleur de memoire et procede de commande de remplacement de cache
US7673102B2 (en) 2006-05-17 2010-03-02 Qualcomm Incorporated Method and system for maximum residency replacement of cache memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL281825A (fr) * 1961-08-08
GB1124017A (en) * 1964-12-17 1968-08-14 English Electric Computers Ltd Data storage apparatus
US3840862A (en) * 1973-09-27 1974-10-08 Honeywell Inf Systems Status indicator apparatus for tag directory in associative stores
JPS5090259A (fr) * 1973-12-10 1975-07-19

Also Published As

Publication number Publication date
AU523670B2 (en) 1982-08-12
GB2009982A (en) 1979-06-20
DE2853165C2 (fr) 1989-09-21
JPS5489438A (en) 1979-07-16
FR2411465B1 (fr) 1986-05-30
AU4224578A (en) 1980-06-12
DE2853165A1 (de) 1979-06-13
FR2411465A1 (fr) 1979-07-06
GB2009982B (en) 1982-03-24

Similar Documents

Publication Publication Date Title
US4354232A (en) Cache memory command buffer circuit
US4521850A (en) Instruction buffer associated with a cache memory unit
US5530829A (en) Track and record mode caching scheme for a storage system employing a scatter index table with pointer and a track directory
US4471429A (en) Apparatus for cache clearing
US4736293A (en) Interleaved set-associative memory
US4493026A (en) Set associative sector cache
US3670307A (en) Interstorage transfer mechanism
CA1180463A (fr) Methode et dispositif d'adressage en antememoire pour systeme de stockage a disques a antememoire
US3771137A (en) Memory control in a multipurpose system utilizing a broadcast
US5450564A (en) Method and apparatus for cache memory access with separate fetch and store queues
US6401181B1 (en) Dynamic allocation of physical memory space
US5418927A (en) I/O cache controller containing a buffer memory partitioned into lines accessible by corresponding I/O devices and a directory to track the lines
EP0492859A2 (fr) Mémoire tampon de traduction d'adresse
EP0260862A2 (fr) Tampon de sortie en file d'attente
GB1313528A (en) Two-level storage system
SE413815B (sv) Databehandlingssystem
US3771142A (en) Digital data storage system
US4714990A (en) Data storage apparatus
CA1304827C (fr) Dispositif de commande pour memoire tampon
GB2065941A (en) Cache store system
CA1121515A (fr) Mecanisme de selection d'adresse d'antememoire
US4173781A (en) System of coherent management of exchanges between two contiguous levels of a hierarchy of memories
JPH0319976B2 (fr)
EP0093428B1 (fr) Mémoire tampon à circuit d'échanges
US4920536A (en) Error recovery scheme for destaging cache data in a multi-memory system

Legal Events

Date Code Title Description
MKEX Expiry