CA1094635A - Master-slave voltage regultor employing pulse width modulation - Google Patents
Master-slave voltage regultor employing pulse width modulationInfo
- Publication number
- CA1094635A CA1094635A CA295,097A CA295097A CA1094635A CA 1094635 A CA1094635 A CA 1094635A CA 295097 A CA295097 A CA 295097A CA 1094635 A CA1094635 A CA 1094635A
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- Prior art keywords
- pulse width
- voltage
- width modulator
- magnitude
- converter circuit
- Prior art date
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- 238000004804 winding Methods 0.000 claims abstract description 35
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 230000001105 regulatory effect Effects 0.000 claims abstract description 16
- 230000001131 transforming effect Effects 0.000 claims abstract description 5
- 230000001276 controlling effect Effects 0.000 claims description 12
- 238000012544 monitoring process Methods 0.000 claims description 4
- 230000010354 integration Effects 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 241001481828 Glyptocephalus cynoglossus Species 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 229940035564 duration Drugs 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/22—Conversion of DC power input into DC power output with intermediate conversion into AC
- H02M3/24—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters
- H02M3/28—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC
- H02M3/325—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/337—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
- H02M3/3376—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current
- H02M3/3378—Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration with automatic control of output voltage or current in a push-pull configuration of the parallel type
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Inverter Devices (AREA)
Abstract
MASTER-SLAVE VOLTAGE REGULATOR
EMPLOYING PULSE WIDTH MODULATION
Abstract of the Disclosure A pulse width modulation (PWM) converter circuit for transforming a first DC voltage into a second voltage (AC or DC), wherein the magnitude of the second voltage is regulated by the converter circuit. The converter circuit comprises a clock circuit, a master pulse width modulator (PWM) circuit and n slave pulse width modulator (PWM) circuits. The clock circuit provides a symmetrical train of rectangular pulses on each of n+l conductors, wherein only one pulse occurs on any one of the conductors at one time. The master PWM means is responsive both to the train of pulses on one of the n+l conductors and to a feedback signal indicative of the magnitude of the second voltage; the master PWM means controls the flow of current, due to the first DC voltage, through a portion of a transformer primary winding. Each of the slave PWM circuits is responsive both to the train of pulses on n of the n+l conductors, in a one-to-one relationship, and to an output control signal based both upon the feedback signal, indicative of the magnitude of the second voltage, and upon the difference in the magnitude of the charge passed by the master PWM circuit and the charge passed by the respective slave PWM circuits, each of the slave PWM circuits controls the flow of current, due to the first DC voltage, through a portion of the transformer primary winding.
- i -
EMPLOYING PULSE WIDTH MODULATION
Abstract of the Disclosure A pulse width modulation (PWM) converter circuit for transforming a first DC voltage into a second voltage (AC or DC), wherein the magnitude of the second voltage is regulated by the converter circuit. The converter circuit comprises a clock circuit, a master pulse width modulator (PWM) circuit and n slave pulse width modulator (PWM) circuits. The clock circuit provides a symmetrical train of rectangular pulses on each of n+l conductors, wherein only one pulse occurs on any one of the conductors at one time. The master PWM means is responsive both to the train of pulses on one of the n+l conductors and to a feedback signal indicative of the magnitude of the second voltage; the master PWM means controls the flow of current, due to the first DC voltage, through a portion of a transformer primary winding. Each of the slave PWM circuits is responsive both to the train of pulses on n of the n+l conductors, in a one-to-one relationship, and to an output control signal based both upon the feedback signal, indicative of the magnitude of the second voltage, and upon the difference in the magnitude of the charge passed by the master PWM circuit and the charge passed by the respective slave PWM circuits, each of the slave PWM circuits controls the flow of current, due to the first DC voltage, through a portion of the transformer primary winding.
- i -
Description
3~
This invention relates generally to DC
power supplies, and more particularly to a DC to DC
voltage converter employing Pulse Width Modulation (PWM) regulation, for producing a regulated output volta~e (AC or DC) from a first input DC voltage.
The principle of PWM regulation is well known in the art. PWM regulators operate on the basic principle that the incoming DC voltage, which is to be regulated, is chopped or pulsed by means of switched devices (e.g. transistors). The rectangular pulses thus obtained are applied, via a transformer, to a rec-tifier circuit (including a smoothing filter) for producing the desired regulated DC output voltage. By converting the input voltage into a train of pulses, the magnitude of the rectified output voltage can be regulated by varying the width of the pulses while maintaining the frequency of the pulses constant. Automatic control of such a system is accomplished by monitoring the magnitude of the DC output voltage and by providing suitable circuitry to var~ the width of the pulses, as required, in order to maintain the magnitude of the DC output voltage at the required level.
Examples of prior art devices include those depicted in the following U.S. patents, and attention is directed to them:
3,670,234 dated June 13, 1972 to James Mo Joyce;
3,789,288 dated Jan. 29, 1974 to ~.H. ~ssow, et al;
3,806,791 dated April 23, 1974 to Leo J. Johnson;
3,870,943 dated March 11, 1975 to H.R. Weischedel, et al; and 3,988,661 dated Oct. 26, 1976 to Danie~ J. McCoy.
3~;i One problem existing in prior art circuits employing PWM regulators is that of maintaining current balance between the alternately switched devices (e.g., transistors) which convert the DC input voltage into a train of pulses. These switched devices form the inverter portion of the power supply, and for optimum performance from the circuit, the power handled by each such switched device should be equal to the power handled by any other switched device in the circuit.
Another problem in prior art circuits occurs when multiple power supplles are connected in parallel to supply higher power to a common load. Prior art circuits, for power sharing between several power supplies, have been complex and cumbersome.
The present invention, while based upon the known principles of PWM regulation, e~ploys a novel master slave type of arrangement for controlling the width of the pulses produced by the inverter portion of the circuit. This master-slave type o~ arrangement allows for several slave units to be employed with a single master unit, and it also allows for two or more power supplies to be parallelea, while ensuring current sharing between power supplies. The master unit and the slave unit are identical in construction; they acquire their distinctiveness ~i.e., master or slave) depending upon how they are wired into the circuit.
In accordance with one embodiment of the present invention, a power supply (or DC to DC voltage converter) comprises one master unit and one slave unit.
A clock circuit with one output line -Eor the master unit i3~i and one output line for the salve unit is provided. The clock produces a train of rectangular pulses on each of its output lines, with only one pulse on one line at any given time, and all the pulses being of equal duration.
The master unit comprises a transistor switch which is employed to interrupt the input DC voltage in response to a siynal based upon the train of pulses the master unit receives from the clock, but modified by a control signal indicative of the reyulated output voltage of the power supply. The slave unit comprises a transistor switch which is e~ployed to interrupt the input DC voltage in response to a signal based upon the train of pulses the slave unit receives from the clock, but modified by a control signal indicative both of the regulated output voltage of the power supply and the difference in charge passed by the master and slave units. The current pulses, passed by the transistors of the master and slave units, pass through the primary windiny of a transformer. The voltage induced in the secondary winding of this transformer is rectified and filtered, producing the required regulated output voltage.
In another embodiment, the present invention is a pulse width modulation converter circui-t for transforminy a first DC voltage into a second voltage, wherein the magnitude of the second voltage is regulated by the converter circuit, the converter circuit comprising:
a clock means for providing a symmetrical train of pulses on each of n+l conductors, wherein only one pulse occurs on any one of the conductors at any given instant in time, and wherein n is a positive integer 3~i equal to, or greater than, l;
a master pulse width modulator means responsive both to the train of pulses on one of the n+1 conductors and to a feedback signal indicative of the magnitude of the second voltage, the master pulse width modulator means controlling the flow of current, due to the first DC voltage, through a portion of a transformer primary winding;
n slave pulse width modulator means, each of the slave pulse width modulator means being responsive both to the train of pulses on one of the n+l conductors, in a one-to-one relationship, and to an output control signal based both upon the feedback signal, indicative of the magnitude of the second voltage, and upon the difference in themagnitude of the charge passed by the master pulse width modulator means and the charge passed by the respective slave pulse width modulator means, each of the slave pulse width modulator means controlling the flow of current, due to the first DC voltage, through a portion of the transformer primary winding.
In yet anothPr embodiment, the present invention is a pulse width modula-tion converter circuit for transforming a first DC voltage into a second voltage, wherein the magnitude of the second voltage is regulated by the converter circuit, the Gonvertex circuit comprising:
a clock means for providing a symmetrical train of rectangular pulses on each of n+l conductors, wherein only one pulse occurs on any one of the conductors at any given instant in time, and wherein n is a positive integer e~ual to, or greater than, 1;
3~;
a master pulse width modulator means responsive both to the train of pulses on one of the n+l conductors and to a feedback signal indicative of the magnitude of the second voltage, the master pulse width modulator means controlling the flow of current, due to the first DC voltage, through a portion of a transformer prlmary wlnding;
n slave pulse width modulator means, each of the slave pulse width modulator means being responsive both to the train of pulses on one of the n+l conductors, in a one-to-one relationship, and to an output control signal, the output control signal being based both upon the feedback signal indicative of the magnitude of the second voltage, and upon the difference in the magnitude of the charge passed by the master pulse width modulator means and the charge passed by the respective slave pulse width modulator means, each of the slave pulse width modulator means controlling the flow of current, due to the first DC
voltage, through a separate and distinct portion of the transformer primary winding;
a rectifier means connected to the secondary winding of the transformer for rectifying the resultant voltage appearing across the secondary winding, thereby producing the second voltage;
a control circuitry means for monitoring the second voltage and for providing the ~eedback signal indicative of the magnitude of the second voltage.
The invention will ~ow be described in more detail with reference to the accompanying drawings, wherein li~eparts in each of the several figures are identified by the same reference characters, and wherein:
,~1 ,!,~ . ~
Figure l is a simplified block diagram of the present invention;
Figure 2 is a simplified schematic diagram of one particular embodiment of the present invention; and Figure 3 is a simplified block diagram depicting two power converters (according to the preferred embodiment of the present invention) connected for parallel operation.
Figure 1 is a simplified block diagram - o~ the present invention. It comprises a master pulse width modulator (PWM) 10 and n slave pulse width modulators (PWM) indicated as lOa through lOn inclusive.
A cloc~ 12 provides a train of rectangular pulses on each of n~l lines (or conductors), with the pulse on line 14 being applied to master PWM lO and the pulses on lines 14a through 14n being applied to slave PWM's lOa through lOn, respectively. Clock 12 functions so that there is only one plllse on any o~ the lines 14 through 14n inclusive at any given time.
As with any pulse width modulated power regulator, the purpose of the master PWM lO and the slave PWM's lOa to lOn is to interrupt the input DC voltage.
The input DC voltage is applied to terminals lS and 16, with the positive being applied to terminal 16. Master PWM 10 and each slave PWM lOa to lOn contains a switching transistor 18 to 18n respectively. Terminal 16 is connected to the collectors of each of the transistors 18 to 18n via windings 20 to 20n, respectively~ The emit-ters of each of the transistors are connected to the ~ 6 --63~
negative terminal 15 via resistors 22 to 22n respectively.
Resistors 22 to 22n are very low in value, having a resistance of approximately one ohm each; they are used as sensing resistors. It should also be noted that the windings 20 through 20n form a primary winding for a transformer 23. The windings 20 to 20n can be considered as an n+l phase primary winding, wye connected. The secondary of transformer 23 is comprised of n+l windings indicated by the reference numerals 24 through 24n. The windings 24 to 24n can be considered as an n+l phase secondary winding, wye connected. ~ rectifier circuit 25 is connected to the windings 24 through 24n to produce a regulated DC output voltage on terminals 47 and 48.
If desired, a smaller number of secondary windings 24 to 24n can be used and also, if desired, a larger number of output voltages can be obtained from rectifier 25 than shown.
Feedback control circuitry 26 monitors the DC output voltage of rectifier 25 and produces a feedback control signal 27 on line 28. Signal 27 is fed to master PWM 10 and, via summing circuits 2~a through 29n, to slave PWM's lOa thxough lOn respectively.
The current being passed by transistors 18 of master PWM 10 flows through resistor 22 and the magnitude of ~ ~ the voltage drop across resistor 22 is indicative of the ;~ magnitude of the current passing through resistor 22 and consequently through transistor 18. This voltage drop is applied to summing circuits 30a through 30n via line 31. The remaining inputs of each of the summing circuits 30a through 30n are fed with the voltages developed ~, across reslstors 22a through 22n respectively as appear on lines 32a through 32n respectively. The summing ~ircuits 30a throug~ 30n sum the signals appearing at their respective inputs algebraically, according to the signs shown in the ~igure. It should be noted that the signals appearing at the respective inputs o~ summing circuits 30a to 30n do not appear simultaneously, but rather appear sequentially. In other words, when line 31 is carrying a pulse signal, lines 32a to 32n are at zero potential; similarly, when line 32a is carrying a pulse signal, line 31 and lines 32b to 32n are at zero potential, etc. The output of each summing circuit 30a through 30n is applied to an integrator 33a through 33n respectively.
The output of each integrator 33a to 33n alternates about a median value since the input of each integrator 33a to 33n consists of a series of rectangular pulses of appro~imately the same magnitude and duration, and of alternating polarity. The output of each integrator 33a through 33n is in turn applied to summing circuits 29a through 29l1 respectively. The summing circuits 29a through 29n sum the signals appearing a-t their inputs algebraically, according to the signs shown in the figure.
The output of each summing circuit 29a through 29n is applied to slave PWM lOa through lOn respectively, for control purposes. The output signal of each summing circuit 29a through 29n is indicated by the reference characters 34a through 34n respectively. The signals 34a through 34n are employed to modify the length of time that each transistor 18a through 18n respectively, is turned on in response to the pulses ~rom clock 12.
. . , 3~
Figure 2 is a schematic of a circuit constructed according to the block diagram of figure 1, wherein n=l (i.e. there is only one slave PWM)o Clock circuit 12 is of conventional design and produces a first train of rectangular pulses (negative going) on line 1~
and a second train of rectangular pulses (negative going) on line 14a; the pulses on each line 14 and 14a having a duty cycle of 50% and the pulses on line 14 being 180 out of phase with the pulses on line 14a. The frequency of the pulses is 20 XHz.
The pulses on line 14 are applied to capaeitor 35 of master P~M 10. The other end of capaeitor 35 is eonneeted to inverter 36 whieh is in turn eonneeted to the base of transistor 18. Sinee line 14 applies a train of rectangular pulses to eapaeitor 35, the output of eapaeitor 35, applied to the input of inverter 36, has a deeaying exponential waveform.
Inverter 36 transforms this deeaying exponential waveform into a reetangular wave, and of eourse inverts its polarity. ~ feedbaek control signal 27 from the output of feedbaek control eireuitry 26 is applied to the input of inver-ter 36 via resistor 37. The effect of feedback eontrol signal 27 is to set a "base" level for inverter 36 and thus aid in eontrolling the duty cycle of the rectangular wave produced by inverter 36, and consequently eontrol the amount of time that transistor 18 is conducting current. Signal 27 will he described later, in more detailO
The input voltage which is to be regulated i5 applied to terminals 15 and 16, with terminal 16 g _ ;3~
having positive polarity. Terminal 16 is connected to the junction of the two windings 20 and 2Oa. When transistor 18 is conducting (i.e. turned onJ current flows from terminal 16 through winding 20 to the collector of transistor 18, from the emitter of transistor 18 through resistor 22 and thence to terminal 15.
Slave PWM lOa operates in a similar fashion. Line 14a applies a train of rectangular pulses to capacitor 39 of slave PWM lOa. The other end of capacitor 39 is connected to the input of inverter 40 which is in turn connected to the base of transistor 18a. Line 14a applies a train of rectangular pulses to capacitor 39, and the output of capacitor 39, applied to the input of inverter 40, has a decaying exponential waveform. Inverter 40 transforms this decaying exponential waveform into a rectangular wave, and inverts its polarity. An output control signal 34a is applied to the input of inverter 40 via resistor 42. The function of control signal 34a is to set a "base" level for inver-ter 40 and thus aid in controlling the duty cycle of the rectangular wave produced b~ inverter 40, and consequently control the amount of time that transistor 18a is conducting current. The derivation of control signal 34a will be discussed later, in more detail.
Transistor 18a of slave PWM lOa functions in a manner similar to transistor 18 of master PWM 10.
When transistor 18a of slave PWM 10 is turned on, current flows from te~minal 16, through winding 20a, through transistor 18a, through resistor 22a and finally to terminal 15.
~ 'P
The effect of current alternately f lowing and not flowing in windings 20 and 20a induces voltages in windings 24 and 24a, of transformer 23. This voltage is rectified by diodes 43 and 44 as shown in the figure.
An inductor 45 and a capacitor 46 provide filtering to smooth the regulated DC output which is provided at output terminals 47 and 48, with terminal 47 being of positive polarity.
Feedback control circuitry 26 senses the voltage across terminals 47 and 48 and provides a feedback control signal 27 which is applied to the input of inverter 36 via resistor 37. As mentioned previously, signal 27 provides a "base" level for inverter 36.
Providing a base level for inverter 36 means that the magnitude of the signal required from capacitor 35 for changing the output o~ inverter 36 is varlable; i.e. the threshold voltage for inverter 36 is effectively adjust-able. This results in adjusting the duty cycle of the rectangular wave produced by inverter 36 and thereby adjusting the "on" time of transistor 18. This provides a feedback control function by adjusting the duty cycle of master PWM 10.
The desired magnitude of the output voltage across the terminals 47 and 48 is adjusted by varyin~ the value of rheostat 49 which, in series with resis-tor 50, is connected across terminals 47 and 48 as shown in Figure 2. Rheostat 49 and resistor 50 form a voltage divider, the output of which is applied to the non~inverting (~) input of operational amplifier 51. A
voltage of approximately ~30 volts is applied to terminal ii3~i 52. Zener diode 53 is employed with resistors 54 and 55 to provide a regulated reference input voltage to the inverting (-) input of operational amplifier 51.
Resistor 56 ls a feedback resistor for amplifier 51, connected as shown in the figure.
Symmetry control circuit 57 o~ figure 2 incorporates the functions performed in figure 1 by summing circuit 30a, integrator 33a, and summing circuit 29a. It can be seen that circuit 57 senses the current passed by mas er PWM 10 by sensing the voltage drop across resistor 22; this voltage drop is applied to the inverting (-) input of operational amplifier 58 via line 31 and resistor 59. Circuit 57 also senses the current passed by slave PWM lOa by sensing the voltage drop across resistor 22a; this voltage drop is applied to the non-inverting (~) input of operational amplifier 58 via line 32a and resistor 60. The integration function of circuit 57 is provided by resistor 61 and capacitor 62 connected in parallel between the output of operational amplifier 58 and its inverting (-) input, as is well known in the art. The operation of summing the integrated output with the feedback control signal 27 ti.e~ summing circuit 29a of figure 1) is performed in figure 2 by referencing the non~inverting (+) input of operational amplifier 58 to the output (i.e. signal 27~ of operational amplifier 51 via the parallel connection of resistor 63 and capacitor 64. Output signal 34a is applied to the input of inverter 40 via resistor 42.
The purpose of signal 34a is to provide a "base"level for inverter 40. Setting a "base" level for inverter 40 controls the point at which inverter 40 changes its output state (between a logic 0 and a logic 1) and consequently controls how long transistor 18a conducts current; i.e. the threshold voltage for inverter 40 is effectively adjustable. If, for example, transistor 18 of PWM 10 is conducting for a longer period of time than is transistor 18a of PW~ lOa, then the pulse signal on line 31 applied to the inverting (-) input of amplifier 58 will last longer then the pulse signal (on line 32a) applied to the non-inverting (+) input of amplifier 58 and (assuming equal magnitudes of the two aforementioned pulse signals) the output signal 34a of amplifier 58 will consequently increase in a negative direction. This results in an increased negative bias on inverter 40, and consequently inverter 40 produces a longer positive pulse on its output, thereby causing transistor 18a to conduct current for a longer period of time. Similarly, if transistor 18 of PWM 10 is conducting for a shorter period of time then is transistor 18a of PW~l lOa, then the pulse signal on line 31 applied to the inverting (-) input of amplifier 58 will be of less dura-tion than the pulse signal applied to the non-inverting (+) input of amplifier 58 and (still assuming equal magnitudes of -the two afore-mentioned pulse signals) the output signal 34a of amplifier 58 will consequently increase in a positive direction.
This results in a decreased negative bias on inverter 40, and consequantly inverter 40 produces a shorter positive pulse on its output, thereby causing transistor 18a to conduct current for a shorter period of time, than it was p~eviously.
3~i In the general case (i.e. when the magnitude of the current pulses passed by transistors 18 and 18a, and consequently the pulse signals on lines 31 and 32a, are not necessarily of equal magnitude) it is desired ,rO~/~,cr to ensure that the-p~0~e~t of the current (I~ and the duration of conduction (t), of transistor 18, is the same as the product of the same parameters for transistor l~a (i.e. Ixt for transistor 18 is the same as Ixt for transistor 18a). Expressed in other words, it is desired that the charge (Ixt) passed by transistor 18 is the same as the charge (Ixt) passed by transistor 18a.
Figure 3 depic~s two converter circuits 65a and 65b constructed according to a preferred embodiment of the present invention, shown in simplified block diagram form, and shown interconnected for parallel operation. Converter circuits 65a and 65b are identical to one another, and they are very similar to the circuit shown in figures 1 and 2. ~ecause of this similarity, components of circuits 65a and 65b have been assigned a reference character exactl~ one hundred (100) higher than the analogous component in figure 1. For example, clock 12 of figure 1 is depicted a sclock 112 in converter circuit 65a of figure 3, and slave P~1M lOa of figure 1 is depicted as slave P~M llOa of figure 3.
Converter circuits 65a and 65b function in an analogous manner to the circuit of -figure 1.
The differences between circuit 65a (and 65b) of figure 3 and the circuit of figure 1 are as follows. The circuit of figure 1 is sho~n for the general case of one master PWM 10 and n slave PWM's indicated as lOa through lOn; circuit 65a of figure 3 is shown for the specific case of one master pT~ 110 and only one slave PWM llOa. Circuit 65a o:E figure 3 includes additional circuitry employed with master PWM 113 to enable PWM 110 to act as a slave PWM when circuit 65a is employed in parallel operation with one or more additional power supplies (e.g. with circuit 65b as depicted in figure 3).
The additional circuitry employed with master pr~M 110 includes line 132, sumrning circuit 130, inte~rator 133, summing circuit 129 and two single pole single throw (SPST) switches 66 and 67 (interconnected to operate in unison), all as shown and as interconnected in figure 3.
~ witches 66 and 67 function to change master PWM from functioning as a '~Master" unit to functioning as a "slave" unit~ When switches 66 and 67 are in the open position, as in circuit 65a of figure 3, master PWM 110 functions in the same manner as does slave PWM llOa (or as does slave PWM lOa of figure 1). When switches 66 and 67 are in the closed position, as in circuit 65b of figure 3, master PWM 110 functions in the same manne~ as does master PWM 10 of figure 1. I-t should be noted -that the only difference between circuits 65a and 65b is the:position of the switches 66 and 67. I-E
additional converter circuits (identical to circuits 65a and 65b) were co~nected in parallel with converter circuits 65a and 65b, -the additional converter circuits would have their switches 66 and 67 in the open position so that PWM 110 of circuit 65b is the only master pr,~ operating as a "Master" unit in the combination. It should also be noted that the output terminals 147 and 1~8 of circuits 65a and 65b are connected in parallel to provide power to terminals 68 and 69; the input terminals 115 and 116 of each circuit 65a and 65b are also connected in parallel, but have not been so shown in figure 3 so as to avoid undue cluttering of the figure. Additionally, when circuits 65a and 65b are connected in parallel, line 128 of circuit 65a is connected to line 128 of circuit 65b, and line 131 of circuit 65a is connected to line 131 of circuit 65b~
~::
This invention relates generally to DC
power supplies, and more particularly to a DC to DC
voltage converter employing Pulse Width Modulation (PWM) regulation, for producing a regulated output volta~e (AC or DC) from a first input DC voltage.
The principle of PWM regulation is well known in the art. PWM regulators operate on the basic principle that the incoming DC voltage, which is to be regulated, is chopped or pulsed by means of switched devices (e.g. transistors). The rectangular pulses thus obtained are applied, via a transformer, to a rec-tifier circuit (including a smoothing filter) for producing the desired regulated DC output voltage. By converting the input voltage into a train of pulses, the magnitude of the rectified output voltage can be regulated by varying the width of the pulses while maintaining the frequency of the pulses constant. Automatic control of such a system is accomplished by monitoring the magnitude of the DC output voltage and by providing suitable circuitry to var~ the width of the pulses, as required, in order to maintain the magnitude of the DC output voltage at the required level.
Examples of prior art devices include those depicted in the following U.S. patents, and attention is directed to them:
3,670,234 dated June 13, 1972 to James Mo Joyce;
3,789,288 dated Jan. 29, 1974 to ~.H. ~ssow, et al;
3,806,791 dated April 23, 1974 to Leo J. Johnson;
3,870,943 dated March 11, 1975 to H.R. Weischedel, et al; and 3,988,661 dated Oct. 26, 1976 to Danie~ J. McCoy.
3~;i One problem existing in prior art circuits employing PWM regulators is that of maintaining current balance between the alternately switched devices (e.g., transistors) which convert the DC input voltage into a train of pulses. These switched devices form the inverter portion of the power supply, and for optimum performance from the circuit, the power handled by each such switched device should be equal to the power handled by any other switched device in the circuit.
Another problem in prior art circuits occurs when multiple power supplles are connected in parallel to supply higher power to a common load. Prior art circuits, for power sharing between several power supplies, have been complex and cumbersome.
The present invention, while based upon the known principles of PWM regulation, e~ploys a novel master slave type of arrangement for controlling the width of the pulses produced by the inverter portion of the circuit. This master-slave type o~ arrangement allows for several slave units to be employed with a single master unit, and it also allows for two or more power supplies to be parallelea, while ensuring current sharing between power supplies. The master unit and the slave unit are identical in construction; they acquire their distinctiveness ~i.e., master or slave) depending upon how they are wired into the circuit.
In accordance with one embodiment of the present invention, a power supply (or DC to DC voltage converter) comprises one master unit and one slave unit.
A clock circuit with one output line -Eor the master unit i3~i and one output line for the salve unit is provided. The clock produces a train of rectangular pulses on each of its output lines, with only one pulse on one line at any given time, and all the pulses being of equal duration.
The master unit comprises a transistor switch which is employed to interrupt the input DC voltage in response to a siynal based upon the train of pulses the master unit receives from the clock, but modified by a control signal indicative of the reyulated output voltage of the power supply. The slave unit comprises a transistor switch which is e~ployed to interrupt the input DC voltage in response to a signal based upon the train of pulses the slave unit receives from the clock, but modified by a control signal indicative both of the regulated output voltage of the power supply and the difference in charge passed by the master and slave units. The current pulses, passed by the transistors of the master and slave units, pass through the primary windiny of a transformer. The voltage induced in the secondary winding of this transformer is rectified and filtered, producing the required regulated output voltage.
In another embodiment, the present invention is a pulse width modulation converter circui-t for transforminy a first DC voltage into a second voltage, wherein the magnitude of the second voltage is regulated by the converter circuit, the converter circuit comprising:
a clock means for providing a symmetrical train of pulses on each of n+l conductors, wherein only one pulse occurs on any one of the conductors at any given instant in time, and wherein n is a positive integer 3~i equal to, or greater than, l;
a master pulse width modulator means responsive both to the train of pulses on one of the n+1 conductors and to a feedback signal indicative of the magnitude of the second voltage, the master pulse width modulator means controlling the flow of current, due to the first DC voltage, through a portion of a transformer primary winding;
n slave pulse width modulator means, each of the slave pulse width modulator means being responsive both to the train of pulses on one of the n+l conductors, in a one-to-one relationship, and to an output control signal based both upon the feedback signal, indicative of the magnitude of the second voltage, and upon the difference in themagnitude of the charge passed by the master pulse width modulator means and the charge passed by the respective slave pulse width modulator means, each of the slave pulse width modulator means controlling the flow of current, due to the first DC voltage, through a portion of the transformer primary winding.
In yet anothPr embodiment, the present invention is a pulse width modula-tion converter circuit for transforming a first DC voltage into a second voltage, wherein the magnitude of the second voltage is regulated by the converter circuit, the Gonvertex circuit comprising:
a clock means for providing a symmetrical train of rectangular pulses on each of n+l conductors, wherein only one pulse occurs on any one of the conductors at any given instant in time, and wherein n is a positive integer e~ual to, or greater than, 1;
3~;
a master pulse width modulator means responsive both to the train of pulses on one of the n+l conductors and to a feedback signal indicative of the magnitude of the second voltage, the master pulse width modulator means controlling the flow of current, due to the first DC voltage, through a portion of a transformer prlmary wlnding;
n slave pulse width modulator means, each of the slave pulse width modulator means being responsive both to the train of pulses on one of the n+l conductors, in a one-to-one relationship, and to an output control signal, the output control signal being based both upon the feedback signal indicative of the magnitude of the second voltage, and upon the difference in the magnitude of the charge passed by the master pulse width modulator means and the charge passed by the respective slave pulse width modulator means, each of the slave pulse width modulator means controlling the flow of current, due to the first DC
voltage, through a separate and distinct portion of the transformer primary winding;
a rectifier means connected to the secondary winding of the transformer for rectifying the resultant voltage appearing across the secondary winding, thereby producing the second voltage;
a control circuitry means for monitoring the second voltage and for providing the ~eedback signal indicative of the magnitude of the second voltage.
The invention will ~ow be described in more detail with reference to the accompanying drawings, wherein li~eparts in each of the several figures are identified by the same reference characters, and wherein:
,~1 ,!,~ . ~
Figure l is a simplified block diagram of the present invention;
Figure 2 is a simplified schematic diagram of one particular embodiment of the present invention; and Figure 3 is a simplified block diagram depicting two power converters (according to the preferred embodiment of the present invention) connected for parallel operation.
Figure 1 is a simplified block diagram - o~ the present invention. It comprises a master pulse width modulator (PWM) 10 and n slave pulse width modulators (PWM) indicated as lOa through lOn inclusive.
A cloc~ 12 provides a train of rectangular pulses on each of n~l lines (or conductors), with the pulse on line 14 being applied to master PWM lO and the pulses on lines 14a through 14n being applied to slave PWM's lOa through lOn, respectively. Clock 12 functions so that there is only one plllse on any o~ the lines 14 through 14n inclusive at any given time.
As with any pulse width modulated power regulator, the purpose of the master PWM lO and the slave PWM's lOa to lOn is to interrupt the input DC voltage.
The input DC voltage is applied to terminals lS and 16, with the positive being applied to terminal 16. Master PWM 10 and each slave PWM lOa to lOn contains a switching transistor 18 to 18n respectively. Terminal 16 is connected to the collectors of each of the transistors 18 to 18n via windings 20 to 20n, respectively~ The emit-ters of each of the transistors are connected to the ~ 6 --63~
negative terminal 15 via resistors 22 to 22n respectively.
Resistors 22 to 22n are very low in value, having a resistance of approximately one ohm each; they are used as sensing resistors. It should also be noted that the windings 20 through 20n form a primary winding for a transformer 23. The windings 20 to 20n can be considered as an n+l phase primary winding, wye connected. The secondary of transformer 23 is comprised of n+l windings indicated by the reference numerals 24 through 24n. The windings 24 to 24n can be considered as an n+l phase secondary winding, wye connected. ~ rectifier circuit 25 is connected to the windings 24 through 24n to produce a regulated DC output voltage on terminals 47 and 48.
If desired, a smaller number of secondary windings 24 to 24n can be used and also, if desired, a larger number of output voltages can be obtained from rectifier 25 than shown.
Feedback control circuitry 26 monitors the DC output voltage of rectifier 25 and produces a feedback control signal 27 on line 28. Signal 27 is fed to master PWM 10 and, via summing circuits 2~a through 29n, to slave PWM's lOa thxough lOn respectively.
The current being passed by transistors 18 of master PWM 10 flows through resistor 22 and the magnitude of ~ ~ the voltage drop across resistor 22 is indicative of the ;~ magnitude of the current passing through resistor 22 and consequently through transistor 18. This voltage drop is applied to summing circuits 30a through 30n via line 31. The remaining inputs of each of the summing circuits 30a through 30n are fed with the voltages developed ~, across reslstors 22a through 22n respectively as appear on lines 32a through 32n respectively. The summing ~ircuits 30a throug~ 30n sum the signals appearing at their respective inputs algebraically, according to the signs shown in the ~igure. It should be noted that the signals appearing at the respective inputs o~ summing circuits 30a to 30n do not appear simultaneously, but rather appear sequentially. In other words, when line 31 is carrying a pulse signal, lines 32a to 32n are at zero potential; similarly, when line 32a is carrying a pulse signal, line 31 and lines 32b to 32n are at zero potential, etc. The output of each summing circuit 30a through 30n is applied to an integrator 33a through 33n respectively.
The output of each integrator 33a to 33n alternates about a median value since the input of each integrator 33a to 33n consists of a series of rectangular pulses of appro~imately the same magnitude and duration, and of alternating polarity. The output of each integrator 33a through 33n is in turn applied to summing circuits 29a through 29l1 respectively. The summing circuits 29a through 29n sum the signals appearing a-t their inputs algebraically, according to the signs shown in the figure.
The output of each summing circuit 29a through 29n is applied to slave PWM lOa through lOn respectively, for control purposes. The output signal of each summing circuit 29a through 29n is indicated by the reference characters 34a through 34n respectively. The signals 34a through 34n are employed to modify the length of time that each transistor 18a through 18n respectively, is turned on in response to the pulses ~rom clock 12.
. . , 3~
Figure 2 is a schematic of a circuit constructed according to the block diagram of figure 1, wherein n=l (i.e. there is only one slave PWM)o Clock circuit 12 is of conventional design and produces a first train of rectangular pulses (negative going) on line 1~
and a second train of rectangular pulses (negative going) on line 14a; the pulses on each line 14 and 14a having a duty cycle of 50% and the pulses on line 14 being 180 out of phase with the pulses on line 14a. The frequency of the pulses is 20 XHz.
The pulses on line 14 are applied to capaeitor 35 of master P~M 10. The other end of capaeitor 35 is eonneeted to inverter 36 whieh is in turn eonneeted to the base of transistor 18. Sinee line 14 applies a train of rectangular pulses to eapaeitor 35, the output of eapaeitor 35, applied to the input of inverter 36, has a deeaying exponential waveform.
Inverter 36 transforms this deeaying exponential waveform into a reetangular wave, and of eourse inverts its polarity. ~ feedbaek control signal 27 from the output of feedbaek control eireuitry 26 is applied to the input of inver-ter 36 via resistor 37. The effect of feedback eontrol signal 27 is to set a "base" level for inverter 36 and thus aid in eontrolling the duty cycle of the rectangular wave produced by inverter 36, and consequently eontrol the amount of time that transistor 18 is conducting current. Signal 27 will he described later, in more detailO
The input voltage which is to be regulated i5 applied to terminals 15 and 16, with terminal 16 g _ ;3~
having positive polarity. Terminal 16 is connected to the junction of the two windings 20 and 2Oa. When transistor 18 is conducting (i.e. turned onJ current flows from terminal 16 through winding 20 to the collector of transistor 18, from the emitter of transistor 18 through resistor 22 and thence to terminal 15.
Slave PWM lOa operates in a similar fashion. Line 14a applies a train of rectangular pulses to capacitor 39 of slave PWM lOa. The other end of capacitor 39 is connected to the input of inverter 40 which is in turn connected to the base of transistor 18a. Line 14a applies a train of rectangular pulses to capacitor 39, and the output of capacitor 39, applied to the input of inverter 40, has a decaying exponential waveform. Inverter 40 transforms this decaying exponential waveform into a rectangular wave, and inverts its polarity. An output control signal 34a is applied to the input of inverter 40 via resistor 42. The function of control signal 34a is to set a "base" level for inver-ter 40 and thus aid in controlling the duty cycle of the rectangular wave produced b~ inverter 40, and consequently control the amount of time that transistor 18a is conducting current. The derivation of control signal 34a will be discussed later, in more detail.
Transistor 18a of slave PWM lOa functions in a manner similar to transistor 18 of master PWM 10.
When transistor 18a of slave PWM 10 is turned on, current flows from te~minal 16, through winding 20a, through transistor 18a, through resistor 22a and finally to terminal 15.
~ 'P
The effect of current alternately f lowing and not flowing in windings 20 and 20a induces voltages in windings 24 and 24a, of transformer 23. This voltage is rectified by diodes 43 and 44 as shown in the figure.
An inductor 45 and a capacitor 46 provide filtering to smooth the regulated DC output which is provided at output terminals 47 and 48, with terminal 47 being of positive polarity.
Feedback control circuitry 26 senses the voltage across terminals 47 and 48 and provides a feedback control signal 27 which is applied to the input of inverter 36 via resistor 37. As mentioned previously, signal 27 provides a "base" level for inverter 36.
Providing a base level for inverter 36 means that the magnitude of the signal required from capacitor 35 for changing the output o~ inverter 36 is varlable; i.e. the threshold voltage for inverter 36 is effectively adjust-able. This results in adjusting the duty cycle of the rectangular wave produced by inverter 36 and thereby adjusting the "on" time of transistor 18. This provides a feedback control function by adjusting the duty cycle of master PWM 10.
The desired magnitude of the output voltage across the terminals 47 and 48 is adjusted by varyin~ the value of rheostat 49 which, in series with resis-tor 50, is connected across terminals 47 and 48 as shown in Figure 2. Rheostat 49 and resistor 50 form a voltage divider, the output of which is applied to the non~inverting (~) input of operational amplifier 51. A
voltage of approximately ~30 volts is applied to terminal ii3~i 52. Zener diode 53 is employed with resistors 54 and 55 to provide a regulated reference input voltage to the inverting (-) input of operational amplifier 51.
Resistor 56 ls a feedback resistor for amplifier 51, connected as shown in the figure.
Symmetry control circuit 57 o~ figure 2 incorporates the functions performed in figure 1 by summing circuit 30a, integrator 33a, and summing circuit 29a. It can be seen that circuit 57 senses the current passed by mas er PWM 10 by sensing the voltage drop across resistor 22; this voltage drop is applied to the inverting (-) input of operational amplifier 58 via line 31 and resistor 59. Circuit 57 also senses the current passed by slave PWM lOa by sensing the voltage drop across resistor 22a; this voltage drop is applied to the non-inverting (~) input of operational amplifier 58 via line 32a and resistor 60. The integration function of circuit 57 is provided by resistor 61 and capacitor 62 connected in parallel between the output of operational amplifier 58 and its inverting (-) input, as is well known in the art. The operation of summing the integrated output with the feedback control signal 27 ti.e~ summing circuit 29a of figure 1) is performed in figure 2 by referencing the non~inverting (+) input of operational amplifier 58 to the output (i.e. signal 27~ of operational amplifier 51 via the parallel connection of resistor 63 and capacitor 64. Output signal 34a is applied to the input of inverter 40 via resistor 42.
The purpose of signal 34a is to provide a "base"level for inverter 40. Setting a "base" level for inverter 40 controls the point at which inverter 40 changes its output state (between a logic 0 and a logic 1) and consequently controls how long transistor 18a conducts current; i.e. the threshold voltage for inverter 40 is effectively adjustable. If, for example, transistor 18 of PWM 10 is conducting for a longer period of time than is transistor 18a of PW~ lOa, then the pulse signal on line 31 applied to the inverting (-) input of amplifier 58 will last longer then the pulse signal (on line 32a) applied to the non-inverting (+) input of amplifier 58 and (assuming equal magnitudes of the two aforementioned pulse signals) the output signal 34a of amplifier 58 will consequently increase in a negative direction. This results in an increased negative bias on inverter 40, and consequently inverter 40 produces a longer positive pulse on its output, thereby causing transistor 18a to conduct current for a longer period of time. Similarly, if transistor 18 of PWM 10 is conducting for a shorter period of time then is transistor 18a of PW~l lOa, then the pulse signal on line 31 applied to the inverting (-) input of amplifier 58 will be of less dura-tion than the pulse signal applied to the non-inverting (+) input of amplifier 58 and (still assuming equal magnitudes of -the two afore-mentioned pulse signals) the output signal 34a of amplifier 58 will consequently increase in a positive direction.
This results in a decreased negative bias on inverter 40, and consequantly inverter 40 produces a shorter positive pulse on its output, thereby causing transistor 18a to conduct current for a shorter period of time, than it was p~eviously.
3~i In the general case (i.e. when the magnitude of the current pulses passed by transistors 18 and 18a, and consequently the pulse signals on lines 31 and 32a, are not necessarily of equal magnitude) it is desired ,rO~/~,cr to ensure that the-p~0~e~t of the current (I~ and the duration of conduction (t), of transistor 18, is the same as the product of the same parameters for transistor l~a (i.e. Ixt for transistor 18 is the same as Ixt for transistor 18a). Expressed in other words, it is desired that the charge (Ixt) passed by transistor 18 is the same as the charge (Ixt) passed by transistor 18a.
Figure 3 depic~s two converter circuits 65a and 65b constructed according to a preferred embodiment of the present invention, shown in simplified block diagram form, and shown interconnected for parallel operation. Converter circuits 65a and 65b are identical to one another, and they are very similar to the circuit shown in figures 1 and 2. ~ecause of this similarity, components of circuits 65a and 65b have been assigned a reference character exactl~ one hundred (100) higher than the analogous component in figure 1. For example, clock 12 of figure 1 is depicted a sclock 112 in converter circuit 65a of figure 3, and slave P~1M lOa of figure 1 is depicted as slave P~M llOa of figure 3.
Converter circuits 65a and 65b function in an analogous manner to the circuit of -figure 1.
The differences between circuit 65a (and 65b) of figure 3 and the circuit of figure 1 are as follows. The circuit of figure 1 is sho~n for the general case of one master PWM 10 and n slave PWM's indicated as lOa through lOn; circuit 65a of figure 3 is shown for the specific case of one master pT~ 110 and only one slave PWM llOa. Circuit 65a o:E figure 3 includes additional circuitry employed with master PWM 113 to enable PWM 110 to act as a slave PWM when circuit 65a is employed in parallel operation with one or more additional power supplies (e.g. with circuit 65b as depicted in figure 3).
The additional circuitry employed with master pr~M 110 includes line 132, sumrning circuit 130, inte~rator 133, summing circuit 129 and two single pole single throw (SPST) switches 66 and 67 (interconnected to operate in unison), all as shown and as interconnected in figure 3.
~ witches 66 and 67 function to change master PWM from functioning as a '~Master" unit to functioning as a "slave" unit~ When switches 66 and 67 are in the open position, as in circuit 65a of figure 3, master PWM 110 functions in the same manner as does slave PWM llOa (or as does slave PWM lOa of figure 1). When switches 66 and 67 are in the closed position, as in circuit 65b of figure 3, master PWM 110 functions in the same manne~ as does master PWM 10 of figure 1. I-t should be noted -that the only difference between circuits 65a and 65b is the:position of the switches 66 and 67. I-E
additional converter circuits (identical to circuits 65a and 65b) were co~nected in parallel with converter circuits 65a and 65b, -the additional converter circuits would have their switches 66 and 67 in the open position so that PWM 110 of circuit 65b is the only master pr,~ operating as a "Master" unit in the combination. It should also be noted that the output terminals 147 and 1~8 of circuits 65a and 65b are connected in parallel to provide power to terminals 68 and 69; the input terminals 115 and 116 of each circuit 65a and 65b are also connected in parallel, but have not been so shown in figure 3 so as to avoid undue cluttering of the figure. Additionally, when circuits 65a and 65b are connected in parallel, line 128 of circuit 65a is connected to line 128 of circuit 65b, and line 131 of circuit 65a is connected to line 131 of circuit 65b~
~::
Claims (11)
WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED
ARE DEFINED AS FOLLOWS:-
1. A pulse width modulation converter circuit for transforming a first DC voltage into a second voltage, wherein the magnitude of said second voltage is regulated by said converter circuit, said converter circuit comprising:
a clock means for providing a symmetrical train of pulses on each of n+l conductors, wherein only one pulse occurs on any one of said conductors at any given instant in time, and wherein n is a positive integer equal to, or greater than, l;
a master pulse width modulator means responsive both to the train of pulses on one of said n+l conductors and to a feedback signal indicative of the magnitude of said second voltage, said master pulse width modulator means controlling the flow of current, due to said first DC voltage, through a portion of a transformer primary winding;
n slave pulse width modulator means, each said slave pulse width modulator means being responsive both to the train of pulses on one of said n+l conductors, in a one-to-one relationship, and to an output control signal based both upon said feedback signal, indicative of the magnitude of said second voltage, and upon the difference in the magnitude of the charge passed by said master pulse width modulator means and the charge passed by said respective slave pulse width modulator means, each said slave pulse width modulator means controlling the flow of current, due to said first DC voltage, through a portion of said transformer primary winding.
a clock means for providing a symmetrical train of pulses on each of n+l conductors, wherein only one pulse occurs on any one of said conductors at any given instant in time, and wherein n is a positive integer equal to, or greater than, l;
a master pulse width modulator means responsive both to the train of pulses on one of said n+l conductors and to a feedback signal indicative of the magnitude of said second voltage, said master pulse width modulator means controlling the flow of current, due to said first DC voltage, through a portion of a transformer primary winding;
n slave pulse width modulator means, each said slave pulse width modulator means being responsive both to the train of pulses on one of said n+l conductors, in a one-to-one relationship, and to an output control signal based both upon said feedback signal, indicative of the magnitude of said second voltage, and upon the difference in the magnitude of the charge passed by said master pulse width modulator means and the charge passed by said respective slave pulse width modulator means, each said slave pulse width modulator means controlling the flow of current, due to said first DC voltage, through a portion of said transformer primary winding.
2. The pulse width modulation converter circuit of claim 1 wherein n=1.
3. A pulse width modulation converter circuit for transforming a first DC voltage into a second voltage, wherein the magnitude of said second voltage is regulated by said converter circuit, said converter circuit comprising:
a clock means for providing a symmetrical train of rectangular pulses on each of n+1 conductors, wherein only one pulse occurs on any one of said conductors at any given instant in time, and wherein n is a positive integer equal to, or greater than, 1;
a master pulse width modulator means responsive both to the train of pulses on one of said n+1 conductors and to a feedback signal indicative of the magnitude of said second voltage, said master pulse width modulator means controlling the flow of current, due to said first DC voltage, through a portion of a transformer primary winding;
n slave pulse width modulator means, each said slave pulse width modulator means being responsive both to the train of pulses on one of said n+1 conductors, in a one-to-one relationship, and to an output control signal, said output control signal being based both upon said feedback signal indicative of the magnitude of said second voltage, and upon the difference in the magnitude of the charge passed by said master pulse width modulator means and the charge passed by said respective slave pulse width modulator means, each said slave pulse width modulator means controlling the flow of current, due to said first DC voltage, through a separate and distinct portion of the transformer primary winding;
a rectifier means connected to a secondary winding of said transformer for rectifying the resultant voltage appearing across said secondary winding, thereby producing said second voltage;
a control circuitry means for monitoring said second voltage and for providing said feedback signal indicative of the magnitude of said second voltage.
a clock means for providing a symmetrical train of rectangular pulses on each of n+1 conductors, wherein only one pulse occurs on any one of said conductors at any given instant in time, and wherein n is a positive integer equal to, or greater than, 1;
a master pulse width modulator means responsive both to the train of pulses on one of said n+1 conductors and to a feedback signal indicative of the magnitude of said second voltage, said master pulse width modulator means controlling the flow of current, due to said first DC voltage, through a portion of a transformer primary winding;
n slave pulse width modulator means, each said slave pulse width modulator means being responsive both to the train of pulses on one of said n+1 conductors, in a one-to-one relationship, and to an output control signal, said output control signal being based both upon said feedback signal indicative of the magnitude of said second voltage, and upon the difference in the magnitude of the charge passed by said master pulse width modulator means and the charge passed by said respective slave pulse width modulator means, each said slave pulse width modulator means controlling the flow of current, due to said first DC voltage, through a separate and distinct portion of the transformer primary winding;
a rectifier means connected to a secondary winding of said transformer for rectifying the resultant voltage appearing across said secondary winding, thereby producing said second voltage;
a control circuitry means for monitoring said second voltage and for providing said feedback signal indicative of the magnitude of said second voltage.
4. The pulse width modulator converter circuit of claim 3, wherein said output control signal is produced as follows: the first algebraic sum of 1) the negative of a signal indicative of the magnitude of the current being passed by said master pulse width modulator means and 2) a signal indicative of the magnitude of the current being passed by the slave pulse width modulator means being controlled is taken; said first algebraic sum is integrated, with respect to time; the second algebraic sum of 1) the resultant integration of said first algebraic sum and 2) a signal indicative of the magnitude of said second voltage is taken, and said second algebraic sum is said output control signal.
5. The pulse width modulator converter circuit of claim 4, wherein said transformer has an n+l phase primary winding, wye connected, and an n+l phase secondary winding, wye connected.
6. The pulse width modulator converter circuit of claim 3, 4, or 5 wherein n=1.
7. A pulse width modulation converter circuit for transforming a first DC voltage into a second voltage, wherein the magnitude of said second voltage is regulated by said converter circuit, said converter circuit comprising:
a clock means for providing a first symmetrical train of rectangular pulses on a first conductor, and a second symmetrical train of rectangular pulses on a second conductor, said second train of pulses being 180 degrees out of phase with said first train of pulses;
a master pulse width modulator means responsive both to said first train of pulses and to a feedback signal indicative of the magnitude of said second voltage, said master pulse width modulator means controlling the flow of current, due to said first DC
voltage, through a first portion of a transformer primary winding;
one slave pulse width modulator means responsive both to said second train of pulses and to an output control signal based both upon said feedback signal indicative of the magnitude of said second voltage, and upon the difference in the magnitude of the charge passed by said master pulse width modulator means and by said slave pulse width modulator means, said slave pulse width modulator means controlling the flow of current, due to said first DC voltage, through a second portion of said transformer primary winding.
a clock means for providing a first symmetrical train of rectangular pulses on a first conductor, and a second symmetrical train of rectangular pulses on a second conductor, said second train of pulses being 180 degrees out of phase with said first train of pulses;
a master pulse width modulator means responsive both to said first train of pulses and to a feedback signal indicative of the magnitude of said second voltage, said master pulse width modulator means controlling the flow of current, due to said first DC
voltage, through a first portion of a transformer primary winding;
one slave pulse width modulator means responsive both to said second train of pulses and to an output control signal based both upon said feedback signal indicative of the magnitude of said second voltage, and upon the difference in the magnitude of the charge passed by said master pulse width modulator means and by said slave pulse width modulator means, said slave pulse width modulator means controlling the flow of current, due to said first DC voltage, through a second portion of said transformer primary winding.
8. The pulse width modulation converter circuit of claim 7 further including a rectifier means connected to a secondary winding of said transformer for rectifying the resultant voltage appearing across said secondary winding, thereby producing a second DC
voltage; and feedback control circuitry means for monitoring said second DC voltage and for providing said feedback signal indicative of the magnitude of said second DC
voltage.
voltage; and feedback control circuitry means for monitoring said second DC voltage and for providing said feedback signal indicative of the magnitude of said second DC
voltage.
9. The pulse width modulation converter circuit of claim 8, wherein said output control signal is produced as follows: the first algebraic sum of 1) the negative of a signal indicative of the magnitude of the current being passed by said master pulse width modulator means and 2) a signal indicative of the magnitude of the current being passed by the slave pulse width modulator means is taken;
the second algebraic sum of 1) the resultant integration of said first algebraic sum and 2) a signal indicative of the magnitude of said second DC voltage is taken, and the resultant signal so produced is said output control signal.
the second algebraic sum of 1) the resultant integration of said first algebraic sum and 2) a signal indicative of the magnitude of said second DC voltage is taken, and the resultant signal so produced is said output control signal.
10. The pulse width modulation converter circuit of claim 7, 8 or 9 wherein said master pulse width modulator means is identical in construction to said slave pulse width modulator means.
11. The pulse width modulation converter circuit of claim 8 wherein said converter circuit is operated in parallel with the outputs of one or more additional converter circuits wherein said additional converter circuits are substantially identical to said converter circuit of claim 8 with the exception that said additional converter circuits have their master pulse width modulators connected and operated as slave pulse width modulators and their feedback control circuitry means are disabled; said modulator converter circuit of claim 8 provides the master pulse width modulator function, and the feedback control circuitry function, for all said converter circuits connected in parallel.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA295,097A CA1094635A (en) | 1978-01-17 | 1978-01-17 | Master-slave voltage regultor employing pulse width modulation |
| GB79566A GB2012501B (en) | 1978-01-17 | 1979-01-08 | Master-slave voltage regulator employing pulse width modulation |
| FR7900995A FR2414751A1 (en) | 1978-01-17 | 1979-01-16 | VARIABLE WIDTH PULSE MODULATION VOLTAGE REGULATOR |
| SE7900391A SE440842B (en) | 1978-01-17 | 1979-01-16 | PULSBREDDSMODULATIONSOMVANDLARKRETS |
| JP54002331A JPS607908B2 (en) | 1978-01-17 | 1979-01-16 | Master-slave voltage regulator with pulse width modulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA295,097A CA1094635A (en) | 1978-01-17 | 1978-01-17 | Master-slave voltage regultor employing pulse width modulation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1094635A true CA1094635A (en) | 1981-01-27 |
Family
ID=4110560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA295,097A Expired CA1094635A (en) | 1978-01-17 | 1978-01-17 | Master-slave voltage regultor employing pulse width modulation |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS607908B2 (en) |
| CA (1) | CA1094635A (en) |
| FR (1) | FR2414751A1 (en) |
| GB (1) | GB2012501B (en) |
| SE (1) | SE440842B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2120500A (en) * | 1982-05-04 | 1983-11-30 | Gen Electric | Control signal and isolation circuits |
| US5563540A (en) * | 1993-09-17 | 1996-10-08 | International Business Machines Corporation | Electronic switch having programmable means to reduce noise coupling |
| US5376830A (en) * | 1993-09-17 | 1994-12-27 | International Business Machines Corporation | High frequency slope compensation circuit for current programmed converter |
| US5521809A (en) * | 1993-09-17 | 1996-05-28 | International Business Machines Corporation | Current share circuit for DC to DC converters |
| EP1061629B1 (en) * | 1999-06-07 | 2004-08-25 | STMicroelectronics S.r.l. | Single wire current sharing control technique for parallel/redundant operation of a plurality of PWM converters |
| US6642631B1 (en) * | 2000-10-17 | 2003-11-04 | Semiconductor Components Industries Llc | Circuit and method of direct duty cycle current sharing |
| DE10112039A1 (en) * | 2001-03-14 | 2002-10-02 | Infineon Technologies Ag | Providing supply voltage to load involves setting output currents of voltage supply modules depending on current measurement signal of one module selected as reference current signal |
| DE102004017146B4 (en) * | 2004-04-07 | 2006-02-16 | Infineon Technologies Ag | Switching converter with at least two converter stages |
| DE102005002570A1 (en) | 2005-01-19 | 2006-07-27 | Infineon Technologies Ag | Control circuit for buck converter, has signal converter designed so that absolute difference value between one control signal and amplitude value of sinusoidal signal relates to difference of another signal and amplitude value |
| DE102006013524B4 (en) | 2006-03-23 | 2012-02-02 | Infineon Technologies Ag | Switching converter with several converter stages |
| DE102007049774B3 (en) * | 2007-10-17 | 2009-07-02 | Siemens Ag | Inverters, in particular solar inverters, with load balancing control |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3297936A (en) * | 1963-04-19 | 1967-01-10 | Gen Motors Corp | Converter circuit employing pulse width modulation |
| US3619758A (en) * | 1970-09-29 | 1971-11-09 | Honeywell Inc | Dc voltage conversion apparatus |
| DE2319068C3 (en) * | 1973-04-16 | 1979-02-01 | Ulrich Dipl.-Ing. 8047 Karlsfeld Timme | Protective circuit |
| US4032830A (en) * | 1975-07-03 | 1977-06-28 | Burroughs Corporation | Modular constant current power supply |
-
1978
- 1978-01-17 CA CA295,097A patent/CA1094635A/en not_active Expired
-
1979
- 1979-01-08 GB GB79566A patent/GB2012501B/en not_active Expired
- 1979-01-16 SE SE7900391A patent/SE440842B/en not_active IP Right Cessation
- 1979-01-16 FR FR7900995A patent/FR2414751A1/en active Granted
- 1979-01-16 JP JP54002331A patent/JPS607908B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| FR2414751A1 (en) | 1979-08-10 |
| FR2414751B1 (en) | 1984-08-24 |
| JPS607908B2 (en) | 1985-02-27 |
| GB2012501A (en) | 1979-07-25 |
| SE7900391L (en) | 1979-07-18 |
| JPS54113055A (en) | 1979-09-04 |
| SE440842B (en) | 1985-08-19 |
| GB2012501B (en) | 1982-05-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |